tg3.c 349 KB

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  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2007 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include <linux/compiler.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/in.h>
  25. #include <linux/init.h>
  26. #include <linux/ioport.h>
  27. #include <linux/pci.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/skbuff.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/mii.h>
  33. #include <linux/if_vlan.h>
  34. #include <linux/ip.h>
  35. #include <linux/tcp.h>
  36. #include <linux/workqueue.h>
  37. #include <linux/prefetch.h>
  38. #include <linux/dma-mapping.h>
  39. #include <net/checksum.h>
  40. #include <net/ip.h>
  41. #include <asm/system.h>
  42. #include <asm/io.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/uaccess.h>
  45. #ifdef CONFIG_SPARC
  46. #include <asm/idprom.h>
  47. #include <asm/prom.h>
  48. #endif
  49. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  50. #define TG3_VLAN_TAG_USED 1
  51. #else
  52. #define TG3_VLAN_TAG_USED 0
  53. #endif
  54. #define TG3_TSO_SUPPORT 1
  55. #include "tg3.h"
  56. #define DRV_MODULE_NAME "tg3"
  57. #define PFX DRV_MODULE_NAME ": "
  58. #define DRV_MODULE_VERSION "3.79"
  59. #define DRV_MODULE_RELDATE "July 18, 2007"
  60. #define TG3_DEF_MAC_MODE 0
  61. #define TG3_DEF_RX_MODE 0
  62. #define TG3_DEF_TX_MODE 0
  63. #define TG3_DEF_MSG_ENABLE \
  64. (NETIF_MSG_DRV | \
  65. NETIF_MSG_PROBE | \
  66. NETIF_MSG_LINK | \
  67. NETIF_MSG_TIMER | \
  68. NETIF_MSG_IFDOWN | \
  69. NETIF_MSG_IFUP | \
  70. NETIF_MSG_RX_ERR | \
  71. NETIF_MSG_TX_ERR)
  72. /* length of time before we decide the hardware is borked,
  73. * and dev->tx_timeout() should be called to fix the problem
  74. */
  75. #define TG3_TX_TIMEOUT (5 * HZ)
  76. /* hardware minimum and maximum for a single frame's data payload */
  77. #define TG3_MIN_MTU 60
  78. #define TG3_MAX_MTU(tp) \
  79. ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  80. /* These numbers seem to be hard coded in the NIC firmware somehow.
  81. * You can't change the ring sizes, but you can change where you place
  82. * them in the NIC onboard memory.
  83. */
  84. #define TG3_RX_RING_SIZE 512
  85. #define TG3_DEF_RX_RING_PENDING 200
  86. #define TG3_RX_JUMBO_RING_SIZE 256
  87. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  88. /* Do not place this n-ring entries value into the tp struct itself,
  89. * we really want to expose these constants to GCC so that modulo et
  90. * al. operations are done with shifts and masks instead of with
  91. * hw multiply/modulo instructions. Another solution would be to
  92. * replace things like '% foo' with '& (foo - 1)'.
  93. */
  94. #define TG3_RX_RCB_RING_SIZE(tp) \
  95. ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
  96. #define TG3_TX_RING_SIZE 512
  97. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  98. #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  99. TG3_RX_RING_SIZE)
  100. #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  101. TG3_RX_JUMBO_RING_SIZE)
  102. #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
  103. TG3_RX_RCB_RING_SIZE(tp))
  104. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  105. TG3_TX_RING_SIZE)
  106. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  107. #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
  108. #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
  109. /* minimum number of free TX descriptors required to wake up TX process */
  110. #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
  111. /* number of ETHTOOL_GSTATS u64's */
  112. #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
  113. #define TG3_NUM_TEST 6
  114. static char version[] __devinitdata =
  115. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  116. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  117. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  118. MODULE_LICENSE("GPL");
  119. MODULE_VERSION(DRV_MODULE_VERSION);
  120. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  121. module_param(tg3_debug, int, 0);
  122. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  123. static struct pci_device_id tg3_pci_tbl[] = {
  124. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  125. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  126. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  127. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  128. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  129. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  130. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  131. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  132. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  133. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  134. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  135. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  136. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  137. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  138. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  139. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
  152. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  153. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
  154. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  155. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  156. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  157. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  158. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
  159. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  160. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  161. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  162. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  163. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  164. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  165. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  166. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  167. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
  168. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  169. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  170. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  171. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  172. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  173. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  174. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  175. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  176. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  177. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  178. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  179. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  180. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  181. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  182. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  183. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  184. {}
  185. };
  186. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  187. static const struct {
  188. const char string[ETH_GSTRING_LEN];
  189. } ethtool_stats_keys[TG3_NUM_STATS] = {
  190. { "rx_octets" },
  191. { "rx_fragments" },
  192. { "rx_ucast_packets" },
  193. { "rx_mcast_packets" },
  194. { "rx_bcast_packets" },
  195. { "rx_fcs_errors" },
  196. { "rx_align_errors" },
  197. { "rx_xon_pause_rcvd" },
  198. { "rx_xoff_pause_rcvd" },
  199. { "rx_mac_ctrl_rcvd" },
  200. { "rx_xoff_entered" },
  201. { "rx_frame_too_long_errors" },
  202. { "rx_jabbers" },
  203. { "rx_undersize_packets" },
  204. { "rx_in_length_errors" },
  205. { "rx_out_length_errors" },
  206. { "rx_64_or_less_octet_packets" },
  207. { "rx_65_to_127_octet_packets" },
  208. { "rx_128_to_255_octet_packets" },
  209. { "rx_256_to_511_octet_packets" },
  210. { "rx_512_to_1023_octet_packets" },
  211. { "rx_1024_to_1522_octet_packets" },
  212. { "rx_1523_to_2047_octet_packets" },
  213. { "rx_2048_to_4095_octet_packets" },
  214. { "rx_4096_to_8191_octet_packets" },
  215. { "rx_8192_to_9022_octet_packets" },
  216. { "tx_octets" },
  217. { "tx_collisions" },
  218. { "tx_xon_sent" },
  219. { "tx_xoff_sent" },
  220. { "tx_flow_control" },
  221. { "tx_mac_errors" },
  222. { "tx_single_collisions" },
  223. { "tx_mult_collisions" },
  224. { "tx_deferred" },
  225. { "tx_excessive_collisions" },
  226. { "tx_late_collisions" },
  227. { "tx_collide_2times" },
  228. { "tx_collide_3times" },
  229. { "tx_collide_4times" },
  230. { "tx_collide_5times" },
  231. { "tx_collide_6times" },
  232. { "tx_collide_7times" },
  233. { "tx_collide_8times" },
  234. { "tx_collide_9times" },
  235. { "tx_collide_10times" },
  236. { "tx_collide_11times" },
  237. { "tx_collide_12times" },
  238. { "tx_collide_13times" },
  239. { "tx_collide_14times" },
  240. { "tx_collide_15times" },
  241. { "tx_ucast_packets" },
  242. { "tx_mcast_packets" },
  243. { "tx_bcast_packets" },
  244. { "tx_carrier_sense_errors" },
  245. { "tx_discards" },
  246. { "tx_errors" },
  247. { "dma_writeq_full" },
  248. { "dma_write_prioq_full" },
  249. { "rxbds_empty" },
  250. { "rx_discards" },
  251. { "rx_errors" },
  252. { "rx_threshold_hit" },
  253. { "dma_readq_full" },
  254. { "dma_read_prioq_full" },
  255. { "tx_comp_queue_full" },
  256. { "ring_set_send_prod_index" },
  257. { "ring_status_update" },
  258. { "nic_irqs" },
  259. { "nic_avoided_irqs" },
  260. { "nic_tx_threshold_hit" }
  261. };
  262. static const struct {
  263. const char string[ETH_GSTRING_LEN];
  264. } ethtool_test_keys[TG3_NUM_TEST] = {
  265. { "nvram test (online) " },
  266. { "link test (online) " },
  267. { "register test (offline)" },
  268. { "memory test (offline)" },
  269. { "loopback test (offline)" },
  270. { "interrupt test (offline)" },
  271. };
  272. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  273. {
  274. writel(val, tp->regs + off);
  275. }
  276. static u32 tg3_read32(struct tg3 *tp, u32 off)
  277. {
  278. return (readl(tp->regs + off));
  279. }
  280. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  281. {
  282. unsigned long flags;
  283. spin_lock_irqsave(&tp->indirect_lock, flags);
  284. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  285. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  286. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  287. }
  288. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  289. {
  290. writel(val, tp->regs + off);
  291. readl(tp->regs + off);
  292. }
  293. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  294. {
  295. unsigned long flags;
  296. u32 val;
  297. spin_lock_irqsave(&tp->indirect_lock, flags);
  298. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  299. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  300. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  301. return val;
  302. }
  303. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  304. {
  305. unsigned long flags;
  306. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  307. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  308. TG3_64BIT_REG_LOW, val);
  309. return;
  310. }
  311. if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
  312. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  313. TG3_64BIT_REG_LOW, val);
  314. return;
  315. }
  316. spin_lock_irqsave(&tp->indirect_lock, flags);
  317. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  318. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  319. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  320. /* In indirect mode when disabling interrupts, we also need
  321. * to clear the interrupt bit in the GRC local ctrl register.
  322. */
  323. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  324. (val == 0x1)) {
  325. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  326. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  327. }
  328. }
  329. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  330. {
  331. unsigned long flags;
  332. u32 val;
  333. spin_lock_irqsave(&tp->indirect_lock, flags);
  334. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  335. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  336. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  337. return val;
  338. }
  339. /* usec_wait specifies the wait time in usec when writing to certain registers
  340. * where it is unsafe to read back the register without some delay.
  341. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  342. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  343. */
  344. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  345. {
  346. if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
  347. (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  348. /* Non-posted methods */
  349. tp->write32(tp, off, val);
  350. else {
  351. /* Posted method */
  352. tg3_write32(tp, off, val);
  353. if (usec_wait)
  354. udelay(usec_wait);
  355. tp->read32(tp, off);
  356. }
  357. /* Wait again after the read for the posted method to guarantee that
  358. * the wait time is met.
  359. */
  360. if (usec_wait)
  361. udelay(usec_wait);
  362. }
  363. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  364. {
  365. tp->write32_mbox(tp, off, val);
  366. if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  367. !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  368. tp->read32_mbox(tp, off);
  369. }
  370. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  371. {
  372. void __iomem *mbox = tp->regs + off;
  373. writel(val, mbox);
  374. if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  375. writel(val, mbox);
  376. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  377. readl(mbox);
  378. }
  379. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  380. {
  381. return (readl(tp->regs + off + GRCMBOX_BASE));
  382. }
  383. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  384. {
  385. writel(val, tp->regs + off + GRCMBOX_BASE);
  386. }
  387. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  388. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  389. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  390. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  391. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  392. #define tw32(reg,val) tp->write32(tp, reg, val)
  393. #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
  394. #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
  395. #define tr32(reg) tp->read32(tp, reg)
  396. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  397. {
  398. unsigned long flags;
  399. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  400. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  401. return;
  402. spin_lock_irqsave(&tp->indirect_lock, flags);
  403. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  404. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  405. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  406. /* Always leave this as zero. */
  407. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  408. } else {
  409. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  410. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  411. /* Always leave this as zero. */
  412. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  413. }
  414. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  415. }
  416. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  417. {
  418. unsigned long flags;
  419. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  420. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  421. *val = 0;
  422. return;
  423. }
  424. spin_lock_irqsave(&tp->indirect_lock, flags);
  425. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  426. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  427. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  428. /* Always leave this as zero. */
  429. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  430. } else {
  431. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  432. *val = tr32(TG3PCI_MEM_WIN_DATA);
  433. /* Always leave this as zero. */
  434. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  435. }
  436. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  437. }
  438. static void tg3_disable_ints(struct tg3 *tp)
  439. {
  440. tw32(TG3PCI_MISC_HOST_CTRL,
  441. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  442. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  443. }
  444. static inline void tg3_cond_int(struct tg3 *tp)
  445. {
  446. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  447. (tp->hw_status->status & SD_STATUS_UPDATED))
  448. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  449. else
  450. tw32(HOSTCC_MODE, tp->coalesce_mode |
  451. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  452. }
  453. static void tg3_enable_ints(struct tg3 *tp)
  454. {
  455. tp->irq_sync = 0;
  456. wmb();
  457. tw32(TG3PCI_MISC_HOST_CTRL,
  458. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  459. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  460. (tp->last_tag << 24));
  461. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  462. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  463. (tp->last_tag << 24));
  464. tg3_cond_int(tp);
  465. }
  466. static inline unsigned int tg3_has_work(struct tg3 *tp)
  467. {
  468. struct tg3_hw_status *sblk = tp->hw_status;
  469. unsigned int work_exists = 0;
  470. /* check for phy events */
  471. if (!(tp->tg3_flags &
  472. (TG3_FLAG_USE_LINKCHG_REG |
  473. TG3_FLAG_POLL_SERDES))) {
  474. if (sblk->status & SD_STATUS_LINK_CHG)
  475. work_exists = 1;
  476. }
  477. /* check for RX/TX work to do */
  478. if (sblk->idx[0].tx_consumer != tp->tx_cons ||
  479. sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
  480. work_exists = 1;
  481. return work_exists;
  482. }
  483. /* tg3_restart_ints
  484. * similar to tg3_enable_ints, but it accurately determines whether there
  485. * is new work pending and can return without flushing the PIO write
  486. * which reenables interrupts
  487. */
  488. static void tg3_restart_ints(struct tg3 *tp)
  489. {
  490. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  491. tp->last_tag << 24);
  492. mmiowb();
  493. /* When doing tagged status, this work check is unnecessary.
  494. * The last_tag we write above tells the chip which piece of
  495. * work we've completed.
  496. */
  497. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  498. tg3_has_work(tp))
  499. tw32(HOSTCC_MODE, tp->coalesce_mode |
  500. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  501. }
  502. static inline void tg3_netif_stop(struct tg3 *tp)
  503. {
  504. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  505. netif_poll_disable(tp->dev);
  506. netif_tx_disable(tp->dev);
  507. }
  508. static inline void tg3_netif_start(struct tg3 *tp)
  509. {
  510. netif_wake_queue(tp->dev);
  511. /* NOTE: unconditional netif_wake_queue is only appropriate
  512. * so long as all callers are assured to have free tx slots
  513. * (such as after tg3_init_hw)
  514. */
  515. netif_poll_enable(tp->dev);
  516. tp->hw_status->status |= SD_STATUS_UPDATED;
  517. tg3_enable_ints(tp);
  518. }
  519. static void tg3_switch_clocks(struct tg3 *tp)
  520. {
  521. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  522. u32 orig_clock_ctrl;
  523. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  524. return;
  525. orig_clock_ctrl = clock_ctrl;
  526. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  527. CLOCK_CTRL_CLKRUN_OENABLE |
  528. 0x1f);
  529. tp->pci_clock_ctrl = clock_ctrl;
  530. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  531. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  532. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  533. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  534. }
  535. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  536. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  537. clock_ctrl |
  538. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  539. 40);
  540. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  541. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  542. 40);
  543. }
  544. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  545. }
  546. #define PHY_BUSY_LOOPS 5000
  547. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  548. {
  549. u32 frame_val;
  550. unsigned int loops;
  551. int ret;
  552. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  553. tw32_f(MAC_MI_MODE,
  554. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  555. udelay(80);
  556. }
  557. *val = 0x0;
  558. frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  559. MI_COM_PHY_ADDR_MASK);
  560. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  561. MI_COM_REG_ADDR_MASK);
  562. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  563. tw32_f(MAC_MI_COM, frame_val);
  564. loops = PHY_BUSY_LOOPS;
  565. while (loops != 0) {
  566. udelay(10);
  567. frame_val = tr32(MAC_MI_COM);
  568. if ((frame_val & MI_COM_BUSY) == 0) {
  569. udelay(5);
  570. frame_val = tr32(MAC_MI_COM);
  571. break;
  572. }
  573. loops -= 1;
  574. }
  575. ret = -EBUSY;
  576. if (loops != 0) {
  577. *val = frame_val & MI_COM_DATA_MASK;
  578. ret = 0;
  579. }
  580. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  581. tw32_f(MAC_MI_MODE, tp->mi_mode);
  582. udelay(80);
  583. }
  584. return ret;
  585. }
  586. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  587. {
  588. u32 frame_val;
  589. unsigned int loops;
  590. int ret;
  591. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
  592. (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
  593. return 0;
  594. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  595. tw32_f(MAC_MI_MODE,
  596. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  597. udelay(80);
  598. }
  599. frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  600. MI_COM_PHY_ADDR_MASK);
  601. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  602. MI_COM_REG_ADDR_MASK);
  603. frame_val |= (val & MI_COM_DATA_MASK);
  604. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  605. tw32_f(MAC_MI_COM, frame_val);
  606. loops = PHY_BUSY_LOOPS;
  607. while (loops != 0) {
  608. udelay(10);
  609. frame_val = tr32(MAC_MI_COM);
  610. if ((frame_val & MI_COM_BUSY) == 0) {
  611. udelay(5);
  612. frame_val = tr32(MAC_MI_COM);
  613. break;
  614. }
  615. loops -= 1;
  616. }
  617. ret = -EBUSY;
  618. if (loops != 0)
  619. ret = 0;
  620. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  621. tw32_f(MAC_MI_MODE, tp->mi_mode);
  622. udelay(80);
  623. }
  624. return ret;
  625. }
  626. static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
  627. {
  628. u32 phy;
  629. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  630. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  631. return;
  632. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  633. u32 ephy;
  634. if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
  635. tg3_writephy(tp, MII_TG3_EPHY_TEST,
  636. ephy | MII_TG3_EPHY_SHADOW_EN);
  637. if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
  638. if (enable)
  639. phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
  640. else
  641. phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
  642. tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
  643. }
  644. tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
  645. }
  646. } else {
  647. phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
  648. MII_TG3_AUXCTL_SHDWSEL_MISC;
  649. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
  650. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
  651. if (enable)
  652. phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  653. else
  654. phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  655. phy |= MII_TG3_AUXCTL_MISC_WREN;
  656. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  657. }
  658. }
  659. }
  660. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  661. {
  662. u32 val;
  663. if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
  664. return;
  665. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
  666. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
  667. tg3_writephy(tp, MII_TG3_AUX_CTRL,
  668. (val | (1 << 15) | (1 << 4)));
  669. }
  670. static int tg3_bmcr_reset(struct tg3 *tp)
  671. {
  672. u32 phy_control;
  673. int limit, err;
  674. /* OK, reset it, and poll the BMCR_RESET bit until it
  675. * clears or we time out.
  676. */
  677. phy_control = BMCR_RESET;
  678. err = tg3_writephy(tp, MII_BMCR, phy_control);
  679. if (err != 0)
  680. return -EBUSY;
  681. limit = 5000;
  682. while (limit--) {
  683. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  684. if (err != 0)
  685. return -EBUSY;
  686. if ((phy_control & BMCR_RESET) == 0) {
  687. udelay(40);
  688. break;
  689. }
  690. udelay(10);
  691. }
  692. if (limit <= 0)
  693. return -EBUSY;
  694. return 0;
  695. }
  696. static int tg3_wait_macro_done(struct tg3 *tp)
  697. {
  698. int limit = 100;
  699. while (limit--) {
  700. u32 tmp32;
  701. if (!tg3_readphy(tp, 0x16, &tmp32)) {
  702. if ((tmp32 & 0x1000) == 0)
  703. break;
  704. }
  705. }
  706. if (limit <= 0)
  707. return -EBUSY;
  708. return 0;
  709. }
  710. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  711. {
  712. static const u32 test_pat[4][6] = {
  713. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  714. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  715. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  716. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  717. };
  718. int chan;
  719. for (chan = 0; chan < 4; chan++) {
  720. int i;
  721. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  722. (chan * 0x2000) | 0x0200);
  723. tg3_writephy(tp, 0x16, 0x0002);
  724. for (i = 0; i < 6; i++)
  725. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  726. test_pat[chan][i]);
  727. tg3_writephy(tp, 0x16, 0x0202);
  728. if (tg3_wait_macro_done(tp)) {
  729. *resetp = 1;
  730. return -EBUSY;
  731. }
  732. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  733. (chan * 0x2000) | 0x0200);
  734. tg3_writephy(tp, 0x16, 0x0082);
  735. if (tg3_wait_macro_done(tp)) {
  736. *resetp = 1;
  737. return -EBUSY;
  738. }
  739. tg3_writephy(tp, 0x16, 0x0802);
  740. if (tg3_wait_macro_done(tp)) {
  741. *resetp = 1;
  742. return -EBUSY;
  743. }
  744. for (i = 0; i < 6; i += 2) {
  745. u32 low, high;
  746. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  747. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  748. tg3_wait_macro_done(tp)) {
  749. *resetp = 1;
  750. return -EBUSY;
  751. }
  752. low &= 0x7fff;
  753. high &= 0x000f;
  754. if (low != test_pat[chan][i] ||
  755. high != test_pat[chan][i+1]) {
  756. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  757. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  758. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  759. return -EBUSY;
  760. }
  761. }
  762. }
  763. return 0;
  764. }
  765. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  766. {
  767. int chan;
  768. for (chan = 0; chan < 4; chan++) {
  769. int i;
  770. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  771. (chan * 0x2000) | 0x0200);
  772. tg3_writephy(tp, 0x16, 0x0002);
  773. for (i = 0; i < 6; i++)
  774. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  775. tg3_writephy(tp, 0x16, 0x0202);
  776. if (tg3_wait_macro_done(tp))
  777. return -EBUSY;
  778. }
  779. return 0;
  780. }
  781. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  782. {
  783. u32 reg32, phy9_orig;
  784. int retries, do_phy_reset, err;
  785. retries = 10;
  786. do_phy_reset = 1;
  787. do {
  788. if (do_phy_reset) {
  789. err = tg3_bmcr_reset(tp);
  790. if (err)
  791. return err;
  792. do_phy_reset = 0;
  793. }
  794. /* Disable transmitter and interrupt. */
  795. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  796. continue;
  797. reg32 |= 0x3000;
  798. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  799. /* Set full-duplex, 1000 mbps. */
  800. tg3_writephy(tp, MII_BMCR,
  801. BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
  802. /* Set to master mode. */
  803. if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
  804. continue;
  805. tg3_writephy(tp, MII_TG3_CTRL,
  806. (MII_TG3_CTRL_AS_MASTER |
  807. MII_TG3_CTRL_ENABLE_AS_MASTER));
  808. /* Enable SM_DSP_CLOCK and 6dB. */
  809. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  810. /* Block the PHY control access. */
  811. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  812. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
  813. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  814. if (!err)
  815. break;
  816. } while (--retries);
  817. err = tg3_phy_reset_chanpat(tp);
  818. if (err)
  819. return err;
  820. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  821. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
  822. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  823. tg3_writephy(tp, 0x16, 0x0000);
  824. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  825. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  826. /* Set Extended packet length bit for jumbo frames */
  827. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
  828. }
  829. else {
  830. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  831. }
  832. tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
  833. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  834. reg32 &= ~0x3000;
  835. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  836. } else if (!err)
  837. err = -EBUSY;
  838. return err;
  839. }
  840. static void tg3_link_report(struct tg3 *);
  841. /* This will reset the tigon3 PHY if there is no valid
  842. * link unless the FORCE argument is non-zero.
  843. */
  844. static int tg3_phy_reset(struct tg3 *tp)
  845. {
  846. u32 phy_status;
  847. int err;
  848. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  849. u32 val;
  850. val = tr32(GRC_MISC_CFG);
  851. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  852. udelay(40);
  853. }
  854. err = tg3_readphy(tp, MII_BMSR, &phy_status);
  855. err |= tg3_readphy(tp, MII_BMSR, &phy_status);
  856. if (err != 0)
  857. return -EBUSY;
  858. if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
  859. netif_carrier_off(tp->dev);
  860. tg3_link_report(tp);
  861. }
  862. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  863. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  864. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  865. err = tg3_phy_reset_5703_4_5(tp);
  866. if (err)
  867. return err;
  868. goto out;
  869. }
  870. err = tg3_bmcr_reset(tp);
  871. if (err)
  872. return err;
  873. out:
  874. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
  875. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  876. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  877. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
  878. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  879. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
  880. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  881. }
  882. if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
  883. tg3_writephy(tp, 0x1c, 0x8d68);
  884. tg3_writephy(tp, 0x1c, 0x8d68);
  885. }
  886. if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
  887. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  888. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  889. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
  890. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  891. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
  892. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
  893. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
  894. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  895. }
  896. else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
  897. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  898. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  899. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
  900. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  901. tg3_writephy(tp, MII_TG3_TEST1,
  902. MII_TG3_TEST1_TRIM_EN | 0x4);
  903. } else
  904. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  905. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  906. }
  907. /* Set Extended packet length bit (bit 14) on all chips that */
  908. /* support jumbo frames */
  909. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  910. /* Cannot do read-modify-write on 5401 */
  911. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  912. } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
  913. u32 phy_reg;
  914. /* Set bit 14 with read-modify-write to preserve other bits */
  915. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
  916. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
  917. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
  918. }
  919. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  920. * jumbo frames transmission.
  921. */
  922. if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
  923. u32 phy_reg;
  924. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
  925. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  926. phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  927. }
  928. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  929. /* adjust output voltage */
  930. tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
  931. }
  932. tg3_phy_toggle_automdix(tp, 1);
  933. tg3_phy_set_wirespeed(tp);
  934. return 0;
  935. }
  936. static void tg3_frob_aux_power(struct tg3 *tp)
  937. {
  938. struct tg3 *tp_peer = tp;
  939. if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
  940. return;
  941. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  942. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  943. struct net_device *dev_peer;
  944. dev_peer = pci_get_drvdata(tp->pdev_peer);
  945. /* remove_one() may have been run on the peer. */
  946. if (!dev_peer)
  947. tp_peer = tp;
  948. else
  949. tp_peer = netdev_priv(dev_peer);
  950. }
  951. if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  952. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
  953. (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  954. (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  955. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  956. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  957. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  958. (GRC_LCLCTRL_GPIO_OE0 |
  959. GRC_LCLCTRL_GPIO_OE1 |
  960. GRC_LCLCTRL_GPIO_OE2 |
  961. GRC_LCLCTRL_GPIO_OUTPUT0 |
  962. GRC_LCLCTRL_GPIO_OUTPUT1),
  963. 100);
  964. } else {
  965. u32 no_gpio2;
  966. u32 grc_local_ctrl = 0;
  967. if (tp_peer != tp &&
  968. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  969. return;
  970. /* Workaround to prevent overdrawing Amps. */
  971. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  972. ASIC_REV_5714) {
  973. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  974. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  975. grc_local_ctrl, 100);
  976. }
  977. /* On 5753 and variants, GPIO2 cannot be used. */
  978. no_gpio2 = tp->nic_sram_data_cfg &
  979. NIC_SRAM_DATA_CFG_NO_GPIO2;
  980. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  981. GRC_LCLCTRL_GPIO_OE1 |
  982. GRC_LCLCTRL_GPIO_OE2 |
  983. GRC_LCLCTRL_GPIO_OUTPUT1 |
  984. GRC_LCLCTRL_GPIO_OUTPUT2;
  985. if (no_gpio2) {
  986. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  987. GRC_LCLCTRL_GPIO_OUTPUT2);
  988. }
  989. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  990. grc_local_ctrl, 100);
  991. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  992. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  993. grc_local_ctrl, 100);
  994. if (!no_gpio2) {
  995. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  996. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  997. grc_local_ctrl, 100);
  998. }
  999. }
  1000. } else {
  1001. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  1002. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  1003. if (tp_peer != tp &&
  1004. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  1005. return;
  1006. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1007. (GRC_LCLCTRL_GPIO_OE1 |
  1008. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1009. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1010. GRC_LCLCTRL_GPIO_OE1, 100);
  1011. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1012. (GRC_LCLCTRL_GPIO_OE1 |
  1013. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1014. }
  1015. }
  1016. }
  1017. static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
  1018. {
  1019. if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
  1020. return 1;
  1021. else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
  1022. if (speed != SPEED_10)
  1023. return 1;
  1024. } else if (speed == SPEED_10)
  1025. return 1;
  1026. return 0;
  1027. }
  1028. static int tg3_setup_phy(struct tg3 *, int);
  1029. #define RESET_KIND_SHUTDOWN 0
  1030. #define RESET_KIND_INIT 1
  1031. #define RESET_KIND_SUSPEND 2
  1032. static void tg3_write_sig_post_reset(struct tg3 *, int);
  1033. static int tg3_halt_cpu(struct tg3 *, u32);
  1034. static int tg3_nvram_lock(struct tg3 *);
  1035. static void tg3_nvram_unlock(struct tg3 *);
  1036. static void tg3_power_down_phy(struct tg3 *tp)
  1037. {
  1038. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  1039. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  1040. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  1041. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  1042. sg_dig_ctrl |=
  1043. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  1044. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  1045. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  1046. }
  1047. return;
  1048. }
  1049. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1050. u32 val;
  1051. tg3_bmcr_reset(tp);
  1052. val = tr32(GRC_MISC_CFG);
  1053. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  1054. udelay(40);
  1055. return;
  1056. } else {
  1057. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1058. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  1059. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
  1060. }
  1061. /* The PHY should not be powered down on some chips because
  1062. * of bugs.
  1063. */
  1064. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1065. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1066. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
  1067. (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
  1068. return;
  1069. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  1070. }
  1071. static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
  1072. {
  1073. u32 misc_host_ctrl;
  1074. u16 power_control, power_caps;
  1075. int pm = tp->pm_cap;
  1076. /* Make sure register accesses (indirect or otherwise)
  1077. * will function correctly.
  1078. */
  1079. pci_write_config_dword(tp->pdev,
  1080. TG3PCI_MISC_HOST_CTRL,
  1081. tp->misc_host_ctrl);
  1082. pci_read_config_word(tp->pdev,
  1083. pm + PCI_PM_CTRL,
  1084. &power_control);
  1085. power_control |= PCI_PM_CTRL_PME_STATUS;
  1086. power_control &= ~(PCI_PM_CTRL_STATE_MASK);
  1087. switch (state) {
  1088. case PCI_D0:
  1089. power_control |= 0;
  1090. pci_write_config_word(tp->pdev,
  1091. pm + PCI_PM_CTRL,
  1092. power_control);
  1093. udelay(100); /* Delay after power state change */
  1094. /* Switch out of Vaux if it is a NIC */
  1095. if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
  1096. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
  1097. return 0;
  1098. case PCI_D1:
  1099. power_control |= 1;
  1100. break;
  1101. case PCI_D2:
  1102. power_control |= 2;
  1103. break;
  1104. case PCI_D3hot:
  1105. power_control |= 3;
  1106. break;
  1107. default:
  1108. printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
  1109. "requested.\n",
  1110. tp->dev->name, state);
  1111. return -EINVAL;
  1112. };
  1113. power_control |= PCI_PM_CTRL_PME_ENABLE;
  1114. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  1115. tw32(TG3PCI_MISC_HOST_CTRL,
  1116. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  1117. if (tp->link_config.phy_is_low_power == 0) {
  1118. tp->link_config.phy_is_low_power = 1;
  1119. tp->link_config.orig_speed = tp->link_config.speed;
  1120. tp->link_config.orig_duplex = tp->link_config.duplex;
  1121. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  1122. }
  1123. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  1124. tp->link_config.speed = SPEED_10;
  1125. tp->link_config.duplex = DUPLEX_HALF;
  1126. tp->link_config.autoneg = AUTONEG_ENABLE;
  1127. tg3_setup_phy(tp, 0);
  1128. }
  1129. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1130. u32 val;
  1131. val = tr32(GRC_VCPU_EXT_CTRL);
  1132. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  1133. } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  1134. int i;
  1135. u32 val;
  1136. for (i = 0; i < 200; i++) {
  1137. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  1138. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  1139. break;
  1140. msleep(1);
  1141. }
  1142. }
  1143. if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
  1144. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  1145. WOL_DRV_STATE_SHUTDOWN |
  1146. WOL_DRV_WOL |
  1147. WOL_SET_MAGIC_PKT);
  1148. pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
  1149. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
  1150. u32 mac_mode;
  1151. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  1152. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
  1153. udelay(40);
  1154. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  1155. mac_mode = MAC_MODE_PORT_MODE_GMII;
  1156. else
  1157. mac_mode = MAC_MODE_PORT_MODE_MII;
  1158. mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
  1159. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  1160. ASIC_REV_5700) {
  1161. u32 speed = (tp->tg3_flags &
  1162. TG3_FLAG_WOL_SPEED_100MB) ?
  1163. SPEED_100 : SPEED_10;
  1164. if (tg3_5700_link_polarity(tp, speed))
  1165. mac_mode |= MAC_MODE_LINK_POLARITY;
  1166. else
  1167. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  1168. }
  1169. } else {
  1170. mac_mode = MAC_MODE_PORT_MODE_TBI;
  1171. }
  1172. if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  1173. tw32(MAC_LED_CTRL, tp->led_ctrl);
  1174. if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
  1175. (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
  1176. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  1177. tw32_f(MAC_MODE, mac_mode);
  1178. udelay(100);
  1179. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  1180. udelay(10);
  1181. }
  1182. if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
  1183. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1184. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  1185. u32 base_val;
  1186. base_val = tp->pci_clock_ctrl;
  1187. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  1188. CLOCK_CTRL_TXCLK_DISABLE);
  1189. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  1190. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  1191. } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  1192. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
  1193. /* do nothing */
  1194. } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  1195. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
  1196. u32 newbits1, newbits2;
  1197. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1198. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1199. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  1200. CLOCK_CTRL_TXCLK_DISABLE |
  1201. CLOCK_CTRL_ALTCLK);
  1202. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  1203. } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  1204. newbits1 = CLOCK_CTRL_625_CORE;
  1205. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  1206. } else {
  1207. newbits1 = CLOCK_CTRL_ALTCLK;
  1208. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  1209. }
  1210. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  1211. 40);
  1212. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  1213. 40);
  1214. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  1215. u32 newbits3;
  1216. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1217. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1218. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  1219. CLOCK_CTRL_TXCLK_DISABLE |
  1220. CLOCK_CTRL_44MHZ_CORE);
  1221. } else {
  1222. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  1223. }
  1224. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  1225. tp->pci_clock_ctrl | newbits3, 40);
  1226. }
  1227. }
  1228. if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
  1229. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  1230. tg3_power_down_phy(tp);
  1231. tg3_frob_aux_power(tp);
  1232. /* Workaround for unstable PLL clock */
  1233. if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  1234. (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  1235. u32 val = tr32(0x7d00);
  1236. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  1237. tw32(0x7d00, val);
  1238. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  1239. int err;
  1240. err = tg3_nvram_lock(tp);
  1241. tg3_halt_cpu(tp, RX_CPU_BASE);
  1242. if (!err)
  1243. tg3_nvram_unlock(tp);
  1244. }
  1245. }
  1246. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  1247. /* Finally, set the new power state. */
  1248. pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
  1249. udelay(100); /* Delay after power state change */
  1250. return 0;
  1251. }
  1252. static void tg3_link_report(struct tg3 *tp)
  1253. {
  1254. if (!netif_carrier_ok(tp->dev)) {
  1255. if (netif_msg_link(tp))
  1256. printk(KERN_INFO PFX "%s: Link is down.\n",
  1257. tp->dev->name);
  1258. } else if (netif_msg_link(tp)) {
  1259. printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
  1260. tp->dev->name,
  1261. (tp->link_config.active_speed == SPEED_1000 ?
  1262. 1000 :
  1263. (tp->link_config.active_speed == SPEED_100 ?
  1264. 100 : 10)),
  1265. (tp->link_config.active_duplex == DUPLEX_FULL ?
  1266. "full" : "half"));
  1267. printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
  1268. "%s for RX.\n",
  1269. tp->dev->name,
  1270. (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
  1271. (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
  1272. }
  1273. }
  1274. static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
  1275. {
  1276. u32 new_tg3_flags = 0;
  1277. u32 old_rx_mode = tp->rx_mode;
  1278. u32 old_tx_mode = tp->tx_mode;
  1279. if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
  1280. /* Convert 1000BaseX flow control bits to 1000BaseT
  1281. * bits before resolving flow control.
  1282. */
  1283. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  1284. local_adv &= ~(ADVERTISE_PAUSE_CAP |
  1285. ADVERTISE_PAUSE_ASYM);
  1286. remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
  1287. if (local_adv & ADVERTISE_1000XPAUSE)
  1288. local_adv |= ADVERTISE_PAUSE_CAP;
  1289. if (local_adv & ADVERTISE_1000XPSE_ASYM)
  1290. local_adv |= ADVERTISE_PAUSE_ASYM;
  1291. if (remote_adv & LPA_1000XPAUSE)
  1292. remote_adv |= LPA_PAUSE_CAP;
  1293. if (remote_adv & LPA_1000XPAUSE_ASYM)
  1294. remote_adv |= LPA_PAUSE_ASYM;
  1295. }
  1296. if (local_adv & ADVERTISE_PAUSE_CAP) {
  1297. if (local_adv & ADVERTISE_PAUSE_ASYM) {
  1298. if (remote_adv & LPA_PAUSE_CAP)
  1299. new_tg3_flags |=
  1300. (TG3_FLAG_RX_PAUSE |
  1301. TG3_FLAG_TX_PAUSE);
  1302. else if (remote_adv & LPA_PAUSE_ASYM)
  1303. new_tg3_flags |=
  1304. (TG3_FLAG_RX_PAUSE);
  1305. } else {
  1306. if (remote_adv & LPA_PAUSE_CAP)
  1307. new_tg3_flags |=
  1308. (TG3_FLAG_RX_PAUSE |
  1309. TG3_FLAG_TX_PAUSE);
  1310. }
  1311. } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
  1312. if ((remote_adv & LPA_PAUSE_CAP) &&
  1313. (remote_adv & LPA_PAUSE_ASYM))
  1314. new_tg3_flags |= TG3_FLAG_TX_PAUSE;
  1315. }
  1316. tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
  1317. tp->tg3_flags |= new_tg3_flags;
  1318. } else {
  1319. new_tg3_flags = tp->tg3_flags;
  1320. }
  1321. if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
  1322. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1323. else
  1324. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1325. if (old_rx_mode != tp->rx_mode) {
  1326. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1327. }
  1328. if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
  1329. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1330. else
  1331. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1332. if (old_tx_mode != tp->tx_mode) {
  1333. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1334. }
  1335. }
  1336. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  1337. {
  1338. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  1339. case MII_TG3_AUX_STAT_10HALF:
  1340. *speed = SPEED_10;
  1341. *duplex = DUPLEX_HALF;
  1342. break;
  1343. case MII_TG3_AUX_STAT_10FULL:
  1344. *speed = SPEED_10;
  1345. *duplex = DUPLEX_FULL;
  1346. break;
  1347. case MII_TG3_AUX_STAT_100HALF:
  1348. *speed = SPEED_100;
  1349. *duplex = DUPLEX_HALF;
  1350. break;
  1351. case MII_TG3_AUX_STAT_100FULL:
  1352. *speed = SPEED_100;
  1353. *duplex = DUPLEX_FULL;
  1354. break;
  1355. case MII_TG3_AUX_STAT_1000HALF:
  1356. *speed = SPEED_1000;
  1357. *duplex = DUPLEX_HALF;
  1358. break;
  1359. case MII_TG3_AUX_STAT_1000FULL:
  1360. *speed = SPEED_1000;
  1361. *duplex = DUPLEX_FULL;
  1362. break;
  1363. default:
  1364. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1365. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  1366. SPEED_10;
  1367. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  1368. DUPLEX_HALF;
  1369. break;
  1370. }
  1371. *speed = SPEED_INVALID;
  1372. *duplex = DUPLEX_INVALID;
  1373. break;
  1374. };
  1375. }
  1376. static void tg3_phy_copper_begin(struct tg3 *tp)
  1377. {
  1378. u32 new_adv;
  1379. int i;
  1380. if (tp->link_config.phy_is_low_power) {
  1381. /* Entering low power mode. Disable gigabit and
  1382. * 100baseT advertisements.
  1383. */
  1384. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1385. new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  1386. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  1387. if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
  1388. new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
  1389. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1390. } else if (tp->link_config.speed == SPEED_INVALID) {
  1391. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  1392. tp->link_config.advertising &=
  1393. ~(ADVERTISED_1000baseT_Half |
  1394. ADVERTISED_1000baseT_Full);
  1395. new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  1396. if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
  1397. new_adv |= ADVERTISE_10HALF;
  1398. if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
  1399. new_adv |= ADVERTISE_10FULL;
  1400. if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
  1401. new_adv |= ADVERTISE_100HALF;
  1402. if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
  1403. new_adv |= ADVERTISE_100FULL;
  1404. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1405. if (tp->link_config.advertising &
  1406. (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
  1407. new_adv = 0;
  1408. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  1409. new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
  1410. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  1411. new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
  1412. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
  1413. (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1414. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
  1415. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  1416. MII_TG3_CTRL_ENABLE_AS_MASTER);
  1417. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  1418. } else {
  1419. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1420. }
  1421. } else {
  1422. /* Asking for a specific link mode. */
  1423. if (tp->link_config.speed == SPEED_1000) {
  1424. new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
  1425. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1426. if (tp->link_config.duplex == DUPLEX_FULL)
  1427. new_adv = MII_TG3_CTRL_ADV_1000_FULL;
  1428. else
  1429. new_adv = MII_TG3_CTRL_ADV_1000_HALF;
  1430. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1431. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  1432. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  1433. MII_TG3_CTRL_ENABLE_AS_MASTER);
  1434. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  1435. } else {
  1436. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1437. new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
  1438. if (tp->link_config.speed == SPEED_100) {
  1439. if (tp->link_config.duplex == DUPLEX_FULL)
  1440. new_adv |= ADVERTISE_100FULL;
  1441. else
  1442. new_adv |= ADVERTISE_100HALF;
  1443. } else {
  1444. if (tp->link_config.duplex == DUPLEX_FULL)
  1445. new_adv |= ADVERTISE_10FULL;
  1446. else
  1447. new_adv |= ADVERTISE_10HALF;
  1448. }
  1449. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1450. }
  1451. }
  1452. if (tp->link_config.autoneg == AUTONEG_DISABLE &&
  1453. tp->link_config.speed != SPEED_INVALID) {
  1454. u32 bmcr, orig_bmcr;
  1455. tp->link_config.active_speed = tp->link_config.speed;
  1456. tp->link_config.active_duplex = tp->link_config.duplex;
  1457. bmcr = 0;
  1458. switch (tp->link_config.speed) {
  1459. default:
  1460. case SPEED_10:
  1461. break;
  1462. case SPEED_100:
  1463. bmcr |= BMCR_SPEED100;
  1464. break;
  1465. case SPEED_1000:
  1466. bmcr |= TG3_BMCR_SPEED1000;
  1467. break;
  1468. };
  1469. if (tp->link_config.duplex == DUPLEX_FULL)
  1470. bmcr |= BMCR_FULLDPLX;
  1471. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  1472. (bmcr != orig_bmcr)) {
  1473. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  1474. for (i = 0; i < 1500; i++) {
  1475. u32 tmp;
  1476. udelay(10);
  1477. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  1478. tg3_readphy(tp, MII_BMSR, &tmp))
  1479. continue;
  1480. if (!(tmp & BMSR_LSTATUS)) {
  1481. udelay(40);
  1482. break;
  1483. }
  1484. }
  1485. tg3_writephy(tp, MII_BMCR, bmcr);
  1486. udelay(40);
  1487. }
  1488. } else {
  1489. tg3_writephy(tp, MII_BMCR,
  1490. BMCR_ANENABLE | BMCR_ANRESTART);
  1491. }
  1492. }
  1493. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  1494. {
  1495. int err;
  1496. /* Turn off tap power management. */
  1497. /* Set Extended packet length bit */
  1498. err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  1499. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
  1500. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
  1501. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
  1502. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
  1503. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  1504. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
  1505. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  1506. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
  1507. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  1508. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
  1509. udelay(40);
  1510. return err;
  1511. }
  1512. static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
  1513. {
  1514. u32 adv_reg, all_mask = 0;
  1515. if (mask & ADVERTISED_10baseT_Half)
  1516. all_mask |= ADVERTISE_10HALF;
  1517. if (mask & ADVERTISED_10baseT_Full)
  1518. all_mask |= ADVERTISE_10FULL;
  1519. if (mask & ADVERTISED_100baseT_Half)
  1520. all_mask |= ADVERTISE_100HALF;
  1521. if (mask & ADVERTISED_100baseT_Full)
  1522. all_mask |= ADVERTISE_100FULL;
  1523. if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
  1524. return 0;
  1525. if ((adv_reg & all_mask) != all_mask)
  1526. return 0;
  1527. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  1528. u32 tg3_ctrl;
  1529. all_mask = 0;
  1530. if (mask & ADVERTISED_1000baseT_Half)
  1531. all_mask |= ADVERTISE_1000HALF;
  1532. if (mask & ADVERTISED_1000baseT_Full)
  1533. all_mask |= ADVERTISE_1000FULL;
  1534. if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
  1535. return 0;
  1536. if ((tg3_ctrl & all_mask) != all_mask)
  1537. return 0;
  1538. }
  1539. return 1;
  1540. }
  1541. static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
  1542. {
  1543. int current_link_up;
  1544. u32 bmsr, dummy;
  1545. u16 current_speed;
  1546. u8 current_duplex;
  1547. int i, err;
  1548. tw32(MAC_EVENT, 0);
  1549. tw32_f(MAC_STATUS,
  1550. (MAC_STATUS_SYNC_CHANGED |
  1551. MAC_STATUS_CFG_CHANGED |
  1552. MAC_STATUS_MI_COMPLETION |
  1553. MAC_STATUS_LNKSTATE_CHANGED));
  1554. udelay(40);
  1555. tp->mi_mode = MAC_MI_MODE_BASE;
  1556. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1557. udelay(80);
  1558. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
  1559. /* Some third-party PHYs need to be reset on link going
  1560. * down.
  1561. */
  1562. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1563. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1564. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  1565. netif_carrier_ok(tp->dev)) {
  1566. tg3_readphy(tp, MII_BMSR, &bmsr);
  1567. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1568. !(bmsr & BMSR_LSTATUS))
  1569. force_reset = 1;
  1570. }
  1571. if (force_reset)
  1572. tg3_phy_reset(tp);
  1573. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  1574. tg3_readphy(tp, MII_BMSR, &bmsr);
  1575. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  1576. !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
  1577. bmsr = 0;
  1578. if (!(bmsr & BMSR_LSTATUS)) {
  1579. err = tg3_init_5401phy_dsp(tp);
  1580. if (err)
  1581. return err;
  1582. tg3_readphy(tp, MII_BMSR, &bmsr);
  1583. for (i = 0; i < 1000; i++) {
  1584. udelay(10);
  1585. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1586. (bmsr & BMSR_LSTATUS)) {
  1587. udelay(40);
  1588. break;
  1589. }
  1590. }
  1591. if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
  1592. !(bmsr & BMSR_LSTATUS) &&
  1593. tp->link_config.active_speed == SPEED_1000) {
  1594. err = tg3_phy_reset(tp);
  1595. if (!err)
  1596. err = tg3_init_5401phy_dsp(tp);
  1597. if (err)
  1598. return err;
  1599. }
  1600. }
  1601. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1602. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
  1603. /* 5701 {A0,B0} CRC bug workaround */
  1604. tg3_writephy(tp, 0x15, 0x0a75);
  1605. tg3_writephy(tp, 0x1c, 0x8c68);
  1606. tg3_writephy(tp, 0x1c, 0x8d68);
  1607. tg3_writephy(tp, 0x1c, 0x8c68);
  1608. }
  1609. /* Clear pending interrupts... */
  1610. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  1611. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  1612. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
  1613. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  1614. else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  1615. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  1616. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1617. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1618. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  1619. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1620. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  1621. else
  1622. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  1623. }
  1624. current_link_up = 0;
  1625. current_speed = SPEED_INVALID;
  1626. current_duplex = DUPLEX_INVALID;
  1627. if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
  1628. u32 val;
  1629. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
  1630. tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
  1631. if (!(val & (1 << 10))) {
  1632. val |= (1 << 10);
  1633. tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
  1634. goto relink;
  1635. }
  1636. }
  1637. bmsr = 0;
  1638. for (i = 0; i < 100; i++) {
  1639. tg3_readphy(tp, MII_BMSR, &bmsr);
  1640. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1641. (bmsr & BMSR_LSTATUS))
  1642. break;
  1643. udelay(40);
  1644. }
  1645. if (bmsr & BMSR_LSTATUS) {
  1646. u32 aux_stat, bmcr;
  1647. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  1648. for (i = 0; i < 2000; i++) {
  1649. udelay(10);
  1650. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  1651. aux_stat)
  1652. break;
  1653. }
  1654. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  1655. &current_speed,
  1656. &current_duplex);
  1657. bmcr = 0;
  1658. for (i = 0; i < 200; i++) {
  1659. tg3_readphy(tp, MII_BMCR, &bmcr);
  1660. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  1661. continue;
  1662. if (bmcr && bmcr != 0x7fff)
  1663. break;
  1664. udelay(10);
  1665. }
  1666. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  1667. if (bmcr & BMCR_ANENABLE) {
  1668. current_link_up = 1;
  1669. /* Force autoneg restart if we are exiting
  1670. * low power mode.
  1671. */
  1672. if (!tg3_copper_is_advertising_all(tp,
  1673. tp->link_config.advertising))
  1674. current_link_up = 0;
  1675. } else {
  1676. current_link_up = 0;
  1677. }
  1678. } else {
  1679. if (!(bmcr & BMCR_ANENABLE) &&
  1680. tp->link_config.speed == current_speed &&
  1681. tp->link_config.duplex == current_duplex) {
  1682. current_link_up = 1;
  1683. } else {
  1684. current_link_up = 0;
  1685. }
  1686. }
  1687. tp->link_config.active_speed = current_speed;
  1688. tp->link_config.active_duplex = current_duplex;
  1689. }
  1690. if (current_link_up == 1 &&
  1691. (tp->link_config.active_duplex == DUPLEX_FULL) &&
  1692. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  1693. u32 local_adv, remote_adv;
  1694. if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
  1695. local_adv = 0;
  1696. local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  1697. if (tg3_readphy(tp, MII_LPA, &remote_adv))
  1698. remote_adv = 0;
  1699. remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
  1700. /* If we are not advertising full pause capability,
  1701. * something is wrong. Bring the link down and reconfigure.
  1702. */
  1703. if (local_adv != ADVERTISE_PAUSE_CAP) {
  1704. current_link_up = 0;
  1705. } else {
  1706. tg3_setup_flow_control(tp, local_adv, remote_adv);
  1707. }
  1708. }
  1709. relink:
  1710. if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
  1711. u32 tmp;
  1712. tg3_phy_copper_begin(tp);
  1713. tg3_readphy(tp, MII_BMSR, &tmp);
  1714. if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
  1715. (tmp & BMSR_LSTATUS))
  1716. current_link_up = 1;
  1717. }
  1718. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  1719. if (current_link_up == 1) {
  1720. if (tp->link_config.active_speed == SPEED_100 ||
  1721. tp->link_config.active_speed == SPEED_10)
  1722. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  1723. else
  1724. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1725. } else
  1726. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1727. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  1728. if (tp->link_config.active_duplex == DUPLEX_HALF)
  1729. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  1730. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  1731. if (current_link_up == 1 &&
  1732. tg3_5700_link_polarity(tp, tp->link_config.active_speed))
  1733. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  1734. else
  1735. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  1736. }
  1737. /* ??? Without this setting Netgear GA302T PHY does not
  1738. * ??? send/receive packets...
  1739. */
  1740. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
  1741. tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
  1742. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  1743. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1744. udelay(80);
  1745. }
  1746. tw32_f(MAC_MODE, tp->mac_mode);
  1747. udelay(40);
  1748. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  1749. /* Polled via timer. */
  1750. tw32_f(MAC_EVENT, 0);
  1751. } else {
  1752. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  1753. }
  1754. udelay(40);
  1755. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
  1756. current_link_up == 1 &&
  1757. tp->link_config.active_speed == SPEED_1000 &&
  1758. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
  1759. (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
  1760. udelay(120);
  1761. tw32_f(MAC_STATUS,
  1762. (MAC_STATUS_SYNC_CHANGED |
  1763. MAC_STATUS_CFG_CHANGED));
  1764. udelay(40);
  1765. tg3_write_mem(tp,
  1766. NIC_SRAM_FIRMWARE_MBOX,
  1767. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  1768. }
  1769. if (current_link_up != netif_carrier_ok(tp->dev)) {
  1770. if (current_link_up)
  1771. netif_carrier_on(tp->dev);
  1772. else
  1773. netif_carrier_off(tp->dev);
  1774. tg3_link_report(tp);
  1775. }
  1776. return 0;
  1777. }
  1778. struct tg3_fiber_aneginfo {
  1779. int state;
  1780. #define ANEG_STATE_UNKNOWN 0
  1781. #define ANEG_STATE_AN_ENABLE 1
  1782. #define ANEG_STATE_RESTART_INIT 2
  1783. #define ANEG_STATE_RESTART 3
  1784. #define ANEG_STATE_DISABLE_LINK_OK 4
  1785. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  1786. #define ANEG_STATE_ABILITY_DETECT 6
  1787. #define ANEG_STATE_ACK_DETECT_INIT 7
  1788. #define ANEG_STATE_ACK_DETECT 8
  1789. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  1790. #define ANEG_STATE_COMPLETE_ACK 10
  1791. #define ANEG_STATE_IDLE_DETECT_INIT 11
  1792. #define ANEG_STATE_IDLE_DETECT 12
  1793. #define ANEG_STATE_LINK_OK 13
  1794. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  1795. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  1796. u32 flags;
  1797. #define MR_AN_ENABLE 0x00000001
  1798. #define MR_RESTART_AN 0x00000002
  1799. #define MR_AN_COMPLETE 0x00000004
  1800. #define MR_PAGE_RX 0x00000008
  1801. #define MR_NP_LOADED 0x00000010
  1802. #define MR_TOGGLE_TX 0x00000020
  1803. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  1804. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  1805. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  1806. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  1807. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  1808. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  1809. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  1810. #define MR_TOGGLE_RX 0x00002000
  1811. #define MR_NP_RX 0x00004000
  1812. #define MR_LINK_OK 0x80000000
  1813. unsigned long link_time, cur_time;
  1814. u32 ability_match_cfg;
  1815. int ability_match_count;
  1816. char ability_match, idle_match, ack_match;
  1817. u32 txconfig, rxconfig;
  1818. #define ANEG_CFG_NP 0x00000080
  1819. #define ANEG_CFG_ACK 0x00000040
  1820. #define ANEG_CFG_RF2 0x00000020
  1821. #define ANEG_CFG_RF1 0x00000010
  1822. #define ANEG_CFG_PS2 0x00000001
  1823. #define ANEG_CFG_PS1 0x00008000
  1824. #define ANEG_CFG_HD 0x00004000
  1825. #define ANEG_CFG_FD 0x00002000
  1826. #define ANEG_CFG_INVAL 0x00001f06
  1827. };
  1828. #define ANEG_OK 0
  1829. #define ANEG_DONE 1
  1830. #define ANEG_TIMER_ENAB 2
  1831. #define ANEG_FAILED -1
  1832. #define ANEG_STATE_SETTLE_TIME 10000
  1833. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  1834. struct tg3_fiber_aneginfo *ap)
  1835. {
  1836. unsigned long delta;
  1837. u32 rx_cfg_reg;
  1838. int ret;
  1839. if (ap->state == ANEG_STATE_UNKNOWN) {
  1840. ap->rxconfig = 0;
  1841. ap->link_time = 0;
  1842. ap->cur_time = 0;
  1843. ap->ability_match_cfg = 0;
  1844. ap->ability_match_count = 0;
  1845. ap->ability_match = 0;
  1846. ap->idle_match = 0;
  1847. ap->ack_match = 0;
  1848. }
  1849. ap->cur_time++;
  1850. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  1851. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  1852. if (rx_cfg_reg != ap->ability_match_cfg) {
  1853. ap->ability_match_cfg = rx_cfg_reg;
  1854. ap->ability_match = 0;
  1855. ap->ability_match_count = 0;
  1856. } else {
  1857. if (++ap->ability_match_count > 1) {
  1858. ap->ability_match = 1;
  1859. ap->ability_match_cfg = rx_cfg_reg;
  1860. }
  1861. }
  1862. if (rx_cfg_reg & ANEG_CFG_ACK)
  1863. ap->ack_match = 1;
  1864. else
  1865. ap->ack_match = 0;
  1866. ap->idle_match = 0;
  1867. } else {
  1868. ap->idle_match = 1;
  1869. ap->ability_match_cfg = 0;
  1870. ap->ability_match_count = 0;
  1871. ap->ability_match = 0;
  1872. ap->ack_match = 0;
  1873. rx_cfg_reg = 0;
  1874. }
  1875. ap->rxconfig = rx_cfg_reg;
  1876. ret = ANEG_OK;
  1877. switch(ap->state) {
  1878. case ANEG_STATE_UNKNOWN:
  1879. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  1880. ap->state = ANEG_STATE_AN_ENABLE;
  1881. /* fallthru */
  1882. case ANEG_STATE_AN_ENABLE:
  1883. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  1884. if (ap->flags & MR_AN_ENABLE) {
  1885. ap->link_time = 0;
  1886. ap->cur_time = 0;
  1887. ap->ability_match_cfg = 0;
  1888. ap->ability_match_count = 0;
  1889. ap->ability_match = 0;
  1890. ap->idle_match = 0;
  1891. ap->ack_match = 0;
  1892. ap->state = ANEG_STATE_RESTART_INIT;
  1893. } else {
  1894. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  1895. }
  1896. break;
  1897. case ANEG_STATE_RESTART_INIT:
  1898. ap->link_time = ap->cur_time;
  1899. ap->flags &= ~(MR_NP_LOADED);
  1900. ap->txconfig = 0;
  1901. tw32(MAC_TX_AUTO_NEG, 0);
  1902. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  1903. tw32_f(MAC_MODE, tp->mac_mode);
  1904. udelay(40);
  1905. ret = ANEG_TIMER_ENAB;
  1906. ap->state = ANEG_STATE_RESTART;
  1907. /* fallthru */
  1908. case ANEG_STATE_RESTART:
  1909. delta = ap->cur_time - ap->link_time;
  1910. if (delta > ANEG_STATE_SETTLE_TIME) {
  1911. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  1912. } else {
  1913. ret = ANEG_TIMER_ENAB;
  1914. }
  1915. break;
  1916. case ANEG_STATE_DISABLE_LINK_OK:
  1917. ret = ANEG_DONE;
  1918. break;
  1919. case ANEG_STATE_ABILITY_DETECT_INIT:
  1920. ap->flags &= ~(MR_TOGGLE_TX);
  1921. ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
  1922. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  1923. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  1924. tw32_f(MAC_MODE, tp->mac_mode);
  1925. udelay(40);
  1926. ap->state = ANEG_STATE_ABILITY_DETECT;
  1927. break;
  1928. case ANEG_STATE_ABILITY_DETECT:
  1929. if (ap->ability_match != 0 && ap->rxconfig != 0) {
  1930. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  1931. }
  1932. break;
  1933. case ANEG_STATE_ACK_DETECT_INIT:
  1934. ap->txconfig |= ANEG_CFG_ACK;
  1935. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  1936. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  1937. tw32_f(MAC_MODE, tp->mac_mode);
  1938. udelay(40);
  1939. ap->state = ANEG_STATE_ACK_DETECT;
  1940. /* fallthru */
  1941. case ANEG_STATE_ACK_DETECT:
  1942. if (ap->ack_match != 0) {
  1943. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  1944. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  1945. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  1946. } else {
  1947. ap->state = ANEG_STATE_AN_ENABLE;
  1948. }
  1949. } else if (ap->ability_match != 0 &&
  1950. ap->rxconfig == 0) {
  1951. ap->state = ANEG_STATE_AN_ENABLE;
  1952. }
  1953. break;
  1954. case ANEG_STATE_COMPLETE_ACK_INIT:
  1955. if (ap->rxconfig & ANEG_CFG_INVAL) {
  1956. ret = ANEG_FAILED;
  1957. break;
  1958. }
  1959. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  1960. MR_LP_ADV_HALF_DUPLEX |
  1961. MR_LP_ADV_SYM_PAUSE |
  1962. MR_LP_ADV_ASYM_PAUSE |
  1963. MR_LP_ADV_REMOTE_FAULT1 |
  1964. MR_LP_ADV_REMOTE_FAULT2 |
  1965. MR_LP_ADV_NEXT_PAGE |
  1966. MR_TOGGLE_RX |
  1967. MR_NP_RX);
  1968. if (ap->rxconfig & ANEG_CFG_FD)
  1969. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  1970. if (ap->rxconfig & ANEG_CFG_HD)
  1971. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  1972. if (ap->rxconfig & ANEG_CFG_PS1)
  1973. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  1974. if (ap->rxconfig & ANEG_CFG_PS2)
  1975. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  1976. if (ap->rxconfig & ANEG_CFG_RF1)
  1977. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  1978. if (ap->rxconfig & ANEG_CFG_RF2)
  1979. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  1980. if (ap->rxconfig & ANEG_CFG_NP)
  1981. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  1982. ap->link_time = ap->cur_time;
  1983. ap->flags ^= (MR_TOGGLE_TX);
  1984. if (ap->rxconfig & 0x0008)
  1985. ap->flags |= MR_TOGGLE_RX;
  1986. if (ap->rxconfig & ANEG_CFG_NP)
  1987. ap->flags |= MR_NP_RX;
  1988. ap->flags |= MR_PAGE_RX;
  1989. ap->state = ANEG_STATE_COMPLETE_ACK;
  1990. ret = ANEG_TIMER_ENAB;
  1991. break;
  1992. case ANEG_STATE_COMPLETE_ACK:
  1993. if (ap->ability_match != 0 &&
  1994. ap->rxconfig == 0) {
  1995. ap->state = ANEG_STATE_AN_ENABLE;
  1996. break;
  1997. }
  1998. delta = ap->cur_time - ap->link_time;
  1999. if (delta > ANEG_STATE_SETTLE_TIME) {
  2000. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  2001. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2002. } else {
  2003. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  2004. !(ap->flags & MR_NP_RX)) {
  2005. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2006. } else {
  2007. ret = ANEG_FAILED;
  2008. }
  2009. }
  2010. }
  2011. break;
  2012. case ANEG_STATE_IDLE_DETECT_INIT:
  2013. ap->link_time = ap->cur_time;
  2014. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2015. tw32_f(MAC_MODE, tp->mac_mode);
  2016. udelay(40);
  2017. ap->state = ANEG_STATE_IDLE_DETECT;
  2018. ret = ANEG_TIMER_ENAB;
  2019. break;
  2020. case ANEG_STATE_IDLE_DETECT:
  2021. if (ap->ability_match != 0 &&
  2022. ap->rxconfig == 0) {
  2023. ap->state = ANEG_STATE_AN_ENABLE;
  2024. break;
  2025. }
  2026. delta = ap->cur_time - ap->link_time;
  2027. if (delta > ANEG_STATE_SETTLE_TIME) {
  2028. /* XXX another gem from the Broadcom driver :( */
  2029. ap->state = ANEG_STATE_LINK_OK;
  2030. }
  2031. break;
  2032. case ANEG_STATE_LINK_OK:
  2033. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  2034. ret = ANEG_DONE;
  2035. break;
  2036. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  2037. /* ??? unimplemented */
  2038. break;
  2039. case ANEG_STATE_NEXT_PAGE_WAIT:
  2040. /* ??? unimplemented */
  2041. break;
  2042. default:
  2043. ret = ANEG_FAILED;
  2044. break;
  2045. };
  2046. return ret;
  2047. }
  2048. static int fiber_autoneg(struct tg3 *tp, u32 *flags)
  2049. {
  2050. int res = 0;
  2051. struct tg3_fiber_aneginfo aninfo;
  2052. int status = ANEG_FAILED;
  2053. unsigned int tick;
  2054. u32 tmp;
  2055. tw32_f(MAC_TX_AUTO_NEG, 0);
  2056. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  2057. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  2058. udelay(40);
  2059. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  2060. udelay(40);
  2061. memset(&aninfo, 0, sizeof(aninfo));
  2062. aninfo.flags |= MR_AN_ENABLE;
  2063. aninfo.state = ANEG_STATE_UNKNOWN;
  2064. aninfo.cur_time = 0;
  2065. tick = 0;
  2066. while (++tick < 195000) {
  2067. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  2068. if (status == ANEG_DONE || status == ANEG_FAILED)
  2069. break;
  2070. udelay(1);
  2071. }
  2072. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2073. tw32_f(MAC_MODE, tp->mac_mode);
  2074. udelay(40);
  2075. *flags = aninfo.flags;
  2076. if (status == ANEG_DONE &&
  2077. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  2078. MR_LP_ADV_FULL_DUPLEX)))
  2079. res = 1;
  2080. return res;
  2081. }
  2082. static void tg3_init_bcm8002(struct tg3 *tp)
  2083. {
  2084. u32 mac_status = tr32(MAC_STATUS);
  2085. int i;
  2086. /* Reset when initting first time or we have a link. */
  2087. if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
  2088. !(mac_status & MAC_STATUS_PCS_SYNCED))
  2089. return;
  2090. /* Set PLL lock range. */
  2091. tg3_writephy(tp, 0x16, 0x8007);
  2092. /* SW reset */
  2093. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  2094. /* Wait for reset to complete. */
  2095. /* XXX schedule_timeout() ... */
  2096. for (i = 0; i < 500; i++)
  2097. udelay(10);
  2098. /* Config mode; select PMA/Ch 1 regs. */
  2099. tg3_writephy(tp, 0x10, 0x8411);
  2100. /* Enable auto-lock and comdet, select txclk for tx. */
  2101. tg3_writephy(tp, 0x11, 0x0a10);
  2102. tg3_writephy(tp, 0x18, 0x00a0);
  2103. tg3_writephy(tp, 0x16, 0x41ff);
  2104. /* Assert and deassert POR. */
  2105. tg3_writephy(tp, 0x13, 0x0400);
  2106. udelay(40);
  2107. tg3_writephy(tp, 0x13, 0x0000);
  2108. tg3_writephy(tp, 0x11, 0x0a50);
  2109. udelay(40);
  2110. tg3_writephy(tp, 0x11, 0x0a10);
  2111. /* Wait for signal to stabilize */
  2112. /* XXX schedule_timeout() ... */
  2113. for (i = 0; i < 15000; i++)
  2114. udelay(10);
  2115. /* Deselect the channel register so we can read the PHYID
  2116. * later.
  2117. */
  2118. tg3_writephy(tp, 0x10, 0x8011);
  2119. }
  2120. static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  2121. {
  2122. u32 sg_dig_ctrl, sg_dig_status;
  2123. u32 serdes_cfg, expected_sg_dig_ctrl;
  2124. int workaround, port_a;
  2125. int current_link_up;
  2126. serdes_cfg = 0;
  2127. expected_sg_dig_ctrl = 0;
  2128. workaround = 0;
  2129. port_a = 1;
  2130. current_link_up = 0;
  2131. if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
  2132. tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
  2133. workaround = 1;
  2134. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  2135. port_a = 0;
  2136. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  2137. /* preserve bits 20-23 for voltage regulator */
  2138. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  2139. }
  2140. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  2141. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  2142. if (sg_dig_ctrl & (1 << 31)) {
  2143. if (workaround) {
  2144. u32 val = serdes_cfg;
  2145. if (port_a)
  2146. val |= 0xc010000;
  2147. else
  2148. val |= 0x4010000;
  2149. tw32_f(MAC_SERDES_CFG, val);
  2150. }
  2151. tw32_f(SG_DIG_CTRL, 0x01388400);
  2152. }
  2153. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  2154. tg3_setup_flow_control(tp, 0, 0);
  2155. current_link_up = 1;
  2156. }
  2157. goto out;
  2158. }
  2159. /* Want auto-negotiation. */
  2160. expected_sg_dig_ctrl = 0x81388400;
  2161. /* Pause capability */
  2162. expected_sg_dig_ctrl |= (1 << 11);
  2163. /* Asymettric pause */
  2164. expected_sg_dig_ctrl |= (1 << 12);
  2165. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  2166. if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
  2167. tp->serdes_counter &&
  2168. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  2169. MAC_STATUS_RCVD_CFG)) ==
  2170. MAC_STATUS_PCS_SYNCED)) {
  2171. tp->serdes_counter--;
  2172. current_link_up = 1;
  2173. goto out;
  2174. }
  2175. restart_autoneg:
  2176. if (workaround)
  2177. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  2178. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
  2179. udelay(5);
  2180. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  2181. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  2182. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2183. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  2184. MAC_STATUS_SIGNAL_DET)) {
  2185. sg_dig_status = tr32(SG_DIG_STATUS);
  2186. mac_status = tr32(MAC_STATUS);
  2187. if ((sg_dig_status & (1 << 1)) &&
  2188. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  2189. u32 local_adv, remote_adv;
  2190. local_adv = ADVERTISE_PAUSE_CAP;
  2191. remote_adv = 0;
  2192. if (sg_dig_status & (1 << 19))
  2193. remote_adv |= LPA_PAUSE_CAP;
  2194. if (sg_dig_status & (1 << 20))
  2195. remote_adv |= LPA_PAUSE_ASYM;
  2196. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2197. current_link_up = 1;
  2198. tp->serdes_counter = 0;
  2199. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2200. } else if (!(sg_dig_status & (1 << 1))) {
  2201. if (tp->serdes_counter)
  2202. tp->serdes_counter--;
  2203. else {
  2204. if (workaround) {
  2205. u32 val = serdes_cfg;
  2206. if (port_a)
  2207. val |= 0xc010000;
  2208. else
  2209. val |= 0x4010000;
  2210. tw32_f(MAC_SERDES_CFG, val);
  2211. }
  2212. tw32_f(SG_DIG_CTRL, 0x01388400);
  2213. udelay(40);
  2214. /* Link parallel detection - link is up */
  2215. /* only if we have PCS_SYNC and not */
  2216. /* receiving config code words */
  2217. mac_status = tr32(MAC_STATUS);
  2218. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  2219. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  2220. tg3_setup_flow_control(tp, 0, 0);
  2221. current_link_up = 1;
  2222. tp->tg3_flags2 |=
  2223. TG3_FLG2_PARALLEL_DETECT;
  2224. tp->serdes_counter =
  2225. SERDES_PARALLEL_DET_TIMEOUT;
  2226. } else
  2227. goto restart_autoneg;
  2228. }
  2229. }
  2230. } else {
  2231. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  2232. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2233. }
  2234. out:
  2235. return current_link_up;
  2236. }
  2237. static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  2238. {
  2239. int current_link_up = 0;
  2240. if (!(mac_status & MAC_STATUS_PCS_SYNCED))
  2241. goto out;
  2242. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2243. u32 flags;
  2244. int i;
  2245. if (fiber_autoneg(tp, &flags)) {
  2246. u32 local_adv, remote_adv;
  2247. local_adv = ADVERTISE_PAUSE_CAP;
  2248. remote_adv = 0;
  2249. if (flags & MR_LP_ADV_SYM_PAUSE)
  2250. remote_adv |= LPA_PAUSE_CAP;
  2251. if (flags & MR_LP_ADV_ASYM_PAUSE)
  2252. remote_adv |= LPA_PAUSE_ASYM;
  2253. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2254. current_link_up = 1;
  2255. }
  2256. for (i = 0; i < 30; i++) {
  2257. udelay(20);
  2258. tw32_f(MAC_STATUS,
  2259. (MAC_STATUS_SYNC_CHANGED |
  2260. MAC_STATUS_CFG_CHANGED));
  2261. udelay(40);
  2262. if ((tr32(MAC_STATUS) &
  2263. (MAC_STATUS_SYNC_CHANGED |
  2264. MAC_STATUS_CFG_CHANGED)) == 0)
  2265. break;
  2266. }
  2267. mac_status = tr32(MAC_STATUS);
  2268. if (current_link_up == 0 &&
  2269. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  2270. !(mac_status & MAC_STATUS_RCVD_CFG))
  2271. current_link_up = 1;
  2272. } else {
  2273. /* Forcing 1000FD link up. */
  2274. current_link_up = 1;
  2275. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  2276. udelay(40);
  2277. tw32_f(MAC_MODE, tp->mac_mode);
  2278. udelay(40);
  2279. }
  2280. out:
  2281. return current_link_up;
  2282. }
  2283. static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
  2284. {
  2285. u32 orig_pause_cfg;
  2286. u16 orig_active_speed;
  2287. u8 orig_active_duplex;
  2288. u32 mac_status;
  2289. int current_link_up;
  2290. int i;
  2291. orig_pause_cfg =
  2292. (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
  2293. TG3_FLAG_TX_PAUSE));
  2294. orig_active_speed = tp->link_config.active_speed;
  2295. orig_active_duplex = tp->link_config.active_duplex;
  2296. if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
  2297. netif_carrier_ok(tp->dev) &&
  2298. (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
  2299. mac_status = tr32(MAC_STATUS);
  2300. mac_status &= (MAC_STATUS_PCS_SYNCED |
  2301. MAC_STATUS_SIGNAL_DET |
  2302. MAC_STATUS_CFG_CHANGED |
  2303. MAC_STATUS_RCVD_CFG);
  2304. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  2305. MAC_STATUS_SIGNAL_DET)) {
  2306. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  2307. MAC_STATUS_CFG_CHANGED));
  2308. return 0;
  2309. }
  2310. }
  2311. tw32_f(MAC_TX_AUTO_NEG, 0);
  2312. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  2313. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  2314. tw32_f(MAC_MODE, tp->mac_mode);
  2315. udelay(40);
  2316. if (tp->phy_id == PHY_ID_BCM8002)
  2317. tg3_init_bcm8002(tp);
  2318. /* Enable link change event even when serdes polling. */
  2319. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2320. udelay(40);
  2321. current_link_up = 0;
  2322. mac_status = tr32(MAC_STATUS);
  2323. if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
  2324. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  2325. else
  2326. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  2327. tp->hw_status->status =
  2328. (SD_STATUS_UPDATED |
  2329. (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
  2330. for (i = 0; i < 100; i++) {
  2331. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  2332. MAC_STATUS_CFG_CHANGED));
  2333. udelay(5);
  2334. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  2335. MAC_STATUS_CFG_CHANGED |
  2336. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  2337. break;
  2338. }
  2339. mac_status = tr32(MAC_STATUS);
  2340. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  2341. current_link_up = 0;
  2342. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  2343. tp->serdes_counter == 0) {
  2344. tw32_f(MAC_MODE, (tp->mac_mode |
  2345. MAC_MODE_SEND_CONFIGS));
  2346. udelay(1);
  2347. tw32_f(MAC_MODE, tp->mac_mode);
  2348. }
  2349. }
  2350. if (current_link_up == 1) {
  2351. tp->link_config.active_speed = SPEED_1000;
  2352. tp->link_config.active_duplex = DUPLEX_FULL;
  2353. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  2354. LED_CTRL_LNKLED_OVERRIDE |
  2355. LED_CTRL_1000MBPS_ON));
  2356. } else {
  2357. tp->link_config.active_speed = SPEED_INVALID;
  2358. tp->link_config.active_duplex = DUPLEX_INVALID;
  2359. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  2360. LED_CTRL_LNKLED_OVERRIDE |
  2361. LED_CTRL_TRAFFIC_OVERRIDE));
  2362. }
  2363. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2364. if (current_link_up)
  2365. netif_carrier_on(tp->dev);
  2366. else
  2367. netif_carrier_off(tp->dev);
  2368. tg3_link_report(tp);
  2369. } else {
  2370. u32 now_pause_cfg =
  2371. tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
  2372. TG3_FLAG_TX_PAUSE);
  2373. if (orig_pause_cfg != now_pause_cfg ||
  2374. orig_active_speed != tp->link_config.active_speed ||
  2375. orig_active_duplex != tp->link_config.active_duplex)
  2376. tg3_link_report(tp);
  2377. }
  2378. return 0;
  2379. }
  2380. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
  2381. {
  2382. int current_link_up, err = 0;
  2383. u32 bmsr, bmcr;
  2384. u16 current_speed;
  2385. u8 current_duplex;
  2386. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2387. tw32_f(MAC_MODE, tp->mac_mode);
  2388. udelay(40);
  2389. tw32(MAC_EVENT, 0);
  2390. tw32_f(MAC_STATUS,
  2391. (MAC_STATUS_SYNC_CHANGED |
  2392. MAC_STATUS_CFG_CHANGED |
  2393. MAC_STATUS_MI_COMPLETION |
  2394. MAC_STATUS_LNKSTATE_CHANGED));
  2395. udelay(40);
  2396. if (force_reset)
  2397. tg3_phy_reset(tp);
  2398. current_link_up = 0;
  2399. current_speed = SPEED_INVALID;
  2400. current_duplex = DUPLEX_INVALID;
  2401. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2402. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2403. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  2404. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  2405. bmsr |= BMSR_LSTATUS;
  2406. else
  2407. bmsr &= ~BMSR_LSTATUS;
  2408. }
  2409. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  2410. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  2411. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  2412. /* do nothing, just check for link up at the end */
  2413. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2414. u32 adv, new_adv;
  2415. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  2416. new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  2417. ADVERTISE_1000XPAUSE |
  2418. ADVERTISE_1000XPSE_ASYM |
  2419. ADVERTISE_SLCT);
  2420. /* Always advertise symmetric PAUSE just like copper */
  2421. new_adv |= ADVERTISE_1000XPAUSE;
  2422. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  2423. new_adv |= ADVERTISE_1000XHALF;
  2424. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  2425. new_adv |= ADVERTISE_1000XFULL;
  2426. if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
  2427. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2428. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  2429. tg3_writephy(tp, MII_BMCR, bmcr);
  2430. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2431. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  2432. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2433. return err;
  2434. }
  2435. } else {
  2436. u32 new_bmcr;
  2437. bmcr &= ~BMCR_SPEED1000;
  2438. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  2439. if (tp->link_config.duplex == DUPLEX_FULL)
  2440. new_bmcr |= BMCR_FULLDPLX;
  2441. if (new_bmcr != bmcr) {
  2442. /* BMCR_SPEED1000 is a reserved bit that needs
  2443. * to be set on write.
  2444. */
  2445. new_bmcr |= BMCR_SPEED1000;
  2446. /* Force a linkdown */
  2447. if (netif_carrier_ok(tp->dev)) {
  2448. u32 adv;
  2449. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  2450. adv &= ~(ADVERTISE_1000XFULL |
  2451. ADVERTISE_1000XHALF |
  2452. ADVERTISE_SLCT);
  2453. tg3_writephy(tp, MII_ADVERTISE, adv);
  2454. tg3_writephy(tp, MII_BMCR, bmcr |
  2455. BMCR_ANRESTART |
  2456. BMCR_ANENABLE);
  2457. udelay(10);
  2458. netif_carrier_off(tp->dev);
  2459. }
  2460. tg3_writephy(tp, MII_BMCR, new_bmcr);
  2461. bmcr = new_bmcr;
  2462. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2463. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2464. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  2465. ASIC_REV_5714) {
  2466. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  2467. bmsr |= BMSR_LSTATUS;
  2468. else
  2469. bmsr &= ~BMSR_LSTATUS;
  2470. }
  2471. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2472. }
  2473. }
  2474. if (bmsr & BMSR_LSTATUS) {
  2475. current_speed = SPEED_1000;
  2476. current_link_up = 1;
  2477. if (bmcr & BMCR_FULLDPLX)
  2478. current_duplex = DUPLEX_FULL;
  2479. else
  2480. current_duplex = DUPLEX_HALF;
  2481. if (bmcr & BMCR_ANENABLE) {
  2482. u32 local_adv, remote_adv, common;
  2483. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  2484. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  2485. common = local_adv & remote_adv;
  2486. if (common & (ADVERTISE_1000XHALF |
  2487. ADVERTISE_1000XFULL)) {
  2488. if (common & ADVERTISE_1000XFULL)
  2489. current_duplex = DUPLEX_FULL;
  2490. else
  2491. current_duplex = DUPLEX_HALF;
  2492. tg3_setup_flow_control(tp, local_adv,
  2493. remote_adv);
  2494. }
  2495. else
  2496. current_link_up = 0;
  2497. }
  2498. }
  2499. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  2500. if (tp->link_config.active_duplex == DUPLEX_HALF)
  2501. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  2502. tw32_f(MAC_MODE, tp->mac_mode);
  2503. udelay(40);
  2504. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2505. tp->link_config.active_speed = current_speed;
  2506. tp->link_config.active_duplex = current_duplex;
  2507. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2508. if (current_link_up)
  2509. netif_carrier_on(tp->dev);
  2510. else {
  2511. netif_carrier_off(tp->dev);
  2512. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2513. }
  2514. tg3_link_report(tp);
  2515. }
  2516. return err;
  2517. }
  2518. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  2519. {
  2520. if (tp->serdes_counter) {
  2521. /* Give autoneg time to complete. */
  2522. tp->serdes_counter--;
  2523. return;
  2524. }
  2525. if (!netif_carrier_ok(tp->dev) &&
  2526. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  2527. u32 bmcr;
  2528. tg3_readphy(tp, MII_BMCR, &bmcr);
  2529. if (bmcr & BMCR_ANENABLE) {
  2530. u32 phy1, phy2;
  2531. /* Select shadow register 0x1f */
  2532. tg3_writephy(tp, 0x1c, 0x7c00);
  2533. tg3_readphy(tp, 0x1c, &phy1);
  2534. /* Select expansion interrupt status register */
  2535. tg3_writephy(tp, 0x17, 0x0f01);
  2536. tg3_readphy(tp, 0x15, &phy2);
  2537. tg3_readphy(tp, 0x15, &phy2);
  2538. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  2539. /* We have signal detect and not receiving
  2540. * config code words, link is up by parallel
  2541. * detection.
  2542. */
  2543. bmcr &= ~BMCR_ANENABLE;
  2544. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  2545. tg3_writephy(tp, MII_BMCR, bmcr);
  2546. tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
  2547. }
  2548. }
  2549. }
  2550. else if (netif_carrier_ok(tp->dev) &&
  2551. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  2552. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  2553. u32 phy2;
  2554. /* Select expansion interrupt status register */
  2555. tg3_writephy(tp, 0x17, 0x0f01);
  2556. tg3_readphy(tp, 0x15, &phy2);
  2557. if (phy2 & 0x20) {
  2558. u32 bmcr;
  2559. /* Config code words received, turn on autoneg. */
  2560. tg3_readphy(tp, MII_BMCR, &bmcr);
  2561. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  2562. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2563. }
  2564. }
  2565. }
  2566. static int tg3_setup_phy(struct tg3 *tp, int force_reset)
  2567. {
  2568. int err;
  2569. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  2570. err = tg3_setup_fiber_phy(tp, force_reset);
  2571. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  2572. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  2573. } else {
  2574. err = tg3_setup_copper_phy(tp, force_reset);
  2575. }
  2576. if (tp->link_config.active_speed == SPEED_1000 &&
  2577. tp->link_config.active_duplex == DUPLEX_HALF)
  2578. tw32(MAC_TX_LENGTHS,
  2579. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2580. (6 << TX_LENGTHS_IPG_SHIFT) |
  2581. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  2582. else
  2583. tw32(MAC_TX_LENGTHS,
  2584. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2585. (6 << TX_LENGTHS_IPG_SHIFT) |
  2586. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  2587. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  2588. if (netif_carrier_ok(tp->dev)) {
  2589. tw32(HOSTCC_STAT_COAL_TICKS,
  2590. tp->coal.stats_block_coalesce_usecs);
  2591. } else {
  2592. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  2593. }
  2594. }
  2595. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
  2596. u32 val = tr32(PCIE_PWR_MGMT_THRESH);
  2597. if (!netif_carrier_ok(tp->dev))
  2598. val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
  2599. tp->pwrmgmt_thresh;
  2600. else
  2601. val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
  2602. tw32(PCIE_PWR_MGMT_THRESH, val);
  2603. }
  2604. return err;
  2605. }
  2606. /* This is called whenever we suspect that the system chipset is re-
  2607. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  2608. * is bogus tx completions. We try to recover by setting the
  2609. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  2610. * in the workqueue.
  2611. */
  2612. static void tg3_tx_recover(struct tg3 *tp)
  2613. {
  2614. BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
  2615. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  2616. printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
  2617. "mapped I/O cycles to the network device, attempting to "
  2618. "recover. Please report the problem to the driver maintainer "
  2619. "and include system chipset information.\n", tp->dev->name);
  2620. spin_lock(&tp->lock);
  2621. tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
  2622. spin_unlock(&tp->lock);
  2623. }
  2624. static inline u32 tg3_tx_avail(struct tg3 *tp)
  2625. {
  2626. smp_mb();
  2627. return (tp->tx_pending -
  2628. ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
  2629. }
  2630. /* Tigon3 never reports partial packet sends. So we do not
  2631. * need special logic to handle SKBs that have not had all
  2632. * of their frags sent yet, like SunGEM does.
  2633. */
  2634. static void tg3_tx(struct tg3 *tp)
  2635. {
  2636. u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
  2637. u32 sw_idx = tp->tx_cons;
  2638. while (sw_idx != hw_idx) {
  2639. struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
  2640. struct sk_buff *skb = ri->skb;
  2641. int i, tx_bug = 0;
  2642. if (unlikely(skb == NULL)) {
  2643. tg3_tx_recover(tp);
  2644. return;
  2645. }
  2646. pci_unmap_single(tp->pdev,
  2647. pci_unmap_addr(ri, mapping),
  2648. skb_headlen(skb),
  2649. PCI_DMA_TODEVICE);
  2650. ri->skb = NULL;
  2651. sw_idx = NEXT_TX(sw_idx);
  2652. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2653. ri = &tp->tx_buffers[sw_idx];
  2654. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  2655. tx_bug = 1;
  2656. pci_unmap_page(tp->pdev,
  2657. pci_unmap_addr(ri, mapping),
  2658. skb_shinfo(skb)->frags[i].size,
  2659. PCI_DMA_TODEVICE);
  2660. sw_idx = NEXT_TX(sw_idx);
  2661. }
  2662. dev_kfree_skb(skb);
  2663. if (unlikely(tx_bug)) {
  2664. tg3_tx_recover(tp);
  2665. return;
  2666. }
  2667. }
  2668. tp->tx_cons = sw_idx;
  2669. /* Need to make the tx_cons update visible to tg3_start_xmit()
  2670. * before checking for netif_queue_stopped(). Without the
  2671. * memory barrier, there is a small possibility that tg3_start_xmit()
  2672. * will miss it and cause the queue to be stopped forever.
  2673. */
  2674. smp_mb();
  2675. if (unlikely(netif_queue_stopped(tp->dev) &&
  2676. (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
  2677. netif_tx_lock(tp->dev);
  2678. if (netif_queue_stopped(tp->dev) &&
  2679. (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
  2680. netif_wake_queue(tp->dev);
  2681. netif_tx_unlock(tp->dev);
  2682. }
  2683. }
  2684. /* Returns size of skb allocated or < 0 on error.
  2685. *
  2686. * We only need to fill in the address because the other members
  2687. * of the RX descriptor are invariant, see tg3_init_rings.
  2688. *
  2689. * Note the purposeful assymetry of cpu vs. chip accesses. For
  2690. * posting buffers we only dirty the first cache line of the RX
  2691. * descriptor (containing the address). Whereas for the RX status
  2692. * buffers the cpu only reads the last cacheline of the RX descriptor
  2693. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  2694. */
  2695. static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
  2696. int src_idx, u32 dest_idx_unmasked)
  2697. {
  2698. struct tg3_rx_buffer_desc *desc;
  2699. struct ring_info *map, *src_map;
  2700. struct sk_buff *skb;
  2701. dma_addr_t mapping;
  2702. int skb_size, dest_idx;
  2703. src_map = NULL;
  2704. switch (opaque_key) {
  2705. case RXD_OPAQUE_RING_STD:
  2706. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  2707. desc = &tp->rx_std[dest_idx];
  2708. map = &tp->rx_std_buffers[dest_idx];
  2709. if (src_idx >= 0)
  2710. src_map = &tp->rx_std_buffers[src_idx];
  2711. skb_size = tp->rx_pkt_buf_sz;
  2712. break;
  2713. case RXD_OPAQUE_RING_JUMBO:
  2714. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  2715. desc = &tp->rx_jumbo[dest_idx];
  2716. map = &tp->rx_jumbo_buffers[dest_idx];
  2717. if (src_idx >= 0)
  2718. src_map = &tp->rx_jumbo_buffers[src_idx];
  2719. skb_size = RX_JUMBO_PKT_BUF_SZ;
  2720. break;
  2721. default:
  2722. return -EINVAL;
  2723. };
  2724. /* Do not overwrite any of the map or rp information
  2725. * until we are sure we can commit to a new buffer.
  2726. *
  2727. * Callers depend upon this behavior and assume that
  2728. * we leave everything unchanged if we fail.
  2729. */
  2730. skb = netdev_alloc_skb(tp->dev, skb_size);
  2731. if (skb == NULL)
  2732. return -ENOMEM;
  2733. skb_reserve(skb, tp->rx_offset);
  2734. mapping = pci_map_single(tp->pdev, skb->data,
  2735. skb_size - tp->rx_offset,
  2736. PCI_DMA_FROMDEVICE);
  2737. map->skb = skb;
  2738. pci_unmap_addr_set(map, mapping, mapping);
  2739. if (src_map != NULL)
  2740. src_map->skb = NULL;
  2741. desc->addr_hi = ((u64)mapping >> 32);
  2742. desc->addr_lo = ((u64)mapping & 0xffffffff);
  2743. return skb_size;
  2744. }
  2745. /* We only need to move over in the address because the other
  2746. * members of the RX descriptor are invariant. See notes above
  2747. * tg3_alloc_rx_skb for full details.
  2748. */
  2749. static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
  2750. int src_idx, u32 dest_idx_unmasked)
  2751. {
  2752. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  2753. struct ring_info *src_map, *dest_map;
  2754. int dest_idx;
  2755. switch (opaque_key) {
  2756. case RXD_OPAQUE_RING_STD:
  2757. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  2758. dest_desc = &tp->rx_std[dest_idx];
  2759. dest_map = &tp->rx_std_buffers[dest_idx];
  2760. src_desc = &tp->rx_std[src_idx];
  2761. src_map = &tp->rx_std_buffers[src_idx];
  2762. break;
  2763. case RXD_OPAQUE_RING_JUMBO:
  2764. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  2765. dest_desc = &tp->rx_jumbo[dest_idx];
  2766. dest_map = &tp->rx_jumbo_buffers[dest_idx];
  2767. src_desc = &tp->rx_jumbo[src_idx];
  2768. src_map = &tp->rx_jumbo_buffers[src_idx];
  2769. break;
  2770. default:
  2771. return;
  2772. };
  2773. dest_map->skb = src_map->skb;
  2774. pci_unmap_addr_set(dest_map, mapping,
  2775. pci_unmap_addr(src_map, mapping));
  2776. dest_desc->addr_hi = src_desc->addr_hi;
  2777. dest_desc->addr_lo = src_desc->addr_lo;
  2778. src_map->skb = NULL;
  2779. }
  2780. #if TG3_VLAN_TAG_USED
  2781. static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
  2782. {
  2783. return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
  2784. }
  2785. #endif
  2786. /* The RX ring scheme is composed of multiple rings which post fresh
  2787. * buffers to the chip, and one special ring the chip uses to report
  2788. * status back to the host.
  2789. *
  2790. * The special ring reports the status of received packets to the
  2791. * host. The chip does not write into the original descriptor the
  2792. * RX buffer was obtained from. The chip simply takes the original
  2793. * descriptor as provided by the host, updates the status and length
  2794. * field, then writes this into the next status ring entry.
  2795. *
  2796. * Each ring the host uses to post buffers to the chip is described
  2797. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  2798. * it is first placed into the on-chip ram. When the packet's length
  2799. * is known, it walks down the TG3_BDINFO entries to select the ring.
  2800. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  2801. * which is within the range of the new packet's length is chosen.
  2802. *
  2803. * The "separate ring for rx status" scheme may sound queer, but it makes
  2804. * sense from a cache coherency perspective. If only the host writes
  2805. * to the buffer post rings, and only the chip writes to the rx status
  2806. * rings, then cache lines never move beyond shared-modified state.
  2807. * If both the host and chip were to write into the same ring, cache line
  2808. * eviction could occur since both entities want it in an exclusive state.
  2809. */
  2810. static int tg3_rx(struct tg3 *tp, int budget)
  2811. {
  2812. u32 work_mask, rx_std_posted = 0;
  2813. u32 sw_idx = tp->rx_rcb_ptr;
  2814. u16 hw_idx;
  2815. int received;
  2816. hw_idx = tp->hw_status->idx[0].rx_producer;
  2817. /*
  2818. * We need to order the read of hw_idx and the read of
  2819. * the opaque cookie.
  2820. */
  2821. rmb();
  2822. work_mask = 0;
  2823. received = 0;
  2824. while (sw_idx != hw_idx && budget > 0) {
  2825. struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
  2826. unsigned int len;
  2827. struct sk_buff *skb;
  2828. dma_addr_t dma_addr;
  2829. u32 opaque_key, desc_idx, *post_ptr;
  2830. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  2831. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  2832. if (opaque_key == RXD_OPAQUE_RING_STD) {
  2833. dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
  2834. mapping);
  2835. skb = tp->rx_std_buffers[desc_idx].skb;
  2836. post_ptr = &tp->rx_std_ptr;
  2837. rx_std_posted++;
  2838. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  2839. dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
  2840. mapping);
  2841. skb = tp->rx_jumbo_buffers[desc_idx].skb;
  2842. post_ptr = &tp->rx_jumbo_ptr;
  2843. }
  2844. else {
  2845. goto next_pkt_nopost;
  2846. }
  2847. work_mask |= opaque_key;
  2848. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  2849. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  2850. drop_it:
  2851. tg3_recycle_rx(tp, opaque_key,
  2852. desc_idx, *post_ptr);
  2853. drop_it_no_recycle:
  2854. /* Other statistics kept track of by card. */
  2855. tp->net_stats.rx_dropped++;
  2856. goto next_pkt;
  2857. }
  2858. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
  2859. if (len > RX_COPY_THRESHOLD
  2860. && tp->rx_offset == 2
  2861. /* rx_offset != 2 iff this is a 5701 card running
  2862. * in PCI-X mode [see tg3_get_invariants()] */
  2863. ) {
  2864. int skb_size;
  2865. skb_size = tg3_alloc_rx_skb(tp, opaque_key,
  2866. desc_idx, *post_ptr);
  2867. if (skb_size < 0)
  2868. goto drop_it;
  2869. pci_unmap_single(tp->pdev, dma_addr,
  2870. skb_size - tp->rx_offset,
  2871. PCI_DMA_FROMDEVICE);
  2872. skb_put(skb, len);
  2873. } else {
  2874. struct sk_buff *copy_skb;
  2875. tg3_recycle_rx(tp, opaque_key,
  2876. desc_idx, *post_ptr);
  2877. copy_skb = netdev_alloc_skb(tp->dev, len + 2);
  2878. if (copy_skb == NULL)
  2879. goto drop_it_no_recycle;
  2880. skb_reserve(copy_skb, 2);
  2881. skb_put(copy_skb, len);
  2882. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  2883. skb_copy_from_linear_data(skb, copy_skb->data, len);
  2884. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  2885. /* We'll reuse the original ring buffer. */
  2886. skb = copy_skb;
  2887. }
  2888. if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
  2889. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  2890. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  2891. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  2892. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2893. else
  2894. skb->ip_summed = CHECKSUM_NONE;
  2895. skb->protocol = eth_type_trans(skb, tp->dev);
  2896. #if TG3_VLAN_TAG_USED
  2897. if (tp->vlgrp != NULL &&
  2898. desc->type_flags & RXD_FLAG_VLAN) {
  2899. tg3_vlan_rx(tp, skb,
  2900. desc->err_vlan & RXD_VLAN_MASK);
  2901. } else
  2902. #endif
  2903. netif_receive_skb(skb);
  2904. tp->dev->last_rx = jiffies;
  2905. received++;
  2906. budget--;
  2907. next_pkt:
  2908. (*post_ptr)++;
  2909. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  2910. u32 idx = *post_ptr % TG3_RX_RING_SIZE;
  2911. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
  2912. TG3_64BIT_REG_LOW, idx);
  2913. work_mask &= ~RXD_OPAQUE_RING_STD;
  2914. rx_std_posted = 0;
  2915. }
  2916. next_pkt_nopost:
  2917. sw_idx++;
  2918. sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
  2919. /* Refresh hw_idx to see if there is new work */
  2920. if (sw_idx == hw_idx) {
  2921. hw_idx = tp->hw_status->idx[0].rx_producer;
  2922. rmb();
  2923. }
  2924. }
  2925. /* ACK the status ring. */
  2926. tp->rx_rcb_ptr = sw_idx;
  2927. tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
  2928. /* Refill RX ring(s). */
  2929. if (work_mask & RXD_OPAQUE_RING_STD) {
  2930. sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
  2931. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  2932. sw_idx);
  2933. }
  2934. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  2935. sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
  2936. tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  2937. sw_idx);
  2938. }
  2939. mmiowb();
  2940. return received;
  2941. }
  2942. static int tg3_poll(struct net_device *netdev, int *budget)
  2943. {
  2944. struct tg3 *tp = netdev_priv(netdev);
  2945. struct tg3_hw_status *sblk = tp->hw_status;
  2946. int done;
  2947. /* handle link change and other phy events */
  2948. if (!(tp->tg3_flags &
  2949. (TG3_FLAG_USE_LINKCHG_REG |
  2950. TG3_FLAG_POLL_SERDES))) {
  2951. if (sblk->status & SD_STATUS_LINK_CHG) {
  2952. sblk->status = SD_STATUS_UPDATED |
  2953. (sblk->status & ~SD_STATUS_LINK_CHG);
  2954. spin_lock(&tp->lock);
  2955. tg3_setup_phy(tp, 0);
  2956. spin_unlock(&tp->lock);
  2957. }
  2958. }
  2959. /* run TX completion thread */
  2960. if (sblk->idx[0].tx_consumer != tp->tx_cons) {
  2961. tg3_tx(tp);
  2962. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
  2963. netif_rx_complete(netdev);
  2964. schedule_work(&tp->reset_task);
  2965. return 0;
  2966. }
  2967. }
  2968. /* run RX thread, within the bounds set by NAPI.
  2969. * All RX "locking" is done by ensuring outside
  2970. * code synchronizes with dev->poll()
  2971. */
  2972. if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
  2973. int orig_budget = *budget;
  2974. int work_done;
  2975. if (orig_budget > netdev->quota)
  2976. orig_budget = netdev->quota;
  2977. work_done = tg3_rx(tp, orig_budget);
  2978. *budget -= work_done;
  2979. netdev->quota -= work_done;
  2980. }
  2981. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  2982. tp->last_tag = sblk->status_tag;
  2983. rmb();
  2984. } else
  2985. sblk->status &= ~SD_STATUS_UPDATED;
  2986. /* if no more work, tell net stack and NIC we're done */
  2987. done = !tg3_has_work(tp);
  2988. if (done) {
  2989. netif_rx_complete(netdev);
  2990. tg3_restart_ints(tp);
  2991. }
  2992. return (done ? 0 : 1);
  2993. }
  2994. static void tg3_irq_quiesce(struct tg3 *tp)
  2995. {
  2996. BUG_ON(tp->irq_sync);
  2997. tp->irq_sync = 1;
  2998. smp_mb();
  2999. synchronize_irq(tp->pdev->irq);
  3000. }
  3001. static inline int tg3_irq_sync(struct tg3 *tp)
  3002. {
  3003. return tp->irq_sync;
  3004. }
  3005. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  3006. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  3007. * with as well. Most of the time, this is not necessary except when
  3008. * shutting down the device.
  3009. */
  3010. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  3011. {
  3012. spin_lock_bh(&tp->lock);
  3013. if (irq_sync)
  3014. tg3_irq_quiesce(tp);
  3015. }
  3016. static inline void tg3_full_unlock(struct tg3 *tp)
  3017. {
  3018. spin_unlock_bh(&tp->lock);
  3019. }
  3020. /* One-shot MSI handler - Chip automatically disables interrupt
  3021. * after sending MSI so driver doesn't have to do it.
  3022. */
  3023. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  3024. {
  3025. struct net_device *dev = dev_id;
  3026. struct tg3 *tp = netdev_priv(dev);
  3027. prefetch(tp->hw_status);
  3028. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3029. if (likely(!tg3_irq_sync(tp)))
  3030. netif_rx_schedule(dev); /* schedule NAPI poll */
  3031. return IRQ_HANDLED;
  3032. }
  3033. /* MSI ISR - No need to check for interrupt sharing and no need to
  3034. * flush status block and interrupt mailbox. PCI ordering rules
  3035. * guarantee that MSI will arrive after the status block.
  3036. */
  3037. static irqreturn_t tg3_msi(int irq, void *dev_id)
  3038. {
  3039. struct net_device *dev = dev_id;
  3040. struct tg3 *tp = netdev_priv(dev);
  3041. prefetch(tp->hw_status);
  3042. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3043. /*
  3044. * Writing any value to intr-mbox-0 clears PCI INTA# and
  3045. * chip-internal interrupt pending events.
  3046. * Writing non-zero to intr-mbox-0 additional tells the
  3047. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3048. * event coalescing.
  3049. */
  3050. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3051. if (likely(!tg3_irq_sync(tp)))
  3052. netif_rx_schedule(dev); /* schedule NAPI poll */
  3053. return IRQ_RETVAL(1);
  3054. }
  3055. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  3056. {
  3057. struct net_device *dev = dev_id;
  3058. struct tg3 *tp = netdev_priv(dev);
  3059. struct tg3_hw_status *sblk = tp->hw_status;
  3060. unsigned int handled = 1;
  3061. /* In INTx mode, it is possible for the interrupt to arrive at
  3062. * the CPU before the status block posted prior to the interrupt.
  3063. * Reading the PCI State register will confirm whether the
  3064. * interrupt is ours and will flush the status block.
  3065. */
  3066. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  3067. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  3068. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3069. handled = 0;
  3070. goto out;
  3071. }
  3072. }
  3073. /*
  3074. * Writing any value to intr-mbox-0 clears PCI INTA# and
  3075. * chip-internal interrupt pending events.
  3076. * Writing non-zero to intr-mbox-0 additional tells the
  3077. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3078. * event coalescing.
  3079. *
  3080. * Flush the mailbox to de-assert the IRQ immediately to prevent
  3081. * spurious interrupts. The flush impacts performance but
  3082. * excessive spurious interrupts can be worse in some cases.
  3083. */
  3084. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3085. if (tg3_irq_sync(tp))
  3086. goto out;
  3087. sblk->status &= ~SD_STATUS_UPDATED;
  3088. if (likely(tg3_has_work(tp))) {
  3089. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3090. netif_rx_schedule(dev); /* schedule NAPI poll */
  3091. } else {
  3092. /* No work, shared interrupt perhaps? re-enable
  3093. * interrupts, and flush that PCI write
  3094. */
  3095. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  3096. 0x00000000);
  3097. }
  3098. out:
  3099. return IRQ_RETVAL(handled);
  3100. }
  3101. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  3102. {
  3103. struct net_device *dev = dev_id;
  3104. struct tg3 *tp = netdev_priv(dev);
  3105. struct tg3_hw_status *sblk = tp->hw_status;
  3106. unsigned int handled = 1;
  3107. /* In INTx mode, it is possible for the interrupt to arrive at
  3108. * the CPU before the status block posted prior to the interrupt.
  3109. * Reading the PCI State register will confirm whether the
  3110. * interrupt is ours and will flush the status block.
  3111. */
  3112. if (unlikely(sblk->status_tag == tp->last_tag)) {
  3113. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  3114. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3115. handled = 0;
  3116. goto out;
  3117. }
  3118. }
  3119. /*
  3120. * writing any value to intr-mbox-0 clears PCI INTA# and
  3121. * chip-internal interrupt pending events.
  3122. * writing non-zero to intr-mbox-0 additional tells the
  3123. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3124. * event coalescing.
  3125. *
  3126. * Flush the mailbox to de-assert the IRQ immediately to prevent
  3127. * spurious interrupts. The flush impacts performance but
  3128. * excessive spurious interrupts can be worse in some cases.
  3129. */
  3130. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3131. if (tg3_irq_sync(tp))
  3132. goto out;
  3133. if (netif_rx_schedule_prep(dev)) {
  3134. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3135. /* Update last_tag to mark that this status has been
  3136. * seen. Because interrupt may be shared, we may be
  3137. * racing with tg3_poll(), so only update last_tag
  3138. * if tg3_poll() is not scheduled.
  3139. */
  3140. tp->last_tag = sblk->status_tag;
  3141. __netif_rx_schedule(dev);
  3142. }
  3143. out:
  3144. return IRQ_RETVAL(handled);
  3145. }
  3146. /* ISR for interrupt test */
  3147. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  3148. {
  3149. struct net_device *dev = dev_id;
  3150. struct tg3 *tp = netdev_priv(dev);
  3151. struct tg3_hw_status *sblk = tp->hw_status;
  3152. if ((sblk->status & SD_STATUS_UPDATED) ||
  3153. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3154. tg3_disable_ints(tp);
  3155. return IRQ_RETVAL(1);
  3156. }
  3157. return IRQ_RETVAL(0);
  3158. }
  3159. static int tg3_init_hw(struct tg3 *, int);
  3160. static int tg3_halt(struct tg3 *, int, int);
  3161. /* Restart hardware after configuration changes, self-test, etc.
  3162. * Invoked with tp->lock held.
  3163. */
  3164. static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
  3165. {
  3166. int err;
  3167. err = tg3_init_hw(tp, reset_phy);
  3168. if (err) {
  3169. printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
  3170. "aborting.\n", tp->dev->name);
  3171. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  3172. tg3_full_unlock(tp);
  3173. del_timer_sync(&tp->timer);
  3174. tp->irq_sync = 0;
  3175. netif_poll_enable(tp->dev);
  3176. dev_close(tp->dev);
  3177. tg3_full_lock(tp, 0);
  3178. }
  3179. return err;
  3180. }
  3181. #ifdef CONFIG_NET_POLL_CONTROLLER
  3182. static void tg3_poll_controller(struct net_device *dev)
  3183. {
  3184. struct tg3 *tp = netdev_priv(dev);
  3185. tg3_interrupt(tp->pdev->irq, dev);
  3186. }
  3187. #endif
  3188. static void tg3_reset_task(struct work_struct *work)
  3189. {
  3190. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  3191. unsigned int restart_timer;
  3192. tg3_full_lock(tp, 0);
  3193. if (!netif_running(tp->dev)) {
  3194. tg3_full_unlock(tp);
  3195. return;
  3196. }
  3197. tg3_full_unlock(tp);
  3198. tg3_netif_stop(tp);
  3199. tg3_full_lock(tp, 1);
  3200. restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
  3201. tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
  3202. if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
  3203. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  3204. tp->write32_rx_mbox = tg3_write_flush_reg32;
  3205. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  3206. tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
  3207. }
  3208. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  3209. if (tg3_init_hw(tp, 1))
  3210. goto out;
  3211. tg3_netif_start(tp);
  3212. if (restart_timer)
  3213. mod_timer(&tp->timer, jiffies + 1);
  3214. out:
  3215. tg3_full_unlock(tp);
  3216. }
  3217. static void tg3_dump_short_state(struct tg3 *tp)
  3218. {
  3219. printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
  3220. tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
  3221. printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
  3222. tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
  3223. }
  3224. static void tg3_tx_timeout(struct net_device *dev)
  3225. {
  3226. struct tg3 *tp = netdev_priv(dev);
  3227. if (netif_msg_tx_err(tp)) {
  3228. printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
  3229. dev->name);
  3230. tg3_dump_short_state(tp);
  3231. }
  3232. schedule_work(&tp->reset_task);
  3233. }
  3234. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  3235. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  3236. {
  3237. u32 base = (u32) mapping & 0xffffffff;
  3238. return ((base > 0xffffdcc0) &&
  3239. (base + len + 8 < base));
  3240. }
  3241. /* Test for DMA addresses > 40-bit */
  3242. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  3243. int len)
  3244. {
  3245. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  3246. if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
  3247. return (((u64) mapping + len) > DMA_40BIT_MASK);
  3248. return 0;
  3249. #else
  3250. return 0;
  3251. #endif
  3252. }
  3253. static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
  3254. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  3255. static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
  3256. u32 last_plus_one, u32 *start,
  3257. u32 base_flags, u32 mss)
  3258. {
  3259. struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
  3260. dma_addr_t new_addr = 0;
  3261. u32 entry = *start;
  3262. int i, ret = 0;
  3263. if (!new_skb) {
  3264. ret = -1;
  3265. } else {
  3266. /* New SKB is guaranteed to be linear. */
  3267. entry = *start;
  3268. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  3269. PCI_DMA_TODEVICE);
  3270. /* Make sure new skb does not cross any 4G boundaries.
  3271. * Drop the packet if it does.
  3272. */
  3273. if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
  3274. ret = -1;
  3275. dev_kfree_skb(new_skb);
  3276. new_skb = NULL;
  3277. } else {
  3278. tg3_set_txd(tp, entry, new_addr, new_skb->len,
  3279. base_flags, 1 | (mss << 1));
  3280. *start = NEXT_TX(entry);
  3281. }
  3282. }
  3283. /* Now clean up the sw ring entries. */
  3284. i = 0;
  3285. while (entry != last_plus_one) {
  3286. int len;
  3287. if (i == 0)
  3288. len = skb_headlen(skb);
  3289. else
  3290. len = skb_shinfo(skb)->frags[i-1].size;
  3291. pci_unmap_single(tp->pdev,
  3292. pci_unmap_addr(&tp->tx_buffers[entry], mapping),
  3293. len, PCI_DMA_TODEVICE);
  3294. if (i == 0) {
  3295. tp->tx_buffers[entry].skb = new_skb;
  3296. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
  3297. } else {
  3298. tp->tx_buffers[entry].skb = NULL;
  3299. }
  3300. entry = NEXT_TX(entry);
  3301. i++;
  3302. }
  3303. dev_kfree_skb(skb);
  3304. return ret;
  3305. }
  3306. static void tg3_set_txd(struct tg3 *tp, int entry,
  3307. dma_addr_t mapping, int len, u32 flags,
  3308. u32 mss_and_is_end)
  3309. {
  3310. struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
  3311. int is_end = (mss_and_is_end & 0x1);
  3312. u32 mss = (mss_and_is_end >> 1);
  3313. u32 vlan_tag = 0;
  3314. if (is_end)
  3315. flags |= TXD_FLAG_END;
  3316. if (flags & TXD_FLAG_VLAN) {
  3317. vlan_tag = flags >> 16;
  3318. flags &= 0xffff;
  3319. }
  3320. vlan_tag |= (mss << TXD_MSS_SHIFT);
  3321. txd->addr_hi = ((u64) mapping >> 32);
  3322. txd->addr_lo = ((u64) mapping & 0xffffffff);
  3323. txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
  3324. txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
  3325. }
  3326. /* hard_start_xmit for devices that don't have any bugs and
  3327. * support TG3_FLG2_HW_TSO_2 only.
  3328. */
  3329. static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  3330. {
  3331. struct tg3 *tp = netdev_priv(dev);
  3332. dma_addr_t mapping;
  3333. u32 len, entry, base_flags, mss;
  3334. len = skb_headlen(skb);
  3335. /* We are running in BH disabled context with netif_tx_lock
  3336. * and TX reclaim runs via tp->poll inside of a software
  3337. * interrupt. Furthermore, IRQ processing runs lockless so we have
  3338. * no IRQ context deadlocks to worry about either. Rejoice!
  3339. */
  3340. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  3341. if (!netif_queue_stopped(dev)) {
  3342. netif_stop_queue(dev);
  3343. /* This is a hard error, log it. */
  3344. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  3345. "queue awake!\n", dev->name);
  3346. }
  3347. return NETDEV_TX_BUSY;
  3348. }
  3349. entry = tp->tx_prod;
  3350. base_flags = 0;
  3351. mss = 0;
  3352. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  3353. int tcp_opt_len, ip_tcp_len;
  3354. if (skb_header_cloned(skb) &&
  3355. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  3356. dev_kfree_skb(skb);
  3357. goto out_unlock;
  3358. }
  3359. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  3360. mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
  3361. else {
  3362. struct iphdr *iph = ip_hdr(skb);
  3363. tcp_opt_len = tcp_optlen(skb);
  3364. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  3365. iph->check = 0;
  3366. iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
  3367. mss |= (ip_tcp_len + tcp_opt_len) << 9;
  3368. }
  3369. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  3370. TXD_FLAG_CPU_POST_DMA);
  3371. tcp_hdr(skb)->check = 0;
  3372. }
  3373. else if (skb->ip_summed == CHECKSUM_PARTIAL)
  3374. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  3375. #if TG3_VLAN_TAG_USED
  3376. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  3377. base_flags |= (TXD_FLAG_VLAN |
  3378. (vlan_tx_tag_get(skb) << 16));
  3379. #endif
  3380. /* Queue skb data, a.k.a. the main skb fragment. */
  3381. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  3382. tp->tx_buffers[entry].skb = skb;
  3383. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3384. tg3_set_txd(tp, entry, mapping, len, base_flags,
  3385. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  3386. entry = NEXT_TX(entry);
  3387. /* Now loop through additional data fragments, and queue them. */
  3388. if (skb_shinfo(skb)->nr_frags > 0) {
  3389. unsigned int i, last;
  3390. last = skb_shinfo(skb)->nr_frags - 1;
  3391. for (i = 0; i <= last; i++) {
  3392. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3393. len = frag->size;
  3394. mapping = pci_map_page(tp->pdev,
  3395. frag->page,
  3396. frag->page_offset,
  3397. len, PCI_DMA_TODEVICE);
  3398. tp->tx_buffers[entry].skb = NULL;
  3399. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3400. tg3_set_txd(tp, entry, mapping, len,
  3401. base_flags, (i == last) | (mss << 1));
  3402. entry = NEXT_TX(entry);
  3403. }
  3404. }
  3405. /* Packets are ready, update Tx producer idx local and on card. */
  3406. tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
  3407. tp->tx_prod = entry;
  3408. if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
  3409. netif_stop_queue(dev);
  3410. if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
  3411. netif_wake_queue(tp->dev);
  3412. }
  3413. out_unlock:
  3414. mmiowb();
  3415. dev->trans_start = jiffies;
  3416. return NETDEV_TX_OK;
  3417. }
  3418. static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
  3419. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  3420. * TSO header is greater than 80 bytes.
  3421. */
  3422. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  3423. {
  3424. struct sk_buff *segs, *nskb;
  3425. /* Estimate the number of fragments in the worst case */
  3426. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
  3427. netif_stop_queue(tp->dev);
  3428. if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
  3429. return NETDEV_TX_BUSY;
  3430. netif_wake_queue(tp->dev);
  3431. }
  3432. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  3433. if (unlikely(IS_ERR(segs)))
  3434. goto tg3_tso_bug_end;
  3435. do {
  3436. nskb = segs;
  3437. segs = segs->next;
  3438. nskb->next = NULL;
  3439. tg3_start_xmit_dma_bug(nskb, tp->dev);
  3440. } while (segs);
  3441. tg3_tso_bug_end:
  3442. dev_kfree_skb(skb);
  3443. return NETDEV_TX_OK;
  3444. }
  3445. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  3446. * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
  3447. */
  3448. static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
  3449. {
  3450. struct tg3 *tp = netdev_priv(dev);
  3451. dma_addr_t mapping;
  3452. u32 len, entry, base_flags, mss;
  3453. int would_hit_hwbug;
  3454. len = skb_headlen(skb);
  3455. /* We are running in BH disabled context with netif_tx_lock
  3456. * and TX reclaim runs via tp->poll inside of a software
  3457. * interrupt. Furthermore, IRQ processing runs lockless so we have
  3458. * no IRQ context deadlocks to worry about either. Rejoice!
  3459. */
  3460. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  3461. if (!netif_queue_stopped(dev)) {
  3462. netif_stop_queue(dev);
  3463. /* This is a hard error, log it. */
  3464. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  3465. "queue awake!\n", dev->name);
  3466. }
  3467. return NETDEV_TX_BUSY;
  3468. }
  3469. entry = tp->tx_prod;
  3470. base_flags = 0;
  3471. if (skb->ip_summed == CHECKSUM_PARTIAL)
  3472. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  3473. mss = 0;
  3474. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  3475. struct iphdr *iph;
  3476. int tcp_opt_len, ip_tcp_len, hdr_len;
  3477. if (skb_header_cloned(skb) &&
  3478. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  3479. dev_kfree_skb(skb);
  3480. goto out_unlock;
  3481. }
  3482. tcp_opt_len = tcp_optlen(skb);
  3483. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  3484. hdr_len = ip_tcp_len + tcp_opt_len;
  3485. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  3486. (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
  3487. return (tg3_tso_bug(tp, skb));
  3488. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  3489. TXD_FLAG_CPU_POST_DMA);
  3490. iph = ip_hdr(skb);
  3491. iph->check = 0;
  3492. iph->tot_len = htons(mss + hdr_len);
  3493. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  3494. tcp_hdr(skb)->check = 0;
  3495. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  3496. } else
  3497. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  3498. iph->daddr, 0,
  3499. IPPROTO_TCP,
  3500. 0);
  3501. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
  3502. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
  3503. if (tcp_opt_len || iph->ihl > 5) {
  3504. int tsflags;
  3505. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  3506. mss |= (tsflags << 11);
  3507. }
  3508. } else {
  3509. if (tcp_opt_len || iph->ihl > 5) {
  3510. int tsflags;
  3511. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  3512. base_flags |= tsflags << 12;
  3513. }
  3514. }
  3515. }
  3516. #if TG3_VLAN_TAG_USED
  3517. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  3518. base_flags |= (TXD_FLAG_VLAN |
  3519. (vlan_tx_tag_get(skb) << 16));
  3520. #endif
  3521. /* Queue skb data, a.k.a. the main skb fragment. */
  3522. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  3523. tp->tx_buffers[entry].skb = skb;
  3524. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3525. would_hit_hwbug = 0;
  3526. if (tg3_4g_overflow_test(mapping, len))
  3527. would_hit_hwbug = 1;
  3528. tg3_set_txd(tp, entry, mapping, len, base_flags,
  3529. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  3530. entry = NEXT_TX(entry);
  3531. /* Now loop through additional data fragments, and queue them. */
  3532. if (skb_shinfo(skb)->nr_frags > 0) {
  3533. unsigned int i, last;
  3534. last = skb_shinfo(skb)->nr_frags - 1;
  3535. for (i = 0; i <= last; i++) {
  3536. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3537. len = frag->size;
  3538. mapping = pci_map_page(tp->pdev,
  3539. frag->page,
  3540. frag->page_offset,
  3541. len, PCI_DMA_TODEVICE);
  3542. tp->tx_buffers[entry].skb = NULL;
  3543. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3544. if (tg3_4g_overflow_test(mapping, len))
  3545. would_hit_hwbug = 1;
  3546. if (tg3_40bit_overflow_test(tp, mapping, len))
  3547. would_hit_hwbug = 1;
  3548. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  3549. tg3_set_txd(tp, entry, mapping, len,
  3550. base_flags, (i == last)|(mss << 1));
  3551. else
  3552. tg3_set_txd(tp, entry, mapping, len,
  3553. base_flags, (i == last));
  3554. entry = NEXT_TX(entry);
  3555. }
  3556. }
  3557. if (would_hit_hwbug) {
  3558. u32 last_plus_one = entry;
  3559. u32 start;
  3560. start = entry - 1 - skb_shinfo(skb)->nr_frags;
  3561. start &= (TG3_TX_RING_SIZE - 1);
  3562. /* If the workaround fails due to memory/mapping
  3563. * failure, silently drop this packet.
  3564. */
  3565. if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
  3566. &start, base_flags, mss))
  3567. goto out_unlock;
  3568. entry = start;
  3569. }
  3570. /* Packets are ready, update Tx producer idx local and on card. */
  3571. tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
  3572. tp->tx_prod = entry;
  3573. if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
  3574. netif_stop_queue(dev);
  3575. if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
  3576. netif_wake_queue(tp->dev);
  3577. }
  3578. out_unlock:
  3579. mmiowb();
  3580. dev->trans_start = jiffies;
  3581. return NETDEV_TX_OK;
  3582. }
  3583. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  3584. int new_mtu)
  3585. {
  3586. dev->mtu = new_mtu;
  3587. if (new_mtu > ETH_DATA_LEN) {
  3588. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  3589. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  3590. ethtool_op_set_tso(dev, 0);
  3591. }
  3592. else
  3593. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  3594. } else {
  3595. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  3596. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  3597. tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
  3598. }
  3599. }
  3600. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  3601. {
  3602. struct tg3 *tp = netdev_priv(dev);
  3603. int err;
  3604. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  3605. return -EINVAL;
  3606. if (!netif_running(dev)) {
  3607. /* We'll just catch it later when the
  3608. * device is up'd.
  3609. */
  3610. tg3_set_mtu(dev, tp, new_mtu);
  3611. return 0;
  3612. }
  3613. tg3_netif_stop(tp);
  3614. tg3_full_lock(tp, 1);
  3615. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  3616. tg3_set_mtu(dev, tp, new_mtu);
  3617. err = tg3_restart_hw(tp, 0);
  3618. if (!err)
  3619. tg3_netif_start(tp);
  3620. tg3_full_unlock(tp);
  3621. return err;
  3622. }
  3623. /* Free up pending packets in all rx/tx rings.
  3624. *
  3625. * The chip has been shut down and the driver detached from
  3626. * the networking, so no interrupts or new tx packets will
  3627. * end up in the driver. tp->{tx,}lock is not held and we are not
  3628. * in an interrupt context and thus may sleep.
  3629. */
  3630. static void tg3_free_rings(struct tg3 *tp)
  3631. {
  3632. struct ring_info *rxp;
  3633. int i;
  3634. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  3635. rxp = &tp->rx_std_buffers[i];
  3636. if (rxp->skb == NULL)
  3637. continue;
  3638. pci_unmap_single(tp->pdev,
  3639. pci_unmap_addr(rxp, mapping),
  3640. tp->rx_pkt_buf_sz - tp->rx_offset,
  3641. PCI_DMA_FROMDEVICE);
  3642. dev_kfree_skb_any(rxp->skb);
  3643. rxp->skb = NULL;
  3644. }
  3645. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  3646. rxp = &tp->rx_jumbo_buffers[i];
  3647. if (rxp->skb == NULL)
  3648. continue;
  3649. pci_unmap_single(tp->pdev,
  3650. pci_unmap_addr(rxp, mapping),
  3651. RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
  3652. PCI_DMA_FROMDEVICE);
  3653. dev_kfree_skb_any(rxp->skb);
  3654. rxp->skb = NULL;
  3655. }
  3656. for (i = 0; i < TG3_TX_RING_SIZE; ) {
  3657. struct tx_ring_info *txp;
  3658. struct sk_buff *skb;
  3659. int j;
  3660. txp = &tp->tx_buffers[i];
  3661. skb = txp->skb;
  3662. if (skb == NULL) {
  3663. i++;
  3664. continue;
  3665. }
  3666. pci_unmap_single(tp->pdev,
  3667. pci_unmap_addr(txp, mapping),
  3668. skb_headlen(skb),
  3669. PCI_DMA_TODEVICE);
  3670. txp->skb = NULL;
  3671. i++;
  3672. for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
  3673. txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
  3674. pci_unmap_page(tp->pdev,
  3675. pci_unmap_addr(txp, mapping),
  3676. skb_shinfo(skb)->frags[j].size,
  3677. PCI_DMA_TODEVICE);
  3678. i++;
  3679. }
  3680. dev_kfree_skb_any(skb);
  3681. }
  3682. }
  3683. /* Initialize tx/rx rings for packet processing.
  3684. *
  3685. * The chip has been shut down and the driver detached from
  3686. * the networking, so no interrupts or new tx packets will
  3687. * end up in the driver. tp->{tx,}lock are held and thus
  3688. * we may not sleep.
  3689. */
  3690. static int tg3_init_rings(struct tg3 *tp)
  3691. {
  3692. u32 i;
  3693. /* Free up all the SKBs. */
  3694. tg3_free_rings(tp);
  3695. /* Zero out all descriptors. */
  3696. memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
  3697. memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
  3698. memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  3699. memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
  3700. tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
  3701. if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
  3702. (tp->dev->mtu > ETH_DATA_LEN))
  3703. tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
  3704. /* Initialize invariants of the rings, we only set this
  3705. * stuff once. This works because the card does not
  3706. * write into the rx buffer posting rings.
  3707. */
  3708. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  3709. struct tg3_rx_buffer_desc *rxd;
  3710. rxd = &tp->rx_std[i];
  3711. rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
  3712. << RXD_LEN_SHIFT;
  3713. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  3714. rxd->opaque = (RXD_OPAQUE_RING_STD |
  3715. (i << RXD_OPAQUE_INDEX_SHIFT));
  3716. }
  3717. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  3718. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  3719. struct tg3_rx_buffer_desc *rxd;
  3720. rxd = &tp->rx_jumbo[i];
  3721. rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
  3722. << RXD_LEN_SHIFT;
  3723. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  3724. RXD_FLAG_JUMBO;
  3725. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  3726. (i << RXD_OPAQUE_INDEX_SHIFT));
  3727. }
  3728. }
  3729. /* Now allocate fresh SKBs for each rx ring. */
  3730. for (i = 0; i < tp->rx_pending; i++) {
  3731. if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
  3732. printk(KERN_WARNING PFX
  3733. "%s: Using a smaller RX standard ring, "
  3734. "only %d out of %d buffers were allocated "
  3735. "successfully.\n",
  3736. tp->dev->name, i, tp->rx_pending);
  3737. if (i == 0)
  3738. return -ENOMEM;
  3739. tp->rx_pending = i;
  3740. break;
  3741. }
  3742. }
  3743. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  3744. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  3745. if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
  3746. -1, i) < 0) {
  3747. printk(KERN_WARNING PFX
  3748. "%s: Using a smaller RX jumbo ring, "
  3749. "only %d out of %d buffers were "
  3750. "allocated successfully.\n",
  3751. tp->dev->name, i, tp->rx_jumbo_pending);
  3752. if (i == 0) {
  3753. tg3_free_rings(tp);
  3754. return -ENOMEM;
  3755. }
  3756. tp->rx_jumbo_pending = i;
  3757. break;
  3758. }
  3759. }
  3760. }
  3761. return 0;
  3762. }
  3763. /*
  3764. * Must not be invoked with interrupt sources disabled and
  3765. * the hardware shutdown down.
  3766. */
  3767. static void tg3_free_consistent(struct tg3 *tp)
  3768. {
  3769. kfree(tp->rx_std_buffers);
  3770. tp->rx_std_buffers = NULL;
  3771. if (tp->rx_std) {
  3772. pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
  3773. tp->rx_std, tp->rx_std_mapping);
  3774. tp->rx_std = NULL;
  3775. }
  3776. if (tp->rx_jumbo) {
  3777. pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  3778. tp->rx_jumbo, tp->rx_jumbo_mapping);
  3779. tp->rx_jumbo = NULL;
  3780. }
  3781. if (tp->rx_rcb) {
  3782. pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  3783. tp->rx_rcb, tp->rx_rcb_mapping);
  3784. tp->rx_rcb = NULL;
  3785. }
  3786. if (tp->tx_ring) {
  3787. pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
  3788. tp->tx_ring, tp->tx_desc_mapping);
  3789. tp->tx_ring = NULL;
  3790. }
  3791. if (tp->hw_status) {
  3792. pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
  3793. tp->hw_status, tp->status_mapping);
  3794. tp->hw_status = NULL;
  3795. }
  3796. if (tp->hw_stats) {
  3797. pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
  3798. tp->hw_stats, tp->stats_mapping);
  3799. tp->hw_stats = NULL;
  3800. }
  3801. }
  3802. /*
  3803. * Must not be invoked with interrupt sources disabled and
  3804. * the hardware shutdown down. Can sleep.
  3805. */
  3806. static int tg3_alloc_consistent(struct tg3 *tp)
  3807. {
  3808. tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
  3809. (TG3_RX_RING_SIZE +
  3810. TG3_RX_JUMBO_RING_SIZE)) +
  3811. (sizeof(struct tx_ring_info) *
  3812. TG3_TX_RING_SIZE),
  3813. GFP_KERNEL);
  3814. if (!tp->rx_std_buffers)
  3815. return -ENOMEM;
  3816. tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
  3817. tp->tx_buffers = (struct tx_ring_info *)
  3818. &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
  3819. tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
  3820. &tp->rx_std_mapping);
  3821. if (!tp->rx_std)
  3822. goto err_out;
  3823. tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  3824. &tp->rx_jumbo_mapping);
  3825. if (!tp->rx_jumbo)
  3826. goto err_out;
  3827. tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  3828. &tp->rx_rcb_mapping);
  3829. if (!tp->rx_rcb)
  3830. goto err_out;
  3831. tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
  3832. &tp->tx_desc_mapping);
  3833. if (!tp->tx_ring)
  3834. goto err_out;
  3835. tp->hw_status = pci_alloc_consistent(tp->pdev,
  3836. TG3_HW_STATUS_SIZE,
  3837. &tp->status_mapping);
  3838. if (!tp->hw_status)
  3839. goto err_out;
  3840. tp->hw_stats = pci_alloc_consistent(tp->pdev,
  3841. sizeof(struct tg3_hw_stats),
  3842. &tp->stats_mapping);
  3843. if (!tp->hw_stats)
  3844. goto err_out;
  3845. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  3846. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  3847. return 0;
  3848. err_out:
  3849. tg3_free_consistent(tp);
  3850. return -ENOMEM;
  3851. }
  3852. #define MAX_WAIT_CNT 1000
  3853. /* To stop a block, clear the enable bit and poll till it
  3854. * clears. tp->lock is held.
  3855. */
  3856. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
  3857. {
  3858. unsigned int i;
  3859. u32 val;
  3860. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  3861. switch (ofs) {
  3862. case RCVLSC_MODE:
  3863. case DMAC_MODE:
  3864. case MBFREE_MODE:
  3865. case BUFMGR_MODE:
  3866. case MEMARB_MODE:
  3867. /* We can't enable/disable these bits of the
  3868. * 5705/5750, just say success.
  3869. */
  3870. return 0;
  3871. default:
  3872. break;
  3873. };
  3874. }
  3875. val = tr32(ofs);
  3876. val &= ~enable_bit;
  3877. tw32_f(ofs, val);
  3878. for (i = 0; i < MAX_WAIT_CNT; i++) {
  3879. udelay(100);
  3880. val = tr32(ofs);
  3881. if ((val & enable_bit) == 0)
  3882. break;
  3883. }
  3884. if (i == MAX_WAIT_CNT && !silent) {
  3885. printk(KERN_ERR PFX "tg3_stop_block timed out, "
  3886. "ofs=%lx enable_bit=%x\n",
  3887. ofs, enable_bit);
  3888. return -ENODEV;
  3889. }
  3890. return 0;
  3891. }
  3892. /* tp->lock is held. */
  3893. static int tg3_abort_hw(struct tg3 *tp, int silent)
  3894. {
  3895. int i, err;
  3896. tg3_disable_ints(tp);
  3897. tp->rx_mode &= ~RX_MODE_ENABLE;
  3898. tw32_f(MAC_RX_MODE, tp->rx_mode);
  3899. udelay(10);
  3900. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  3901. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  3902. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  3903. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  3904. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  3905. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  3906. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  3907. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  3908. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  3909. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  3910. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  3911. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  3912. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  3913. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  3914. tw32_f(MAC_MODE, tp->mac_mode);
  3915. udelay(40);
  3916. tp->tx_mode &= ~TX_MODE_ENABLE;
  3917. tw32_f(MAC_TX_MODE, tp->tx_mode);
  3918. for (i = 0; i < MAX_WAIT_CNT; i++) {
  3919. udelay(100);
  3920. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  3921. break;
  3922. }
  3923. if (i >= MAX_WAIT_CNT) {
  3924. printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
  3925. "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
  3926. tp->dev->name, tr32(MAC_TX_MODE));
  3927. err |= -ENODEV;
  3928. }
  3929. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  3930. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  3931. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  3932. tw32(FTQ_RESET, 0xffffffff);
  3933. tw32(FTQ_RESET, 0x00000000);
  3934. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  3935. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  3936. if (tp->hw_status)
  3937. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  3938. if (tp->hw_stats)
  3939. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  3940. return err;
  3941. }
  3942. /* tp->lock is held. */
  3943. static int tg3_nvram_lock(struct tg3 *tp)
  3944. {
  3945. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  3946. int i;
  3947. if (tp->nvram_lock_cnt == 0) {
  3948. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  3949. for (i = 0; i < 8000; i++) {
  3950. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  3951. break;
  3952. udelay(20);
  3953. }
  3954. if (i == 8000) {
  3955. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  3956. return -ENODEV;
  3957. }
  3958. }
  3959. tp->nvram_lock_cnt++;
  3960. }
  3961. return 0;
  3962. }
  3963. /* tp->lock is held. */
  3964. static void tg3_nvram_unlock(struct tg3 *tp)
  3965. {
  3966. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  3967. if (tp->nvram_lock_cnt > 0)
  3968. tp->nvram_lock_cnt--;
  3969. if (tp->nvram_lock_cnt == 0)
  3970. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  3971. }
  3972. }
  3973. /* tp->lock is held. */
  3974. static void tg3_enable_nvram_access(struct tg3 *tp)
  3975. {
  3976. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  3977. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
  3978. u32 nvaccess = tr32(NVRAM_ACCESS);
  3979. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  3980. }
  3981. }
  3982. /* tp->lock is held. */
  3983. static void tg3_disable_nvram_access(struct tg3 *tp)
  3984. {
  3985. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  3986. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
  3987. u32 nvaccess = tr32(NVRAM_ACCESS);
  3988. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  3989. }
  3990. }
  3991. /* tp->lock is held. */
  3992. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  3993. {
  3994. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  3995. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  3996. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  3997. switch (kind) {
  3998. case RESET_KIND_INIT:
  3999. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4000. DRV_STATE_START);
  4001. break;
  4002. case RESET_KIND_SHUTDOWN:
  4003. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4004. DRV_STATE_UNLOAD);
  4005. break;
  4006. case RESET_KIND_SUSPEND:
  4007. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4008. DRV_STATE_SUSPEND);
  4009. break;
  4010. default:
  4011. break;
  4012. };
  4013. }
  4014. }
  4015. /* tp->lock is held. */
  4016. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  4017. {
  4018. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  4019. switch (kind) {
  4020. case RESET_KIND_INIT:
  4021. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4022. DRV_STATE_START_DONE);
  4023. break;
  4024. case RESET_KIND_SHUTDOWN:
  4025. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4026. DRV_STATE_UNLOAD_DONE);
  4027. break;
  4028. default:
  4029. break;
  4030. };
  4031. }
  4032. }
  4033. /* tp->lock is held. */
  4034. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  4035. {
  4036. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  4037. switch (kind) {
  4038. case RESET_KIND_INIT:
  4039. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4040. DRV_STATE_START);
  4041. break;
  4042. case RESET_KIND_SHUTDOWN:
  4043. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4044. DRV_STATE_UNLOAD);
  4045. break;
  4046. case RESET_KIND_SUSPEND:
  4047. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4048. DRV_STATE_SUSPEND);
  4049. break;
  4050. default:
  4051. break;
  4052. };
  4053. }
  4054. }
  4055. static int tg3_poll_fw(struct tg3 *tp)
  4056. {
  4057. int i;
  4058. u32 val;
  4059. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4060. /* Wait up to 20ms for init done. */
  4061. for (i = 0; i < 200; i++) {
  4062. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  4063. return 0;
  4064. udelay(100);
  4065. }
  4066. return -ENODEV;
  4067. }
  4068. /* Wait for firmware initialization to complete. */
  4069. for (i = 0; i < 100000; i++) {
  4070. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  4071. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  4072. break;
  4073. udelay(10);
  4074. }
  4075. /* Chip might not be fitted with firmware. Some Sun onboard
  4076. * parts are configured like that. So don't signal the timeout
  4077. * of the above loop as an error, but do report the lack of
  4078. * running firmware once.
  4079. */
  4080. if (i >= 100000 &&
  4081. !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
  4082. tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
  4083. printk(KERN_INFO PFX "%s: No firmware running.\n",
  4084. tp->dev->name);
  4085. }
  4086. return 0;
  4087. }
  4088. /* Save PCI command register before chip reset */
  4089. static void tg3_save_pci_state(struct tg3 *tp)
  4090. {
  4091. u32 val;
  4092. pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
  4093. tp->pci_cmd = val;
  4094. }
  4095. /* Restore PCI state after chip reset */
  4096. static void tg3_restore_pci_state(struct tg3 *tp)
  4097. {
  4098. u32 val;
  4099. /* Re-enable indirect register accesses. */
  4100. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  4101. tp->misc_host_ctrl);
  4102. /* Set MAX PCI retry to zero. */
  4103. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  4104. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  4105. (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
  4106. val |= PCISTATE_RETRY_SAME_DMA;
  4107. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  4108. pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
  4109. /* Make sure PCI-X relaxed ordering bit is clear. */
  4110. pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
  4111. val &= ~PCIX_CAPS_RELAXED_ORDERING;
  4112. pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
  4113. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  4114. u32 val;
  4115. /* Chip reset on 5780 will reset MSI enable bit,
  4116. * so need to restore it.
  4117. */
  4118. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  4119. u16 ctrl;
  4120. pci_read_config_word(tp->pdev,
  4121. tp->msi_cap + PCI_MSI_FLAGS,
  4122. &ctrl);
  4123. pci_write_config_word(tp->pdev,
  4124. tp->msi_cap + PCI_MSI_FLAGS,
  4125. ctrl | PCI_MSI_FLAGS_ENABLE);
  4126. val = tr32(MSGINT_MODE);
  4127. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  4128. }
  4129. }
  4130. }
  4131. static void tg3_stop_fw(struct tg3 *);
  4132. /* tp->lock is held. */
  4133. static int tg3_chip_reset(struct tg3 *tp)
  4134. {
  4135. u32 val;
  4136. void (*write_op)(struct tg3 *, u32, u32);
  4137. int err;
  4138. tg3_nvram_lock(tp);
  4139. /* No matching tg3_nvram_unlock() after this because
  4140. * chip reset below will undo the nvram lock.
  4141. */
  4142. tp->nvram_lock_cnt = 0;
  4143. /* GRC_MISC_CFG core clock reset will clear the memory
  4144. * enable bit in PCI register 4 and the MSI enable bit
  4145. * on some chips, so we save relevant registers here.
  4146. */
  4147. tg3_save_pci_state(tp);
  4148. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  4149. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  4150. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  4151. tw32(GRC_FASTBOOT_PC, 0);
  4152. /*
  4153. * We must avoid the readl() that normally takes place.
  4154. * It locks machines, causes machine checks, and other
  4155. * fun things. So, temporarily disable the 5701
  4156. * hardware workaround, while we do the reset.
  4157. */
  4158. write_op = tp->write32;
  4159. if (write_op == tg3_write_flush_reg32)
  4160. tp->write32 = tg3_write32;
  4161. /* Prevent the irq handler from reading or writing PCI registers
  4162. * during chip reset when the memory enable bit in the PCI command
  4163. * register may be cleared. The chip does not generate interrupt
  4164. * at this time, but the irq handler may still be called due to irq
  4165. * sharing or irqpoll.
  4166. */
  4167. tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
  4168. if (tp->hw_status) {
  4169. tp->hw_status->status = 0;
  4170. tp->hw_status->status_tag = 0;
  4171. }
  4172. tp->last_tag = 0;
  4173. smp_mb();
  4174. synchronize_irq(tp->pdev->irq);
  4175. /* do the reset */
  4176. val = GRC_MISC_CFG_CORECLK_RESET;
  4177. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  4178. if (tr32(0x7e2c) == 0x60) {
  4179. tw32(0x7e2c, 0x20);
  4180. }
  4181. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  4182. tw32(GRC_MISC_CFG, (1 << 29));
  4183. val |= (1 << 29);
  4184. }
  4185. }
  4186. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4187. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  4188. tw32(GRC_VCPU_EXT_CTRL,
  4189. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  4190. }
  4191. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  4192. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  4193. tw32(GRC_MISC_CFG, val);
  4194. /* restore 5701 hardware bug workaround write method */
  4195. tp->write32 = write_op;
  4196. /* Unfortunately, we have to delay before the PCI read back.
  4197. * Some 575X chips even will not respond to a PCI cfg access
  4198. * when the reset command is given to the chip.
  4199. *
  4200. * How do these hardware designers expect things to work
  4201. * properly if the PCI write is posted for a long period
  4202. * of time? It is always necessary to have some method by
  4203. * which a register read back can occur to push the write
  4204. * out which does the reset.
  4205. *
  4206. * For most tg3 variants the trick below was working.
  4207. * Ho hum...
  4208. */
  4209. udelay(120);
  4210. /* Flush PCI posted writes. The normal MMIO registers
  4211. * are inaccessible at this time so this is the only
  4212. * way to make this reliably (actually, this is no longer
  4213. * the case, see above). I tried to use indirect
  4214. * register read/write but this upset some 5701 variants.
  4215. */
  4216. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  4217. udelay(120);
  4218. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  4219. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
  4220. int i;
  4221. u32 cfg_val;
  4222. /* Wait for link training to complete. */
  4223. for (i = 0; i < 5000; i++)
  4224. udelay(100);
  4225. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  4226. pci_write_config_dword(tp->pdev, 0xc4,
  4227. cfg_val | (1 << 15));
  4228. }
  4229. /* Set PCIE max payload size and clear error status. */
  4230. pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
  4231. }
  4232. tg3_restore_pci_state(tp);
  4233. tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
  4234. val = 0;
  4235. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  4236. val = tr32(MEMARB_MODE);
  4237. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  4238. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
  4239. tg3_stop_fw(tp);
  4240. tw32(0x5000, 0x400);
  4241. }
  4242. tw32(GRC_MODE, tp->grc_mode);
  4243. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
  4244. u32 val = tr32(0xc4);
  4245. tw32(0xc4, val | (1 << 15));
  4246. }
  4247. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  4248. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  4249. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  4250. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
  4251. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  4252. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  4253. }
  4254. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  4255. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  4256. tw32_f(MAC_MODE, tp->mac_mode);
  4257. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  4258. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  4259. tw32_f(MAC_MODE, tp->mac_mode);
  4260. } else
  4261. tw32_f(MAC_MODE, 0);
  4262. udelay(40);
  4263. err = tg3_poll_fw(tp);
  4264. if (err)
  4265. return err;
  4266. if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  4267. tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  4268. u32 val = tr32(0x7c00);
  4269. tw32(0x7c00, val | (1 << 25));
  4270. }
  4271. /* Reprobe ASF enable state. */
  4272. tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
  4273. tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
  4274. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  4275. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  4276. u32 nic_cfg;
  4277. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  4278. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  4279. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  4280. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  4281. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  4282. }
  4283. }
  4284. return 0;
  4285. }
  4286. /* tp->lock is held. */
  4287. static void tg3_stop_fw(struct tg3 *tp)
  4288. {
  4289. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  4290. u32 val;
  4291. int i;
  4292. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  4293. val = tr32(GRC_RX_CPU_EVENT);
  4294. val |= (1 << 14);
  4295. tw32(GRC_RX_CPU_EVENT, val);
  4296. /* Wait for RX cpu to ACK the event. */
  4297. for (i = 0; i < 100; i++) {
  4298. if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
  4299. break;
  4300. udelay(1);
  4301. }
  4302. }
  4303. }
  4304. /* tp->lock is held. */
  4305. static int tg3_halt(struct tg3 *tp, int kind, int silent)
  4306. {
  4307. int err;
  4308. tg3_stop_fw(tp);
  4309. tg3_write_sig_pre_reset(tp, kind);
  4310. tg3_abort_hw(tp, silent);
  4311. err = tg3_chip_reset(tp);
  4312. tg3_write_sig_legacy(tp, kind);
  4313. tg3_write_sig_post_reset(tp, kind);
  4314. if (err)
  4315. return err;
  4316. return 0;
  4317. }
  4318. #define TG3_FW_RELEASE_MAJOR 0x0
  4319. #define TG3_FW_RELASE_MINOR 0x0
  4320. #define TG3_FW_RELEASE_FIX 0x0
  4321. #define TG3_FW_START_ADDR 0x08000000
  4322. #define TG3_FW_TEXT_ADDR 0x08000000
  4323. #define TG3_FW_TEXT_LEN 0x9c0
  4324. #define TG3_FW_RODATA_ADDR 0x080009c0
  4325. #define TG3_FW_RODATA_LEN 0x60
  4326. #define TG3_FW_DATA_ADDR 0x08000a40
  4327. #define TG3_FW_DATA_LEN 0x20
  4328. #define TG3_FW_SBSS_ADDR 0x08000a60
  4329. #define TG3_FW_SBSS_LEN 0xc
  4330. #define TG3_FW_BSS_ADDR 0x08000a70
  4331. #define TG3_FW_BSS_LEN 0x10
  4332. static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
  4333. 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
  4334. 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
  4335. 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
  4336. 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
  4337. 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
  4338. 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
  4339. 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
  4340. 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
  4341. 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
  4342. 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
  4343. 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
  4344. 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
  4345. 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
  4346. 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
  4347. 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
  4348. 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  4349. 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
  4350. 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
  4351. 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
  4352. 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  4353. 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
  4354. 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
  4355. 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  4356. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4357. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4358. 0, 0, 0, 0, 0, 0,
  4359. 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
  4360. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4361. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4362. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4363. 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
  4364. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
  4365. 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
  4366. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
  4367. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4368. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4369. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
  4370. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4371. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4372. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4373. 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
  4374. 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
  4375. 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
  4376. 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
  4377. 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
  4378. 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
  4379. 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
  4380. 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
  4381. 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
  4382. 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
  4383. 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
  4384. 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
  4385. 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
  4386. 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
  4387. 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
  4388. 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
  4389. 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
  4390. 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
  4391. 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
  4392. 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
  4393. 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
  4394. 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
  4395. 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
  4396. 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
  4397. 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
  4398. 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
  4399. 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
  4400. 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
  4401. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
  4402. 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
  4403. 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
  4404. 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
  4405. 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
  4406. 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
  4407. 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
  4408. 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
  4409. 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
  4410. 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
  4411. 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
  4412. 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
  4413. 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
  4414. 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
  4415. 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
  4416. 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
  4417. 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
  4418. 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
  4419. 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
  4420. 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
  4421. 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
  4422. 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
  4423. 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
  4424. };
  4425. static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
  4426. 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
  4427. 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
  4428. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  4429. 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
  4430. 0x00000000
  4431. };
  4432. #if 0 /* All zeros, don't eat up space with it. */
  4433. u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
  4434. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  4435. 0x00000000, 0x00000000, 0x00000000, 0x00000000
  4436. };
  4437. #endif
  4438. #define RX_CPU_SCRATCH_BASE 0x30000
  4439. #define RX_CPU_SCRATCH_SIZE 0x04000
  4440. #define TX_CPU_SCRATCH_BASE 0x34000
  4441. #define TX_CPU_SCRATCH_SIZE 0x04000
  4442. /* tp->lock is held. */
  4443. static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
  4444. {
  4445. int i;
  4446. BUG_ON(offset == TX_CPU_BASE &&
  4447. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
  4448. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4449. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  4450. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  4451. return 0;
  4452. }
  4453. if (offset == RX_CPU_BASE) {
  4454. for (i = 0; i < 10000; i++) {
  4455. tw32(offset + CPU_STATE, 0xffffffff);
  4456. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  4457. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  4458. break;
  4459. }
  4460. tw32(offset + CPU_STATE, 0xffffffff);
  4461. tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
  4462. udelay(10);
  4463. } else {
  4464. for (i = 0; i < 10000; i++) {
  4465. tw32(offset + CPU_STATE, 0xffffffff);
  4466. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  4467. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  4468. break;
  4469. }
  4470. }
  4471. if (i >= 10000) {
  4472. printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
  4473. "and %s CPU\n",
  4474. tp->dev->name,
  4475. (offset == RX_CPU_BASE ? "RX" : "TX"));
  4476. return -ENODEV;
  4477. }
  4478. /* Clear firmware's nvram arbitration. */
  4479. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  4480. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  4481. return 0;
  4482. }
  4483. struct fw_info {
  4484. unsigned int text_base;
  4485. unsigned int text_len;
  4486. const u32 *text_data;
  4487. unsigned int rodata_base;
  4488. unsigned int rodata_len;
  4489. const u32 *rodata_data;
  4490. unsigned int data_base;
  4491. unsigned int data_len;
  4492. const u32 *data_data;
  4493. };
  4494. /* tp->lock is held. */
  4495. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
  4496. int cpu_scratch_size, struct fw_info *info)
  4497. {
  4498. int err, lock_err, i;
  4499. void (*write_op)(struct tg3 *, u32, u32);
  4500. if (cpu_base == TX_CPU_BASE &&
  4501. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  4502. printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
  4503. "TX cpu firmware on %s which is 5705.\n",
  4504. tp->dev->name);
  4505. return -EINVAL;
  4506. }
  4507. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  4508. write_op = tg3_write_mem;
  4509. else
  4510. write_op = tg3_write_indirect_reg32;
  4511. /* It is possible that bootcode is still loading at this point.
  4512. * Get the nvram lock first before halting the cpu.
  4513. */
  4514. lock_err = tg3_nvram_lock(tp);
  4515. err = tg3_halt_cpu(tp, cpu_base);
  4516. if (!lock_err)
  4517. tg3_nvram_unlock(tp);
  4518. if (err)
  4519. goto out;
  4520. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  4521. write_op(tp, cpu_scratch_base + i, 0);
  4522. tw32(cpu_base + CPU_STATE, 0xffffffff);
  4523. tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  4524. for (i = 0; i < (info->text_len / sizeof(u32)); i++)
  4525. write_op(tp, (cpu_scratch_base +
  4526. (info->text_base & 0xffff) +
  4527. (i * sizeof(u32))),
  4528. (info->text_data ?
  4529. info->text_data[i] : 0));
  4530. for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
  4531. write_op(tp, (cpu_scratch_base +
  4532. (info->rodata_base & 0xffff) +
  4533. (i * sizeof(u32))),
  4534. (info->rodata_data ?
  4535. info->rodata_data[i] : 0));
  4536. for (i = 0; i < (info->data_len / sizeof(u32)); i++)
  4537. write_op(tp, (cpu_scratch_base +
  4538. (info->data_base & 0xffff) +
  4539. (i * sizeof(u32))),
  4540. (info->data_data ?
  4541. info->data_data[i] : 0));
  4542. err = 0;
  4543. out:
  4544. return err;
  4545. }
  4546. /* tp->lock is held. */
  4547. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  4548. {
  4549. struct fw_info info;
  4550. int err, i;
  4551. info.text_base = TG3_FW_TEXT_ADDR;
  4552. info.text_len = TG3_FW_TEXT_LEN;
  4553. info.text_data = &tg3FwText[0];
  4554. info.rodata_base = TG3_FW_RODATA_ADDR;
  4555. info.rodata_len = TG3_FW_RODATA_LEN;
  4556. info.rodata_data = &tg3FwRodata[0];
  4557. info.data_base = TG3_FW_DATA_ADDR;
  4558. info.data_len = TG3_FW_DATA_LEN;
  4559. info.data_data = NULL;
  4560. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  4561. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  4562. &info);
  4563. if (err)
  4564. return err;
  4565. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  4566. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  4567. &info);
  4568. if (err)
  4569. return err;
  4570. /* Now startup only the RX cpu. */
  4571. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4572. tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
  4573. for (i = 0; i < 5; i++) {
  4574. if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
  4575. break;
  4576. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4577. tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  4578. tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
  4579. udelay(1000);
  4580. }
  4581. if (i >= 5) {
  4582. printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
  4583. "to set RX CPU PC, is %08x should be %08x\n",
  4584. tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
  4585. TG3_FW_TEXT_ADDR);
  4586. return -ENODEV;
  4587. }
  4588. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4589. tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
  4590. return 0;
  4591. }
  4592. #define TG3_TSO_FW_RELEASE_MAJOR 0x1
  4593. #define TG3_TSO_FW_RELASE_MINOR 0x6
  4594. #define TG3_TSO_FW_RELEASE_FIX 0x0
  4595. #define TG3_TSO_FW_START_ADDR 0x08000000
  4596. #define TG3_TSO_FW_TEXT_ADDR 0x08000000
  4597. #define TG3_TSO_FW_TEXT_LEN 0x1aa0
  4598. #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
  4599. #define TG3_TSO_FW_RODATA_LEN 0x60
  4600. #define TG3_TSO_FW_DATA_ADDR 0x08001b20
  4601. #define TG3_TSO_FW_DATA_LEN 0x30
  4602. #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
  4603. #define TG3_TSO_FW_SBSS_LEN 0x2c
  4604. #define TG3_TSO_FW_BSS_ADDR 0x08001b80
  4605. #define TG3_TSO_FW_BSS_LEN 0x894
  4606. static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
  4607. 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
  4608. 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
  4609. 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  4610. 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
  4611. 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
  4612. 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
  4613. 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
  4614. 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
  4615. 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
  4616. 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
  4617. 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
  4618. 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
  4619. 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
  4620. 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
  4621. 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
  4622. 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
  4623. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
  4624. 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
  4625. 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
  4626. 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
  4627. 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
  4628. 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
  4629. 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
  4630. 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
  4631. 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
  4632. 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
  4633. 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
  4634. 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
  4635. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
  4636. 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  4637. 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
  4638. 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
  4639. 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
  4640. 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
  4641. 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
  4642. 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
  4643. 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
  4644. 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
  4645. 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
  4646. 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
  4647. 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
  4648. 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
  4649. 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
  4650. 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
  4651. 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
  4652. 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
  4653. 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
  4654. 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
  4655. 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
  4656. 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
  4657. 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
  4658. 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
  4659. 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
  4660. 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
  4661. 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
  4662. 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
  4663. 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
  4664. 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
  4665. 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
  4666. 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
  4667. 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
  4668. 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
  4669. 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
  4670. 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
  4671. 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
  4672. 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
  4673. 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
  4674. 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
  4675. 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
  4676. 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
  4677. 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
  4678. 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
  4679. 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
  4680. 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
  4681. 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
  4682. 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
  4683. 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
  4684. 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
  4685. 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
  4686. 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
  4687. 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
  4688. 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
  4689. 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
  4690. 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
  4691. 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
  4692. 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
  4693. 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
  4694. 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
  4695. 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
  4696. 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
  4697. 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
  4698. 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
  4699. 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
  4700. 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
  4701. 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
  4702. 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
  4703. 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
  4704. 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
  4705. 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
  4706. 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
  4707. 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
  4708. 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
  4709. 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
  4710. 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
  4711. 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
  4712. 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
  4713. 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
  4714. 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
  4715. 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
  4716. 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
  4717. 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
  4718. 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
  4719. 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
  4720. 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
  4721. 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
  4722. 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
  4723. 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
  4724. 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
  4725. 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
  4726. 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
  4727. 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
  4728. 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
  4729. 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
  4730. 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
  4731. 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
  4732. 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
  4733. 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
  4734. 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
  4735. 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
  4736. 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
  4737. 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
  4738. 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
  4739. 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
  4740. 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
  4741. 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
  4742. 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
  4743. 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
  4744. 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
  4745. 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
  4746. 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
  4747. 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
  4748. 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
  4749. 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
  4750. 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
  4751. 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
  4752. 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
  4753. 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
  4754. 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
  4755. 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
  4756. 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
  4757. 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
  4758. 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
  4759. 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
  4760. 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
  4761. 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
  4762. 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
  4763. 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
  4764. 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
  4765. 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
  4766. 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
  4767. 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
  4768. 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
  4769. 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
  4770. 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
  4771. 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
  4772. 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
  4773. 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
  4774. 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
  4775. 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
  4776. 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
  4777. 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
  4778. 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
  4779. 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
  4780. 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
  4781. 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
  4782. 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
  4783. 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
  4784. 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
  4785. 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
  4786. 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
  4787. 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
  4788. 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
  4789. 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
  4790. 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
  4791. 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
  4792. 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
  4793. 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
  4794. 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
  4795. 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
  4796. 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
  4797. 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
  4798. 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
  4799. 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
  4800. 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
  4801. 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
  4802. 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
  4803. 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
  4804. 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
  4805. 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
  4806. 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
  4807. 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
  4808. 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
  4809. 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
  4810. 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
  4811. 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
  4812. 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
  4813. 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
  4814. 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
  4815. 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
  4816. 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
  4817. 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
  4818. 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
  4819. 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
  4820. 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
  4821. 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
  4822. 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
  4823. 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
  4824. 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
  4825. 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
  4826. 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
  4827. 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
  4828. 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
  4829. 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
  4830. 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
  4831. 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
  4832. 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
  4833. 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
  4834. 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
  4835. 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
  4836. 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
  4837. 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
  4838. 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
  4839. 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
  4840. 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
  4841. 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
  4842. 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
  4843. 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
  4844. 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
  4845. 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
  4846. 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
  4847. 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
  4848. 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
  4849. 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
  4850. 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
  4851. 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
  4852. 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
  4853. 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
  4854. 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
  4855. 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
  4856. 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
  4857. 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
  4858. 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
  4859. 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
  4860. 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
  4861. 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
  4862. 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
  4863. 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
  4864. 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
  4865. 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
  4866. 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
  4867. 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
  4868. 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
  4869. 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
  4870. 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
  4871. 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
  4872. 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
  4873. 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
  4874. 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
  4875. 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
  4876. 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
  4877. 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
  4878. 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
  4879. 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
  4880. 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
  4881. 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
  4882. 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
  4883. 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
  4884. 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
  4885. 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
  4886. 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
  4887. 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
  4888. 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
  4889. 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
  4890. 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
  4891. };
  4892. static const u32 tg3TsoFwRodata[] = {
  4893. 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  4894. 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
  4895. 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
  4896. 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
  4897. 0x00000000,
  4898. };
  4899. static const u32 tg3TsoFwData[] = {
  4900. 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
  4901. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  4902. 0x00000000,
  4903. };
  4904. /* 5705 needs a special version of the TSO firmware. */
  4905. #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
  4906. #define TG3_TSO5_FW_RELASE_MINOR 0x2
  4907. #define TG3_TSO5_FW_RELEASE_FIX 0x0
  4908. #define TG3_TSO5_FW_START_ADDR 0x00010000
  4909. #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
  4910. #define TG3_TSO5_FW_TEXT_LEN 0xe90
  4911. #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
  4912. #define TG3_TSO5_FW_RODATA_LEN 0x50
  4913. #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
  4914. #define TG3_TSO5_FW_DATA_LEN 0x20
  4915. #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
  4916. #define TG3_TSO5_FW_SBSS_LEN 0x28
  4917. #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
  4918. #define TG3_TSO5_FW_BSS_LEN 0x88
  4919. static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
  4920. 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
  4921. 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
  4922. 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  4923. 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
  4924. 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
  4925. 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
  4926. 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  4927. 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
  4928. 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
  4929. 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
  4930. 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
  4931. 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
  4932. 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
  4933. 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
  4934. 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
  4935. 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
  4936. 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
  4937. 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
  4938. 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
  4939. 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
  4940. 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
  4941. 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
  4942. 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
  4943. 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
  4944. 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
  4945. 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
  4946. 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
  4947. 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
  4948. 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
  4949. 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
  4950. 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  4951. 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
  4952. 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
  4953. 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
  4954. 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
  4955. 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
  4956. 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
  4957. 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
  4958. 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
  4959. 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
  4960. 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
  4961. 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
  4962. 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
  4963. 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
  4964. 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
  4965. 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
  4966. 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
  4967. 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
  4968. 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
  4969. 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
  4970. 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
  4971. 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
  4972. 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
  4973. 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
  4974. 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
  4975. 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
  4976. 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
  4977. 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
  4978. 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
  4979. 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
  4980. 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
  4981. 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
  4982. 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
  4983. 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
  4984. 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
  4985. 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
  4986. 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  4987. 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
  4988. 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
  4989. 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
  4990. 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
  4991. 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
  4992. 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
  4993. 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
  4994. 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
  4995. 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
  4996. 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
  4997. 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
  4998. 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
  4999. 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
  5000. 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
  5001. 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
  5002. 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
  5003. 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
  5004. 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
  5005. 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
  5006. 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
  5007. 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
  5008. 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
  5009. 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
  5010. 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
  5011. 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
  5012. 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
  5013. 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
  5014. 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
  5015. 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
  5016. 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
  5017. 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
  5018. 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
  5019. 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
  5020. 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
  5021. 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
  5022. 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
  5023. 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
  5024. 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
  5025. 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
  5026. 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  5027. 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  5028. 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
  5029. 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
  5030. 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
  5031. 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
  5032. 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
  5033. 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
  5034. 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
  5035. 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
  5036. 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
  5037. 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  5038. 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  5039. 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
  5040. 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
  5041. 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
  5042. 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
  5043. 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  5044. 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
  5045. 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
  5046. 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
  5047. 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
  5048. 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
  5049. 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
  5050. 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
  5051. 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
  5052. 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
  5053. 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
  5054. 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
  5055. 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
  5056. 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
  5057. 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
  5058. 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
  5059. 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
  5060. 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
  5061. 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
  5062. 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
  5063. 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
  5064. 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
  5065. 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
  5066. 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
  5067. 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  5068. 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
  5069. 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
  5070. 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
  5071. 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  5072. 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
  5073. 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
  5074. 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  5075. 0x00000000, 0x00000000, 0x00000000,
  5076. };
  5077. static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
  5078. 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  5079. 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
  5080. 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  5081. 0x00000000, 0x00000000, 0x00000000,
  5082. };
  5083. static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
  5084. 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
  5085. 0x00000000, 0x00000000, 0x00000000,
  5086. };
  5087. /* tp->lock is held. */
  5088. static int tg3_load_tso_firmware(struct tg3 *tp)
  5089. {
  5090. struct fw_info info;
  5091. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  5092. int err, i;
  5093. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5094. return 0;
  5095. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5096. info.text_base = TG3_TSO5_FW_TEXT_ADDR;
  5097. info.text_len = TG3_TSO5_FW_TEXT_LEN;
  5098. info.text_data = &tg3Tso5FwText[0];
  5099. info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
  5100. info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
  5101. info.rodata_data = &tg3Tso5FwRodata[0];
  5102. info.data_base = TG3_TSO5_FW_DATA_ADDR;
  5103. info.data_len = TG3_TSO5_FW_DATA_LEN;
  5104. info.data_data = &tg3Tso5FwData[0];
  5105. cpu_base = RX_CPU_BASE;
  5106. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  5107. cpu_scratch_size = (info.text_len +
  5108. info.rodata_len +
  5109. info.data_len +
  5110. TG3_TSO5_FW_SBSS_LEN +
  5111. TG3_TSO5_FW_BSS_LEN);
  5112. } else {
  5113. info.text_base = TG3_TSO_FW_TEXT_ADDR;
  5114. info.text_len = TG3_TSO_FW_TEXT_LEN;
  5115. info.text_data = &tg3TsoFwText[0];
  5116. info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
  5117. info.rodata_len = TG3_TSO_FW_RODATA_LEN;
  5118. info.rodata_data = &tg3TsoFwRodata[0];
  5119. info.data_base = TG3_TSO_FW_DATA_ADDR;
  5120. info.data_len = TG3_TSO_FW_DATA_LEN;
  5121. info.data_data = &tg3TsoFwData[0];
  5122. cpu_base = TX_CPU_BASE;
  5123. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  5124. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  5125. }
  5126. err = tg3_load_firmware_cpu(tp, cpu_base,
  5127. cpu_scratch_base, cpu_scratch_size,
  5128. &info);
  5129. if (err)
  5130. return err;
  5131. /* Now startup the cpu. */
  5132. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5133. tw32_f(cpu_base + CPU_PC, info.text_base);
  5134. for (i = 0; i < 5; i++) {
  5135. if (tr32(cpu_base + CPU_PC) == info.text_base)
  5136. break;
  5137. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5138. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  5139. tw32_f(cpu_base + CPU_PC, info.text_base);
  5140. udelay(1000);
  5141. }
  5142. if (i >= 5) {
  5143. printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
  5144. "to set CPU PC, is %08x should be %08x\n",
  5145. tp->dev->name, tr32(cpu_base + CPU_PC),
  5146. info.text_base);
  5147. return -ENODEV;
  5148. }
  5149. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5150. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  5151. return 0;
  5152. }
  5153. /* tp->lock is held. */
  5154. static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
  5155. {
  5156. u32 addr_high, addr_low;
  5157. int i;
  5158. addr_high = ((tp->dev->dev_addr[0] << 8) |
  5159. tp->dev->dev_addr[1]);
  5160. addr_low = ((tp->dev->dev_addr[2] << 24) |
  5161. (tp->dev->dev_addr[3] << 16) |
  5162. (tp->dev->dev_addr[4] << 8) |
  5163. (tp->dev->dev_addr[5] << 0));
  5164. for (i = 0; i < 4; i++) {
  5165. if (i == 1 && skip_mac_1)
  5166. continue;
  5167. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  5168. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  5169. }
  5170. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  5171. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  5172. for (i = 0; i < 12; i++) {
  5173. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  5174. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  5175. }
  5176. }
  5177. addr_high = (tp->dev->dev_addr[0] +
  5178. tp->dev->dev_addr[1] +
  5179. tp->dev->dev_addr[2] +
  5180. tp->dev->dev_addr[3] +
  5181. tp->dev->dev_addr[4] +
  5182. tp->dev->dev_addr[5]) &
  5183. TX_BACKOFF_SEED_MASK;
  5184. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  5185. }
  5186. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  5187. {
  5188. struct tg3 *tp = netdev_priv(dev);
  5189. struct sockaddr *addr = p;
  5190. int err = 0, skip_mac_1 = 0;
  5191. if (!is_valid_ether_addr(addr->sa_data))
  5192. return -EINVAL;
  5193. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  5194. if (!netif_running(dev))
  5195. return 0;
  5196. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  5197. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  5198. addr0_high = tr32(MAC_ADDR_0_HIGH);
  5199. addr0_low = tr32(MAC_ADDR_0_LOW);
  5200. addr1_high = tr32(MAC_ADDR_1_HIGH);
  5201. addr1_low = tr32(MAC_ADDR_1_LOW);
  5202. /* Skip MAC addr 1 if ASF is using it. */
  5203. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  5204. !(addr1_high == 0 && addr1_low == 0))
  5205. skip_mac_1 = 1;
  5206. }
  5207. spin_lock_bh(&tp->lock);
  5208. __tg3_set_mac_addr(tp, skip_mac_1);
  5209. spin_unlock_bh(&tp->lock);
  5210. return err;
  5211. }
  5212. /* tp->lock is held. */
  5213. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  5214. dma_addr_t mapping, u32 maxlen_flags,
  5215. u32 nic_addr)
  5216. {
  5217. tg3_write_mem(tp,
  5218. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  5219. ((u64) mapping >> 32));
  5220. tg3_write_mem(tp,
  5221. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  5222. ((u64) mapping & 0xffffffff));
  5223. tg3_write_mem(tp,
  5224. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  5225. maxlen_flags);
  5226. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5227. tg3_write_mem(tp,
  5228. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  5229. nic_addr);
  5230. }
  5231. static void __tg3_set_rx_mode(struct net_device *);
  5232. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  5233. {
  5234. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  5235. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  5236. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  5237. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  5238. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5239. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  5240. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  5241. }
  5242. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  5243. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  5244. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5245. u32 val = ec->stats_block_coalesce_usecs;
  5246. if (!netif_carrier_ok(tp->dev))
  5247. val = 0;
  5248. tw32(HOSTCC_STAT_COAL_TICKS, val);
  5249. }
  5250. }
  5251. /* tp->lock is held. */
  5252. static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
  5253. {
  5254. u32 val, rdmac_mode;
  5255. int i, err, limit;
  5256. tg3_disable_ints(tp);
  5257. tg3_stop_fw(tp);
  5258. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  5259. if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
  5260. tg3_abort_hw(tp, 1);
  5261. }
  5262. if (reset_phy)
  5263. tg3_phy_reset(tp);
  5264. err = tg3_chip_reset(tp);
  5265. if (err)
  5266. return err;
  5267. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  5268. /* This works around an issue with Athlon chipsets on
  5269. * B3 tigon3 silicon. This bit has no effect on any
  5270. * other revision. But do not set this on PCI Express
  5271. * chips.
  5272. */
  5273. if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  5274. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  5275. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  5276. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  5277. (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  5278. val = tr32(TG3PCI_PCISTATE);
  5279. val |= PCISTATE_RETRY_SAME_DMA;
  5280. tw32(TG3PCI_PCISTATE, val);
  5281. }
  5282. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
  5283. /* Enable some hw fixes. */
  5284. val = tr32(TG3PCI_MSI_DATA);
  5285. val |= (1 << 26) | (1 << 28) | (1 << 29);
  5286. tw32(TG3PCI_MSI_DATA, val);
  5287. }
  5288. /* Descriptor ring init may make accesses to the
  5289. * NIC SRAM area to setup the TX descriptors, so we
  5290. * can only do this after the hardware has been
  5291. * successfully reset.
  5292. */
  5293. err = tg3_init_rings(tp);
  5294. if (err)
  5295. return err;
  5296. /* This value is determined during the probe time DMA
  5297. * engine test, tg3_test_dma.
  5298. */
  5299. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  5300. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  5301. GRC_MODE_4X_NIC_SEND_RINGS |
  5302. GRC_MODE_NO_TX_PHDR_CSUM |
  5303. GRC_MODE_NO_RX_PHDR_CSUM);
  5304. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  5305. /* Pseudo-header checksum is done by hardware logic and not
  5306. * the offload processers, so make the chip do the pseudo-
  5307. * header checksums on receive. For transmit it is more
  5308. * convenient to do the pseudo-header checksum in software
  5309. * as Linux does that on transmit for us in all cases.
  5310. */
  5311. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  5312. tw32(GRC_MODE,
  5313. tp->grc_mode |
  5314. (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
  5315. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  5316. val = tr32(GRC_MISC_CFG);
  5317. val &= ~0xff;
  5318. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  5319. tw32(GRC_MISC_CFG, val);
  5320. /* Initialize MBUF/DESC pool. */
  5321. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  5322. /* Do nothing. */
  5323. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  5324. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  5325. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  5326. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  5327. else
  5328. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  5329. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  5330. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  5331. }
  5332. else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  5333. int fw_len;
  5334. fw_len = (TG3_TSO5_FW_TEXT_LEN +
  5335. TG3_TSO5_FW_RODATA_LEN +
  5336. TG3_TSO5_FW_DATA_LEN +
  5337. TG3_TSO5_FW_SBSS_LEN +
  5338. TG3_TSO5_FW_BSS_LEN);
  5339. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  5340. tw32(BUFMGR_MB_POOL_ADDR,
  5341. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  5342. tw32(BUFMGR_MB_POOL_SIZE,
  5343. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  5344. }
  5345. if (tp->dev->mtu <= ETH_DATA_LEN) {
  5346. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  5347. tp->bufmgr_config.mbuf_read_dma_low_water);
  5348. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  5349. tp->bufmgr_config.mbuf_mac_rx_low_water);
  5350. tw32(BUFMGR_MB_HIGH_WATER,
  5351. tp->bufmgr_config.mbuf_high_water);
  5352. } else {
  5353. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  5354. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  5355. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  5356. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  5357. tw32(BUFMGR_MB_HIGH_WATER,
  5358. tp->bufmgr_config.mbuf_high_water_jumbo);
  5359. }
  5360. tw32(BUFMGR_DMA_LOW_WATER,
  5361. tp->bufmgr_config.dma_low_water);
  5362. tw32(BUFMGR_DMA_HIGH_WATER,
  5363. tp->bufmgr_config.dma_high_water);
  5364. tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
  5365. for (i = 0; i < 2000; i++) {
  5366. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  5367. break;
  5368. udelay(10);
  5369. }
  5370. if (i >= 2000) {
  5371. printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
  5372. tp->dev->name);
  5373. return -ENODEV;
  5374. }
  5375. /* Setup replenish threshold. */
  5376. val = tp->rx_pending / 8;
  5377. if (val == 0)
  5378. val = 1;
  5379. else if (val > tp->rx_std_max_post)
  5380. val = tp->rx_std_max_post;
  5381. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5382. if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
  5383. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  5384. if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
  5385. val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
  5386. }
  5387. tw32(RCVBDI_STD_THRESH, val);
  5388. /* Initialize TG3_BDINFO's at:
  5389. * RCVDBDI_STD_BD: standard eth size rx ring
  5390. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  5391. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  5392. *
  5393. * like so:
  5394. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  5395. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  5396. * ring attribute flags
  5397. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  5398. *
  5399. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  5400. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  5401. *
  5402. * The size of each ring is fixed in the firmware, but the location is
  5403. * configurable.
  5404. */
  5405. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5406. ((u64) tp->rx_std_mapping >> 32));
  5407. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  5408. ((u64) tp->rx_std_mapping & 0xffffffff));
  5409. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  5410. NIC_SRAM_RX_BUFFER_DESC);
  5411. /* Don't even try to program the JUMBO/MINI buffer descriptor
  5412. * configs on 5705.
  5413. */
  5414. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  5415. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5416. RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
  5417. } else {
  5418. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5419. RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  5420. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5421. BDINFO_FLAGS_DISABLED);
  5422. /* Setup replenish threshold. */
  5423. tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
  5424. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  5425. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5426. ((u64) tp->rx_jumbo_mapping >> 32));
  5427. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  5428. ((u64) tp->rx_jumbo_mapping & 0xffffffff));
  5429. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5430. RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  5431. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  5432. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  5433. } else {
  5434. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5435. BDINFO_FLAGS_DISABLED);
  5436. }
  5437. }
  5438. /* There is only one send ring on 5705/5750, no need to explicitly
  5439. * disable the others.
  5440. */
  5441. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5442. /* Clear out send RCB ring in SRAM. */
  5443. for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
  5444. tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  5445. BDINFO_FLAGS_DISABLED);
  5446. }
  5447. tp->tx_prod = 0;
  5448. tp->tx_cons = 0;
  5449. tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5450. tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5451. tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
  5452. tp->tx_desc_mapping,
  5453. (TG3_TX_RING_SIZE <<
  5454. BDINFO_FLAGS_MAXLEN_SHIFT),
  5455. NIC_SRAM_TX_BUFFER_DESC);
  5456. /* There is only one receive return ring on 5705/5750, no need
  5457. * to explicitly disable the others.
  5458. */
  5459. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5460. for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
  5461. i += TG3_BDINFO_SIZE) {
  5462. tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  5463. BDINFO_FLAGS_DISABLED);
  5464. }
  5465. }
  5466. tp->rx_rcb_ptr = 0;
  5467. tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5468. tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
  5469. tp->rx_rcb_mapping,
  5470. (TG3_RX_RCB_RING_SIZE(tp) <<
  5471. BDINFO_FLAGS_MAXLEN_SHIFT),
  5472. 0);
  5473. tp->rx_std_ptr = tp->rx_pending;
  5474. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  5475. tp->rx_std_ptr);
  5476. tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
  5477. tp->rx_jumbo_pending : 0;
  5478. tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  5479. tp->rx_jumbo_ptr);
  5480. /* Initialize MAC address and backoff seed. */
  5481. __tg3_set_mac_addr(tp, 0);
  5482. /* MTU + ethernet header + FCS + optional VLAN tag */
  5483. tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
  5484. /* The slot time is changed by tg3_setup_phy if we
  5485. * run at gigabit with half duplex.
  5486. */
  5487. tw32(MAC_TX_LENGTHS,
  5488. (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  5489. (6 << TX_LENGTHS_IPG_SHIFT) |
  5490. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  5491. /* Receive rules. */
  5492. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  5493. tw32(RCVLPC_CONFIG, 0x0181);
  5494. /* Calculate RDMAC_MODE setting early, we need it to determine
  5495. * the RCVLPC_STATE_ENABLE mask.
  5496. */
  5497. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  5498. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  5499. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  5500. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  5501. RDMAC_MODE_LNGREAD_ENAB);
  5502. /* If statement applies to 5705 and 5750 PCI devices only */
  5503. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  5504. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  5505. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
  5506. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
  5507. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5508. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  5509. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  5510. !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
  5511. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  5512. }
  5513. }
  5514. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  5515. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  5516. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5517. rdmac_mode |= (1 << 27);
  5518. /* Receive/send statistics. */
  5519. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  5520. val = tr32(RCVLPC_STATS_ENABLE);
  5521. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  5522. tw32(RCVLPC_STATS_ENABLE, val);
  5523. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  5524. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  5525. val = tr32(RCVLPC_STATS_ENABLE);
  5526. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  5527. tw32(RCVLPC_STATS_ENABLE, val);
  5528. } else {
  5529. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  5530. }
  5531. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  5532. tw32(SNDDATAI_STATSENAB, 0xffffff);
  5533. tw32(SNDDATAI_STATSCTRL,
  5534. (SNDDATAI_SCTRL_ENABLE |
  5535. SNDDATAI_SCTRL_FASTUPD));
  5536. /* Setup host coalescing engine. */
  5537. tw32(HOSTCC_MODE, 0);
  5538. for (i = 0; i < 2000; i++) {
  5539. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  5540. break;
  5541. udelay(10);
  5542. }
  5543. __tg3_set_coalesce(tp, &tp->coal);
  5544. /* set status block DMA address */
  5545. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5546. ((u64) tp->status_mapping >> 32));
  5547. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  5548. ((u64) tp->status_mapping & 0xffffffff));
  5549. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5550. /* Status/statistics block address. See tg3_timer,
  5551. * the tg3_periodic_fetch_stats call there, and
  5552. * tg3_get_stats to see how this works for 5705/5750 chips.
  5553. */
  5554. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5555. ((u64) tp->stats_mapping >> 32));
  5556. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  5557. ((u64) tp->stats_mapping & 0xffffffff));
  5558. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  5559. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  5560. }
  5561. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  5562. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  5563. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  5564. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5565. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  5566. /* Clear statistics/status block in chip, and status block in ram. */
  5567. for (i = NIC_SRAM_STATS_BLK;
  5568. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  5569. i += sizeof(u32)) {
  5570. tg3_write_mem(tp, i, 0);
  5571. udelay(40);
  5572. }
  5573. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  5574. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  5575. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  5576. /* reset to prevent losing 1st rx packet intermittently */
  5577. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  5578. udelay(10);
  5579. }
  5580. tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  5581. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
  5582. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  5583. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  5584. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
  5585. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  5586. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  5587. udelay(40);
  5588. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  5589. * If TG3_FLG2_IS_NIC is zero, we should read the
  5590. * register to preserve the GPIO settings for LOMs. The GPIOs,
  5591. * whether used as inputs or outputs, are set by boot code after
  5592. * reset.
  5593. */
  5594. if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
  5595. u32 gpio_mask;
  5596. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  5597. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  5598. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  5599. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  5600. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  5601. GRC_LCLCTRL_GPIO_OUTPUT3;
  5602. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  5603. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  5604. tp->grc_local_ctrl &= ~gpio_mask;
  5605. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  5606. /* GPIO1 must be driven high for eeprom write protect */
  5607. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
  5608. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  5609. GRC_LCLCTRL_GPIO_OUTPUT1);
  5610. }
  5611. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  5612. udelay(100);
  5613. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
  5614. tp->last_tag = 0;
  5615. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5616. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  5617. udelay(40);
  5618. }
  5619. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  5620. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  5621. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  5622. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  5623. WDMAC_MODE_LNGREAD_ENAB);
  5624. /* If statement applies to 5705 and 5750 PCI devices only */
  5625. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  5626. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  5627. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
  5628. if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
  5629. (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
  5630. tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
  5631. /* nothing */
  5632. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  5633. !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  5634. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  5635. val |= WDMAC_MODE_RX_ACCEL;
  5636. }
  5637. }
  5638. /* Enable host coalescing bug fix */
  5639. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
  5640. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
  5641. val |= (1 << 29);
  5642. tw32_f(WDMAC_MODE, val);
  5643. udelay(40);
  5644. if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
  5645. val = tr32(TG3PCI_X_CAPS);
  5646. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
  5647. val &= ~PCIX_CAPS_BURST_MASK;
  5648. val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
  5649. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  5650. val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
  5651. val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
  5652. }
  5653. tw32(TG3PCI_X_CAPS, val);
  5654. }
  5655. tw32_f(RDMAC_MODE, rdmac_mode);
  5656. udelay(40);
  5657. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  5658. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5659. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  5660. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  5661. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  5662. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  5663. tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
  5664. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  5665. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5666. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  5667. tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
  5668. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  5669. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  5670. err = tg3_load_5701_a0_firmware_fix(tp);
  5671. if (err)
  5672. return err;
  5673. }
  5674. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  5675. err = tg3_load_tso_firmware(tp);
  5676. if (err)
  5677. return err;
  5678. }
  5679. tp->tx_mode = TX_MODE_ENABLE;
  5680. tw32_f(MAC_TX_MODE, tp->tx_mode);
  5681. udelay(100);
  5682. tp->rx_mode = RX_MODE_ENABLE;
  5683. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  5684. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  5685. tw32_f(MAC_RX_MODE, tp->rx_mode);
  5686. udelay(10);
  5687. if (tp->link_config.phy_is_low_power) {
  5688. tp->link_config.phy_is_low_power = 0;
  5689. tp->link_config.speed = tp->link_config.orig_speed;
  5690. tp->link_config.duplex = tp->link_config.orig_duplex;
  5691. tp->link_config.autoneg = tp->link_config.orig_autoneg;
  5692. }
  5693. tp->mi_mode = MAC_MI_MODE_BASE;
  5694. tw32_f(MAC_MI_MODE, tp->mi_mode);
  5695. udelay(80);
  5696. tw32(MAC_LED_CTRL, tp->led_ctrl);
  5697. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  5698. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  5699. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  5700. udelay(10);
  5701. }
  5702. tw32_f(MAC_RX_MODE, tp->rx_mode);
  5703. udelay(10);
  5704. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  5705. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
  5706. !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
  5707. /* Set drive transmission level to 1.2V */
  5708. /* only if the signal pre-emphasis bit is not set */
  5709. val = tr32(MAC_SERDES_CFG);
  5710. val &= 0xfffff000;
  5711. val |= 0x880;
  5712. tw32(MAC_SERDES_CFG, val);
  5713. }
  5714. if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
  5715. tw32(MAC_SERDES_CFG, 0x616000);
  5716. }
  5717. /* Prevent chip from dropping frames when flow control
  5718. * is enabled.
  5719. */
  5720. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
  5721. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  5722. (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  5723. /* Use hardware link auto-negotiation */
  5724. tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
  5725. }
  5726. if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
  5727. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  5728. u32 tmp;
  5729. tmp = tr32(SERDES_RX_CTRL);
  5730. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  5731. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  5732. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  5733. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  5734. }
  5735. err = tg3_setup_phy(tp, 0);
  5736. if (err)
  5737. return err;
  5738. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  5739. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
  5740. u32 tmp;
  5741. /* Clear CRC stats. */
  5742. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  5743. tg3_writephy(tp, MII_TG3_TEST1,
  5744. tmp | MII_TG3_TEST1_CRC_EN);
  5745. tg3_readphy(tp, 0x14, &tmp);
  5746. }
  5747. }
  5748. __tg3_set_rx_mode(tp->dev);
  5749. /* Initialize receive rules. */
  5750. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  5751. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  5752. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  5753. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  5754. if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  5755. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  5756. limit = 8;
  5757. else
  5758. limit = 16;
  5759. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  5760. limit -= 4;
  5761. switch (limit) {
  5762. case 16:
  5763. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  5764. case 15:
  5765. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  5766. case 14:
  5767. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  5768. case 13:
  5769. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  5770. case 12:
  5771. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  5772. case 11:
  5773. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  5774. case 10:
  5775. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  5776. case 9:
  5777. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  5778. case 8:
  5779. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  5780. case 7:
  5781. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  5782. case 6:
  5783. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  5784. case 5:
  5785. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  5786. case 4:
  5787. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  5788. case 3:
  5789. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  5790. case 2:
  5791. case 1:
  5792. default:
  5793. break;
  5794. };
  5795. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  5796. return 0;
  5797. }
  5798. /* Called at device open time to get the chip ready for
  5799. * packet processing. Invoked with tp->lock held.
  5800. */
  5801. static int tg3_init_hw(struct tg3 *tp, int reset_phy)
  5802. {
  5803. int err;
  5804. /* Force the chip into D0. */
  5805. err = tg3_set_power_state(tp, PCI_D0);
  5806. if (err)
  5807. goto out;
  5808. tg3_switch_clocks(tp);
  5809. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  5810. err = tg3_reset_hw(tp, reset_phy);
  5811. out:
  5812. return err;
  5813. }
  5814. #define TG3_STAT_ADD32(PSTAT, REG) \
  5815. do { u32 __val = tr32(REG); \
  5816. (PSTAT)->low += __val; \
  5817. if ((PSTAT)->low < __val) \
  5818. (PSTAT)->high += 1; \
  5819. } while (0)
  5820. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  5821. {
  5822. struct tg3_hw_stats *sp = tp->hw_stats;
  5823. if (!netif_carrier_ok(tp->dev))
  5824. return;
  5825. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  5826. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  5827. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  5828. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  5829. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  5830. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  5831. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  5832. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  5833. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  5834. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  5835. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  5836. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  5837. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  5838. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  5839. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  5840. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  5841. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  5842. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  5843. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  5844. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  5845. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  5846. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  5847. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  5848. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  5849. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  5850. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  5851. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  5852. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  5853. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  5854. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  5855. }
  5856. static void tg3_timer(unsigned long __opaque)
  5857. {
  5858. struct tg3 *tp = (struct tg3 *) __opaque;
  5859. if (tp->irq_sync)
  5860. goto restart_timer;
  5861. spin_lock(&tp->lock);
  5862. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  5863. /* All of this garbage is because when using non-tagged
  5864. * IRQ status the mailbox/status_block protocol the chip
  5865. * uses with the cpu is race prone.
  5866. */
  5867. if (tp->hw_status->status & SD_STATUS_UPDATED) {
  5868. tw32(GRC_LOCAL_CTRL,
  5869. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  5870. } else {
  5871. tw32(HOSTCC_MODE, tp->coalesce_mode |
  5872. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  5873. }
  5874. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  5875. tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
  5876. spin_unlock(&tp->lock);
  5877. schedule_work(&tp->reset_task);
  5878. return;
  5879. }
  5880. }
  5881. /* This part only runs once per second. */
  5882. if (!--tp->timer_counter) {
  5883. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  5884. tg3_periodic_fetch_stats(tp);
  5885. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  5886. u32 mac_stat;
  5887. int phy_event;
  5888. mac_stat = tr32(MAC_STATUS);
  5889. phy_event = 0;
  5890. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
  5891. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  5892. phy_event = 1;
  5893. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  5894. phy_event = 1;
  5895. if (phy_event)
  5896. tg3_setup_phy(tp, 0);
  5897. } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
  5898. u32 mac_stat = tr32(MAC_STATUS);
  5899. int need_setup = 0;
  5900. if (netif_carrier_ok(tp->dev) &&
  5901. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  5902. need_setup = 1;
  5903. }
  5904. if (! netif_carrier_ok(tp->dev) &&
  5905. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  5906. MAC_STATUS_SIGNAL_DET))) {
  5907. need_setup = 1;
  5908. }
  5909. if (need_setup) {
  5910. if (!tp->serdes_counter) {
  5911. tw32_f(MAC_MODE,
  5912. (tp->mac_mode &
  5913. ~MAC_MODE_PORT_MODE_MASK));
  5914. udelay(40);
  5915. tw32_f(MAC_MODE, tp->mac_mode);
  5916. udelay(40);
  5917. }
  5918. tg3_setup_phy(tp, 0);
  5919. }
  5920. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  5921. tg3_serdes_parallel_detect(tp);
  5922. tp->timer_counter = tp->timer_multiplier;
  5923. }
  5924. /* Heartbeat is only sent once every 2 seconds.
  5925. *
  5926. * The heartbeat is to tell the ASF firmware that the host
  5927. * driver is still alive. In the event that the OS crashes,
  5928. * ASF needs to reset the hardware to free up the FIFO space
  5929. * that may be filled with rx packets destined for the host.
  5930. * If the FIFO is full, ASF will no longer function properly.
  5931. *
  5932. * Unintended resets have been reported on real time kernels
  5933. * where the timer doesn't run on time. Netpoll will also have
  5934. * same problem.
  5935. *
  5936. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  5937. * to check the ring condition when the heartbeat is expiring
  5938. * before doing the reset. This will prevent most unintended
  5939. * resets.
  5940. */
  5941. if (!--tp->asf_counter) {
  5942. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  5943. u32 val;
  5944. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  5945. FWCMD_NICDRV_ALIVE3);
  5946. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  5947. /* 5 seconds timeout */
  5948. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
  5949. val = tr32(GRC_RX_CPU_EVENT);
  5950. val |= (1 << 14);
  5951. tw32(GRC_RX_CPU_EVENT, val);
  5952. }
  5953. tp->asf_counter = tp->asf_multiplier;
  5954. }
  5955. spin_unlock(&tp->lock);
  5956. restart_timer:
  5957. tp->timer.expires = jiffies + tp->timer_offset;
  5958. add_timer(&tp->timer);
  5959. }
  5960. static int tg3_request_irq(struct tg3 *tp)
  5961. {
  5962. irq_handler_t fn;
  5963. unsigned long flags;
  5964. struct net_device *dev = tp->dev;
  5965. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  5966. fn = tg3_msi;
  5967. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  5968. fn = tg3_msi_1shot;
  5969. flags = IRQF_SAMPLE_RANDOM;
  5970. } else {
  5971. fn = tg3_interrupt;
  5972. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  5973. fn = tg3_interrupt_tagged;
  5974. flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
  5975. }
  5976. return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
  5977. }
  5978. static int tg3_test_interrupt(struct tg3 *tp)
  5979. {
  5980. struct net_device *dev = tp->dev;
  5981. int err, i, intr_ok = 0;
  5982. if (!netif_running(dev))
  5983. return -ENODEV;
  5984. tg3_disable_ints(tp);
  5985. free_irq(tp->pdev->irq, dev);
  5986. err = request_irq(tp->pdev->irq, tg3_test_isr,
  5987. IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
  5988. if (err)
  5989. return err;
  5990. tp->hw_status->status &= ~SD_STATUS_UPDATED;
  5991. tg3_enable_ints(tp);
  5992. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  5993. HOSTCC_MODE_NOW);
  5994. for (i = 0; i < 5; i++) {
  5995. u32 int_mbox, misc_host_ctrl;
  5996. int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
  5997. TG3_64BIT_REG_LOW);
  5998. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  5999. if ((int_mbox != 0) ||
  6000. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  6001. intr_ok = 1;
  6002. break;
  6003. }
  6004. msleep(10);
  6005. }
  6006. tg3_disable_ints(tp);
  6007. free_irq(tp->pdev->irq, dev);
  6008. err = tg3_request_irq(tp);
  6009. if (err)
  6010. return err;
  6011. if (intr_ok)
  6012. return 0;
  6013. return -EIO;
  6014. }
  6015. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  6016. * successfully restored
  6017. */
  6018. static int tg3_test_msi(struct tg3 *tp)
  6019. {
  6020. struct net_device *dev = tp->dev;
  6021. int err;
  6022. u16 pci_cmd;
  6023. if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
  6024. return 0;
  6025. /* Turn off SERR reporting in case MSI terminates with Master
  6026. * Abort.
  6027. */
  6028. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  6029. pci_write_config_word(tp->pdev, PCI_COMMAND,
  6030. pci_cmd & ~PCI_COMMAND_SERR);
  6031. err = tg3_test_interrupt(tp);
  6032. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  6033. if (!err)
  6034. return 0;
  6035. /* other failures */
  6036. if (err != -EIO)
  6037. return err;
  6038. /* MSI test failed, go back to INTx mode */
  6039. printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
  6040. "switching to INTx mode. Please report this failure to "
  6041. "the PCI maintainer and include system chipset information.\n",
  6042. tp->dev->name);
  6043. free_irq(tp->pdev->irq, dev);
  6044. pci_disable_msi(tp->pdev);
  6045. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6046. err = tg3_request_irq(tp);
  6047. if (err)
  6048. return err;
  6049. /* Need to reset the chip because the MSI cycle may have terminated
  6050. * with Master Abort.
  6051. */
  6052. tg3_full_lock(tp, 1);
  6053. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6054. err = tg3_init_hw(tp, 1);
  6055. tg3_full_unlock(tp);
  6056. if (err)
  6057. free_irq(tp->pdev->irq, dev);
  6058. return err;
  6059. }
  6060. static int tg3_open(struct net_device *dev)
  6061. {
  6062. struct tg3 *tp = netdev_priv(dev);
  6063. int err;
  6064. netif_carrier_off(tp->dev);
  6065. tg3_full_lock(tp, 0);
  6066. err = tg3_set_power_state(tp, PCI_D0);
  6067. if (err) {
  6068. tg3_full_unlock(tp);
  6069. return err;
  6070. }
  6071. tg3_disable_ints(tp);
  6072. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  6073. tg3_full_unlock(tp);
  6074. /* The placement of this call is tied
  6075. * to the setup and use of Host TX descriptors.
  6076. */
  6077. err = tg3_alloc_consistent(tp);
  6078. if (err)
  6079. return err;
  6080. if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
  6081. /* All MSI supporting chips should support tagged
  6082. * status. Assert that this is the case.
  6083. */
  6084. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  6085. printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
  6086. "Not using MSI.\n", tp->dev->name);
  6087. } else if (pci_enable_msi(tp->pdev) == 0) {
  6088. u32 msi_mode;
  6089. msi_mode = tr32(MSGINT_MODE);
  6090. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  6091. tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
  6092. }
  6093. }
  6094. err = tg3_request_irq(tp);
  6095. if (err) {
  6096. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6097. pci_disable_msi(tp->pdev);
  6098. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6099. }
  6100. tg3_free_consistent(tp);
  6101. return err;
  6102. }
  6103. tg3_full_lock(tp, 0);
  6104. err = tg3_init_hw(tp, 1);
  6105. if (err) {
  6106. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6107. tg3_free_rings(tp);
  6108. } else {
  6109. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  6110. tp->timer_offset = HZ;
  6111. else
  6112. tp->timer_offset = HZ / 10;
  6113. BUG_ON(tp->timer_offset > HZ);
  6114. tp->timer_counter = tp->timer_multiplier =
  6115. (HZ / tp->timer_offset);
  6116. tp->asf_counter = tp->asf_multiplier =
  6117. ((HZ / tp->timer_offset) * 2);
  6118. init_timer(&tp->timer);
  6119. tp->timer.expires = jiffies + tp->timer_offset;
  6120. tp->timer.data = (unsigned long) tp;
  6121. tp->timer.function = tg3_timer;
  6122. }
  6123. tg3_full_unlock(tp);
  6124. if (err) {
  6125. free_irq(tp->pdev->irq, dev);
  6126. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6127. pci_disable_msi(tp->pdev);
  6128. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6129. }
  6130. tg3_free_consistent(tp);
  6131. return err;
  6132. }
  6133. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6134. err = tg3_test_msi(tp);
  6135. if (err) {
  6136. tg3_full_lock(tp, 0);
  6137. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6138. pci_disable_msi(tp->pdev);
  6139. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6140. }
  6141. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6142. tg3_free_rings(tp);
  6143. tg3_free_consistent(tp);
  6144. tg3_full_unlock(tp);
  6145. return err;
  6146. }
  6147. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6148. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
  6149. u32 val = tr32(PCIE_TRANSACTION_CFG);
  6150. tw32(PCIE_TRANSACTION_CFG,
  6151. val | PCIE_TRANS_CFG_1SHOT_MSI);
  6152. }
  6153. }
  6154. }
  6155. tg3_full_lock(tp, 0);
  6156. add_timer(&tp->timer);
  6157. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  6158. tg3_enable_ints(tp);
  6159. tg3_full_unlock(tp);
  6160. netif_start_queue(dev);
  6161. return 0;
  6162. }
  6163. #if 0
  6164. /*static*/ void tg3_dump_state(struct tg3 *tp)
  6165. {
  6166. u32 val32, val32_2, val32_3, val32_4, val32_5;
  6167. u16 val16;
  6168. int i;
  6169. pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
  6170. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
  6171. printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
  6172. val16, val32);
  6173. /* MAC block */
  6174. printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
  6175. tr32(MAC_MODE), tr32(MAC_STATUS));
  6176. printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
  6177. tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
  6178. printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
  6179. tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
  6180. printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
  6181. tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
  6182. /* Send data initiator control block */
  6183. printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
  6184. tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
  6185. printk(" SNDDATAI_STATSCTRL[%08x]\n",
  6186. tr32(SNDDATAI_STATSCTRL));
  6187. /* Send data completion control block */
  6188. printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
  6189. /* Send BD ring selector block */
  6190. printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
  6191. tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
  6192. /* Send BD initiator control block */
  6193. printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
  6194. tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
  6195. /* Send BD completion control block */
  6196. printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
  6197. /* Receive list placement control block */
  6198. printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
  6199. tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
  6200. printk(" RCVLPC_STATSCTRL[%08x]\n",
  6201. tr32(RCVLPC_STATSCTRL));
  6202. /* Receive data and receive BD initiator control block */
  6203. printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
  6204. tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
  6205. /* Receive data completion control block */
  6206. printk("DEBUG: RCVDCC_MODE[%08x]\n",
  6207. tr32(RCVDCC_MODE));
  6208. /* Receive BD initiator control block */
  6209. printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
  6210. tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
  6211. /* Receive BD completion control block */
  6212. printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
  6213. tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
  6214. /* Receive list selector control block */
  6215. printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
  6216. tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
  6217. /* Mbuf cluster free block */
  6218. printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
  6219. tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
  6220. /* Host coalescing control block */
  6221. printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
  6222. tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
  6223. printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
  6224. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6225. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  6226. printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
  6227. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6228. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  6229. printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
  6230. tr32(HOSTCC_STATS_BLK_NIC_ADDR));
  6231. printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
  6232. tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
  6233. /* Memory arbiter control block */
  6234. printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
  6235. tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
  6236. /* Buffer manager control block */
  6237. printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
  6238. tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
  6239. printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
  6240. tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
  6241. printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
  6242. "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
  6243. tr32(BUFMGR_DMA_DESC_POOL_ADDR),
  6244. tr32(BUFMGR_DMA_DESC_POOL_SIZE));
  6245. /* Read DMA control block */
  6246. printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
  6247. tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
  6248. /* Write DMA control block */
  6249. printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
  6250. tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
  6251. /* DMA completion block */
  6252. printk("DEBUG: DMAC_MODE[%08x]\n",
  6253. tr32(DMAC_MODE));
  6254. /* GRC block */
  6255. printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
  6256. tr32(GRC_MODE), tr32(GRC_MISC_CFG));
  6257. printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
  6258. tr32(GRC_LOCAL_CTRL));
  6259. /* TG3_BDINFOs */
  6260. printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
  6261. tr32(RCVDBDI_JUMBO_BD + 0x0),
  6262. tr32(RCVDBDI_JUMBO_BD + 0x4),
  6263. tr32(RCVDBDI_JUMBO_BD + 0x8),
  6264. tr32(RCVDBDI_JUMBO_BD + 0xc));
  6265. printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
  6266. tr32(RCVDBDI_STD_BD + 0x0),
  6267. tr32(RCVDBDI_STD_BD + 0x4),
  6268. tr32(RCVDBDI_STD_BD + 0x8),
  6269. tr32(RCVDBDI_STD_BD + 0xc));
  6270. printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
  6271. tr32(RCVDBDI_MINI_BD + 0x0),
  6272. tr32(RCVDBDI_MINI_BD + 0x4),
  6273. tr32(RCVDBDI_MINI_BD + 0x8),
  6274. tr32(RCVDBDI_MINI_BD + 0xc));
  6275. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
  6276. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
  6277. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
  6278. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
  6279. printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
  6280. val32, val32_2, val32_3, val32_4);
  6281. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
  6282. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
  6283. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
  6284. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
  6285. printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
  6286. val32, val32_2, val32_3, val32_4);
  6287. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
  6288. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
  6289. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
  6290. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
  6291. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
  6292. printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
  6293. val32, val32_2, val32_3, val32_4, val32_5);
  6294. /* SW status block */
  6295. printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  6296. tp->hw_status->status,
  6297. tp->hw_status->status_tag,
  6298. tp->hw_status->rx_jumbo_consumer,
  6299. tp->hw_status->rx_consumer,
  6300. tp->hw_status->rx_mini_consumer,
  6301. tp->hw_status->idx[0].rx_producer,
  6302. tp->hw_status->idx[0].tx_consumer);
  6303. /* SW statistics block */
  6304. printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
  6305. ((u32 *)tp->hw_stats)[0],
  6306. ((u32 *)tp->hw_stats)[1],
  6307. ((u32 *)tp->hw_stats)[2],
  6308. ((u32 *)tp->hw_stats)[3]);
  6309. /* Mailboxes */
  6310. printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
  6311. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
  6312. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
  6313. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
  6314. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
  6315. /* NIC side send descriptors. */
  6316. for (i = 0; i < 6; i++) {
  6317. unsigned long txd;
  6318. txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
  6319. + (i * sizeof(struct tg3_tx_buffer_desc));
  6320. printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
  6321. i,
  6322. readl(txd + 0x0), readl(txd + 0x4),
  6323. readl(txd + 0x8), readl(txd + 0xc));
  6324. }
  6325. /* NIC side RX descriptors. */
  6326. for (i = 0; i < 6; i++) {
  6327. unsigned long rxd;
  6328. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
  6329. + (i * sizeof(struct tg3_rx_buffer_desc));
  6330. printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
  6331. i,
  6332. readl(rxd + 0x0), readl(rxd + 0x4),
  6333. readl(rxd + 0x8), readl(rxd + 0xc));
  6334. rxd += (4 * sizeof(u32));
  6335. printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
  6336. i,
  6337. readl(rxd + 0x0), readl(rxd + 0x4),
  6338. readl(rxd + 0x8), readl(rxd + 0xc));
  6339. }
  6340. for (i = 0; i < 6; i++) {
  6341. unsigned long rxd;
  6342. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
  6343. + (i * sizeof(struct tg3_rx_buffer_desc));
  6344. printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
  6345. i,
  6346. readl(rxd + 0x0), readl(rxd + 0x4),
  6347. readl(rxd + 0x8), readl(rxd + 0xc));
  6348. rxd += (4 * sizeof(u32));
  6349. printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
  6350. i,
  6351. readl(rxd + 0x0), readl(rxd + 0x4),
  6352. readl(rxd + 0x8), readl(rxd + 0xc));
  6353. }
  6354. }
  6355. #endif
  6356. static struct net_device_stats *tg3_get_stats(struct net_device *);
  6357. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
  6358. static int tg3_close(struct net_device *dev)
  6359. {
  6360. struct tg3 *tp = netdev_priv(dev);
  6361. cancel_work_sync(&tp->reset_task);
  6362. netif_stop_queue(dev);
  6363. del_timer_sync(&tp->timer);
  6364. tg3_full_lock(tp, 1);
  6365. #if 0
  6366. tg3_dump_state(tp);
  6367. #endif
  6368. tg3_disable_ints(tp);
  6369. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6370. tg3_free_rings(tp);
  6371. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  6372. tg3_full_unlock(tp);
  6373. free_irq(tp->pdev->irq, dev);
  6374. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6375. pci_disable_msi(tp->pdev);
  6376. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6377. }
  6378. memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
  6379. sizeof(tp->net_stats_prev));
  6380. memcpy(&tp->estats_prev, tg3_get_estats(tp),
  6381. sizeof(tp->estats_prev));
  6382. tg3_free_consistent(tp);
  6383. tg3_set_power_state(tp, PCI_D3hot);
  6384. netif_carrier_off(tp->dev);
  6385. return 0;
  6386. }
  6387. static inline unsigned long get_stat64(tg3_stat64_t *val)
  6388. {
  6389. unsigned long ret;
  6390. #if (BITS_PER_LONG == 32)
  6391. ret = val->low;
  6392. #else
  6393. ret = ((u64)val->high << 32) | ((u64)val->low);
  6394. #endif
  6395. return ret;
  6396. }
  6397. static unsigned long calc_crc_errors(struct tg3 *tp)
  6398. {
  6399. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6400. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  6401. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  6402. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  6403. u32 val;
  6404. spin_lock_bh(&tp->lock);
  6405. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  6406. tg3_writephy(tp, MII_TG3_TEST1,
  6407. val | MII_TG3_TEST1_CRC_EN);
  6408. tg3_readphy(tp, 0x14, &val);
  6409. } else
  6410. val = 0;
  6411. spin_unlock_bh(&tp->lock);
  6412. tp->phy_crc_errors += val;
  6413. return tp->phy_crc_errors;
  6414. }
  6415. return get_stat64(&hw_stats->rx_fcs_errors);
  6416. }
  6417. #define ESTAT_ADD(member) \
  6418. estats->member = old_estats->member + \
  6419. get_stat64(&hw_stats->member)
  6420. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
  6421. {
  6422. struct tg3_ethtool_stats *estats = &tp->estats;
  6423. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  6424. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6425. if (!hw_stats)
  6426. return old_estats;
  6427. ESTAT_ADD(rx_octets);
  6428. ESTAT_ADD(rx_fragments);
  6429. ESTAT_ADD(rx_ucast_packets);
  6430. ESTAT_ADD(rx_mcast_packets);
  6431. ESTAT_ADD(rx_bcast_packets);
  6432. ESTAT_ADD(rx_fcs_errors);
  6433. ESTAT_ADD(rx_align_errors);
  6434. ESTAT_ADD(rx_xon_pause_rcvd);
  6435. ESTAT_ADD(rx_xoff_pause_rcvd);
  6436. ESTAT_ADD(rx_mac_ctrl_rcvd);
  6437. ESTAT_ADD(rx_xoff_entered);
  6438. ESTAT_ADD(rx_frame_too_long_errors);
  6439. ESTAT_ADD(rx_jabbers);
  6440. ESTAT_ADD(rx_undersize_packets);
  6441. ESTAT_ADD(rx_in_length_errors);
  6442. ESTAT_ADD(rx_out_length_errors);
  6443. ESTAT_ADD(rx_64_or_less_octet_packets);
  6444. ESTAT_ADD(rx_65_to_127_octet_packets);
  6445. ESTAT_ADD(rx_128_to_255_octet_packets);
  6446. ESTAT_ADD(rx_256_to_511_octet_packets);
  6447. ESTAT_ADD(rx_512_to_1023_octet_packets);
  6448. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  6449. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  6450. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  6451. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  6452. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  6453. ESTAT_ADD(tx_octets);
  6454. ESTAT_ADD(tx_collisions);
  6455. ESTAT_ADD(tx_xon_sent);
  6456. ESTAT_ADD(tx_xoff_sent);
  6457. ESTAT_ADD(tx_flow_control);
  6458. ESTAT_ADD(tx_mac_errors);
  6459. ESTAT_ADD(tx_single_collisions);
  6460. ESTAT_ADD(tx_mult_collisions);
  6461. ESTAT_ADD(tx_deferred);
  6462. ESTAT_ADD(tx_excessive_collisions);
  6463. ESTAT_ADD(tx_late_collisions);
  6464. ESTAT_ADD(tx_collide_2times);
  6465. ESTAT_ADD(tx_collide_3times);
  6466. ESTAT_ADD(tx_collide_4times);
  6467. ESTAT_ADD(tx_collide_5times);
  6468. ESTAT_ADD(tx_collide_6times);
  6469. ESTAT_ADD(tx_collide_7times);
  6470. ESTAT_ADD(tx_collide_8times);
  6471. ESTAT_ADD(tx_collide_9times);
  6472. ESTAT_ADD(tx_collide_10times);
  6473. ESTAT_ADD(tx_collide_11times);
  6474. ESTAT_ADD(tx_collide_12times);
  6475. ESTAT_ADD(tx_collide_13times);
  6476. ESTAT_ADD(tx_collide_14times);
  6477. ESTAT_ADD(tx_collide_15times);
  6478. ESTAT_ADD(tx_ucast_packets);
  6479. ESTAT_ADD(tx_mcast_packets);
  6480. ESTAT_ADD(tx_bcast_packets);
  6481. ESTAT_ADD(tx_carrier_sense_errors);
  6482. ESTAT_ADD(tx_discards);
  6483. ESTAT_ADD(tx_errors);
  6484. ESTAT_ADD(dma_writeq_full);
  6485. ESTAT_ADD(dma_write_prioq_full);
  6486. ESTAT_ADD(rxbds_empty);
  6487. ESTAT_ADD(rx_discards);
  6488. ESTAT_ADD(rx_errors);
  6489. ESTAT_ADD(rx_threshold_hit);
  6490. ESTAT_ADD(dma_readq_full);
  6491. ESTAT_ADD(dma_read_prioq_full);
  6492. ESTAT_ADD(tx_comp_queue_full);
  6493. ESTAT_ADD(ring_set_send_prod_index);
  6494. ESTAT_ADD(ring_status_update);
  6495. ESTAT_ADD(nic_irqs);
  6496. ESTAT_ADD(nic_avoided_irqs);
  6497. ESTAT_ADD(nic_tx_threshold_hit);
  6498. return estats;
  6499. }
  6500. static struct net_device_stats *tg3_get_stats(struct net_device *dev)
  6501. {
  6502. struct tg3 *tp = netdev_priv(dev);
  6503. struct net_device_stats *stats = &tp->net_stats;
  6504. struct net_device_stats *old_stats = &tp->net_stats_prev;
  6505. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6506. if (!hw_stats)
  6507. return old_stats;
  6508. stats->rx_packets = old_stats->rx_packets +
  6509. get_stat64(&hw_stats->rx_ucast_packets) +
  6510. get_stat64(&hw_stats->rx_mcast_packets) +
  6511. get_stat64(&hw_stats->rx_bcast_packets);
  6512. stats->tx_packets = old_stats->tx_packets +
  6513. get_stat64(&hw_stats->tx_ucast_packets) +
  6514. get_stat64(&hw_stats->tx_mcast_packets) +
  6515. get_stat64(&hw_stats->tx_bcast_packets);
  6516. stats->rx_bytes = old_stats->rx_bytes +
  6517. get_stat64(&hw_stats->rx_octets);
  6518. stats->tx_bytes = old_stats->tx_bytes +
  6519. get_stat64(&hw_stats->tx_octets);
  6520. stats->rx_errors = old_stats->rx_errors +
  6521. get_stat64(&hw_stats->rx_errors);
  6522. stats->tx_errors = old_stats->tx_errors +
  6523. get_stat64(&hw_stats->tx_errors) +
  6524. get_stat64(&hw_stats->tx_mac_errors) +
  6525. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  6526. get_stat64(&hw_stats->tx_discards);
  6527. stats->multicast = old_stats->multicast +
  6528. get_stat64(&hw_stats->rx_mcast_packets);
  6529. stats->collisions = old_stats->collisions +
  6530. get_stat64(&hw_stats->tx_collisions);
  6531. stats->rx_length_errors = old_stats->rx_length_errors +
  6532. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  6533. get_stat64(&hw_stats->rx_undersize_packets);
  6534. stats->rx_over_errors = old_stats->rx_over_errors +
  6535. get_stat64(&hw_stats->rxbds_empty);
  6536. stats->rx_frame_errors = old_stats->rx_frame_errors +
  6537. get_stat64(&hw_stats->rx_align_errors);
  6538. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  6539. get_stat64(&hw_stats->tx_discards);
  6540. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  6541. get_stat64(&hw_stats->tx_carrier_sense_errors);
  6542. stats->rx_crc_errors = old_stats->rx_crc_errors +
  6543. calc_crc_errors(tp);
  6544. stats->rx_missed_errors = old_stats->rx_missed_errors +
  6545. get_stat64(&hw_stats->rx_discards);
  6546. return stats;
  6547. }
  6548. static inline u32 calc_crc(unsigned char *buf, int len)
  6549. {
  6550. u32 reg;
  6551. u32 tmp;
  6552. int j, k;
  6553. reg = 0xffffffff;
  6554. for (j = 0; j < len; j++) {
  6555. reg ^= buf[j];
  6556. for (k = 0; k < 8; k++) {
  6557. tmp = reg & 0x01;
  6558. reg >>= 1;
  6559. if (tmp) {
  6560. reg ^= 0xedb88320;
  6561. }
  6562. }
  6563. }
  6564. return ~reg;
  6565. }
  6566. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  6567. {
  6568. /* accept or reject all multicast frames */
  6569. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  6570. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  6571. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  6572. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  6573. }
  6574. static void __tg3_set_rx_mode(struct net_device *dev)
  6575. {
  6576. struct tg3 *tp = netdev_priv(dev);
  6577. u32 rx_mode;
  6578. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  6579. RX_MODE_KEEP_VLAN_TAG);
  6580. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  6581. * flag clear.
  6582. */
  6583. #if TG3_VLAN_TAG_USED
  6584. if (!tp->vlgrp &&
  6585. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  6586. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  6587. #else
  6588. /* By definition, VLAN is disabled always in this
  6589. * case.
  6590. */
  6591. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  6592. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  6593. #endif
  6594. if (dev->flags & IFF_PROMISC) {
  6595. /* Promiscuous mode. */
  6596. rx_mode |= RX_MODE_PROMISC;
  6597. } else if (dev->flags & IFF_ALLMULTI) {
  6598. /* Accept all multicast. */
  6599. tg3_set_multi (tp, 1);
  6600. } else if (dev->mc_count < 1) {
  6601. /* Reject all multicast. */
  6602. tg3_set_multi (tp, 0);
  6603. } else {
  6604. /* Accept one or more multicast(s). */
  6605. struct dev_mc_list *mclist;
  6606. unsigned int i;
  6607. u32 mc_filter[4] = { 0, };
  6608. u32 regidx;
  6609. u32 bit;
  6610. u32 crc;
  6611. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  6612. i++, mclist = mclist->next) {
  6613. crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
  6614. bit = ~crc & 0x7f;
  6615. regidx = (bit & 0x60) >> 5;
  6616. bit &= 0x1f;
  6617. mc_filter[regidx] |= (1 << bit);
  6618. }
  6619. tw32(MAC_HASH_REG_0, mc_filter[0]);
  6620. tw32(MAC_HASH_REG_1, mc_filter[1]);
  6621. tw32(MAC_HASH_REG_2, mc_filter[2]);
  6622. tw32(MAC_HASH_REG_3, mc_filter[3]);
  6623. }
  6624. if (rx_mode != tp->rx_mode) {
  6625. tp->rx_mode = rx_mode;
  6626. tw32_f(MAC_RX_MODE, rx_mode);
  6627. udelay(10);
  6628. }
  6629. }
  6630. static void tg3_set_rx_mode(struct net_device *dev)
  6631. {
  6632. struct tg3 *tp = netdev_priv(dev);
  6633. if (!netif_running(dev))
  6634. return;
  6635. tg3_full_lock(tp, 0);
  6636. __tg3_set_rx_mode(dev);
  6637. tg3_full_unlock(tp);
  6638. }
  6639. #define TG3_REGDUMP_LEN (32 * 1024)
  6640. static int tg3_get_regs_len(struct net_device *dev)
  6641. {
  6642. return TG3_REGDUMP_LEN;
  6643. }
  6644. static void tg3_get_regs(struct net_device *dev,
  6645. struct ethtool_regs *regs, void *_p)
  6646. {
  6647. u32 *p = _p;
  6648. struct tg3 *tp = netdev_priv(dev);
  6649. u8 *orig_p = _p;
  6650. int i;
  6651. regs->version = 0;
  6652. memset(p, 0, TG3_REGDUMP_LEN);
  6653. if (tp->link_config.phy_is_low_power)
  6654. return;
  6655. tg3_full_lock(tp, 0);
  6656. #define __GET_REG32(reg) (*(p)++ = tr32(reg))
  6657. #define GET_REG32_LOOP(base,len) \
  6658. do { p = (u32 *)(orig_p + (base)); \
  6659. for (i = 0; i < len; i += 4) \
  6660. __GET_REG32((base) + i); \
  6661. } while (0)
  6662. #define GET_REG32_1(reg) \
  6663. do { p = (u32 *)(orig_p + (reg)); \
  6664. __GET_REG32((reg)); \
  6665. } while (0)
  6666. GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
  6667. GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
  6668. GET_REG32_LOOP(MAC_MODE, 0x4f0);
  6669. GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
  6670. GET_REG32_1(SNDDATAC_MODE);
  6671. GET_REG32_LOOP(SNDBDS_MODE, 0x80);
  6672. GET_REG32_LOOP(SNDBDI_MODE, 0x48);
  6673. GET_REG32_1(SNDBDC_MODE);
  6674. GET_REG32_LOOP(RCVLPC_MODE, 0x20);
  6675. GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
  6676. GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
  6677. GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
  6678. GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
  6679. GET_REG32_1(RCVDCC_MODE);
  6680. GET_REG32_LOOP(RCVBDI_MODE, 0x20);
  6681. GET_REG32_LOOP(RCVCC_MODE, 0x14);
  6682. GET_REG32_LOOP(RCVLSC_MODE, 0x08);
  6683. GET_REG32_1(MBFREE_MODE);
  6684. GET_REG32_LOOP(HOSTCC_MODE, 0x100);
  6685. GET_REG32_LOOP(MEMARB_MODE, 0x10);
  6686. GET_REG32_LOOP(BUFMGR_MODE, 0x58);
  6687. GET_REG32_LOOP(RDMAC_MODE, 0x08);
  6688. GET_REG32_LOOP(WDMAC_MODE, 0x08);
  6689. GET_REG32_1(RX_CPU_MODE);
  6690. GET_REG32_1(RX_CPU_STATE);
  6691. GET_REG32_1(RX_CPU_PGMCTR);
  6692. GET_REG32_1(RX_CPU_HWBKPT);
  6693. GET_REG32_1(TX_CPU_MODE);
  6694. GET_REG32_1(TX_CPU_STATE);
  6695. GET_REG32_1(TX_CPU_PGMCTR);
  6696. GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
  6697. GET_REG32_LOOP(FTQ_RESET, 0x120);
  6698. GET_REG32_LOOP(MSGINT_MODE, 0x0c);
  6699. GET_REG32_1(DMAC_MODE);
  6700. GET_REG32_LOOP(GRC_MODE, 0x4c);
  6701. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  6702. GET_REG32_LOOP(NVRAM_CMD, 0x24);
  6703. #undef __GET_REG32
  6704. #undef GET_REG32_LOOP
  6705. #undef GET_REG32_1
  6706. tg3_full_unlock(tp);
  6707. }
  6708. static int tg3_get_eeprom_len(struct net_device *dev)
  6709. {
  6710. struct tg3 *tp = netdev_priv(dev);
  6711. return tp->nvram_size;
  6712. }
  6713. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
  6714. static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
  6715. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  6716. {
  6717. struct tg3 *tp = netdev_priv(dev);
  6718. int ret;
  6719. u8 *pd;
  6720. u32 i, offset, len, val, b_offset, b_count;
  6721. if (tp->link_config.phy_is_low_power)
  6722. return -EAGAIN;
  6723. offset = eeprom->offset;
  6724. len = eeprom->len;
  6725. eeprom->len = 0;
  6726. eeprom->magic = TG3_EEPROM_MAGIC;
  6727. if (offset & 3) {
  6728. /* adjustments to start on required 4 byte boundary */
  6729. b_offset = offset & 3;
  6730. b_count = 4 - b_offset;
  6731. if (b_count > len) {
  6732. /* i.e. offset=1 len=2 */
  6733. b_count = len;
  6734. }
  6735. ret = tg3_nvram_read(tp, offset-b_offset, &val);
  6736. if (ret)
  6737. return ret;
  6738. val = cpu_to_le32(val);
  6739. memcpy(data, ((char*)&val) + b_offset, b_count);
  6740. len -= b_count;
  6741. offset += b_count;
  6742. eeprom->len += b_count;
  6743. }
  6744. /* read bytes upto the last 4 byte boundary */
  6745. pd = &data[eeprom->len];
  6746. for (i = 0; i < (len - (len & 3)); i += 4) {
  6747. ret = tg3_nvram_read(tp, offset + i, &val);
  6748. if (ret) {
  6749. eeprom->len += i;
  6750. return ret;
  6751. }
  6752. val = cpu_to_le32(val);
  6753. memcpy(pd + i, &val, 4);
  6754. }
  6755. eeprom->len += i;
  6756. if (len & 3) {
  6757. /* read last bytes not ending on 4 byte boundary */
  6758. pd = &data[eeprom->len];
  6759. b_count = len & 3;
  6760. b_offset = offset + len - b_count;
  6761. ret = tg3_nvram_read(tp, b_offset, &val);
  6762. if (ret)
  6763. return ret;
  6764. val = cpu_to_le32(val);
  6765. memcpy(pd, ((char*)&val), b_count);
  6766. eeprom->len += b_count;
  6767. }
  6768. return 0;
  6769. }
  6770. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
  6771. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  6772. {
  6773. struct tg3 *tp = netdev_priv(dev);
  6774. int ret;
  6775. u32 offset, len, b_offset, odd_len, start, end;
  6776. u8 *buf;
  6777. if (tp->link_config.phy_is_low_power)
  6778. return -EAGAIN;
  6779. if (eeprom->magic != TG3_EEPROM_MAGIC)
  6780. return -EINVAL;
  6781. offset = eeprom->offset;
  6782. len = eeprom->len;
  6783. if ((b_offset = (offset & 3))) {
  6784. /* adjustments to start on required 4 byte boundary */
  6785. ret = tg3_nvram_read(tp, offset-b_offset, &start);
  6786. if (ret)
  6787. return ret;
  6788. start = cpu_to_le32(start);
  6789. len += b_offset;
  6790. offset &= ~3;
  6791. if (len < 4)
  6792. len = 4;
  6793. }
  6794. odd_len = 0;
  6795. if (len & 3) {
  6796. /* adjustments to end on required 4 byte boundary */
  6797. odd_len = 1;
  6798. len = (len + 3) & ~3;
  6799. ret = tg3_nvram_read(tp, offset+len-4, &end);
  6800. if (ret)
  6801. return ret;
  6802. end = cpu_to_le32(end);
  6803. }
  6804. buf = data;
  6805. if (b_offset || odd_len) {
  6806. buf = kmalloc(len, GFP_KERNEL);
  6807. if (buf == 0)
  6808. return -ENOMEM;
  6809. if (b_offset)
  6810. memcpy(buf, &start, 4);
  6811. if (odd_len)
  6812. memcpy(buf+len-4, &end, 4);
  6813. memcpy(buf + b_offset, data, eeprom->len);
  6814. }
  6815. ret = tg3_nvram_write_block(tp, offset, len, buf);
  6816. if (buf != data)
  6817. kfree(buf);
  6818. return ret;
  6819. }
  6820. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  6821. {
  6822. struct tg3 *tp = netdev_priv(dev);
  6823. cmd->supported = (SUPPORTED_Autoneg);
  6824. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  6825. cmd->supported |= (SUPPORTED_1000baseT_Half |
  6826. SUPPORTED_1000baseT_Full);
  6827. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  6828. cmd->supported |= (SUPPORTED_100baseT_Half |
  6829. SUPPORTED_100baseT_Full |
  6830. SUPPORTED_10baseT_Half |
  6831. SUPPORTED_10baseT_Full |
  6832. SUPPORTED_MII);
  6833. cmd->port = PORT_TP;
  6834. } else {
  6835. cmd->supported |= SUPPORTED_FIBRE;
  6836. cmd->port = PORT_FIBRE;
  6837. }
  6838. cmd->advertising = tp->link_config.advertising;
  6839. if (netif_running(dev)) {
  6840. cmd->speed = tp->link_config.active_speed;
  6841. cmd->duplex = tp->link_config.active_duplex;
  6842. }
  6843. cmd->phy_address = PHY_ADDR;
  6844. cmd->transceiver = 0;
  6845. cmd->autoneg = tp->link_config.autoneg;
  6846. cmd->maxtxpkt = 0;
  6847. cmd->maxrxpkt = 0;
  6848. return 0;
  6849. }
  6850. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  6851. {
  6852. struct tg3 *tp = netdev_priv(dev);
  6853. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
  6854. /* These are the only valid advertisement bits allowed. */
  6855. if (cmd->autoneg == AUTONEG_ENABLE &&
  6856. (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
  6857. ADVERTISED_1000baseT_Full |
  6858. ADVERTISED_Autoneg |
  6859. ADVERTISED_FIBRE)))
  6860. return -EINVAL;
  6861. /* Fiber can only do SPEED_1000. */
  6862. else if ((cmd->autoneg != AUTONEG_ENABLE) &&
  6863. (cmd->speed != SPEED_1000))
  6864. return -EINVAL;
  6865. /* Copper cannot force SPEED_1000. */
  6866. } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
  6867. (cmd->speed == SPEED_1000))
  6868. return -EINVAL;
  6869. else if ((cmd->speed == SPEED_1000) &&
  6870. (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
  6871. return -EINVAL;
  6872. tg3_full_lock(tp, 0);
  6873. tp->link_config.autoneg = cmd->autoneg;
  6874. if (cmd->autoneg == AUTONEG_ENABLE) {
  6875. tp->link_config.advertising = cmd->advertising;
  6876. tp->link_config.speed = SPEED_INVALID;
  6877. tp->link_config.duplex = DUPLEX_INVALID;
  6878. } else {
  6879. tp->link_config.advertising = 0;
  6880. tp->link_config.speed = cmd->speed;
  6881. tp->link_config.duplex = cmd->duplex;
  6882. }
  6883. tp->link_config.orig_speed = tp->link_config.speed;
  6884. tp->link_config.orig_duplex = tp->link_config.duplex;
  6885. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  6886. if (netif_running(dev))
  6887. tg3_setup_phy(tp, 1);
  6888. tg3_full_unlock(tp);
  6889. return 0;
  6890. }
  6891. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  6892. {
  6893. struct tg3 *tp = netdev_priv(dev);
  6894. strcpy(info->driver, DRV_MODULE_NAME);
  6895. strcpy(info->version, DRV_MODULE_VERSION);
  6896. strcpy(info->fw_version, tp->fw_ver);
  6897. strcpy(info->bus_info, pci_name(tp->pdev));
  6898. }
  6899. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  6900. {
  6901. struct tg3 *tp = netdev_priv(dev);
  6902. if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
  6903. wol->supported = WAKE_MAGIC;
  6904. else
  6905. wol->supported = 0;
  6906. wol->wolopts = 0;
  6907. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
  6908. wol->wolopts = WAKE_MAGIC;
  6909. memset(&wol->sopass, 0, sizeof(wol->sopass));
  6910. }
  6911. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  6912. {
  6913. struct tg3 *tp = netdev_priv(dev);
  6914. if (wol->wolopts & ~WAKE_MAGIC)
  6915. return -EINVAL;
  6916. if ((wol->wolopts & WAKE_MAGIC) &&
  6917. !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
  6918. return -EINVAL;
  6919. spin_lock_bh(&tp->lock);
  6920. if (wol->wolopts & WAKE_MAGIC)
  6921. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  6922. else
  6923. tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  6924. spin_unlock_bh(&tp->lock);
  6925. return 0;
  6926. }
  6927. static u32 tg3_get_msglevel(struct net_device *dev)
  6928. {
  6929. struct tg3 *tp = netdev_priv(dev);
  6930. return tp->msg_enable;
  6931. }
  6932. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  6933. {
  6934. struct tg3 *tp = netdev_priv(dev);
  6935. tp->msg_enable = value;
  6936. }
  6937. static int tg3_set_tso(struct net_device *dev, u32 value)
  6938. {
  6939. struct tg3 *tp = netdev_priv(dev);
  6940. if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  6941. if (value)
  6942. return -EINVAL;
  6943. return 0;
  6944. }
  6945. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
  6946. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
  6947. if (value)
  6948. dev->features |= NETIF_F_TSO6;
  6949. else
  6950. dev->features &= ~NETIF_F_TSO6;
  6951. }
  6952. return ethtool_op_set_tso(dev, value);
  6953. }
  6954. static int tg3_nway_reset(struct net_device *dev)
  6955. {
  6956. struct tg3 *tp = netdev_priv(dev);
  6957. u32 bmcr;
  6958. int r;
  6959. if (!netif_running(dev))
  6960. return -EAGAIN;
  6961. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  6962. return -EINVAL;
  6963. spin_lock_bh(&tp->lock);
  6964. r = -EINVAL;
  6965. tg3_readphy(tp, MII_BMCR, &bmcr);
  6966. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  6967. ((bmcr & BMCR_ANENABLE) ||
  6968. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
  6969. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  6970. BMCR_ANENABLE);
  6971. r = 0;
  6972. }
  6973. spin_unlock_bh(&tp->lock);
  6974. return r;
  6975. }
  6976. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  6977. {
  6978. struct tg3 *tp = netdev_priv(dev);
  6979. ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
  6980. ering->rx_mini_max_pending = 0;
  6981. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  6982. ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
  6983. else
  6984. ering->rx_jumbo_max_pending = 0;
  6985. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  6986. ering->rx_pending = tp->rx_pending;
  6987. ering->rx_mini_pending = 0;
  6988. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  6989. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  6990. else
  6991. ering->rx_jumbo_pending = 0;
  6992. ering->tx_pending = tp->tx_pending;
  6993. }
  6994. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  6995. {
  6996. struct tg3 *tp = netdev_priv(dev);
  6997. int irq_sync = 0, err = 0;
  6998. if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
  6999. (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
  7000. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  7001. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  7002. ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
  7003. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  7004. return -EINVAL;
  7005. if (netif_running(dev)) {
  7006. tg3_netif_stop(tp);
  7007. irq_sync = 1;
  7008. }
  7009. tg3_full_lock(tp, irq_sync);
  7010. tp->rx_pending = ering->rx_pending;
  7011. if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
  7012. tp->rx_pending > 63)
  7013. tp->rx_pending = 63;
  7014. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  7015. tp->tx_pending = ering->tx_pending;
  7016. if (netif_running(dev)) {
  7017. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7018. err = tg3_restart_hw(tp, 1);
  7019. if (!err)
  7020. tg3_netif_start(tp);
  7021. }
  7022. tg3_full_unlock(tp);
  7023. return err;
  7024. }
  7025. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  7026. {
  7027. struct tg3 *tp = netdev_priv(dev);
  7028. epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
  7029. epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
  7030. epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
  7031. }
  7032. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  7033. {
  7034. struct tg3 *tp = netdev_priv(dev);
  7035. int irq_sync = 0, err = 0;
  7036. if (netif_running(dev)) {
  7037. tg3_netif_stop(tp);
  7038. irq_sync = 1;
  7039. }
  7040. tg3_full_lock(tp, irq_sync);
  7041. if (epause->autoneg)
  7042. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  7043. else
  7044. tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  7045. if (epause->rx_pause)
  7046. tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
  7047. else
  7048. tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
  7049. if (epause->tx_pause)
  7050. tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
  7051. else
  7052. tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
  7053. if (netif_running(dev)) {
  7054. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7055. err = tg3_restart_hw(tp, 1);
  7056. if (!err)
  7057. tg3_netif_start(tp);
  7058. }
  7059. tg3_full_unlock(tp);
  7060. return err;
  7061. }
  7062. static u32 tg3_get_rx_csum(struct net_device *dev)
  7063. {
  7064. struct tg3 *tp = netdev_priv(dev);
  7065. return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
  7066. }
  7067. static int tg3_set_rx_csum(struct net_device *dev, u32 data)
  7068. {
  7069. struct tg3 *tp = netdev_priv(dev);
  7070. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  7071. if (data != 0)
  7072. return -EINVAL;
  7073. return 0;
  7074. }
  7075. spin_lock_bh(&tp->lock);
  7076. if (data)
  7077. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  7078. else
  7079. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  7080. spin_unlock_bh(&tp->lock);
  7081. return 0;
  7082. }
  7083. static int tg3_set_tx_csum(struct net_device *dev, u32 data)
  7084. {
  7085. struct tg3 *tp = netdev_priv(dev);
  7086. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  7087. if (data != 0)
  7088. return -EINVAL;
  7089. return 0;
  7090. }
  7091. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  7092. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  7093. ethtool_op_set_tx_ipv6_csum(dev, data);
  7094. else
  7095. ethtool_op_set_tx_csum(dev, data);
  7096. return 0;
  7097. }
  7098. static int tg3_get_stats_count (struct net_device *dev)
  7099. {
  7100. return TG3_NUM_STATS;
  7101. }
  7102. static int tg3_get_test_count (struct net_device *dev)
  7103. {
  7104. return TG3_NUM_TEST;
  7105. }
  7106. static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
  7107. {
  7108. switch (stringset) {
  7109. case ETH_SS_STATS:
  7110. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  7111. break;
  7112. case ETH_SS_TEST:
  7113. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  7114. break;
  7115. default:
  7116. WARN_ON(1); /* we need a WARN() */
  7117. break;
  7118. }
  7119. }
  7120. static int tg3_phys_id(struct net_device *dev, u32 data)
  7121. {
  7122. struct tg3 *tp = netdev_priv(dev);
  7123. int i;
  7124. if (!netif_running(tp->dev))
  7125. return -EAGAIN;
  7126. if (data == 0)
  7127. data = 2;
  7128. for (i = 0; i < (data * 2); i++) {
  7129. if ((i % 2) == 0)
  7130. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  7131. LED_CTRL_1000MBPS_ON |
  7132. LED_CTRL_100MBPS_ON |
  7133. LED_CTRL_10MBPS_ON |
  7134. LED_CTRL_TRAFFIC_OVERRIDE |
  7135. LED_CTRL_TRAFFIC_BLINK |
  7136. LED_CTRL_TRAFFIC_LED);
  7137. else
  7138. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  7139. LED_CTRL_TRAFFIC_OVERRIDE);
  7140. if (msleep_interruptible(500))
  7141. break;
  7142. }
  7143. tw32(MAC_LED_CTRL, tp->led_ctrl);
  7144. return 0;
  7145. }
  7146. static void tg3_get_ethtool_stats (struct net_device *dev,
  7147. struct ethtool_stats *estats, u64 *tmp_stats)
  7148. {
  7149. struct tg3 *tp = netdev_priv(dev);
  7150. memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
  7151. }
  7152. #define NVRAM_TEST_SIZE 0x100
  7153. #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
  7154. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  7155. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  7156. static int tg3_test_nvram(struct tg3 *tp)
  7157. {
  7158. u32 *buf, csum, magic;
  7159. int i, j, err = 0, size;
  7160. if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
  7161. return -EIO;
  7162. if (magic == TG3_EEPROM_MAGIC)
  7163. size = NVRAM_TEST_SIZE;
  7164. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  7165. if ((magic & 0xe00000) == 0x200000)
  7166. size = NVRAM_SELFBOOT_FORMAT1_SIZE;
  7167. else
  7168. return 0;
  7169. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  7170. size = NVRAM_SELFBOOT_HW_SIZE;
  7171. else
  7172. return -EIO;
  7173. buf = kmalloc(size, GFP_KERNEL);
  7174. if (buf == NULL)
  7175. return -ENOMEM;
  7176. err = -EIO;
  7177. for (i = 0, j = 0; i < size; i += 4, j++) {
  7178. u32 val;
  7179. if ((err = tg3_nvram_read(tp, i, &val)) != 0)
  7180. break;
  7181. buf[j] = cpu_to_le32(val);
  7182. }
  7183. if (i < size)
  7184. goto out;
  7185. /* Selfboot format */
  7186. if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
  7187. TG3_EEPROM_MAGIC_FW) {
  7188. u8 *buf8 = (u8 *) buf, csum8 = 0;
  7189. for (i = 0; i < size; i++)
  7190. csum8 += buf8[i];
  7191. if (csum8 == 0) {
  7192. err = 0;
  7193. goto out;
  7194. }
  7195. err = -EIO;
  7196. goto out;
  7197. }
  7198. if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
  7199. TG3_EEPROM_MAGIC_HW) {
  7200. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  7201. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  7202. u8 *buf8 = (u8 *) buf;
  7203. int j, k;
  7204. /* Separate the parity bits and the data bytes. */
  7205. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  7206. if ((i == 0) || (i == 8)) {
  7207. int l;
  7208. u8 msk;
  7209. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  7210. parity[k++] = buf8[i] & msk;
  7211. i++;
  7212. }
  7213. else if (i == 16) {
  7214. int l;
  7215. u8 msk;
  7216. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  7217. parity[k++] = buf8[i] & msk;
  7218. i++;
  7219. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  7220. parity[k++] = buf8[i] & msk;
  7221. i++;
  7222. }
  7223. data[j++] = buf8[i];
  7224. }
  7225. err = -EIO;
  7226. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  7227. u8 hw8 = hweight8(data[i]);
  7228. if ((hw8 & 0x1) && parity[i])
  7229. goto out;
  7230. else if (!(hw8 & 0x1) && !parity[i])
  7231. goto out;
  7232. }
  7233. err = 0;
  7234. goto out;
  7235. }
  7236. /* Bootstrap checksum at offset 0x10 */
  7237. csum = calc_crc((unsigned char *) buf, 0x10);
  7238. if(csum != cpu_to_le32(buf[0x10/4]))
  7239. goto out;
  7240. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  7241. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  7242. if (csum != cpu_to_le32(buf[0xfc/4]))
  7243. goto out;
  7244. err = 0;
  7245. out:
  7246. kfree(buf);
  7247. return err;
  7248. }
  7249. #define TG3_SERDES_TIMEOUT_SEC 2
  7250. #define TG3_COPPER_TIMEOUT_SEC 6
  7251. static int tg3_test_link(struct tg3 *tp)
  7252. {
  7253. int i, max;
  7254. if (!netif_running(tp->dev))
  7255. return -ENODEV;
  7256. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  7257. max = TG3_SERDES_TIMEOUT_SEC;
  7258. else
  7259. max = TG3_COPPER_TIMEOUT_SEC;
  7260. for (i = 0; i < max; i++) {
  7261. if (netif_carrier_ok(tp->dev))
  7262. return 0;
  7263. if (msleep_interruptible(1000))
  7264. break;
  7265. }
  7266. return -EIO;
  7267. }
  7268. /* Only test the commonly used registers */
  7269. static int tg3_test_registers(struct tg3 *tp)
  7270. {
  7271. int i, is_5705, is_5750;
  7272. u32 offset, read_mask, write_mask, val, save_val, read_val;
  7273. static struct {
  7274. u16 offset;
  7275. u16 flags;
  7276. #define TG3_FL_5705 0x1
  7277. #define TG3_FL_NOT_5705 0x2
  7278. #define TG3_FL_NOT_5788 0x4
  7279. #define TG3_FL_NOT_5750 0x8
  7280. u32 read_mask;
  7281. u32 write_mask;
  7282. } reg_tbl[] = {
  7283. /* MAC Control Registers */
  7284. { MAC_MODE, TG3_FL_NOT_5705,
  7285. 0x00000000, 0x00ef6f8c },
  7286. { MAC_MODE, TG3_FL_5705,
  7287. 0x00000000, 0x01ef6b8c },
  7288. { MAC_STATUS, TG3_FL_NOT_5705,
  7289. 0x03800107, 0x00000000 },
  7290. { MAC_STATUS, TG3_FL_5705,
  7291. 0x03800100, 0x00000000 },
  7292. { MAC_ADDR_0_HIGH, 0x0000,
  7293. 0x00000000, 0x0000ffff },
  7294. { MAC_ADDR_0_LOW, 0x0000,
  7295. 0x00000000, 0xffffffff },
  7296. { MAC_RX_MTU_SIZE, 0x0000,
  7297. 0x00000000, 0x0000ffff },
  7298. { MAC_TX_MODE, 0x0000,
  7299. 0x00000000, 0x00000070 },
  7300. { MAC_TX_LENGTHS, 0x0000,
  7301. 0x00000000, 0x00003fff },
  7302. { MAC_RX_MODE, TG3_FL_NOT_5705,
  7303. 0x00000000, 0x000007fc },
  7304. { MAC_RX_MODE, TG3_FL_5705,
  7305. 0x00000000, 0x000007dc },
  7306. { MAC_HASH_REG_0, 0x0000,
  7307. 0x00000000, 0xffffffff },
  7308. { MAC_HASH_REG_1, 0x0000,
  7309. 0x00000000, 0xffffffff },
  7310. { MAC_HASH_REG_2, 0x0000,
  7311. 0x00000000, 0xffffffff },
  7312. { MAC_HASH_REG_3, 0x0000,
  7313. 0x00000000, 0xffffffff },
  7314. /* Receive Data and Receive BD Initiator Control Registers. */
  7315. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  7316. 0x00000000, 0xffffffff },
  7317. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  7318. 0x00000000, 0xffffffff },
  7319. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  7320. 0x00000000, 0x00000003 },
  7321. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  7322. 0x00000000, 0xffffffff },
  7323. { RCVDBDI_STD_BD+0, 0x0000,
  7324. 0x00000000, 0xffffffff },
  7325. { RCVDBDI_STD_BD+4, 0x0000,
  7326. 0x00000000, 0xffffffff },
  7327. { RCVDBDI_STD_BD+8, 0x0000,
  7328. 0x00000000, 0xffff0002 },
  7329. { RCVDBDI_STD_BD+0xc, 0x0000,
  7330. 0x00000000, 0xffffffff },
  7331. /* Receive BD Initiator Control Registers. */
  7332. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  7333. 0x00000000, 0xffffffff },
  7334. { RCVBDI_STD_THRESH, TG3_FL_5705,
  7335. 0x00000000, 0x000003ff },
  7336. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  7337. 0x00000000, 0xffffffff },
  7338. /* Host Coalescing Control Registers. */
  7339. { HOSTCC_MODE, TG3_FL_NOT_5705,
  7340. 0x00000000, 0x00000004 },
  7341. { HOSTCC_MODE, TG3_FL_5705,
  7342. 0x00000000, 0x000000f6 },
  7343. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  7344. 0x00000000, 0xffffffff },
  7345. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  7346. 0x00000000, 0x000003ff },
  7347. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  7348. 0x00000000, 0xffffffff },
  7349. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  7350. 0x00000000, 0x000003ff },
  7351. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  7352. 0x00000000, 0xffffffff },
  7353. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  7354. 0x00000000, 0x000000ff },
  7355. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  7356. 0x00000000, 0xffffffff },
  7357. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  7358. 0x00000000, 0x000000ff },
  7359. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  7360. 0x00000000, 0xffffffff },
  7361. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  7362. 0x00000000, 0xffffffff },
  7363. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  7364. 0x00000000, 0xffffffff },
  7365. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  7366. 0x00000000, 0x000000ff },
  7367. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  7368. 0x00000000, 0xffffffff },
  7369. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  7370. 0x00000000, 0x000000ff },
  7371. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  7372. 0x00000000, 0xffffffff },
  7373. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  7374. 0x00000000, 0xffffffff },
  7375. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  7376. 0x00000000, 0xffffffff },
  7377. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  7378. 0x00000000, 0xffffffff },
  7379. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  7380. 0x00000000, 0xffffffff },
  7381. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  7382. 0xffffffff, 0x00000000 },
  7383. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  7384. 0xffffffff, 0x00000000 },
  7385. /* Buffer Manager Control Registers. */
  7386. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  7387. 0x00000000, 0x007fff80 },
  7388. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  7389. 0x00000000, 0x007fffff },
  7390. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  7391. 0x00000000, 0x0000003f },
  7392. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  7393. 0x00000000, 0x000001ff },
  7394. { BUFMGR_MB_HIGH_WATER, 0x0000,
  7395. 0x00000000, 0x000001ff },
  7396. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  7397. 0xffffffff, 0x00000000 },
  7398. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  7399. 0xffffffff, 0x00000000 },
  7400. /* Mailbox Registers */
  7401. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  7402. 0x00000000, 0x000001ff },
  7403. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  7404. 0x00000000, 0x000001ff },
  7405. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  7406. 0x00000000, 0x000007ff },
  7407. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  7408. 0x00000000, 0x000001ff },
  7409. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  7410. };
  7411. is_5705 = is_5750 = 0;
  7412. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  7413. is_5705 = 1;
  7414. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  7415. is_5750 = 1;
  7416. }
  7417. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  7418. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  7419. continue;
  7420. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  7421. continue;
  7422. if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  7423. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  7424. continue;
  7425. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  7426. continue;
  7427. offset = (u32) reg_tbl[i].offset;
  7428. read_mask = reg_tbl[i].read_mask;
  7429. write_mask = reg_tbl[i].write_mask;
  7430. /* Save the original register content */
  7431. save_val = tr32(offset);
  7432. /* Determine the read-only value. */
  7433. read_val = save_val & read_mask;
  7434. /* Write zero to the register, then make sure the read-only bits
  7435. * are not changed and the read/write bits are all zeros.
  7436. */
  7437. tw32(offset, 0);
  7438. val = tr32(offset);
  7439. /* Test the read-only and read/write bits. */
  7440. if (((val & read_mask) != read_val) || (val & write_mask))
  7441. goto out;
  7442. /* Write ones to all the bits defined by RdMask and WrMask, then
  7443. * make sure the read-only bits are not changed and the
  7444. * read/write bits are all ones.
  7445. */
  7446. tw32(offset, read_mask | write_mask);
  7447. val = tr32(offset);
  7448. /* Test the read-only bits. */
  7449. if ((val & read_mask) != read_val)
  7450. goto out;
  7451. /* Test the read/write bits. */
  7452. if ((val & write_mask) != write_mask)
  7453. goto out;
  7454. tw32(offset, save_val);
  7455. }
  7456. return 0;
  7457. out:
  7458. if (netif_msg_hw(tp))
  7459. printk(KERN_ERR PFX "Register test failed at offset %x\n",
  7460. offset);
  7461. tw32(offset, save_val);
  7462. return -EIO;
  7463. }
  7464. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  7465. {
  7466. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  7467. int i;
  7468. u32 j;
  7469. for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
  7470. for (j = 0; j < len; j += 4) {
  7471. u32 val;
  7472. tg3_write_mem(tp, offset + j, test_pattern[i]);
  7473. tg3_read_mem(tp, offset + j, &val);
  7474. if (val != test_pattern[i])
  7475. return -EIO;
  7476. }
  7477. }
  7478. return 0;
  7479. }
  7480. static int tg3_test_memory(struct tg3 *tp)
  7481. {
  7482. static struct mem_entry {
  7483. u32 offset;
  7484. u32 len;
  7485. } mem_tbl_570x[] = {
  7486. { 0x00000000, 0x00b50},
  7487. { 0x00002000, 0x1c000},
  7488. { 0xffffffff, 0x00000}
  7489. }, mem_tbl_5705[] = {
  7490. { 0x00000100, 0x0000c},
  7491. { 0x00000200, 0x00008},
  7492. { 0x00004000, 0x00800},
  7493. { 0x00006000, 0x01000},
  7494. { 0x00008000, 0x02000},
  7495. { 0x00010000, 0x0e000},
  7496. { 0xffffffff, 0x00000}
  7497. }, mem_tbl_5755[] = {
  7498. { 0x00000200, 0x00008},
  7499. { 0x00004000, 0x00800},
  7500. { 0x00006000, 0x00800},
  7501. { 0x00008000, 0x02000},
  7502. { 0x00010000, 0x0c000},
  7503. { 0xffffffff, 0x00000}
  7504. }, mem_tbl_5906[] = {
  7505. { 0x00000200, 0x00008},
  7506. { 0x00004000, 0x00400},
  7507. { 0x00006000, 0x00400},
  7508. { 0x00008000, 0x01000},
  7509. { 0x00010000, 0x01000},
  7510. { 0xffffffff, 0x00000}
  7511. };
  7512. struct mem_entry *mem_tbl;
  7513. int err = 0;
  7514. int i;
  7515. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  7516. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  7517. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  7518. mem_tbl = mem_tbl_5755;
  7519. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  7520. mem_tbl = mem_tbl_5906;
  7521. else
  7522. mem_tbl = mem_tbl_5705;
  7523. } else
  7524. mem_tbl = mem_tbl_570x;
  7525. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  7526. if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
  7527. mem_tbl[i].len)) != 0)
  7528. break;
  7529. }
  7530. return err;
  7531. }
  7532. #define TG3_MAC_LOOPBACK 0
  7533. #define TG3_PHY_LOOPBACK 1
  7534. static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
  7535. {
  7536. u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
  7537. u32 desc_idx;
  7538. struct sk_buff *skb, *rx_skb;
  7539. u8 *tx_data;
  7540. dma_addr_t map;
  7541. int num_pkts, tx_len, rx_len, i, err;
  7542. struct tg3_rx_buffer_desc *desc;
  7543. if (loopback_mode == TG3_MAC_LOOPBACK) {
  7544. /* HW errata - mac loopback fails in some cases on 5780.
  7545. * Normal traffic and PHY loopback are not affected by
  7546. * errata.
  7547. */
  7548. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
  7549. return 0;
  7550. mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
  7551. MAC_MODE_PORT_INT_LPBACK;
  7552. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  7553. mac_mode |= MAC_MODE_LINK_POLARITY;
  7554. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  7555. mac_mode |= MAC_MODE_PORT_MODE_MII;
  7556. else
  7557. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  7558. tw32(MAC_MODE, mac_mode);
  7559. } else if (loopback_mode == TG3_PHY_LOOPBACK) {
  7560. u32 val;
  7561. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  7562. u32 phytest;
  7563. if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
  7564. u32 phy;
  7565. tg3_writephy(tp, MII_TG3_EPHY_TEST,
  7566. phytest | MII_TG3_EPHY_SHADOW_EN);
  7567. if (!tg3_readphy(tp, 0x1b, &phy))
  7568. tg3_writephy(tp, 0x1b, phy & ~0x20);
  7569. tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
  7570. }
  7571. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
  7572. } else
  7573. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
  7574. tg3_phy_toggle_automdix(tp, 0);
  7575. tg3_writephy(tp, MII_BMCR, val);
  7576. udelay(40);
  7577. mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  7578. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  7579. tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
  7580. mac_mode |= MAC_MODE_PORT_MODE_MII;
  7581. } else
  7582. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  7583. /* reset to prevent losing 1st rx packet intermittently */
  7584. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  7585. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  7586. udelay(10);
  7587. tw32_f(MAC_RX_MODE, tp->rx_mode);
  7588. }
  7589. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  7590. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
  7591. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  7592. else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
  7593. mac_mode |= MAC_MODE_LINK_POLARITY;
  7594. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  7595. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  7596. }
  7597. tw32(MAC_MODE, mac_mode);
  7598. }
  7599. else
  7600. return -EINVAL;
  7601. err = -EIO;
  7602. tx_len = 1514;
  7603. skb = netdev_alloc_skb(tp->dev, tx_len);
  7604. if (!skb)
  7605. return -ENOMEM;
  7606. tx_data = skb_put(skb, tx_len);
  7607. memcpy(tx_data, tp->dev->dev_addr, 6);
  7608. memset(tx_data + 6, 0x0, 8);
  7609. tw32(MAC_RX_MTU_SIZE, tx_len + 4);
  7610. for (i = 14; i < tx_len; i++)
  7611. tx_data[i] = (u8) (i & 0xff);
  7612. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  7613. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  7614. HOSTCC_MODE_NOW);
  7615. udelay(10);
  7616. rx_start_idx = tp->hw_status->idx[0].rx_producer;
  7617. num_pkts = 0;
  7618. tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
  7619. tp->tx_prod++;
  7620. num_pkts++;
  7621. tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
  7622. tp->tx_prod);
  7623. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
  7624. udelay(10);
  7625. /* 250 usec to allow enough time on some 10/100 Mbps devices. */
  7626. for (i = 0; i < 25; i++) {
  7627. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  7628. HOSTCC_MODE_NOW);
  7629. udelay(10);
  7630. tx_idx = tp->hw_status->idx[0].tx_consumer;
  7631. rx_idx = tp->hw_status->idx[0].rx_producer;
  7632. if ((tx_idx == tp->tx_prod) &&
  7633. (rx_idx == (rx_start_idx + num_pkts)))
  7634. break;
  7635. }
  7636. pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
  7637. dev_kfree_skb(skb);
  7638. if (tx_idx != tp->tx_prod)
  7639. goto out;
  7640. if (rx_idx != rx_start_idx + num_pkts)
  7641. goto out;
  7642. desc = &tp->rx_rcb[rx_start_idx];
  7643. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  7644. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  7645. if (opaque_key != RXD_OPAQUE_RING_STD)
  7646. goto out;
  7647. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  7648. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  7649. goto out;
  7650. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
  7651. if (rx_len != tx_len)
  7652. goto out;
  7653. rx_skb = tp->rx_std_buffers[desc_idx].skb;
  7654. map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
  7655. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
  7656. for (i = 14; i < tx_len; i++) {
  7657. if (*(rx_skb->data + i) != (u8) (i & 0xff))
  7658. goto out;
  7659. }
  7660. err = 0;
  7661. /* tg3_free_rings will unmap and free the rx_skb */
  7662. out:
  7663. return err;
  7664. }
  7665. #define TG3_MAC_LOOPBACK_FAILED 1
  7666. #define TG3_PHY_LOOPBACK_FAILED 2
  7667. #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
  7668. TG3_PHY_LOOPBACK_FAILED)
  7669. static int tg3_test_loopback(struct tg3 *tp)
  7670. {
  7671. int err = 0;
  7672. if (!netif_running(tp->dev))
  7673. return TG3_LOOPBACK_FAILED;
  7674. err = tg3_reset_hw(tp, 1);
  7675. if (err)
  7676. return TG3_LOOPBACK_FAILED;
  7677. if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
  7678. err |= TG3_MAC_LOOPBACK_FAILED;
  7679. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  7680. if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
  7681. err |= TG3_PHY_LOOPBACK_FAILED;
  7682. }
  7683. return err;
  7684. }
  7685. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  7686. u64 *data)
  7687. {
  7688. struct tg3 *tp = netdev_priv(dev);
  7689. if (tp->link_config.phy_is_low_power)
  7690. tg3_set_power_state(tp, PCI_D0);
  7691. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  7692. if (tg3_test_nvram(tp) != 0) {
  7693. etest->flags |= ETH_TEST_FL_FAILED;
  7694. data[0] = 1;
  7695. }
  7696. if (tg3_test_link(tp) != 0) {
  7697. etest->flags |= ETH_TEST_FL_FAILED;
  7698. data[1] = 1;
  7699. }
  7700. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  7701. int err, irq_sync = 0;
  7702. if (netif_running(dev)) {
  7703. tg3_netif_stop(tp);
  7704. irq_sync = 1;
  7705. }
  7706. tg3_full_lock(tp, irq_sync);
  7707. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  7708. err = tg3_nvram_lock(tp);
  7709. tg3_halt_cpu(tp, RX_CPU_BASE);
  7710. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  7711. tg3_halt_cpu(tp, TX_CPU_BASE);
  7712. if (!err)
  7713. tg3_nvram_unlock(tp);
  7714. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  7715. tg3_phy_reset(tp);
  7716. if (tg3_test_registers(tp) != 0) {
  7717. etest->flags |= ETH_TEST_FL_FAILED;
  7718. data[2] = 1;
  7719. }
  7720. if (tg3_test_memory(tp) != 0) {
  7721. etest->flags |= ETH_TEST_FL_FAILED;
  7722. data[3] = 1;
  7723. }
  7724. if ((data[4] = tg3_test_loopback(tp)) != 0)
  7725. etest->flags |= ETH_TEST_FL_FAILED;
  7726. tg3_full_unlock(tp);
  7727. if (tg3_test_interrupt(tp) != 0) {
  7728. etest->flags |= ETH_TEST_FL_FAILED;
  7729. data[5] = 1;
  7730. }
  7731. tg3_full_lock(tp, 0);
  7732. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7733. if (netif_running(dev)) {
  7734. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  7735. if (!tg3_restart_hw(tp, 1))
  7736. tg3_netif_start(tp);
  7737. }
  7738. tg3_full_unlock(tp);
  7739. }
  7740. if (tp->link_config.phy_is_low_power)
  7741. tg3_set_power_state(tp, PCI_D3hot);
  7742. }
  7743. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  7744. {
  7745. struct mii_ioctl_data *data = if_mii(ifr);
  7746. struct tg3 *tp = netdev_priv(dev);
  7747. int err;
  7748. switch(cmd) {
  7749. case SIOCGMIIPHY:
  7750. data->phy_id = PHY_ADDR;
  7751. /* fallthru */
  7752. case SIOCGMIIREG: {
  7753. u32 mii_regval;
  7754. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  7755. break; /* We have no PHY */
  7756. if (tp->link_config.phy_is_low_power)
  7757. return -EAGAIN;
  7758. spin_lock_bh(&tp->lock);
  7759. err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
  7760. spin_unlock_bh(&tp->lock);
  7761. data->val_out = mii_regval;
  7762. return err;
  7763. }
  7764. case SIOCSMIIREG:
  7765. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  7766. break; /* We have no PHY */
  7767. if (!capable(CAP_NET_ADMIN))
  7768. return -EPERM;
  7769. if (tp->link_config.phy_is_low_power)
  7770. return -EAGAIN;
  7771. spin_lock_bh(&tp->lock);
  7772. err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
  7773. spin_unlock_bh(&tp->lock);
  7774. return err;
  7775. default:
  7776. /* do nothing */
  7777. break;
  7778. }
  7779. return -EOPNOTSUPP;
  7780. }
  7781. #if TG3_VLAN_TAG_USED
  7782. static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  7783. {
  7784. struct tg3 *tp = netdev_priv(dev);
  7785. if (netif_running(dev))
  7786. tg3_netif_stop(tp);
  7787. tg3_full_lock(tp, 0);
  7788. tp->vlgrp = grp;
  7789. /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
  7790. __tg3_set_rx_mode(dev);
  7791. if (netif_running(dev))
  7792. tg3_netif_start(tp);
  7793. tg3_full_unlock(tp);
  7794. }
  7795. #endif
  7796. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  7797. {
  7798. struct tg3 *tp = netdev_priv(dev);
  7799. memcpy(ec, &tp->coal, sizeof(*ec));
  7800. return 0;
  7801. }
  7802. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  7803. {
  7804. struct tg3 *tp = netdev_priv(dev);
  7805. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  7806. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  7807. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  7808. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  7809. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  7810. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  7811. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  7812. }
  7813. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  7814. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  7815. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  7816. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  7817. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  7818. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  7819. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  7820. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  7821. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  7822. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  7823. return -EINVAL;
  7824. /* No rx interrupts will be generated if both are zero */
  7825. if ((ec->rx_coalesce_usecs == 0) &&
  7826. (ec->rx_max_coalesced_frames == 0))
  7827. return -EINVAL;
  7828. /* No tx interrupts will be generated if both are zero */
  7829. if ((ec->tx_coalesce_usecs == 0) &&
  7830. (ec->tx_max_coalesced_frames == 0))
  7831. return -EINVAL;
  7832. /* Only copy relevant parameters, ignore all others. */
  7833. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  7834. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  7835. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  7836. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  7837. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  7838. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  7839. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  7840. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  7841. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  7842. if (netif_running(dev)) {
  7843. tg3_full_lock(tp, 0);
  7844. __tg3_set_coalesce(tp, &tp->coal);
  7845. tg3_full_unlock(tp);
  7846. }
  7847. return 0;
  7848. }
  7849. static const struct ethtool_ops tg3_ethtool_ops = {
  7850. .get_settings = tg3_get_settings,
  7851. .set_settings = tg3_set_settings,
  7852. .get_drvinfo = tg3_get_drvinfo,
  7853. .get_regs_len = tg3_get_regs_len,
  7854. .get_regs = tg3_get_regs,
  7855. .get_wol = tg3_get_wol,
  7856. .set_wol = tg3_set_wol,
  7857. .get_msglevel = tg3_get_msglevel,
  7858. .set_msglevel = tg3_set_msglevel,
  7859. .nway_reset = tg3_nway_reset,
  7860. .get_link = ethtool_op_get_link,
  7861. .get_eeprom_len = tg3_get_eeprom_len,
  7862. .get_eeprom = tg3_get_eeprom,
  7863. .set_eeprom = tg3_set_eeprom,
  7864. .get_ringparam = tg3_get_ringparam,
  7865. .set_ringparam = tg3_set_ringparam,
  7866. .get_pauseparam = tg3_get_pauseparam,
  7867. .set_pauseparam = tg3_set_pauseparam,
  7868. .get_rx_csum = tg3_get_rx_csum,
  7869. .set_rx_csum = tg3_set_rx_csum,
  7870. .get_tx_csum = ethtool_op_get_tx_csum,
  7871. .set_tx_csum = tg3_set_tx_csum,
  7872. .get_sg = ethtool_op_get_sg,
  7873. .set_sg = ethtool_op_set_sg,
  7874. .get_tso = ethtool_op_get_tso,
  7875. .set_tso = tg3_set_tso,
  7876. .self_test_count = tg3_get_test_count,
  7877. .self_test = tg3_self_test,
  7878. .get_strings = tg3_get_strings,
  7879. .phys_id = tg3_phys_id,
  7880. .get_stats_count = tg3_get_stats_count,
  7881. .get_ethtool_stats = tg3_get_ethtool_stats,
  7882. .get_coalesce = tg3_get_coalesce,
  7883. .set_coalesce = tg3_set_coalesce,
  7884. .get_perm_addr = ethtool_op_get_perm_addr,
  7885. };
  7886. static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
  7887. {
  7888. u32 cursize, val, magic;
  7889. tp->nvram_size = EEPROM_CHIP_SIZE;
  7890. if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
  7891. return;
  7892. if ((magic != TG3_EEPROM_MAGIC) &&
  7893. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  7894. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  7895. return;
  7896. /*
  7897. * Size the chip by reading offsets at increasing powers of two.
  7898. * When we encounter our validation signature, we know the addressing
  7899. * has wrapped around, and thus have our chip size.
  7900. */
  7901. cursize = 0x10;
  7902. while (cursize < tp->nvram_size) {
  7903. if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
  7904. return;
  7905. if (val == magic)
  7906. break;
  7907. cursize <<= 1;
  7908. }
  7909. tp->nvram_size = cursize;
  7910. }
  7911. static void __devinit tg3_get_nvram_size(struct tg3 *tp)
  7912. {
  7913. u32 val;
  7914. if (tg3_nvram_read_swab(tp, 0, &val) != 0)
  7915. return;
  7916. /* Selfboot format */
  7917. if (val != TG3_EEPROM_MAGIC) {
  7918. tg3_get_eeprom_size(tp);
  7919. return;
  7920. }
  7921. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  7922. if (val != 0) {
  7923. tp->nvram_size = (val >> 16) * 1024;
  7924. return;
  7925. }
  7926. }
  7927. tp->nvram_size = 0x80000;
  7928. }
  7929. static void __devinit tg3_get_nvram_info(struct tg3 *tp)
  7930. {
  7931. u32 nvcfg1;
  7932. nvcfg1 = tr32(NVRAM_CFG1);
  7933. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  7934. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  7935. }
  7936. else {
  7937. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  7938. tw32(NVRAM_CFG1, nvcfg1);
  7939. }
  7940. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
  7941. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  7942. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  7943. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  7944. tp->nvram_jedecnum = JEDEC_ATMEL;
  7945. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  7946. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7947. break;
  7948. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  7949. tp->nvram_jedecnum = JEDEC_ATMEL;
  7950. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  7951. break;
  7952. case FLASH_VENDOR_ATMEL_EEPROM:
  7953. tp->nvram_jedecnum = JEDEC_ATMEL;
  7954. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  7955. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7956. break;
  7957. case FLASH_VENDOR_ST:
  7958. tp->nvram_jedecnum = JEDEC_ST;
  7959. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  7960. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7961. break;
  7962. case FLASH_VENDOR_SAIFUN:
  7963. tp->nvram_jedecnum = JEDEC_SAIFUN;
  7964. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  7965. break;
  7966. case FLASH_VENDOR_SST_SMALL:
  7967. case FLASH_VENDOR_SST_LARGE:
  7968. tp->nvram_jedecnum = JEDEC_SST;
  7969. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  7970. break;
  7971. }
  7972. }
  7973. else {
  7974. tp->nvram_jedecnum = JEDEC_ATMEL;
  7975. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  7976. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7977. }
  7978. }
  7979. static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
  7980. {
  7981. u32 nvcfg1;
  7982. nvcfg1 = tr32(NVRAM_CFG1);
  7983. /* NVRAM protection for TPM */
  7984. if (nvcfg1 & (1 << 27))
  7985. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  7986. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  7987. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  7988. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  7989. tp->nvram_jedecnum = JEDEC_ATMEL;
  7990. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7991. break;
  7992. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  7993. tp->nvram_jedecnum = JEDEC_ATMEL;
  7994. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7995. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  7996. break;
  7997. case FLASH_5752VENDOR_ST_M45PE10:
  7998. case FLASH_5752VENDOR_ST_M45PE20:
  7999. case FLASH_5752VENDOR_ST_M45PE40:
  8000. tp->nvram_jedecnum = JEDEC_ST;
  8001. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8002. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8003. break;
  8004. }
  8005. if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
  8006. switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  8007. case FLASH_5752PAGE_SIZE_256:
  8008. tp->nvram_pagesize = 256;
  8009. break;
  8010. case FLASH_5752PAGE_SIZE_512:
  8011. tp->nvram_pagesize = 512;
  8012. break;
  8013. case FLASH_5752PAGE_SIZE_1K:
  8014. tp->nvram_pagesize = 1024;
  8015. break;
  8016. case FLASH_5752PAGE_SIZE_2K:
  8017. tp->nvram_pagesize = 2048;
  8018. break;
  8019. case FLASH_5752PAGE_SIZE_4K:
  8020. tp->nvram_pagesize = 4096;
  8021. break;
  8022. case FLASH_5752PAGE_SIZE_264:
  8023. tp->nvram_pagesize = 264;
  8024. break;
  8025. }
  8026. }
  8027. else {
  8028. /* For eeprom, set pagesize to maximum eeprom size */
  8029. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8030. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  8031. tw32(NVRAM_CFG1, nvcfg1);
  8032. }
  8033. }
  8034. static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
  8035. {
  8036. u32 nvcfg1, protect = 0;
  8037. nvcfg1 = tr32(NVRAM_CFG1);
  8038. /* NVRAM protection for TPM */
  8039. if (nvcfg1 & (1 << 27)) {
  8040. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  8041. protect = 1;
  8042. }
  8043. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  8044. switch (nvcfg1) {
  8045. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  8046. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  8047. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  8048. case FLASH_5755VENDOR_ATMEL_FLASH_5:
  8049. tp->nvram_jedecnum = JEDEC_ATMEL;
  8050. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8051. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8052. tp->nvram_pagesize = 264;
  8053. if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
  8054. nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
  8055. tp->nvram_size = (protect ? 0x3e200 : 0x80000);
  8056. else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
  8057. tp->nvram_size = (protect ? 0x1f200 : 0x40000);
  8058. else
  8059. tp->nvram_size = (protect ? 0x1f200 : 0x20000);
  8060. break;
  8061. case FLASH_5752VENDOR_ST_M45PE10:
  8062. case FLASH_5752VENDOR_ST_M45PE20:
  8063. case FLASH_5752VENDOR_ST_M45PE40:
  8064. tp->nvram_jedecnum = JEDEC_ST;
  8065. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8066. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8067. tp->nvram_pagesize = 256;
  8068. if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
  8069. tp->nvram_size = (protect ? 0x10000 : 0x20000);
  8070. else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
  8071. tp->nvram_size = (protect ? 0x10000 : 0x40000);
  8072. else
  8073. tp->nvram_size = (protect ? 0x20000 : 0x80000);
  8074. break;
  8075. }
  8076. }
  8077. static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
  8078. {
  8079. u32 nvcfg1;
  8080. nvcfg1 = tr32(NVRAM_CFG1);
  8081. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  8082. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  8083. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  8084. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  8085. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  8086. tp->nvram_jedecnum = JEDEC_ATMEL;
  8087. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8088. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8089. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  8090. tw32(NVRAM_CFG1, nvcfg1);
  8091. break;
  8092. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  8093. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  8094. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  8095. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  8096. tp->nvram_jedecnum = JEDEC_ATMEL;
  8097. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8098. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8099. tp->nvram_pagesize = 264;
  8100. break;
  8101. case FLASH_5752VENDOR_ST_M45PE10:
  8102. case FLASH_5752VENDOR_ST_M45PE20:
  8103. case FLASH_5752VENDOR_ST_M45PE40:
  8104. tp->nvram_jedecnum = JEDEC_ST;
  8105. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8106. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8107. tp->nvram_pagesize = 256;
  8108. break;
  8109. }
  8110. }
  8111. static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
  8112. {
  8113. tp->nvram_jedecnum = JEDEC_ATMEL;
  8114. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8115. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8116. }
  8117. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  8118. static void __devinit tg3_nvram_init(struct tg3 *tp)
  8119. {
  8120. tw32_f(GRC_EEPROM_ADDR,
  8121. (EEPROM_ADDR_FSM_RESET |
  8122. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  8123. EEPROM_ADDR_CLKPERD_SHIFT)));
  8124. msleep(1);
  8125. /* Enable seeprom accesses. */
  8126. tw32_f(GRC_LOCAL_CTRL,
  8127. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  8128. udelay(100);
  8129. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  8130. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  8131. tp->tg3_flags |= TG3_FLAG_NVRAM;
  8132. if (tg3_nvram_lock(tp)) {
  8133. printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
  8134. "tg3_nvram_init failed.\n", tp->dev->name);
  8135. return;
  8136. }
  8137. tg3_enable_nvram_access(tp);
  8138. tp->nvram_size = 0;
  8139. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  8140. tg3_get_5752_nvram_info(tp);
  8141. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  8142. tg3_get_5755_nvram_info(tp);
  8143. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  8144. tg3_get_5787_nvram_info(tp);
  8145. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  8146. tg3_get_5906_nvram_info(tp);
  8147. else
  8148. tg3_get_nvram_info(tp);
  8149. if (tp->nvram_size == 0)
  8150. tg3_get_nvram_size(tp);
  8151. tg3_disable_nvram_access(tp);
  8152. tg3_nvram_unlock(tp);
  8153. } else {
  8154. tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
  8155. tg3_get_eeprom_size(tp);
  8156. }
  8157. }
  8158. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  8159. u32 offset, u32 *val)
  8160. {
  8161. u32 tmp;
  8162. int i;
  8163. if (offset > EEPROM_ADDR_ADDR_MASK ||
  8164. (offset % 4) != 0)
  8165. return -EINVAL;
  8166. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  8167. EEPROM_ADDR_DEVID_MASK |
  8168. EEPROM_ADDR_READ);
  8169. tw32(GRC_EEPROM_ADDR,
  8170. tmp |
  8171. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  8172. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  8173. EEPROM_ADDR_ADDR_MASK) |
  8174. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  8175. for (i = 0; i < 1000; i++) {
  8176. tmp = tr32(GRC_EEPROM_ADDR);
  8177. if (tmp & EEPROM_ADDR_COMPLETE)
  8178. break;
  8179. msleep(1);
  8180. }
  8181. if (!(tmp & EEPROM_ADDR_COMPLETE))
  8182. return -EBUSY;
  8183. *val = tr32(GRC_EEPROM_DATA);
  8184. return 0;
  8185. }
  8186. #define NVRAM_CMD_TIMEOUT 10000
  8187. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  8188. {
  8189. int i;
  8190. tw32(NVRAM_CMD, nvram_cmd);
  8191. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  8192. udelay(10);
  8193. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  8194. udelay(10);
  8195. break;
  8196. }
  8197. }
  8198. if (i == NVRAM_CMD_TIMEOUT) {
  8199. return -EBUSY;
  8200. }
  8201. return 0;
  8202. }
  8203. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  8204. {
  8205. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  8206. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  8207. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  8208. (tp->nvram_jedecnum == JEDEC_ATMEL))
  8209. addr = ((addr / tp->nvram_pagesize) <<
  8210. ATMEL_AT45DB0X1B_PAGE_POS) +
  8211. (addr % tp->nvram_pagesize);
  8212. return addr;
  8213. }
  8214. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  8215. {
  8216. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  8217. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  8218. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  8219. (tp->nvram_jedecnum == JEDEC_ATMEL))
  8220. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  8221. tp->nvram_pagesize) +
  8222. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  8223. return addr;
  8224. }
  8225. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  8226. {
  8227. int ret;
  8228. if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
  8229. return tg3_nvram_read_using_eeprom(tp, offset, val);
  8230. offset = tg3_nvram_phys_addr(tp, offset);
  8231. if (offset > NVRAM_ADDR_MSK)
  8232. return -EINVAL;
  8233. ret = tg3_nvram_lock(tp);
  8234. if (ret)
  8235. return ret;
  8236. tg3_enable_nvram_access(tp);
  8237. tw32(NVRAM_ADDR, offset);
  8238. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  8239. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  8240. if (ret == 0)
  8241. *val = swab32(tr32(NVRAM_RDDATA));
  8242. tg3_disable_nvram_access(tp);
  8243. tg3_nvram_unlock(tp);
  8244. return ret;
  8245. }
  8246. static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
  8247. {
  8248. int err;
  8249. u32 tmp;
  8250. err = tg3_nvram_read(tp, offset, &tmp);
  8251. *val = swab32(tmp);
  8252. return err;
  8253. }
  8254. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  8255. u32 offset, u32 len, u8 *buf)
  8256. {
  8257. int i, j, rc = 0;
  8258. u32 val;
  8259. for (i = 0; i < len; i += 4) {
  8260. u32 addr, data;
  8261. addr = offset + i;
  8262. memcpy(&data, buf + i, 4);
  8263. tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
  8264. val = tr32(GRC_EEPROM_ADDR);
  8265. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  8266. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  8267. EEPROM_ADDR_READ);
  8268. tw32(GRC_EEPROM_ADDR, val |
  8269. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  8270. (addr & EEPROM_ADDR_ADDR_MASK) |
  8271. EEPROM_ADDR_START |
  8272. EEPROM_ADDR_WRITE);
  8273. for (j = 0; j < 1000; j++) {
  8274. val = tr32(GRC_EEPROM_ADDR);
  8275. if (val & EEPROM_ADDR_COMPLETE)
  8276. break;
  8277. msleep(1);
  8278. }
  8279. if (!(val & EEPROM_ADDR_COMPLETE)) {
  8280. rc = -EBUSY;
  8281. break;
  8282. }
  8283. }
  8284. return rc;
  8285. }
  8286. /* offset and length are dword aligned */
  8287. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  8288. u8 *buf)
  8289. {
  8290. int ret = 0;
  8291. u32 pagesize = tp->nvram_pagesize;
  8292. u32 pagemask = pagesize - 1;
  8293. u32 nvram_cmd;
  8294. u8 *tmp;
  8295. tmp = kmalloc(pagesize, GFP_KERNEL);
  8296. if (tmp == NULL)
  8297. return -ENOMEM;
  8298. while (len) {
  8299. int j;
  8300. u32 phy_addr, page_off, size;
  8301. phy_addr = offset & ~pagemask;
  8302. for (j = 0; j < pagesize; j += 4) {
  8303. if ((ret = tg3_nvram_read(tp, phy_addr + j,
  8304. (u32 *) (tmp + j))))
  8305. break;
  8306. }
  8307. if (ret)
  8308. break;
  8309. page_off = offset & pagemask;
  8310. size = pagesize;
  8311. if (len < size)
  8312. size = len;
  8313. len -= size;
  8314. memcpy(tmp + page_off, buf, size);
  8315. offset = offset + (pagesize - page_off);
  8316. tg3_enable_nvram_access(tp);
  8317. /*
  8318. * Before we can erase the flash page, we need
  8319. * to issue a special "write enable" command.
  8320. */
  8321. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8322. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8323. break;
  8324. /* Erase the target page */
  8325. tw32(NVRAM_ADDR, phy_addr);
  8326. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  8327. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  8328. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8329. break;
  8330. /* Issue another write enable to start the write. */
  8331. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8332. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8333. break;
  8334. for (j = 0; j < pagesize; j += 4) {
  8335. u32 data;
  8336. data = *((u32 *) (tmp + j));
  8337. tw32(NVRAM_WRDATA, cpu_to_be32(data));
  8338. tw32(NVRAM_ADDR, phy_addr + j);
  8339. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  8340. NVRAM_CMD_WR;
  8341. if (j == 0)
  8342. nvram_cmd |= NVRAM_CMD_FIRST;
  8343. else if (j == (pagesize - 4))
  8344. nvram_cmd |= NVRAM_CMD_LAST;
  8345. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  8346. break;
  8347. }
  8348. if (ret)
  8349. break;
  8350. }
  8351. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8352. tg3_nvram_exec_cmd(tp, nvram_cmd);
  8353. kfree(tmp);
  8354. return ret;
  8355. }
  8356. /* offset and length are dword aligned */
  8357. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  8358. u8 *buf)
  8359. {
  8360. int i, ret = 0;
  8361. for (i = 0; i < len; i += 4, offset += 4) {
  8362. u32 data, page_off, phy_addr, nvram_cmd;
  8363. memcpy(&data, buf + i, 4);
  8364. tw32(NVRAM_WRDATA, cpu_to_be32(data));
  8365. page_off = offset % tp->nvram_pagesize;
  8366. phy_addr = tg3_nvram_phys_addr(tp, offset);
  8367. tw32(NVRAM_ADDR, phy_addr);
  8368. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  8369. if ((page_off == 0) || (i == 0))
  8370. nvram_cmd |= NVRAM_CMD_FIRST;
  8371. if (page_off == (tp->nvram_pagesize - 4))
  8372. nvram_cmd |= NVRAM_CMD_LAST;
  8373. if (i == (len - 4))
  8374. nvram_cmd |= NVRAM_CMD_LAST;
  8375. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
  8376. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
  8377. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
  8378. (tp->nvram_jedecnum == JEDEC_ST) &&
  8379. (nvram_cmd & NVRAM_CMD_FIRST)) {
  8380. if ((ret = tg3_nvram_exec_cmd(tp,
  8381. NVRAM_CMD_WREN | NVRAM_CMD_GO |
  8382. NVRAM_CMD_DONE)))
  8383. break;
  8384. }
  8385. if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  8386. /* We always do complete word writes to eeprom. */
  8387. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  8388. }
  8389. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  8390. break;
  8391. }
  8392. return ret;
  8393. }
  8394. /* offset and length are dword aligned */
  8395. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  8396. {
  8397. int ret;
  8398. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  8399. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  8400. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  8401. udelay(40);
  8402. }
  8403. if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
  8404. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  8405. }
  8406. else {
  8407. u32 grc_mode;
  8408. ret = tg3_nvram_lock(tp);
  8409. if (ret)
  8410. return ret;
  8411. tg3_enable_nvram_access(tp);
  8412. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  8413. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
  8414. tw32(NVRAM_WRITE1, 0x406);
  8415. grc_mode = tr32(GRC_MODE);
  8416. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  8417. if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
  8418. !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  8419. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  8420. buf);
  8421. }
  8422. else {
  8423. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  8424. buf);
  8425. }
  8426. grc_mode = tr32(GRC_MODE);
  8427. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  8428. tg3_disable_nvram_access(tp);
  8429. tg3_nvram_unlock(tp);
  8430. }
  8431. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  8432. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  8433. udelay(40);
  8434. }
  8435. return ret;
  8436. }
  8437. struct subsys_tbl_ent {
  8438. u16 subsys_vendor, subsys_devid;
  8439. u32 phy_id;
  8440. };
  8441. static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
  8442. /* Broadcom boards. */
  8443. { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
  8444. { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
  8445. { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
  8446. { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
  8447. { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
  8448. { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
  8449. { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
  8450. { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
  8451. { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
  8452. { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
  8453. { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
  8454. /* 3com boards. */
  8455. { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
  8456. { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
  8457. { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
  8458. { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
  8459. { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
  8460. /* DELL boards. */
  8461. { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
  8462. { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
  8463. { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
  8464. { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
  8465. /* Compaq boards. */
  8466. { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
  8467. { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
  8468. { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
  8469. { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
  8470. { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
  8471. /* IBM boards. */
  8472. { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
  8473. };
  8474. static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
  8475. {
  8476. int i;
  8477. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  8478. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  8479. tp->pdev->subsystem_vendor) &&
  8480. (subsys_id_to_phy_id[i].subsys_devid ==
  8481. tp->pdev->subsystem_device))
  8482. return &subsys_id_to_phy_id[i];
  8483. }
  8484. return NULL;
  8485. }
  8486. static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  8487. {
  8488. u32 val;
  8489. u16 pmcsr;
  8490. /* On some early chips the SRAM cannot be accessed in D3hot state,
  8491. * so need make sure we're in D0.
  8492. */
  8493. pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
  8494. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  8495. pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
  8496. msleep(1);
  8497. /* Make sure register accesses (indirect or otherwise)
  8498. * will function correctly.
  8499. */
  8500. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  8501. tp->misc_host_ctrl);
  8502. /* The memory arbiter has to be enabled in order for SRAM accesses
  8503. * to succeed. Normally on powerup the tg3 chip firmware will make
  8504. * sure it is enabled, but other entities such as system netboot
  8505. * code might disable it.
  8506. */
  8507. val = tr32(MEMARB_MODE);
  8508. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  8509. tp->phy_id = PHY_ID_INVALID;
  8510. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  8511. /* Assume an onboard device and WOL capable by default. */
  8512. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
  8513. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  8514. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  8515. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  8516. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  8517. }
  8518. if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
  8519. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  8520. return;
  8521. }
  8522. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  8523. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  8524. u32 nic_cfg, led_cfg;
  8525. u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
  8526. int eeprom_phy_serdes = 0;
  8527. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  8528. tp->nic_sram_data_cfg = nic_cfg;
  8529. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  8530. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  8531. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
  8532. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
  8533. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
  8534. (ver > 0) && (ver < 0x100))
  8535. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  8536. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  8537. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  8538. eeprom_phy_serdes = 1;
  8539. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  8540. if (nic_phy_id != 0) {
  8541. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  8542. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  8543. eeprom_phy_id = (id1 >> 16) << 10;
  8544. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  8545. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  8546. } else
  8547. eeprom_phy_id = 0;
  8548. tp->phy_id = eeprom_phy_id;
  8549. if (eeprom_phy_serdes) {
  8550. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  8551. tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
  8552. else
  8553. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  8554. }
  8555. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  8556. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  8557. SHASTA_EXT_LED_MODE_MASK);
  8558. else
  8559. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  8560. switch (led_cfg) {
  8561. default:
  8562. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  8563. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  8564. break;
  8565. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  8566. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  8567. break;
  8568. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  8569. tp->led_ctrl = LED_CTRL_MODE_MAC;
  8570. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  8571. * read on some older 5700/5701 bootcode.
  8572. */
  8573. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  8574. ASIC_REV_5700 ||
  8575. GET_ASIC_REV(tp->pci_chip_rev_id) ==
  8576. ASIC_REV_5701)
  8577. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  8578. break;
  8579. case SHASTA_EXT_LED_SHARED:
  8580. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  8581. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  8582. tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
  8583. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  8584. LED_CTRL_MODE_PHY_2);
  8585. break;
  8586. case SHASTA_EXT_LED_MAC:
  8587. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  8588. break;
  8589. case SHASTA_EXT_LED_COMBO:
  8590. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  8591. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
  8592. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  8593. LED_CTRL_MODE_PHY_2);
  8594. break;
  8595. };
  8596. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  8597. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
  8598. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  8599. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  8600. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  8601. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
  8602. if ((tp->pdev->subsystem_vendor ==
  8603. PCI_VENDOR_ID_ARIMA) &&
  8604. (tp->pdev->subsystem_device == 0x205a ||
  8605. tp->pdev->subsystem_device == 0x2063))
  8606. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  8607. } else {
  8608. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  8609. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  8610. }
  8611. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  8612. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  8613. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  8614. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  8615. }
  8616. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
  8617. !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
  8618. tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
  8619. if (cfg2 & (1 << 17))
  8620. tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
  8621. /* serdes signal pre-emphasis in register 0x590 set by */
  8622. /* bootcode if bit 18 is set */
  8623. if (cfg2 & (1 << 18))
  8624. tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
  8625. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  8626. u32 cfg3;
  8627. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
  8628. if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
  8629. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  8630. }
  8631. }
  8632. }
  8633. static int __devinit tg3_phy_probe(struct tg3 *tp)
  8634. {
  8635. u32 hw_phy_id_1, hw_phy_id_2;
  8636. u32 hw_phy_id, hw_phy_id_masked;
  8637. int err;
  8638. /* Reading the PHY ID register can conflict with ASF
  8639. * firwmare access to the PHY hardware.
  8640. */
  8641. err = 0;
  8642. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  8643. hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
  8644. } else {
  8645. /* Now read the physical PHY_ID from the chip and verify
  8646. * that it is sane. If it doesn't look good, we fall back
  8647. * to either the hard-coded table based PHY_ID and failing
  8648. * that the value found in the eeprom area.
  8649. */
  8650. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  8651. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  8652. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  8653. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  8654. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  8655. hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
  8656. }
  8657. if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
  8658. tp->phy_id = hw_phy_id;
  8659. if (hw_phy_id_masked == PHY_ID_BCM8002)
  8660. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  8661. else
  8662. tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
  8663. } else {
  8664. if (tp->phy_id != PHY_ID_INVALID) {
  8665. /* Do nothing, phy ID already set up in
  8666. * tg3_get_eeprom_hw_cfg().
  8667. */
  8668. } else {
  8669. struct subsys_tbl_ent *p;
  8670. /* No eeprom signature? Try the hardcoded
  8671. * subsys device table.
  8672. */
  8673. p = lookup_by_subsys(tp);
  8674. if (!p)
  8675. return -ENODEV;
  8676. tp->phy_id = p->phy_id;
  8677. if (!tp->phy_id ||
  8678. tp->phy_id == PHY_ID_BCM8002)
  8679. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  8680. }
  8681. }
  8682. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
  8683. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  8684. u32 bmsr, adv_reg, tg3_ctrl, mask;
  8685. tg3_readphy(tp, MII_BMSR, &bmsr);
  8686. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  8687. (bmsr & BMSR_LSTATUS))
  8688. goto skip_phy_reset;
  8689. err = tg3_phy_reset(tp);
  8690. if (err)
  8691. return err;
  8692. adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  8693. ADVERTISE_100HALF | ADVERTISE_100FULL |
  8694. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  8695. tg3_ctrl = 0;
  8696. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  8697. tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
  8698. MII_TG3_CTRL_ADV_1000_FULL);
  8699. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  8700. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  8701. tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
  8702. MII_TG3_CTRL_ENABLE_AS_MASTER);
  8703. }
  8704. mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  8705. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  8706. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
  8707. if (!tg3_copper_is_advertising_all(tp, mask)) {
  8708. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  8709. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  8710. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  8711. tg3_writephy(tp, MII_BMCR,
  8712. BMCR_ANENABLE | BMCR_ANRESTART);
  8713. }
  8714. tg3_phy_set_wirespeed(tp);
  8715. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  8716. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  8717. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  8718. }
  8719. skip_phy_reset:
  8720. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  8721. err = tg3_init_5401phy_dsp(tp);
  8722. if (err)
  8723. return err;
  8724. }
  8725. if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
  8726. err = tg3_init_5401phy_dsp(tp);
  8727. }
  8728. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  8729. tp->link_config.advertising =
  8730. (ADVERTISED_1000baseT_Half |
  8731. ADVERTISED_1000baseT_Full |
  8732. ADVERTISED_Autoneg |
  8733. ADVERTISED_FIBRE);
  8734. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  8735. tp->link_config.advertising &=
  8736. ~(ADVERTISED_1000baseT_Half |
  8737. ADVERTISED_1000baseT_Full);
  8738. return err;
  8739. }
  8740. static void __devinit tg3_read_partno(struct tg3 *tp)
  8741. {
  8742. unsigned char vpd_data[256];
  8743. unsigned int i;
  8744. u32 magic;
  8745. if (tg3_nvram_read_swab(tp, 0x0, &magic))
  8746. goto out_not_found;
  8747. if (magic == TG3_EEPROM_MAGIC) {
  8748. for (i = 0; i < 256; i += 4) {
  8749. u32 tmp;
  8750. if (tg3_nvram_read(tp, 0x100 + i, &tmp))
  8751. goto out_not_found;
  8752. vpd_data[i + 0] = ((tmp >> 0) & 0xff);
  8753. vpd_data[i + 1] = ((tmp >> 8) & 0xff);
  8754. vpd_data[i + 2] = ((tmp >> 16) & 0xff);
  8755. vpd_data[i + 3] = ((tmp >> 24) & 0xff);
  8756. }
  8757. } else {
  8758. int vpd_cap;
  8759. vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
  8760. for (i = 0; i < 256; i += 4) {
  8761. u32 tmp, j = 0;
  8762. u16 tmp16;
  8763. pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
  8764. i);
  8765. while (j++ < 100) {
  8766. pci_read_config_word(tp->pdev, vpd_cap +
  8767. PCI_VPD_ADDR, &tmp16);
  8768. if (tmp16 & 0x8000)
  8769. break;
  8770. msleep(1);
  8771. }
  8772. if (!(tmp16 & 0x8000))
  8773. goto out_not_found;
  8774. pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
  8775. &tmp);
  8776. tmp = cpu_to_le32(tmp);
  8777. memcpy(&vpd_data[i], &tmp, 4);
  8778. }
  8779. }
  8780. /* Now parse and find the part number. */
  8781. for (i = 0; i < 254; ) {
  8782. unsigned char val = vpd_data[i];
  8783. unsigned int block_end;
  8784. if (val == 0x82 || val == 0x91) {
  8785. i = (i + 3 +
  8786. (vpd_data[i + 1] +
  8787. (vpd_data[i + 2] << 8)));
  8788. continue;
  8789. }
  8790. if (val != 0x90)
  8791. goto out_not_found;
  8792. block_end = (i + 3 +
  8793. (vpd_data[i + 1] +
  8794. (vpd_data[i + 2] << 8)));
  8795. i += 3;
  8796. if (block_end > 256)
  8797. goto out_not_found;
  8798. while (i < (block_end - 2)) {
  8799. if (vpd_data[i + 0] == 'P' &&
  8800. vpd_data[i + 1] == 'N') {
  8801. int partno_len = vpd_data[i + 2];
  8802. i += 3;
  8803. if (partno_len > 24 || (partno_len + i) > 256)
  8804. goto out_not_found;
  8805. memcpy(tp->board_part_number,
  8806. &vpd_data[i], partno_len);
  8807. /* Success. */
  8808. return;
  8809. }
  8810. i += 3 + vpd_data[i + 2];
  8811. }
  8812. /* Part number not found. */
  8813. goto out_not_found;
  8814. }
  8815. out_not_found:
  8816. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  8817. strcpy(tp->board_part_number, "BCM95906");
  8818. else
  8819. strcpy(tp->board_part_number, "none");
  8820. }
  8821. static void __devinit tg3_read_fw_ver(struct tg3 *tp)
  8822. {
  8823. u32 val, offset, start;
  8824. if (tg3_nvram_read_swab(tp, 0, &val))
  8825. return;
  8826. if (val != TG3_EEPROM_MAGIC)
  8827. return;
  8828. if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
  8829. tg3_nvram_read_swab(tp, 0x4, &start))
  8830. return;
  8831. offset = tg3_nvram_logical_addr(tp, offset);
  8832. if (tg3_nvram_read_swab(tp, offset, &val))
  8833. return;
  8834. if ((val & 0xfc000000) == 0x0c000000) {
  8835. u32 ver_offset, addr;
  8836. int i;
  8837. if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
  8838. tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
  8839. return;
  8840. if (val != 0)
  8841. return;
  8842. addr = offset + ver_offset - start;
  8843. for (i = 0; i < 16; i += 4) {
  8844. if (tg3_nvram_read(tp, addr + i, &val))
  8845. return;
  8846. val = cpu_to_le32(val);
  8847. memcpy(tp->fw_ver + i, &val, 4);
  8848. }
  8849. }
  8850. }
  8851. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
  8852. static int __devinit tg3_get_invariants(struct tg3 *tp)
  8853. {
  8854. static struct pci_device_id write_reorder_chipsets[] = {
  8855. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  8856. PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  8857. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  8858. PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  8859. { PCI_DEVICE(PCI_VENDOR_ID_VIA,
  8860. PCI_DEVICE_ID_VIA_8385_0) },
  8861. { },
  8862. };
  8863. u32 misc_ctrl_reg;
  8864. u32 cacheline_sz_reg;
  8865. u32 pci_state_reg, grc_misc_cfg;
  8866. u32 val;
  8867. u16 pci_cmd;
  8868. int err, pcie_cap;
  8869. /* Force memory write invalidate off. If we leave it on,
  8870. * then on 5700_BX chips we have to enable a workaround.
  8871. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  8872. * to match the cacheline size. The Broadcom driver have this
  8873. * workaround but turns MWI off all the times so never uses
  8874. * it. This seems to suggest that the workaround is insufficient.
  8875. */
  8876. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  8877. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  8878. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  8879. /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
  8880. * has the register indirect write enable bit set before
  8881. * we try to access any of the MMIO registers. It is also
  8882. * critical that the PCI-X hw workaround situation is decided
  8883. * before that as well.
  8884. */
  8885. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  8886. &misc_ctrl_reg);
  8887. tp->pci_chip_rev_id = (misc_ctrl_reg >>
  8888. MISC_HOST_CTRL_CHIPREV_SHIFT);
  8889. /* Wrong chip ID in 5752 A0. This code can be removed later
  8890. * as A0 is not in production.
  8891. */
  8892. if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
  8893. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  8894. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  8895. * we need to disable memory and use config. cycles
  8896. * only to access all registers. The 5702/03 chips
  8897. * can mistakenly decode the special cycles from the
  8898. * ICH chipsets as memory write cycles, causing corruption
  8899. * of register and memory space. Only certain ICH bridges
  8900. * will drive special cycles with non-zero data during the
  8901. * address phase which can fall within the 5703's address
  8902. * range. This is not an ICH bug as the PCI spec allows
  8903. * non-zero address during special cycles. However, only
  8904. * these ICH bridges are known to drive non-zero addresses
  8905. * during special cycles.
  8906. *
  8907. * Since special cycles do not cross PCI bridges, we only
  8908. * enable this workaround if the 5703 is on the secondary
  8909. * bus of these ICH bridges.
  8910. */
  8911. if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
  8912. (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
  8913. static struct tg3_dev_id {
  8914. u32 vendor;
  8915. u32 device;
  8916. u32 rev;
  8917. } ich_chipsets[] = {
  8918. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  8919. PCI_ANY_ID },
  8920. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  8921. PCI_ANY_ID },
  8922. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  8923. 0xa },
  8924. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  8925. PCI_ANY_ID },
  8926. { },
  8927. };
  8928. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  8929. struct pci_dev *bridge = NULL;
  8930. while (pci_id->vendor != 0) {
  8931. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  8932. bridge);
  8933. if (!bridge) {
  8934. pci_id++;
  8935. continue;
  8936. }
  8937. if (pci_id->rev != PCI_ANY_ID) {
  8938. if (bridge->revision > pci_id->rev)
  8939. continue;
  8940. }
  8941. if (bridge->subordinate &&
  8942. (bridge->subordinate->number ==
  8943. tp->pdev->bus->number)) {
  8944. tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
  8945. pci_dev_put(bridge);
  8946. break;
  8947. }
  8948. }
  8949. }
  8950. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  8951. * DMA addresses > 40-bit. This bridge may have other additional
  8952. * 57xx devices behind it in some 4-port NIC designs for example.
  8953. * Any tg3 device found behind the bridge will also need the 40-bit
  8954. * DMA workaround.
  8955. */
  8956. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
  8957. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  8958. tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
  8959. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  8960. tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
  8961. }
  8962. else {
  8963. struct pci_dev *bridge = NULL;
  8964. do {
  8965. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  8966. PCI_DEVICE_ID_SERVERWORKS_EPB,
  8967. bridge);
  8968. if (bridge && bridge->subordinate &&
  8969. (bridge->subordinate->number <=
  8970. tp->pdev->bus->number) &&
  8971. (bridge->subordinate->subordinate >=
  8972. tp->pdev->bus->number)) {
  8973. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  8974. pci_dev_put(bridge);
  8975. break;
  8976. }
  8977. } while (bridge);
  8978. }
  8979. /* Initialize misc host control in PCI block. */
  8980. tp->misc_host_ctrl |= (misc_ctrl_reg &
  8981. MISC_HOST_CTRL_CHIPREV);
  8982. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  8983. tp->misc_host_ctrl);
  8984. pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  8985. &cacheline_sz_reg);
  8986. tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
  8987. tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
  8988. tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
  8989. tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
  8990. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  8991. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
  8992. tp->pdev_peer = tg3_find_peer(tp);
  8993. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  8994. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  8995. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  8996. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  8997. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  8998. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  8999. tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
  9000. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
  9001. (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  9002. tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
  9003. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  9004. tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
  9005. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
  9006. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
  9007. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
  9008. tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
  9009. tp->pdev_peer == tp->pdev))
  9010. tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
  9011. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9012. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9013. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9014. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
  9015. tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
  9016. } else {
  9017. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
  9018. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  9019. ASIC_REV_5750 &&
  9020. tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
  9021. tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
  9022. }
  9023. }
  9024. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
  9025. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
  9026. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
  9027. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
  9028. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
  9029. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  9030. tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
  9031. pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
  9032. if (pcie_cap != 0) {
  9033. tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
  9034. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9035. u16 lnkctl;
  9036. pci_read_config_word(tp->pdev,
  9037. pcie_cap + PCI_EXP_LNKCTL,
  9038. &lnkctl);
  9039. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
  9040. tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
  9041. }
  9042. }
  9043. /* If we have an AMD 762 or VIA K8T800 chipset, write
  9044. * reordering to the mailbox registers done by the host
  9045. * controller can cause major troubles. We read back from
  9046. * every mailbox register write to force the writes to be
  9047. * posted to the chip in order.
  9048. */
  9049. if (pci_dev_present(write_reorder_chipsets) &&
  9050. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  9051. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  9052. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  9053. tp->pci_lat_timer < 64) {
  9054. tp->pci_lat_timer = 64;
  9055. cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
  9056. cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
  9057. cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
  9058. cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
  9059. pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  9060. cacheline_sz_reg);
  9061. }
  9062. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  9063. &pci_state_reg);
  9064. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
  9065. tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
  9066. /* If this is a 5700 BX chipset, and we are in PCI-X
  9067. * mode, enable register write workaround.
  9068. *
  9069. * The workaround is to use indirect register accesses
  9070. * for all chip writes not to mailbox registers.
  9071. */
  9072. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
  9073. u32 pm_reg;
  9074. u16 pci_cmd;
  9075. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  9076. /* The chip can have it's power management PCI config
  9077. * space registers clobbered due to this bug.
  9078. * So explicitly force the chip into D0 here.
  9079. */
  9080. pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
  9081. &pm_reg);
  9082. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  9083. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  9084. pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
  9085. pm_reg);
  9086. /* Also, force SERR#/PERR# in PCI command. */
  9087. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9088. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  9089. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9090. }
  9091. }
  9092. /* 5700 BX chips need to have their TX producer index mailboxes
  9093. * written twice to workaround a bug.
  9094. */
  9095. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
  9096. tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
  9097. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  9098. tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
  9099. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  9100. tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
  9101. /* Chip-specific fixup from Broadcom driver */
  9102. if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
  9103. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  9104. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  9105. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  9106. }
  9107. /* Default fast path register access methods */
  9108. tp->read32 = tg3_read32;
  9109. tp->write32 = tg3_write32;
  9110. tp->read32_mbox = tg3_read32;
  9111. tp->write32_mbox = tg3_write32;
  9112. tp->write32_tx_mbox = tg3_write32;
  9113. tp->write32_rx_mbox = tg3_write32;
  9114. /* Various workaround register access methods */
  9115. if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
  9116. tp->write32 = tg3_write_indirect_reg32;
  9117. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  9118. ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  9119. tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
  9120. /*
  9121. * Back to back register writes can cause problems on these
  9122. * chips, the workaround is to read back all reg writes
  9123. * except those to mailbox regs.
  9124. *
  9125. * See tg3_write_indirect_reg32().
  9126. */
  9127. tp->write32 = tg3_write_flush_reg32;
  9128. }
  9129. if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
  9130. (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
  9131. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  9132. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  9133. tp->write32_rx_mbox = tg3_write_flush_reg32;
  9134. }
  9135. if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
  9136. tp->read32 = tg3_read_indirect_reg32;
  9137. tp->write32 = tg3_write_indirect_reg32;
  9138. tp->read32_mbox = tg3_read_indirect_mbox;
  9139. tp->write32_mbox = tg3_write_indirect_mbox;
  9140. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  9141. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  9142. iounmap(tp->regs);
  9143. tp->regs = NULL;
  9144. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9145. pci_cmd &= ~PCI_COMMAND_MEMORY;
  9146. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9147. }
  9148. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9149. tp->read32_mbox = tg3_read32_mbox_5906;
  9150. tp->write32_mbox = tg3_write32_mbox_5906;
  9151. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  9152. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  9153. }
  9154. if (tp->write32 == tg3_write_indirect_reg32 ||
  9155. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  9156. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9157. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  9158. tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
  9159. /* Get eeprom hw config before calling tg3_set_power_state().
  9160. * In particular, the TG3_FLG2_IS_NIC flag must be
  9161. * determined before calling tg3_set_power_state() so that
  9162. * we know whether or not to switch out of Vaux power.
  9163. * When the flag is set, it means that GPIO1 is used for eeprom
  9164. * write protect and also implies that it is a LOM where GPIOs
  9165. * are not used to switch power.
  9166. */
  9167. tg3_get_eeprom_hw_cfg(tp);
  9168. /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
  9169. * GPIO1 driven high will bring 5700's external PHY out of reset.
  9170. * It is also used as eeprom write protect on LOMs.
  9171. */
  9172. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  9173. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  9174. (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
  9175. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  9176. GRC_LCLCTRL_GPIO_OUTPUT1);
  9177. /* Unused GPIO3 must be driven as output on 5752 because there
  9178. * are no pull-up resistors on unused GPIO pins.
  9179. */
  9180. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  9181. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  9182. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  9183. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  9184. /* Force the chip into D0. */
  9185. err = tg3_set_power_state(tp, PCI_D0);
  9186. if (err) {
  9187. printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
  9188. pci_name(tp->pdev));
  9189. return err;
  9190. }
  9191. /* 5700 B0 chips do not support checksumming correctly due
  9192. * to hardware bugs.
  9193. */
  9194. if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
  9195. tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
  9196. /* Derive initial jumbo mode from MTU assigned in
  9197. * ether_setup() via the alloc_etherdev() call
  9198. */
  9199. if (tp->dev->mtu > ETH_DATA_LEN &&
  9200. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  9201. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  9202. /* Determine WakeOnLan speed to use. */
  9203. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9204. tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  9205. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
  9206. tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
  9207. tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
  9208. } else {
  9209. tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
  9210. }
  9211. /* A few boards don't want Ethernet@WireSpeed phy feature */
  9212. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  9213. ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  9214. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
  9215. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
  9216. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
  9217. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  9218. tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
  9219. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
  9220. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
  9221. tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
  9222. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
  9223. tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
  9224. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  9225. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9226. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
  9227. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  9228. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  9229. tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
  9230. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  9231. tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
  9232. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  9233. tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
  9234. }
  9235. tp->coalesce_mode = 0;
  9236. if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
  9237. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
  9238. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  9239. /* Initialize MAC MI mode, polling disabled. */
  9240. tw32_f(MAC_MI_MODE, tp->mi_mode);
  9241. udelay(80);
  9242. /* Initialize data/descriptor byte/word swapping. */
  9243. val = tr32(GRC_MODE);
  9244. val &= GRC_MODE_HOST_STACKUP;
  9245. tw32(GRC_MODE, val | tp->grc_mode);
  9246. tg3_switch_clocks(tp);
  9247. /* Clear this out for sanity. */
  9248. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  9249. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  9250. &pci_state_reg);
  9251. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  9252. (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
  9253. u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
  9254. if (chiprevid == CHIPREV_ID_5701_A0 ||
  9255. chiprevid == CHIPREV_ID_5701_B0 ||
  9256. chiprevid == CHIPREV_ID_5701_B2 ||
  9257. chiprevid == CHIPREV_ID_5701_B5) {
  9258. void __iomem *sram_base;
  9259. /* Write some dummy words into the SRAM status block
  9260. * area, see if it reads back correctly. If the return
  9261. * value is bad, force enable the PCIX workaround.
  9262. */
  9263. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  9264. writel(0x00000000, sram_base);
  9265. writel(0x00000000, sram_base + 4);
  9266. writel(0xffffffff, sram_base + 4);
  9267. if (readl(sram_base) != 0x00000000)
  9268. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  9269. }
  9270. }
  9271. udelay(50);
  9272. tg3_nvram_init(tp);
  9273. grc_misc_cfg = tr32(GRC_MISC_CFG);
  9274. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  9275. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  9276. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  9277. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  9278. tp->tg3_flags2 |= TG3_FLG2_IS_5788;
  9279. if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  9280. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
  9281. tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
  9282. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  9283. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  9284. HOSTCC_MODE_CLRTICK_TXBD);
  9285. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  9286. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  9287. tp->misc_host_ctrl);
  9288. }
  9289. /* these are limited to 10/100 only */
  9290. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  9291. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  9292. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  9293. tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  9294. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
  9295. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
  9296. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
  9297. (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  9298. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
  9299. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
  9300. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
  9301. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9302. tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
  9303. err = tg3_phy_probe(tp);
  9304. if (err) {
  9305. printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
  9306. pci_name(tp->pdev), err);
  9307. /* ... but do not return immediately ... */
  9308. }
  9309. tg3_read_partno(tp);
  9310. tg3_read_fw_ver(tp);
  9311. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  9312. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  9313. } else {
  9314. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  9315. tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
  9316. else
  9317. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  9318. }
  9319. /* 5700 {AX,BX} chips have a broken status block link
  9320. * change bit implementation, so we must use the
  9321. * status register in those cases.
  9322. */
  9323. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  9324. tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
  9325. else
  9326. tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
  9327. /* The led_ctrl is set during tg3_phy_probe, here we might
  9328. * have to force the link status polling mechanism based
  9329. * upon subsystem IDs.
  9330. */
  9331. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  9332. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  9333. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  9334. tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
  9335. TG3_FLAG_USE_LINKCHG_REG);
  9336. }
  9337. /* For all SERDES we poll the MAC status register. */
  9338. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  9339. tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
  9340. else
  9341. tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
  9342. /* All chips before 5787 can get confused if TX buffers
  9343. * straddle the 4GB address boundary in some cases.
  9344. */
  9345. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9346. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9347. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9348. tp->dev->hard_start_xmit = tg3_start_xmit;
  9349. else
  9350. tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
  9351. tp->rx_offset = 2;
  9352. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  9353. (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
  9354. tp->rx_offset = 0;
  9355. tp->rx_std_max_post = TG3_RX_RING_SIZE;
  9356. /* Increment the rx prod index on the rx std ring by at most
  9357. * 8 for these chips to workaround hw errata.
  9358. */
  9359. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  9360. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  9361. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  9362. tp->rx_std_max_post = 8;
  9363. /* By default, disable wake-on-lan. User can change this
  9364. * using ETHTOOL_SWOL.
  9365. */
  9366. tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  9367. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
  9368. tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
  9369. PCIE_PWR_MGMT_L1_THRESH_MSK;
  9370. return err;
  9371. }
  9372. #ifdef CONFIG_SPARC
  9373. static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
  9374. {
  9375. struct net_device *dev = tp->dev;
  9376. struct pci_dev *pdev = tp->pdev;
  9377. struct device_node *dp = pci_device_to_OF_node(pdev);
  9378. const unsigned char *addr;
  9379. int len;
  9380. addr = of_get_property(dp, "local-mac-address", &len);
  9381. if (addr && len == 6) {
  9382. memcpy(dev->dev_addr, addr, 6);
  9383. memcpy(dev->perm_addr, dev->dev_addr, 6);
  9384. return 0;
  9385. }
  9386. return -ENODEV;
  9387. }
  9388. static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
  9389. {
  9390. struct net_device *dev = tp->dev;
  9391. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  9392. memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
  9393. return 0;
  9394. }
  9395. #endif
  9396. static int __devinit tg3_get_device_address(struct tg3 *tp)
  9397. {
  9398. struct net_device *dev = tp->dev;
  9399. u32 hi, lo, mac_offset;
  9400. int addr_ok = 0;
  9401. #ifdef CONFIG_SPARC
  9402. if (!tg3_get_macaddr_sparc(tp))
  9403. return 0;
  9404. #endif
  9405. mac_offset = 0x7c;
  9406. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  9407. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  9408. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  9409. mac_offset = 0xcc;
  9410. if (tg3_nvram_lock(tp))
  9411. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  9412. else
  9413. tg3_nvram_unlock(tp);
  9414. }
  9415. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9416. mac_offset = 0x10;
  9417. /* First try to get it from MAC address mailbox. */
  9418. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  9419. if ((hi >> 16) == 0x484b) {
  9420. dev->dev_addr[0] = (hi >> 8) & 0xff;
  9421. dev->dev_addr[1] = (hi >> 0) & 0xff;
  9422. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  9423. dev->dev_addr[2] = (lo >> 24) & 0xff;
  9424. dev->dev_addr[3] = (lo >> 16) & 0xff;
  9425. dev->dev_addr[4] = (lo >> 8) & 0xff;
  9426. dev->dev_addr[5] = (lo >> 0) & 0xff;
  9427. /* Some old bootcode may report a 0 MAC address in SRAM */
  9428. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  9429. }
  9430. if (!addr_ok) {
  9431. /* Next, try NVRAM. */
  9432. if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
  9433. !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
  9434. dev->dev_addr[0] = ((hi >> 16) & 0xff);
  9435. dev->dev_addr[1] = ((hi >> 24) & 0xff);
  9436. dev->dev_addr[2] = ((lo >> 0) & 0xff);
  9437. dev->dev_addr[3] = ((lo >> 8) & 0xff);
  9438. dev->dev_addr[4] = ((lo >> 16) & 0xff);
  9439. dev->dev_addr[5] = ((lo >> 24) & 0xff);
  9440. }
  9441. /* Finally just fetch it out of the MAC control regs. */
  9442. else {
  9443. hi = tr32(MAC_ADDR_0_HIGH);
  9444. lo = tr32(MAC_ADDR_0_LOW);
  9445. dev->dev_addr[5] = lo & 0xff;
  9446. dev->dev_addr[4] = (lo >> 8) & 0xff;
  9447. dev->dev_addr[3] = (lo >> 16) & 0xff;
  9448. dev->dev_addr[2] = (lo >> 24) & 0xff;
  9449. dev->dev_addr[1] = hi & 0xff;
  9450. dev->dev_addr[0] = (hi >> 8) & 0xff;
  9451. }
  9452. }
  9453. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  9454. #ifdef CONFIG_SPARC64
  9455. if (!tg3_get_default_macaddr_sparc(tp))
  9456. return 0;
  9457. #endif
  9458. return -EINVAL;
  9459. }
  9460. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  9461. return 0;
  9462. }
  9463. #define BOUNDARY_SINGLE_CACHELINE 1
  9464. #define BOUNDARY_MULTI_CACHELINE 2
  9465. static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  9466. {
  9467. int cacheline_size;
  9468. u8 byte;
  9469. int goal;
  9470. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  9471. if (byte == 0)
  9472. cacheline_size = 1024;
  9473. else
  9474. cacheline_size = (int) byte * 4;
  9475. /* On 5703 and later chips, the boundary bits have no
  9476. * effect.
  9477. */
  9478. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  9479. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  9480. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  9481. goto out;
  9482. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  9483. goal = BOUNDARY_MULTI_CACHELINE;
  9484. #else
  9485. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  9486. goal = BOUNDARY_SINGLE_CACHELINE;
  9487. #else
  9488. goal = 0;
  9489. #endif
  9490. #endif
  9491. if (!goal)
  9492. goto out;
  9493. /* PCI controllers on most RISC systems tend to disconnect
  9494. * when a device tries to burst across a cache-line boundary.
  9495. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  9496. *
  9497. * Unfortunately, for PCI-E there are only limited
  9498. * write-side controls for this, and thus for reads
  9499. * we will still get the disconnects. We'll also waste
  9500. * these PCI cycles for both read and write for chips
  9501. * other than 5700 and 5701 which do not implement the
  9502. * boundary bits.
  9503. */
  9504. if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  9505. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  9506. switch (cacheline_size) {
  9507. case 16:
  9508. case 32:
  9509. case 64:
  9510. case 128:
  9511. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9512. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  9513. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  9514. } else {
  9515. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  9516. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  9517. }
  9518. break;
  9519. case 256:
  9520. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  9521. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  9522. break;
  9523. default:
  9524. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  9525. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  9526. break;
  9527. };
  9528. } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9529. switch (cacheline_size) {
  9530. case 16:
  9531. case 32:
  9532. case 64:
  9533. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9534. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  9535. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  9536. break;
  9537. }
  9538. /* fallthrough */
  9539. case 128:
  9540. default:
  9541. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  9542. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  9543. break;
  9544. };
  9545. } else {
  9546. switch (cacheline_size) {
  9547. case 16:
  9548. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9549. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  9550. DMA_RWCTRL_WRITE_BNDRY_16);
  9551. break;
  9552. }
  9553. /* fallthrough */
  9554. case 32:
  9555. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9556. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  9557. DMA_RWCTRL_WRITE_BNDRY_32);
  9558. break;
  9559. }
  9560. /* fallthrough */
  9561. case 64:
  9562. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9563. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  9564. DMA_RWCTRL_WRITE_BNDRY_64);
  9565. break;
  9566. }
  9567. /* fallthrough */
  9568. case 128:
  9569. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9570. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  9571. DMA_RWCTRL_WRITE_BNDRY_128);
  9572. break;
  9573. }
  9574. /* fallthrough */
  9575. case 256:
  9576. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  9577. DMA_RWCTRL_WRITE_BNDRY_256);
  9578. break;
  9579. case 512:
  9580. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  9581. DMA_RWCTRL_WRITE_BNDRY_512);
  9582. break;
  9583. case 1024:
  9584. default:
  9585. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  9586. DMA_RWCTRL_WRITE_BNDRY_1024);
  9587. break;
  9588. };
  9589. }
  9590. out:
  9591. return val;
  9592. }
  9593. static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
  9594. {
  9595. struct tg3_internal_buffer_desc test_desc;
  9596. u32 sram_dma_descs;
  9597. int i, ret;
  9598. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  9599. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  9600. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  9601. tw32(RDMAC_STATUS, 0);
  9602. tw32(WDMAC_STATUS, 0);
  9603. tw32(BUFMGR_MODE, 0);
  9604. tw32(FTQ_RESET, 0);
  9605. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  9606. test_desc.addr_lo = buf_dma & 0xffffffff;
  9607. test_desc.nic_mbuf = 0x00002100;
  9608. test_desc.len = size;
  9609. /*
  9610. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  9611. * the *second* time the tg3 driver was getting loaded after an
  9612. * initial scan.
  9613. *
  9614. * Broadcom tells me:
  9615. * ...the DMA engine is connected to the GRC block and a DMA
  9616. * reset may affect the GRC block in some unpredictable way...
  9617. * The behavior of resets to individual blocks has not been tested.
  9618. *
  9619. * Broadcom noted the GRC reset will also reset all sub-components.
  9620. */
  9621. if (to_device) {
  9622. test_desc.cqid_sqid = (13 << 8) | 2;
  9623. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  9624. udelay(40);
  9625. } else {
  9626. test_desc.cqid_sqid = (16 << 8) | 7;
  9627. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  9628. udelay(40);
  9629. }
  9630. test_desc.flags = 0x00000005;
  9631. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  9632. u32 val;
  9633. val = *(((u32 *)&test_desc) + i);
  9634. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  9635. sram_dma_descs + (i * sizeof(u32)));
  9636. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  9637. }
  9638. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  9639. if (to_device) {
  9640. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  9641. } else {
  9642. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  9643. }
  9644. ret = -ENODEV;
  9645. for (i = 0; i < 40; i++) {
  9646. u32 val;
  9647. if (to_device)
  9648. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  9649. else
  9650. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  9651. if ((val & 0xffff) == sram_dma_descs) {
  9652. ret = 0;
  9653. break;
  9654. }
  9655. udelay(100);
  9656. }
  9657. return ret;
  9658. }
  9659. #define TEST_BUFFER_SIZE 0x2000
  9660. static int __devinit tg3_test_dma(struct tg3 *tp)
  9661. {
  9662. dma_addr_t buf_dma;
  9663. u32 *buf, saved_dma_rwctrl;
  9664. int ret;
  9665. buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
  9666. if (!buf) {
  9667. ret = -ENOMEM;
  9668. goto out_nofree;
  9669. }
  9670. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  9671. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  9672. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  9673. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9674. /* DMA read watermark not used on PCIE */
  9675. tp->dma_rwctrl |= 0x00180000;
  9676. } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  9677. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
  9678. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
  9679. tp->dma_rwctrl |= 0x003f0000;
  9680. else
  9681. tp->dma_rwctrl |= 0x003f000f;
  9682. } else {
  9683. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  9684. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  9685. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  9686. u32 read_water = 0x7;
  9687. /* If the 5704 is behind the EPB bridge, we can
  9688. * do the less restrictive ONE_DMA workaround for
  9689. * better performance.
  9690. */
  9691. if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
  9692. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  9693. tp->dma_rwctrl |= 0x8000;
  9694. else if (ccval == 0x6 || ccval == 0x7)
  9695. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  9696. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
  9697. read_water = 4;
  9698. /* Set bit 23 to enable PCIX hw bug fix */
  9699. tp->dma_rwctrl |=
  9700. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  9701. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  9702. (1 << 23);
  9703. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
  9704. /* 5780 always in PCIX mode */
  9705. tp->dma_rwctrl |= 0x00144000;
  9706. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  9707. /* 5714 always in PCIX mode */
  9708. tp->dma_rwctrl |= 0x00148000;
  9709. } else {
  9710. tp->dma_rwctrl |= 0x001b000f;
  9711. }
  9712. }
  9713. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  9714. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  9715. tp->dma_rwctrl &= 0xfffffff0;
  9716. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9717. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  9718. /* Remove this if it causes problems for some boards. */
  9719. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  9720. /* On 5700/5701 chips, we need to set this bit.
  9721. * Otherwise the chip will issue cacheline transactions
  9722. * to streamable DMA memory with not all the byte
  9723. * enables turned on. This is an error on several
  9724. * RISC PCI controllers, in particular sparc64.
  9725. *
  9726. * On 5703/5704 chips, this bit has been reassigned
  9727. * a different meaning. In particular, it is used
  9728. * on those chips to enable a PCI-X workaround.
  9729. */
  9730. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  9731. }
  9732. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9733. #if 0
  9734. /* Unneeded, already done by tg3_get_invariants. */
  9735. tg3_switch_clocks(tp);
  9736. #endif
  9737. ret = 0;
  9738. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  9739. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  9740. goto out;
  9741. /* It is best to perform DMA test with maximum write burst size
  9742. * to expose the 5700/5701 write DMA bug.
  9743. */
  9744. saved_dma_rwctrl = tp->dma_rwctrl;
  9745. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  9746. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9747. while (1) {
  9748. u32 *p = buf, i;
  9749. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  9750. p[i] = i;
  9751. /* Send the buffer to the chip. */
  9752. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
  9753. if (ret) {
  9754. printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
  9755. break;
  9756. }
  9757. #if 0
  9758. /* validate data reached card RAM correctly. */
  9759. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  9760. u32 val;
  9761. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  9762. if (le32_to_cpu(val) != p[i]) {
  9763. printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
  9764. /* ret = -ENODEV here? */
  9765. }
  9766. p[i] = 0;
  9767. }
  9768. #endif
  9769. /* Now read it back. */
  9770. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
  9771. if (ret) {
  9772. printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
  9773. break;
  9774. }
  9775. /* Verify it. */
  9776. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  9777. if (p[i] == i)
  9778. continue;
  9779. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  9780. DMA_RWCTRL_WRITE_BNDRY_16) {
  9781. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  9782. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  9783. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9784. break;
  9785. } else {
  9786. printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
  9787. ret = -ENODEV;
  9788. goto out;
  9789. }
  9790. }
  9791. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  9792. /* Success. */
  9793. ret = 0;
  9794. break;
  9795. }
  9796. }
  9797. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  9798. DMA_RWCTRL_WRITE_BNDRY_16) {
  9799. static struct pci_device_id dma_wait_state_chipsets[] = {
  9800. { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
  9801. PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  9802. { },
  9803. };
  9804. /* DMA test passed without adjusting DMA boundary,
  9805. * now look for chipsets that are known to expose the
  9806. * DMA bug without failing the test.
  9807. */
  9808. if (pci_dev_present(dma_wait_state_chipsets)) {
  9809. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  9810. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  9811. }
  9812. else
  9813. /* Safe to use the calculated DMA boundary. */
  9814. tp->dma_rwctrl = saved_dma_rwctrl;
  9815. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9816. }
  9817. out:
  9818. pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
  9819. out_nofree:
  9820. return ret;
  9821. }
  9822. static void __devinit tg3_init_link_config(struct tg3 *tp)
  9823. {
  9824. tp->link_config.advertising =
  9825. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  9826. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  9827. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
  9828. ADVERTISED_Autoneg | ADVERTISED_MII);
  9829. tp->link_config.speed = SPEED_INVALID;
  9830. tp->link_config.duplex = DUPLEX_INVALID;
  9831. tp->link_config.autoneg = AUTONEG_ENABLE;
  9832. tp->link_config.active_speed = SPEED_INVALID;
  9833. tp->link_config.active_duplex = DUPLEX_INVALID;
  9834. tp->link_config.phy_is_low_power = 0;
  9835. tp->link_config.orig_speed = SPEED_INVALID;
  9836. tp->link_config.orig_duplex = DUPLEX_INVALID;
  9837. tp->link_config.orig_autoneg = AUTONEG_INVALID;
  9838. }
  9839. static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
  9840. {
  9841. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  9842. tp->bufmgr_config.mbuf_read_dma_low_water =
  9843. DEFAULT_MB_RDMA_LOW_WATER_5705;
  9844. tp->bufmgr_config.mbuf_mac_rx_low_water =
  9845. DEFAULT_MB_MACRX_LOW_WATER_5705;
  9846. tp->bufmgr_config.mbuf_high_water =
  9847. DEFAULT_MB_HIGH_WATER_5705;
  9848. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9849. tp->bufmgr_config.mbuf_mac_rx_low_water =
  9850. DEFAULT_MB_MACRX_LOW_WATER_5906;
  9851. tp->bufmgr_config.mbuf_high_water =
  9852. DEFAULT_MB_HIGH_WATER_5906;
  9853. }
  9854. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  9855. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  9856. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  9857. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  9858. tp->bufmgr_config.mbuf_high_water_jumbo =
  9859. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  9860. } else {
  9861. tp->bufmgr_config.mbuf_read_dma_low_water =
  9862. DEFAULT_MB_RDMA_LOW_WATER;
  9863. tp->bufmgr_config.mbuf_mac_rx_low_water =
  9864. DEFAULT_MB_MACRX_LOW_WATER;
  9865. tp->bufmgr_config.mbuf_high_water =
  9866. DEFAULT_MB_HIGH_WATER;
  9867. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  9868. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  9869. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  9870. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  9871. tp->bufmgr_config.mbuf_high_water_jumbo =
  9872. DEFAULT_MB_HIGH_WATER_JUMBO;
  9873. }
  9874. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  9875. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  9876. }
  9877. static char * __devinit tg3_phy_string(struct tg3 *tp)
  9878. {
  9879. switch (tp->phy_id & PHY_ID_MASK) {
  9880. case PHY_ID_BCM5400: return "5400";
  9881. case PHY_ID_BCM5401: return "5401";
  9882. case PHY_ID_BCM5411: return "5411";
  9883. case PHY_ID_BCM5701: return "5701";
  9884. case PHY_ID_BCM5703: return "5703";
  9885. case PHY_ID_BCM5704: return "5704";
  9886. case PHY_ID_BCM5705: return "5705";
  9887. case PHY_ID_BCM5750: return "5750";
  9888. case PHY_ID_BCM5752: return "5752";
  9889. case PHY_ID_BCM5714: return "5714";
  9890. case PHY_ID_BCM5780: return "5780";
  9891. case PHY_ID_BCM5755: return "5755";
  9892. case PHY_ID_BCM5787: return "5787";
  9893. case PHY_ID_BCM5756: return "5722/5756";
  9894. case PHY_ID_BCM5906: return "5906";
  9895. case PHY_ID_BCM8002: return "8002/serdes";
  9896. case 0: return "serdes";
  9897. default: return "unknown";
  9898. };
  9899. }
  9900. static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
  9901. {
  9902. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9903. strcpy(str, "PCI Express");
  9904. return str;
  9905. } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  9906. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  9907. strcpy(str, "PCIX:");
  9908. if ((clock_ctrl == 7) ||
  9909. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  9910. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  9911. strcat(str, "133MHz");
  9912. else if (clock_ctrl == 0)
  9913. strcat(str, "33MHz");
  9914. else if (clock_ctrl == 2)
  9915. strcat(str, "50MHz");
  9916. else if (clock_ctrl == 4)
  9917. strcat(str, "66MHz");
  9918. else if (clock_ctrl == 6)
  9919. strcat(str, "100MHz");
  9920. } else {
  9921. strcpy(str, "PCI:");
  9922. if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
  9923. strcat(str, "66MHz");
  9924. else
  9925. strcat(str, "33MHz");
  9926. }
  9927. if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
  9928. strcat(str, ":32-bit");
  9929. else
  9930. strcat(str, ":64-bit");
  9931. return str;
  9932. }
  9933. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
  9934. {
  9935. struct pci_dev *peer;
  9936. unsigned int func, devnr = tp->pdev->devfn & ~7;
  9937. for (func = 0; func < 8; func++) {
  9938. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  9939. if (peer && peer != tp->pdev)
  9940. break;
  9941. pci_dev_put(peer);
  9942. }
  9943. /* 5704 can be configured in single-port mode, set peer to
  9944. * tp->pdev in that case.
  9945. */
  9946. if (!peer) {
  9947. peer = tp->pdev;
  9948. return peer;
  9949. }
  9950. /*
  9951. * We don't need to keep the refcount elevated; there's no way
  9952. * to remove one half of this device without removing the other
  9953. */
  9954. pci_dev_put(peer);
  9955. return peer;
  9956. }
  9957. static void __devinit tg3_init_coal(struct tg3 *tp)
  9958. {
  9959. struct ethtool_coalesce *ec = &tp->coal;
  9960. memset(ec, 0, sizeof(*ec));
  9961. ec->cmd = ETHTOOL_GCOALESCE;
  9962. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  9963. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  9964. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  9965. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  9966. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  9967. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  9968. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  9969. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  9970. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  9971. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  9972. HOSTCC_MODE_CLRTICK_TXBD)) {
  9973. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  9974. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  9975. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  9976. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  9977. }
  9978. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  9979. ec->rx_coalesce_usecs_irq = 0;
  9980. ec->tx_coalesce_usecs_irq = 0;
  9981. ec->stats_block_coalesce_usecs = 0;
  9982. }
  9983. }
  9984. static int __devinit tg3_init_one(struct pci_dev *pdev,
  9985. const struct pci_device_id *ent)
  9986. {
  9987. static int tg3_version_printed = 0;
  9988. unsigned long tg3reg_base, tg3reg_len;
  9989. struct net_device *dev;
  9990. struct tg3 *tp;
  9991. int i, err, pm_cap;
  9992. char str[40];
  9993. u64 dma_mask, persist_dma_mask;
  9994. if (tg3_version_printed++ == 0)
  9995. printk(KERN_INFO "%s", version);
  9996. err = pci_enable_device(pdev);
  9997. if (err) {
  9998. printk(KERN_ERR PFX "Cannot enable PCI device, "
  9999. "aborting.\n");
  10000. return err;
  10001. }
  10002. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  10003. printk(KERN_ERR PFX "Cannot find proper PCI device "
  10004. "base address, aborting.\n");
  10005. err = -ENODEV;
  10006. goto err_out_disable_pdev;
  10007. }
  10008. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  10009. if (err) {
  10010. printk(KERN_ERR PFX "Cannot obtain PCI resources, "
  10011. "aborting.\n");
  10012. goto err_out_disable_pdev;
  10013. }
  10014. pci_set_master(pdev);
  10015. /* Find power-management capability. */
  10016. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  10017. if (pm_cap == 0) {
  10018. printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
  10019. "aborting.\n");
  10020. err = -EIO;
  10021. goto err_out_free_res;
  10022. }
  10023. tg3reg_base = pci_resource_start(pdev, 0);
  10024. tg3reg_len = pci_resource_len(pdev, 0);
  10025. dev = alloc_etherdev(sizeof(*tp));
  10026. if (!dev) {
  10027. printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
  10028. err = -ENOMEM;
  10029. goto err_out_free_res;
  10030. }
  10031. SET_MODULE_OWNER(dev);
  10032. SET_NETDEV_DEV(dev, &pdev->dev);
  10033. #if TG3_VLAN_TAG_USED
  10034. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  10035. dev->vlan_rx_register = tg3_vlan_rx_register;
  10036. #endif
  10037. tp = netdev_priv(dev);
  10038. tp->pdev = pdev;
  10039. tp->dev = dev;
  10040. tp->pm_cap = pm_cap;
  10041. tp->mac_mode = TG3_DEF_MAC_MODE;
  10042. tp->rx_mode = TG3_DEF_RX_MODE;
  10043. tp->tx_mode = TG3_DEF_TX_MODE;
  10044. tp->mi_mode = MAC_MI_MODE_BASE;
  10045. if (tg3_debug > 0)
  10046. tp->msg_enable = tg3_debug;
  10047. else
  10048. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  10049. /* The word/byte swap controls here control register access byte
  10050. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  10051. * setting below.
  10052. */
  10053. tp->misc_host_ctrl =
  10054. MISC_HOST_CTRL_MASK_PCI_INT |
  10055. MISC_HOST_CTRL_WORD_SWAP |
  10056. MISC_HOST_CTRL_INDIR_ACCESS |
  10057. MISC_HOST_CTRL_PCISTATE_RW;
  10058. /* The NONFRM (non-frame) byte/word swap controls take effect
  10059. * on descriptor entries, anything which isn't packet data.
  10060. *
  10061. * The StrongARM chips on the board (one for tx, one for rx)
  10062. * are running in big-endian mode.
  10063. */
  10064. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  10065. GRC_MODE_WSWAP_NONFRM_DATA);
  10066. #ifdef __BIG_ENDIAN
  10067. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  10068. #endif
  10069. spin_lock_init(&tp->lock);
  10070. spin_lock_init(&tp->indirect_lock);
  10071. INIT_WORK(&tp->reset_task, tg3_reset_task);
  10072. tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
  10073. if (tp->regs == 0UL) {
  10074. printk(KERN_ERR PFX "Cannot map device registers, "
  10075. "aborting.\n");
  10076. err = -ENOMEM;
  10077. goto err_out_free_dev;
  10078. }
  10079. tg3_init_link_config(tp);
  10080. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  10081. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  10082. tp->tx_pending = TG3_DEF_TX_RING_PENDING;
  10083. dev->open = tg3_open;
  10084. dev->stop = tg3_close;
  10085. dev->get_stats = tg3_get_stats;
  10086. dev->set_multicast_list = tg3_set_rx_mode;
  10087. dev->set_mac_address = tg3_set_mac_addr;
  10088. dev->do_ioctl = tg3_ioctl;
  10089. dev->tx_timeout = tg3_tx_timeout;
  10090. dev->poll = tg3_poll;
  10091. dev->ethtool_ops = &tg3_ethtool_ops;
  10092. dev->weight = 64;
  10093. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  10094. dev->change_mtu = tg3_change_mtu;
  10095. dev->irq = pdev->irq;
  10096. #ifdef CONFIG_NET_POLL_CONTROLLER
  10097. dev->poll_controller = tg3_poll_controller;
  10098. #endif
  10099. err = tg3_get_invariants(tp);
  10100. if (err) {
  10101. printk(KERN_ERR PFX "Problem fetching invariants of chip, "
  10102. "aborting.\n");
  10103. goto err_out_iounmap;
  10104. }
  10105. /* The EPB bridge inside 5714, 5715, and 5780 and any
  10106. * device behind the EPB cannot support DMA addresses > 40-bit.
  10107. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  10108. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  10109. * do DMA address check in tg3_start_xmit().
  10110. */
  10111. if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
  10112. persist_dma_mask = dma_mask = DMA_32BIT_MASK;
  10113. else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
  10114. persist_dma_mask = dma_mask = DMA_40BIT_MASK;
  10115. #ifdef CONFIG_HIGHMEM
  10116. dma_mask = DMA_64BIT_MASK;
  10117. #endif
  10118. } else
  10119. persist_dma_mask = dma_mask = DMA_64BIT_MASK;
  10120. /* Configure DMA attributes. */
  10121. if (dma_mask > DMA_32BIT_MASK) {
  10122. err = pci_set_dma_mask(pdev, dma_mask);
  10123. if (!err) {
  10124. dev->features |= NETIF_F_HIGHDMA;
  10125. err = pci_set_consistent_dma_mask(pdev,
  10126. persist_dma_mask);
  10127. if (err < 0) {
  10128. printk(KERN_ERR PFX "Unable to obtain 64 bit "
  10129. "DMA for consistent allocations\n");
  10130. goto err_out_iounmap;
  10131. }
  10132. }
  10133. }
  10134. if (err || dma_mask == DMA_32BIT_MASK) {
  10135. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  10136. if (err) {
  10137. printk(KERN_ERR PFX "No usable DMA configuration, "
  10138. "aborting.\n");
  10139. goto err_out_iounmap;
  10140. }
  10141. }
  10142. tg3_init_bufmgr_config(tp);
  10143. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  10144. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  10145. }
  10146. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10147. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  10148. tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
  10149. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  10150. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  10151. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  10152. } else {
  10153. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
  10154. }
  10155. /* TSO is on by default on chips that support hardware TSO.
  10156. * Firmware TSO on older chips gives lower performance, so it
  10157. * is off by default, but can be enabled using ethtool.
  10158. */
  10159. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  10160. dev->features |= NETIF_F_TSO;
  10161. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
  10162. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
  10163. dev->features |= NETIF_F_TSO6;
  10164. }
  10165. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
  10166. !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
  10167. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  10168. tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
  10169. tp->rx_pending = 63;
  10170. }
  10171. err = tg3_get_device_address(tp);
  10172. if (err) {
  10173. printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
  10174. "aborting.\n");
  10175. goto err_out_iounmap;
  10176. }
  10177. /*
  10178. * Reset chip in case UNDI or EFI driver did not shutdown
  10179. * DMA self test will enable WDMAC and we'll see (spurious)
  10180. * pending DMA on the PCI bus at that point.
  10181. */
  10182. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  10183. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  10184. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  10185. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10186. }
  10187. err = tg3_test_dma(tp);
  10188. if (err) {
  10189. printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
  10190. goto err_out_iounmap;
  10191. }
  10192. /* Tigon3 can do ipv4 only... and some chips have buggy
  10193. * checksumming.
  10194. */
  10195. if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
  10196. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  10197. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10198. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
  10199. dev->features |= NETIF_F_IPV6_CSUM;
  10200. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  10201. } else
  10202. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  10203. /* flow control autonegotiation is default behavior */
  10204. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  10205. tg3_init_coal(tp);
  10206. pci_set_drvdata(pdev, dev);
  10207. err = register_netdev(dev);
  10208. if (err) {
  10209. printk(KERN_ERR PFX "Cannot register net device, "
  10210. "aborting.\n");
  10211. goto err_out_iounmap;
  10212. }
  10213. printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
  10214. dev->name,
  10215. tp->board_part_number,
  10216. tp->pci_chip_rev_id,
  10217. tg3_phy_string(tp),
  10218. tg3_bus_string(tp, str),
  10219. ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
  10220. ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
  10221. "10/100/1000Base-T")));
  10222. for (i = 0; i < 6; i++)
  10223. printk("%2.2x%c", dev->dev_addr[i],
  10224. i == 5 ? '\n' : ':');
  10225. printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
  10226. "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
  10227. dev->name,
  10228. (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
  10229. (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
  10230. (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
  10231. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
  10232. (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
  10233. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
  10234. printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  10235. dev->name, tp->dma_rwctrl,
  10236. (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
  10237. (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
  10238. return 0;
  10239. err_out_iounmap:
  10240. if (tp->regs) {
  10241. iounmap(tp->regs);
  10242. tp->regs = NULL;
  10243. }
  10244. err_out_free_dev:
  10245. free_netdev(dev);
  10246. err_out_free_res:
  10247. pci_release_regions(pdev);
  10248. err_out_disable_pdev:
  10249. pci_disable_device(pdev);
  10250. pci_set_drvdata(pdev, NULL);
  10251. return err;
  10252. }
  10253. static void __devexit tg3_remove_one(struct pci_dev *pdev)
  10254. {
  10255. struct net_device *dev = pci_get_drvdata(pdev);
  10256. if (dev) {
  10257. struct tg3 *tp = netdev_priv(dev);
  10258. flush_scheduled_work();
  10259. unregister_netdev(dev);
  10260. if (tp->regs) {
  10261. iounmap(tp->regs);
  10262. tp->regs = NULL;
  10263. }
  10264. free_netdev(dev);
  10265. pci_release_regions(pdev);
  10266. pci_disable_device(pdev);
  10267. pci_set_drvdata(pdev, NULL);
  10268. }
  10269. }
  10270. static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
  10271. {
  10272. struct net_device *dev = pci_get_drvdata(pdev);
  10273. struct tg3 *tp = netdev_priv(dev);
  10274. int err;
  10275. if (!netif_running(dev))
  10276. return 0;
  10277. flush_scheduled_work();
  10278. tg3_netif_stop(tp);
  10279. del_timer_sync(&tp->timer);
  10280. tg3_full_lock(tp, 1);
  10281. tg3_disable_ints(tp);
  10282. tg3_full_unlock(tp);
  10283. netif_device_detach(dev);
  10284. tg3_full_lock(tp, 0);
  10285. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10286. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  10287. tg3_full_unlock(tp);
  10288. /* Save MSI address and data for resume. */
  10289. pci_save_state(pdev);
  10290. err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
  10291. if (err) {
  10292. tg3_full_lock(tp, 0);
  10293. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  10294. if (tg3_restart_hw(tp, 1))
  10295. goto out;
  10296. tp->timer.expires = jiffies + tp->timer_offset;
  10297. add_timer(&tp->timer);
  10298. netif_device_attach(dev);
  10299. tg3_netif_start(tp);
  10300. out:
  10301. tg3_full_unlock(tp);
  10302. }
  10303. return err;
  10304. }
  10305. static int tg3_resume(struct pci_dev *pdev)
  10306. {
  10307. struct net_device *dev = pci_get_drvdata(pdev);
  10308. struct tg3 *tp = netdev_priv(dev);
  10309. int err;
  10310. if (!netif_running(dev))
  10311. return 0;
  10312. pci_restore_state(tp->pdev);
  10313. err = tg3_set_power_state(tp, PCI_D0);
  10314. if (err)
  10315. return err;
  10316. netif_device_attach(dev);
  10317. tg3_full_lock(tp, 0);
  10318. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  10319. err = tg3_restart_hw(tp, 1);
  10320. if (err)
  10321. goto out;
  10322. tp->timer.expires = jiffies + tp->timer_offset;
  10323. add_timer(&tp->timer);
  10324. tg3_netif_start(tp);
  10325. out:
  10326. tg3_full_unlock(tp);
  10327. return err;
  10328. }
  10329. static struct pci_driver tg3_driver = {
  10330. .name = DRV_MODULE_NAME,
  10331. .id_table = tg3_pci_tbl,
  10332. .probe = tg3_init_one,
  10333. .remove = __devexit_p(tg3_remove_one),
  10334. .suspend = tg3_suspend,
  10335. .resume = tg3_resume
  10336. };
  10337. static int __init tg3_init(void)
  10338. {
  10339. return pci_register_driver(&tg3_driver);
  10340. }
  10341. static void __exit tg3_cleanup(void)
  10342. {
  10343. pci_unregister_driver(&tg3_driver);
  10344. }
  10345. module_init(tg3_init);
  10346. module_exit(tg3_cleanup);