mv64x60.c 68 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454
  1. /*
  2. * Common routines for the Marvell/Galileo Discovery line of host bridges
  3. * (gt64260, mv64360, mv64460, ...).
  4. *
  5. * Author: Mark A. Greer <mgreer@mvista.com>
  6. *
  7. * 2004 (c) MontaVista, Software, Inc. This file is licensed under
  8. * the terms of the GNU General Public License version 2. This program
  9. * is licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/pci.h>
  15. #include <linux/slab.h>
  16. #include <linux/module.h>
  17. #include <linux/mutex.h>
  18. #include <linux/string.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/mv643xx.h>
  21. #include <linux/platform_device.h>
  22. #include <asm/byteorder.h>
  23. #include <asm/io.h>
  24. #include <asm/irq.h>
  25. #include <asm/uaccess.h>
  26. #include <asm/machdep.h>
  27. #include <asm/pci-bridge.h>
  28. #include <asm/delay.h>
  29. #include <asm/mv64x60.h>
  30. u8 mv64x60_pci_exclude_bridge = 1;
  31. DEFINE_SPINLOCK(mv64x60_lock);
  32. static phys_addr_t mv64x60_bridge_pbase;
  33. static void __iomem *mv64x60_bridge_vbase;
  34. static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID;
  35. static u32 mv64x60_bridge_rev;
  36. #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
  37. static struct pci_controller sysfs_hose_a;
  38. #endif
  39. static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
  40. static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
  41. static void gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus,
  42. u32 window, u32 base);
  43. static void gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
  44. struct pci_controller *hose, u32 bus, u32 base);
  45. static u32 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
  46. static void gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
  47. static void gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
  48. static void gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
  49. static void gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
  50. static void gt64260_disable_all_windows(struct mv64x60_handle *bh,
  51. struct mv64x60_setup_info *si);
  52. static void gt64260a_chip_specific_init(struct mv64x60_handle *bh,
  53. struct mv64x60_setup_info *si);
  54. static void gt64260b_chip_specific_init(struct mv64x60_handle *bh,
  55. struct mv64x60_setup_info *si);
  56. static u32 mv64360_translate_size(u32 base, u32 size, u32 num_bits);
  57. static u32 mv64360_untranslate_size(u32 base, u32 size, u32 num_bits);
  58. static void mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus,
  59. u32 window, u32 base);
  60. static void mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
  61. struct pci_controller *hose, u32 bus, u32 base);
  62. static u32 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window);
  63. static void mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window);
  64. static void mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window);
  65. static void mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window);
  66. static void mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window);
  67. static void mv64360_disable_all_windows(struct mv64x60_handle *bh,
  68. struct mv64x60_setup_info *si);
  69. static void mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
  70. struct mv64x60_setup_info *si,
  71. u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
  72. static void mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base);
  73. static void mv64360_chip_specific_init(struct mv64x60_handle *bh,
  74. struct mv64x60_setup_info *si);
  75. static void mv64460_chip_specific_init(struct mv64x60_handle *bh,
  76. struct mv64x60_setup_info *si);
  77. /*
  78. * Define tables that have the chip-specific info for each type of
  79. * Marvell bridge chip.
  80. */
  81. static struct mv64x60_chip_info gt64260a_ci __initdata = { /* GT64260A */
  82. .translate_size = gt64260_translate_size,
  83. .untranslate_size = gt64260_untranslate_size,
  84. .set_pci2mem_window = gt64260_set_pci2mem_window,
  85. .set_pci2regs_window = gt64260_set_pci2regs_window,
  86. .is_enabled_32bit = gt64260_is_enabled_32bit,
  87. .enable_window_32bit = gt64260_enable_window_32bit,
  88. .disable_window_32bit = gt64260_disable_window_32bit,
  89. .enable_window_64bit = gt64260_enable_window_64bit,
  90. .disable_window_64bit = gt64260_disable_window_64bit,
  91. .disable_all_windows = gt64260_disable_all_windows,
  92. .chip_specific_init = gt64260a_chip_specific_init,
  93. .window_tab_32bit = gt64260_32bit_windows,
  94. .window_tab_64bit = gt64260_64bit_windows,
  95. };
  96. static struct mv64x60_chip_info gt64260b_ci __initdata = { /* GT64260B */
  97. .translate_size = gt64260_translate_size,
  98. .untranslate_size = gt64260_untranslate_size,
  99. .set_pci2mem_window = gt64260_set_pci2mem_window,
  100. .set_pci2regs_window = gt64260_set_pci2regs_window,
  101. .is_enabled_32bit = gt64260_is_enabled_32bit,
  102. .enable_window_32bit = gt64260_enable_window_32bit,
  103. .disable_window_32bit = gt64260_disable_window_32bit,
  104. .enable_window_64bit = gt64260_enable_window_64bit,
  105. .disable_window_64bit = gt64260_disable_window_64bit,
  106. .disable_all_windows = gt64260_disable_all_windows,
  107. .chip_specific_init = gt64260b_chip_specific_init,
  108. .window_tab_32bit = gt64260_32bit_windows,
  109. .window_tab_64bit = gt64260_64bit_windows,
  110. };
  111. static struct mv64x60_chip_info mv64360_ci __initdata = { /* MV64360 */
  112. .translate_size = mv64360_translate_size,
  113. .untranslate_size = mv64360_untranslate_size,
  114. .set_pci2mem_window = mv64360_set_pci2mem_window,
  115. .set_pci2regs_window = mv64360_set_pci2regs_window,
  116. .is_enabled_32bit = mv64360_is_enabled_32bit,
  117. .enable_window_32bit = mv64360_enable_window_32bit,
  118. .disable_window_32bit = mv64360_disable_window_32bit,
  119. .enable_window_64bit = mv64360_enable_window_64bit,
  120. .disable_window_64bit = mv64360_disable_window_64bit,
  121. .disable_all_windows = mv64360_disable_all_windows,
  122. .config_io2mem_windows = mv64360_config_io2mem_windows,
  123. .set_mpsc2regs_window = mv64360_set_mpsc2regs_window,
  124. .chip_specific_init = mv64360_chip_specific_init,
  125. .window_tab_32bit = mv64360_32bit_windows,
  126. .window_tab_64bit = mv64360_64bit_windows,
  127. };
  128. static struct mv64x60_chip_info mv64460_ci __initdata = { /* MV64460 */
  129. .translate_size = mv64360_translate_size,
  130. .untranslate_size = mv64360_untranslate_size,
  131. .set_pci2mem_window = mv64360_set_pci2mem_window,
  132. .set_pci2regs_window = mv64360_set_pci2regs_window,
  133. .is_enabled_32bit = mv64360_is_enabled_32bit,
  134. .enable_window_32bit = mv64360_enable_window_32bit,
  135. .disable_window_32bit = mv64360_disable_window_32bit,
  136. .enable_window_64bit = mv64360_enable_window_64bit,
  137. .disable_window_64bit = mv64360_disable_window_64bit,
  138. .disable_all_windows = mv64360_disable_all_windows,
  139. .config_io2mem_windows = mv64360_config_io2mem_windows,
  140. .set_mpsc2regs_window = mv64360_set_mpsc2regs_window,
  141. .chip_specific_init = mv64460_chip_specific_init,
  142. .window_tab_32bit = mv64360_32bit_windows,
  143. .window_tab_64bit = mv64360_64bit_windows,
  144. };
  145. /*
  146. *****************************************************************************
  147. *
  148. * Platform Device Definitions
  149. *
  150. *****************************************************************************
  151. */
  152. #ifdef CONFIG_SERIAL_MPSC
  153. static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = {
  154. .mrr_val = 0x3ffffe38,
  155. .rcrr_val = 0,
  156. .tcrr_val = 0,
  157. .intr_cause_val = 0,
  158. .intr_mask_val = 0,
  159. };
  160. static struct resource mv64x60_mpsc_shared_resources[] = {
  161. /* Do not change the order of the IORESOURCE_MEM resources */
  162. [0] = {
  163. .name = "mpsc routing base",
  164. .start = MV64x60_MPSC_ROUTING_OFFSET,
  165. .end = MV64x60_MPSC_ROUTING_OFFSET +
  166. MPSC_ROUTING_REG_BLOCK_SIZE - 1,
  167. .flags = IORESOURCE_MEM,
  168. },
  169. [1] = {
  170. .name = "sdma intr base",
  171. .start = MV64x60_SDMA_INTR_OFFSET,
  172. .end = MV64x60_SDMA_INTR_OFFSET +
  173. MPSC_SDMA_INTR_REG_BLOCK_SIZE - 1,
  174. .flags = IORESOURCE_MEM,
  175. },
  176. };
  177. static struct platform_device mpsc_shared_device = { /* Shared device */
  178. .name = MPSC_SHARED_NAME,
  179. .id = 0,
  180. .num_resources = ARRAY_SIZE(mv64x60_mpsc_shared_resources),
  181. .resource = mv64x60_mpsc_shared_resources,
  182. .dev = {
  183. .platform_data = &mv64x60_mpsc_shared_pdata,
  184. },
  185. };
  186. static struct mpsc_pdata mv64x60_mpsc0_pdata = {
  187. .mirror_regs = 0,
  188. .cache_mgmt = 0,
  189. .max_idle = 0,
  190. .default_baud = 9600,
  191. .default_bits = 8,
  192. .default_parity = 'n',
  193. .default_flow = 'n',
  194. .chr_1_val = 0x00000000,
  195. .chr_2_val = 0x00000000,
  196. .chr_10_val = 0x00000003,
  197. .mpcr_val = 0,
  198. .bcr_val = 0,
  199. .brg_can_tune = 0,
  200. .brg_clk_src = 8, /* Default to TCLK */
  201. .brg_clk_freq = 100000000, /* Default to 100 MHz */
  202. };
  203. static struct resource mv64x60_mpsc0_resources[] = {
  204. /* Do not change the order of the IORESOURCE_MEM resources */
  205. [0] = {
  206. .name = "mpsc 0 base",
  207. .start = MV64x60_MPSC_0_OFFSET,
  208. .end = MV64x60_MPSC_0_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
  209. .flags = IORESOURCE_MEM,
  210. },
  211. [1] = {
  212. .name = "sdma 0 base",
  213. .start = MV64x60_SDMA_0_OFFSET,
  214. .end = MV64x60_SDMA_0_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
  215. .flags = IORESOURCE_MEM,
  216. },
  217. [2] = {
  218. .name = "brg 0 base",
  219. .start = MV64x60_BRG_0_OFFSET,
  220. .end = MV64x60_BRG_0_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
  221. .flags = IORESOURCE_MEM,
  222. },
  223. [3] = {
  224. .name = "sdma 0 irq",
  225. .start = MV64x60_IRQ_SDMA_0,
  226. .end = MV64x60_IRQ_SDMA_0,
  227. .flags = IORESOURCE_IRQ,
  228. },
  229. };
  230. static struct platform_device mpsc0_device = {
  231. .name = MPSC_CTLR_NAME,
  232. .id = 0,
  233. .num_resources = ARRAY_SIZE(mv64x60_mpsc0_resources),
  234. .resource = mv64x60_mpsc0_resources,
  235. .dev = {
  236. .platform_data = &mv64x60_mpsc0_pdata,
  237. },
  238. };
  239. static struct mpsc_pdata mv64x60_mpsc1_pdata = {
  240. .mirror_regs = 0,
  241. .cache_mgmt = 0,
  242. .max_idle = 0,
  243. .default_baud = 9600,
  244. .default_bits = 8,
  245. .default_parity = 'n',
  246. .default_flow = 'n',
  247. .chr_1_val = 0x00000000,
  248. .chr_1_val = 0x00000000,
  249. .chr_2_val = 0x00000000,
  250. .chr_10_val = 0x00000003,
  251. .mpcr_val = 0,
  252. .bcr_val = 0,
  253. .brg_can_tune = 0,
  254. .brg_clk_src = 8, /* Default to TCLK */
  255. .brg_clk_freq = 100000000, /* Default to 100 MHz */
  256. };
  257. static struct resource mv64x60_mpsc1_resources[] = {
  258. /* Do not change the order of the IORESOURCE_MEM resources */
  259. [0] = {
  260. .name = "mpsc 1 base",
  261. .start = MV64x60_MPSC_1_OFFSET,
  262. .end = MV64x60_MPSC_1_OFFSET + MPSC_REG_BLOCK_SIZE - 1,
  263. .flags = IORESOURCE_MEM,
  264. },
  265. [1] = {
  266. .name = "sdma 1 base",
  267. .start = MV64x60_SDMA_1_OFFSET,
  268. .end = MV64x60_SDMA_1_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1,
  269. .flags = IORESOURCE_MEM,
  270. },
  271. [2] = {
  272. .name = "brg 1 base",
  273. .start = MV64x60_BRG_1_OFFSET,
  274. .end = MV64x60_BRG_1_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1,
  275. .flags = IORESOURCE_MEM,
  276. },
  277. [3] = {
  278. .name = "sdma 1 irq",
  279. .start = MV64360_IRQ_SDMA_1,
  280. .end = MV64360_IRQ_SDMA_1,
  281. .flags = IORESOURCE_IRQ,
  282. },
  283. };
  284. static struct platform_device mpsc1_device = {
  285. .name = MPSC_CTLR_NAME,
  286. .id = 1,
  287. .num_resources = ARRAY_SIZE(mv64x60_mpsc1_resources),
  288. .resource = mv64x60_mpsc1_resources,
  289. .dev = {
  290. .platform_data = &mv64x60_mpsc1_pdata,
  291. },
  292. };
  293. #endif
  294. #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
  295. static struct resource mv64x60_eth_shared_resources[] = {
  296. [0] = {
  297. .name = "ethernet shared base",
  298. .start = MV643XX_ETH_SHARED_REGS,
  299. .end = MV643XX_ETH_SHARED_REGS +
  300. MV643XX_ETH_SHARED_REGS_SIZE - 1,
  301. .flags = IORESOURCE_MEM,
  302. },
  303. };
  304. static struct platform_device mv64x60_eth_shared_device = {
  305. .name = MV643XX_ETH_SHARED_NAME,
  306. .id = 0,
  307. .num_resources = ARRAY_SIZE(mv64x60_eth_shared_resources),
  308. .resource = mv64x60_eth_shared_resources,
  309. };
  310. #ifdef CONFIG_MV643XX_ETH_0
  311. static struct resource mv64x60_eth0_resources[] = {
  312. [0] = {
  313. .name = "eth0 irq",
  314. .start = MV64x60_IRQ_ETH_0,
  315. .end = MV64x60_IRQ_ETH_0,
  316. .flags = IORESOURCE_IRQ,
  317. },
  318. };
  319. static struct mv643xx_eth_platform_data eth0_pd = {
  320. .port_number = 0,
  321. };
  322. static struct platform_device eth0_device = {
  323. .name = MV643XX_ETH_NAME,
  324. .id = 0,
  325. .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
  326. .resource = mv64x60_eth0_resources,
  327. .dev = {
  328. .platform_data = &eth0_pd,
  329. },
  330. };
  331. #endif
  332. #ifdef CONFIG_MV643XX_ETH_1
  333. static struct resource mv64x60_eth1_resources[] = {
  334. [0] = {
  335. .name = "eth1 irq",
  336. .start = MV64x60_IRQ_ETH_1,
  337. .end = MV64x60_IRQ_ETH_1,
  338. .flags = IORESOURCE_IRQ,
  339. },
  340. };
  341. static struct mv643xx_eth_platform_data eth1_pd = {
  342. .port_number = 1,
  343. };
  344. static struct platform_device eth1_device = {
  345. .name = MV643XX_ETH_NAME,
  346. .id = 1,
  347. .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
  348. .resource = mv64x60_eth1_resources,
  349. .dev = {
  350. .platform_data = &eth1_pd,
  351. },
  352. };
  353. #endif
  354. #ifdef CONFIG_MV643XX_ETH_2
  355. static struct resource mv64x60_eth2_resources[] = {
  356. [0] = {
  357. .name = "eth2 irq",
  358. .start = MV64x60_IRQ_ETH_2,
  359. .end = MV64x60_IRQ_ETH_2,
  360. .flags = IORESOURCE_IRQ,
  361. },
  362. };
  363. static struct mv643xx_eth_platform_data eth2_pd = {
  364. .port_number = 2,
  365. };
  366. static struct platform_device eth2_device = {
  367. .name = MV643XX_ETH_NAME,
  368. .id = 2,
  369. .num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
  370. .resource = mv64x60_eth2_resources,
  371. .dev = {
  372. .platform_data = &eth2_pd,
  373. },
  374. };
  375. #endif
  376. #endif
  377. #ifdef CONFIG_I2C_MV64XXX
  378. static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
  379. .freq_m = 8,
  380. .freq_n = 3,
  381. .timeout = 1000, /* Default timeout of 1 second */
  382. .retries = 1,
  383. };
  384. static struct resource mv64xxx_i2c_resources[] = {
  385. /* Do not change the order of the IORESOURCE_MEM resources */
  386. [0] = {
  387. .name = "mv64xxx i2c base",
  388. .start = MV64XXX_I2C_OFFSET,
  389. .end = MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1,
  390. .flags = IORESOURCE_MEM,
  391. },
  392. [1] = {
  393. .name = "mv64xxx i2c irq",
  394. .start = MV64x60_IRQ_I2C,
  395. .end = MV64x60_IRQ_I2C,
  396. .flags = IORESOURCE_IRQ,
  397. },
  398. };
  399. static struct platform_device i2c_device = {
  400. .name = MV64XXX_I2C_CTLR_NAME,
  401. .id = 0,
  402. .num_resources = ARRAY_SIZE(mv64xxx_i2c_resources),
  403. .resource = mv64xxx_i2c_resources,
  404. .dev = {
  405. .platform_data = &mv64xxx_i2c_pdata,
  406. },
  407. };
  408. #endif
  409. #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
  410. static struct mv64xxx_pdata mv64xxx_pdata = {
  411. .hs_reg_valid = 0,
  412. };
  413. static struct platform_device mv64xxx_device = { /* general mv64x60 stuff */
  414. .name = MV64XXX_DEV_NAME,
  415. .id = 0,
  416. .dev = {
  417. .platform_data = &mv64xxx_pdata,
  418. },
  419. };
  420. #endif
  421. static struct platform_device *mv64x60_pd_devs[] __initdata = {
  422. #ifdef CONFIG_SERIAL_MPSC
  423. &mpsc_shared_device,
  424. &mpsc0_device,
  425. &mpsc1_device,
  426. #endif
  427. #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
  428. &mv64x60_eth_shared_device,
  429. #endif
  430. #ifdef CONFIG_MV643XX_ETH_0
  431. &eth0_device,
  432. #endif
  433. #ifdef CONFIG_MV643XX_ETH_1
  434. &eth1_device,
  435. #endif
  436. #ifdef CONFIG_MV643XX_ETH_2
  437. &eth2_device,
  438. #endif
  439. #ifdef CONFIG_I2C_MV64XXX
  440. &i2c_device,
  441. #endif
  442. #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
  443. &mv64xxx_device,
  444. #endif
  445. };
  446. /*
  447. *****************************************************************************
  448. *
  449. * Bridge Initialization Routines
  450. *
  451. *****************************************************************************
  452. */
  453. /*
  454. * mv64x60_init()
  455. *
  456. * Initialize the bridge based on setting passed in via 'si'. The bridge
  457. * handle, 'bh', will be set so that it can be used to make subsequent
  458. * calls to routines in this file.
  459. */
  460. int __init
  461. mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
  462. {
  463. u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
  464. if (ppc_md.progress)
  465. ppc_md.progress("mv64x60 initialization", 0x0);
  466. spin_lock_init(&mv64x60_lock);
  467. mv64x60_early_init(bh, si);
  468. if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) {
  469. iounmap(bh->v_base);
  470. bh->v_base = 0;
  471. if (ppc_md.progress)
  472. ppc_md.progress("mv64x60_init: Can't determine chip",0);
  473. return -1;
  474. }
  475. bh->ci->disable_all_windows(bh, si);
  476. mv64x60_get_mem_windows(bh, mem_windows);
  477. mv64x60_config_cpu2mem_windows(bh, si, mem_windows);
  478. if (bh->ci->config_io2mem_windows)
  479. bh->ci->config_io2mem_windows(bh, si, mem_windows);
  480. if (bh->ci->set_mpsc2regs_window)
  481. bh->ci->set_mpsc2regs_window(bh, si->phys_reg_base);
  482. if (si->pci_1.enable_bus) {
  483. bh->io_base_b = (u32)ioremap(si->pci_1.pci_io.cpu_base,
  484. si->pci_1.pci_io.size);
  485. isa_io_base = bh->io_base_b;
  486. }
  487. if (si->pci_0.enable_bus) {
  488. bh->io_base_a = (u32)ioremap(si->pci_0.pci_io.cpu_base,
  489. si->pci_0.pci_io.size);
  490. isa_io_base = bh->io_base_a;
  491. mv64x60_alloc_hose(bh, MV64x60_PCI0_CONFIG_ADDR,
  492. MV64x60_PCI0_CONFIG_DATA, &bh->hose_a);
  493. mv64x60_config_resources(bh->hose_a, &si->pci_0, bh->io_base_a);
  494. mv64x60_config_pci_params(bh->hose_a, &si->pci_0);
  495. mv64x60_config_cpu2pci_windows(bh, &si->pci_0, 0);
  496. mv64x60_config_pci2mem_windows(bh, bh->hose_a, &si->pci_0, 0,
  497. mem_windows);
  498. bh->ci->set_pci2regs_window(bh, bh->hose_a, 0,
  499. si->phys_reg_base);
  500. }
  501. if (si->pci_1.enable_bus) {
  502. mv64x60_alloc_hose(bh, MV64x60_PCI1_CONFIG_ADDR,
  503. MV64x60_PCI1_CONFIG_DATA, &bh->hose_b);
  504. mv64x60_config_resources(bh->hose_b, &si->pci_1, bh->io_base_b);
  505. mv64x60_config_pci_params(bh->hose_b, &si->pci_1);
  506. mv64x60_config_cpu2pci_windows(bh, &si->pci_1, 1);
  507. mv64x60_config_pci2mem_windows(bh, bh->hose_b, &si->pci_1, 1,
  508. mem_windows);
  509. bh->ci->set_pci2regs_window(bh, bh->hose_b, 1,
  510. si->phys_reg_base);
  511. }
  512. bh->ci->chip_specific_init(bh, si);
  513. mv64x60_pd_fixup(bh, mv64x60_pd_devs, ARRAY_SIZE(mv64x60_pd_devs));
  514. return 0;
  515. }
  516. /*
  517. * mv64x60_early_init()
  518. *
  519. * Do some bridge work that must take place before we start messing with
  520. * the bridge for real.
  521. */
  522. void __init
  523. mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si)
  524. {
  525. struct pci_controller hose_a, hose_b;
  526. memset(bh, 0, sizeof(*bh));
  527. bh->p_base = si->phys_reg_base;
  528. bh->v_base = ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE);
  529. mv64x60_bridge_pbase = bh->p_base;
  530. mv64x60_bridge_vbase = bh->v_base;
  531. /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */
  532. bh->pci_mode_a = mv64x60_read(bh, MV64x60_PCI0_MODE) &
  533. MV64x60_PCIMODE_MASK;
  534. bh->pci_mode_b = mv64x60_read(bh, MV64x60_PCI1_MODE) &
  535. MV64x60_PCIMODE_MASK;
  536. /* Need temporary hose structs to call mv64x60_set_bus() */
  537. memset(&hose_a, 0, sizeof(hose_a));
  538. memset(&hose_b, 0, sizeof(hose_b));
  539. setup_indirect_pci_nomap(&hose_a, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
  540. bh->v_base + MV64x60_PCI0_CONFIG_DATA);
  541. setup_indirect_pci_nomap(&hose_b, bh->v_base + MV64x60_PCI1_CONFIG_ADDR,
  542. bh->v_base + MV64x60_PCI1_CONFIG_DATA);
  543. bh->hose_a = &hose_a;
  544. bh->hose_b = &hose_b;
  545. #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
  546. /* Save a copy of hose_a for sysfs functions -- hack */
  547. memcpy(&sysfs_hose_a, &hose_a, sizeof(hose_a));
  548. #endif
  549. mv64x60_set_bus(bh, 0, 0);
  550. mv64x60_set_bus(bh, 1, 0);
  551. bh->hose_a = NULL;
  552. bh->hose_b = NULL;
  553. /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */
  554. mv64x60_clr_bits(bh, MV64x60_PCI0_PCI_DECODE_CNTL, 0x00000001);
  555. mv64x60_clr_bits(bh, MV64x60_PCI1_PCI_DECODE_CNTL, 0x00000001);
  556. /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */
  557. mv64x60_clr_bits(bh, MV64x60_CPU_CONFIG, (1<<12));
  558. mv64x60_set_bits(bh, MV64x60_CPU_CONFIG, (1<<27));
  559. mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff);
  560. mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff);
  561. }
  562. /*
  563. *****************************************************************************
  564. *
  565. * Window Config Routines
  566. *
  567. *****************************************************************************
  568. */
  569. /*
  570. * mv64x60_get_32bit_window()
  571. *
  572. * Determine the base address and size of a 32-bit window on the bridge.
  573. */
  574. void __init
  575. mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window,
  576. u32 *base, u32 *size)
  577. {
  578. u32 val, base_reg, size_reg, base_bits, size_bits;
  579. u32 (*get_from_field)(u32 val, u32 num_bits);
  580. base_reg = bh->ci->window_tab_32bit[window].base_reg;
  581. if (base_reg != 0) {
  582. size_reg = bh->ci->window_tab_32bit[window].size_reg;
  583. base_bits = bh->ci->window_tab_32bit[window].base_bits;
  584. size_bits = bh->ci->window_tab_32bit[window].size_bits;
  585. get_from_field= bh->ci->window_tab_32bit[window].get_from_field;
  586. val = mv64x60_read(bh, base_reg);
  587. *base = get_from_field(val, base_bits);
  588. if (size_reg != 0) {
  589. val = mv64x60_read(bh, size_reg);
  590. val = get_from_field(val, size_bits);
  591. *size = bh->ci->untranslate_size(*base, val, size_bits);
  592. } else
  593. *size = 0;
  594. } else {
  595. *base = 0;
  596. *size = 0;
  597. }
  598. pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
  599. window, *base, *size);
  600. }
  601. /*
  602. * mv64x60_set_32bit_window()
  603. *
  604. * Set the base address and size of a 32-bit window on the bridge.
  605. */
  606. void __init
  607. mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window,
  608. u32 base, u32 size, u32 other_bits)
  609. {
  610. u32 val, base_reg, size_reg, base_bits, size_bits;
  611. u32 (*map_to_field)(u32 val, u32 num_bits);
  612. pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n",
  613. window, base, size, other_bits);
  614. base_reg = bh->ci->window_tab_32bit[window].base_reg;
  615. if (base_reg != 0) {
  616. size_reg = bh->ci->window_tab_32bit[window].size_reg;
  617. base_bits = bh->ci->window_tab_32bit[window].base_bits;
  618. size_bits = bh->ci->window_tab_32bit[window].size_bits;
  619. map_to_field = bh->ci->window_tab_32bit[window].map_to_field;
  620. val = map_to_field(base, base_bits) | other_bits;
  621. mv64x60_write(bh, base_reg, val);
  622. if (size_reg != 0) {
  623. val = bh->ci->translate_size(base, size, size_bits);
  624. val = map_to_field(val, size_bits);
  625. mv64x60_write(bh, size_reg, val);
  626. }
  627. (void)mv64x60_read(bh, base_reg); /* Flush FIFO */
  628. }
  629. }
  630. /*
  631. * mv64x60_get_64bit_window()
  632. *
  633. * Determine the base address and size of a 64-bit window on the bridge.
  634. */
  635. void __init
  636. mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window,
  637. u32 *base_hi, u32 *base_lo, u32 *size)
  638. {
  639. u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
  640. u32 (*get_from_field)(u32 val, u32 num_bits);
  641. base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
  642. if (base_lo_reg != 0) {
  643. size_reg = bh->ci->window_tab_64bit[window].size_reg;
  644. base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
  645. size_bits = bh->ci->window_tab_64bit[window].size_bits;
  646. get_from_field= bh->ci->window_tab_64bit[window].get_from_field;
  647. *base_hi = mv64x60_read(bh,
  648. bh->ci->window_tab_64bit[window].base_hi_reg);
  649. val = mv64x60_read(bh, base_lo_reg);
  650. *base_lo = get_from_field(val, base_lo_bits);
  651. if (size_reg != 0) {
  652. val = mv64x60_read(bh, size_reg);
  653. val = get_from_field(val, size_bits);
  654. *size = bh->ci->untranslate_size(*base_lo, val,
  655. size_bits);
  656. } else
  657. *size = 0;
  658. } else {
  659. *base_hi = 0;
  660. *base_lo = 0;
  661. *size = 0;
  662. }
  663. pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
  664. "size: 0x%x\n", window, *base_hi, *base_lo, *size);
  665. }
  666. /*
  667. * mv64x60_set_64bit_window()
  668. *
  669. * Set the base address and size of a 64-bit window on the bridge.
  670. */
  671. void __init
  672. mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
  673. u32 base_hi, u32 base_lo, u32 size, u32 other_bits)
  674. {
  675. u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
  676. u32 (*map_to_field)(u32 val, u32 num_bits);
  677. pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
  678. "size: 0x%x, other: 0x%x\n",
  679. window, base_hi, base_lo, size, other_bits);
  680. base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg;
  681. if (base_lo_reg != 0) {
  682. size_reg = bh->ci->window_tab_64bit[window].size_reg;
  683. base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits;
  684. size_bits = bh->ci->window_tab_64bit[window].size_bits;
  685. map_to_field = bh->ci->window_tab_64bit[window].map_to_field;
  686. mv64x60_write(bh, bh->ci->window_tab_64bit[window].base_hi_reg,
  687. base_hi);
  688. val = map_to_field(base_lo, base_lo_bits) | other_bits;
  689. mv64x60_write(bh, base_lo_reg, val);
  690. if (size_reg != 0) {
  691. val = bh->ci->translate_size(base_lo, size, size_bits);
  692. val = map_to_field(val, size_bits);
  693. mv64x60_write(bh, size_reg, val);
  694. }
  695. (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */
  696. }
  697. }
  698. /*
  699. * mv64x60_mask()
  700. *
  701. * Take the high-order 'num_bits' of 'val' & mask off low bits.
  702. */
  703. u32 __init
  704. mv64x60_mask(u32 val, u32 num_bits)
  705. {
  706. return val & (0xffffffff << (32 - num_bits));
  707. }
  708. /*
  709. * mv64x60_shift_left()
  710. *
  711. * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
  712. */
  713. u32 __init
  714. mv64x60_shift_left(u32 val, u32 num_bits)
  715. {
  716. return val << (32 - num_bits);
  717. }
  718. /*
  719. * mv64x60_shift_right()
  720. *
  721. * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB).
  722. */
  723. u32 __init
  724. mv64x60_shift_right(u32 val, u32 num_bits)
  725. {
  726. return val >> (32 - num_bits);
  727. }
  728. /*
  729. *****************************************************************************
  730. *
  731. * Chip Identification Routines
  732. *
  733. *****************************************************************************
  734. */
  735. /*
  736. * mv64x60_get_type()
  737. *
  738. * Determine the type of bridge chip we have.
  739. */
  740. int __init
  741. mv64x60_get_type(struct mv64x60_handle *bh)
  742. {
  743. struct pci_controller hose;
  744. u16 val;
  745. u8 save_exclude;
  746. memset(&hose, 0, sizeof(hose));
  747. setup_indirect_pci_nomap(&hose, bh->v_base + MV64x60_PCI0_CONFIG_ADDR,
  748. bh->v_base + MV64x60_PCI0_CONFIG_DATA);
  749. save_exclude = mv64x60_pci_exclude_bridge;
  750. mv64x60_pci_exclude_bridge = 0;
  751. /* Sanity check of bridge's Vendor ID */
  752. early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
  753. if (val != PCI_VENDOR_ID_MARVELL) {
  754. mv64x60_pci_exclude_bridge = save_exclude;
  755. return -1;
  756. }
  757. /* Get the revision of the chip */
  758. early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION,
  759. &val);
  760. bh->rev = (u32)(val & 0xff);
  761. /* Figure out the type of Marvell bridge it is */
  762. early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &val);
  763. mv64x60_pci_exclude_bridge = save_exclude;
  764. switch (val) {
  765. case PCI_DEVICE_ID_MARVELL_GT64260:
  766. switch (bh->rev) {
  767. case GT64260_REV_A:
  768. bh->type = MV64x60_TYPE_GT64260A;
  769. break;
  770. default:
  771. printk(KERN_WARNING "Unsupported GT64260 rev %04x\n",
  772. bh->rev);
  773. /* Assume its similar to a 'B' rev and fallthru */
  774. case GT64260_REV_B:
  775. bh->type = MV64x60_TYPE_GT64260B;
  776. break;
  777. }
  778. break;
  779. case PCI_DEVICE_ID_MARVELL_MV64360:
  780. /* Marvell won't tell me how to distinguish a 64361 & 64362 */
  781. bh->type = MV64x60_TYPE_MV64360;
  782. break;
  783. case PCI_DEVICE_ID_MARVELL_MV64460:
  784. bh->type = MV64x60_TYPE_MV64460;
  785. break;
  786. default:
  787. printk(KERN_ERR "Unknown Marvell bridge type %04x\n", val);
  788. return -1;
  789. }
  790. /* Hang onto bridge type & rev for PIC code */
  791. mv64x60_bridge_type = bh->type;
  792. mv64x60_bridge_rev = bh->rev;
  793. return 0;
  794. }
  795. /*
  796. * mv64x60_setup_for_chip()
  797. *
  798. * Set 'bh' to use the proper set of routine for the bridge chip that we have.
  799. */
  800. int __init
  801. mv64x60_setup_for_chip(struct mv64x60_handle *bh)
  802. {
  803. int rc = 0;
  804. /* Set up chip-specific info based on the chip/bridge type */
  805. switch(bh->type) {
  806. case MV64x60_TYPE_GT64260A:
  807. bh->ci = &gt64260a_ci;
  808. break;
  809. case MV64x60_TYPE_GT64260B:
  810. bh->ci = &gt64260b_ci;
  811. break;
  812. case MV64x60_TYPE_MV64360:
  813. bh->ci = &mv64360_ci;
  814. break;
  815. case MV64x60_TYPE_MV64460:
  816. bh->ci = &mv64460_ci;
  817. break;
  818. case MV64x60_TYPE_INVALID:
  819. default:
  820. if (ppc_md.progress)
  821. ppc_md.progress("mv64x60: Unsupported bridge", 0x0);
  822. printk(KERN_ERR "mv64x60: Unsupported bridge\n");
  823. rc = -1;
  824. }
  825. return rc;
  826. }
  827. /*
  828. * mv64x60_get_bridge_vbase()
  829. *
  830. * Return the virtual address of the bridge's registers.
  831. */
  832. void __iomem *
  833. mv64x60_get_bridge_vbase(void)
  834. {
  835. return mv64x60_bridge_vbase;
  836. }
  837. /*
  838. * mv64x60_get_bridge_type()
  839. *
  840. * Return the type of bridge on the platform.
  841. */
  842. u32
  843. mv64x60_get_bridge_type(void)
  844. {
  845. return mv64x60_bridge_type;
  846. }
  847. /*
  848. * mv64x60_get_bridge_rev()
  849. *
  850. * Return the revision of the bridge on the platform.
  851. */
  852. u32
  853. mv64x60_get_bridge_rev(void)
  854. {
  855. return mv64x60_bridge_rev;
  856. }
  857. /*
  858. *****************************************************************************
  859. *
  860. * System Memory Window Related Routines
  861. *
  862. *****************************************************************************
  863. */
  864. /*
  865. * mv64x60_get_mem_size()
  866. *
  867. * Calculate the amount of memory that the memory controller is set up for.
  868. * This should only be used by board-specific code if there is no other
  869. * way to determine the amount of memory in the system.
  870. */
  871. u32 __init
  872. mv64x60_get_mem_size(u32 bridge_base, u32 chip_type)
  873. {
  874. struct mv64x60_handle bh;
  875. u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
  876. u32 rc = 0;
  877. memset(&bh, 0, sizeof(bh));
  878. bh.type = chip_type;
  879. bh.v_base = (void *)bridge_base;
  880. if (!mv64x60_setup_for_chip(&bh)) {
  881. mv64x60_get_mem_windows(&bh, mem_windows);
  882. rc = mv64x60_calc_mem_size(&bh, mem_windows);
  883. }
  884. return rc;
  885. }
  886. /*
  887. * mv64x60_get_mem_windows()
  888. *
  889. * Get the values in the memory controller & return in the 'mem_windows' array.
  890. */
  891. void __init
  892. mv64x60_get_mem_windows(struct mv64x60_handle *bh,
  893. u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
  894. {
  895. u32 i, win;
  896. for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
  897. if (bh->ci->is_enabled_32bit(bh, win))
  898. mv64x60_get_32bit_window(bh, win,
  899. &mem_windows[i][0], &mem_windows[i][1]);
  900. else {
  901. mem_windows[i][0] = 0;
  902. mem_windows[i][1] = 0;
  903. }
  904. }
  905. /*
  906. * mv64x60_calc_mem_size()
  907. *
  908. * Using the memory controller register values in 'mem_windows', determine
  909. * how much memory it is set up for.
  910. */
  911. u32 __init
  912. mv64x60_calc_mem_size(struct mv64x60_handle *bh,
  913. u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
  914. {
  915. u32 i, total = 0;
  916. for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
  917. total += mem_windows[i][1];
  918. return total;
  919. }
  920. /*
  921. *****************************************************************************
  922. *
  923. * CPU->System MEM, PCI Config Routines
  924. *
  925. *****************************************************************************
  926. */
  927. /*
  928. * mv64x60_config_cpu2mem_windows()
  929. *
  930. * Configure CPU->Memory windows on the bridge.
  931. */
  932. static u32 prot_tab[] __initdata = {
  933. MV64x60_CPU_PROT_0_WIN, MV64x60_CPU_PROT_1_WIN,
  934. MV64x60_CPU_PROT_2_WIN, MV64x60_CPU_PROT_3_WIN
  935. };
  936. static u32 cpu_snoop_tab[] __initdata = {
  937. MV64x60_CPU_SNOOP_0_WIN, MV64x60_CPU_SNOOP_1_WIN,
  938. MV64x60_CPU_SNOOP_2_WIN, MV64x60_CPU_SNOOP_3_WIN
  939. };
  940. void __init
  941. mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh,
  942. struct mv64x60_setup_info *si,
  943. u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
  944. {
  945. u32 i, win;
  946. /* Set CPU protection & snoop windows */
  947. for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
  948. if (bh->ci->is_enabled_32bit(bh, win)) {
  949. mv64x60_set_32bit_window(bh, prot_tab[i],
  950. mem_windows[i][0], mem_windows[i][1],
  951. si->cpu_prot_options[i]);
  952. bh->ci->enable_window_32bit(bh, prot_tab[i]);
  953. if (bh->ci->window_tab_32bit[cpu_snoop_tab[i]].
  954. base_reg != 0) {
  955. mv64x60_set_32bit_window(bh, cpu_snoop_tab[i],
  956. mem_windows[i][0], mem_windows[i][1],
  957. si->cpu_snoop_options[i]);
  958. bh->ci->enable_window_32bit(bh,
  959. cpu_snoop_tab[i]);
  960. }
  961. }
  962. }
  963. /*
  964. * mv64x60_config_cpu2pci_windows()
  965. *
  966. * Configure the CPU->PCI windows for one of the PCI buses.
  967. */
  968. static u32 win_tab[2][4] __initdata = {
  969. { MV64x60_CPU2PCI0_IO_WIN, MV64x60_CPU2PCI0_MEM_0_WIN,
  970. MV64x60_CPU2PCI0_MEM_1_WIN, MV64x60_CPU2PCI0_MEM_2_WIN },
  971. { MV64x60_CPU2PCI1_IO_WIN, MV64x60_CPU2PCI1_MEM_0_WIN,
  972. MV64x60_CPU2PCI1_MEM_1_WIN, MV64x60_CPU2PCI1_MEM_2_WIN },
  973. };
  974. static u32 remap_tab[2][4] __initdata = {
  975. { MV64x60_CPU2PCI0_IO_REMAP_WIN, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN,
  976. MV64x60_CPU2PCI0_MEM_1_REMAP_WIN, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN },
  977. { MV64x60_CPU2PCI1_IO_REMAP_WIN, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN,
  978. MV64x60_CPU2PCI1_MEM_1_REMAP_WIN, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN }
  979. };
  980. void __init
  981. mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh,
  982. struct mv64x60_pci_info *pi, u32 bus)
  983. {
  984. int i;
  985. if (pi->pci_io.size > 0) {
  986. mv64x60_set_32bit_window(bh, win_tab[bus][0],
  987. pi->pci_io.cpu_base, pi->pci_io.size, pi->pci_io.swap);
  988. mv64x60_set_32bit_window(bh, remap_tab[bus][0],
  989. pi->pci_io.pci_base_lo, 0, 0);
  990. bh->ci->enable_window_32bit(bh, win_tab[bus][0]);
  991. } else /* Actually, the window should already be disabled */
  992. bh->ci->disable_window_32bit(bh, win_tab[bus][0]);
  993. for (i=0; i<3; i++)
  994. if (pi->pci_mem[i].size > 0) {
  995. mv64x60_set_32bit_window(bh, win_tab[bus][i+1],
  996. pi->pci_mem[i].cpu_base, pi->pci_mem[i].size,
  997. pi->pci_mem[i].swap);
  998. mv64x60_set_64bit_window(bh, remap_tab[bus][i+1],
  999. pi->pci_mem[i].pci_base_hi,
  1000. pi->pci_mem[i].pci_base_lo, 0, 0);
  1001. bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]);
  1002. } else /* Actually, the window should already be disabled */
  1003. bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]);
  1004. }
  1005. /*
  1006. *****************************************************************************
  1007. *
  1008. * PCI->System MEM Config Routines
  1009. *
  1010. *****************************************************************************
  1011. */
  1012. /*
  1013. * mv64x60_config_pci2mem_windows()
  1014. *
  1015. * Configure the PCI->Memory windows on the bridge.
  1016. */
  1017. static u32 pci_acc_tab[2][4] __initdata = {
  1018. { MV64x60_PCI02MEM_ACC_CNTL_0_WIN, MV64x60_PCI02MEM_ACC_CNTL_1_WIN,
  1019. MV64x60_PCI02MEM_ACC_CNTL_2_WIN, MV64x60_PCI02MEM_ACC_CNTL_3_WIN },
  1020. { MV64x60_PCI12MEM_ACC_CNTL_0_WIN, MV64x60_PCI12MEM_ACC_CNTL_1_WIN,
  1021. MV64x60_PCI12MEM_ACC_CNTL_2_WIN, MV64x60_PCI12MEM_ACC_CNTL_3_WIN }
  1022. };
  1023. static u32 pci_snoop_tab[2][4] __initdata = {
  1024. { MV64x60_PCI02MEM_SNOOP_0_WIN, MV64x60_PCI02MEM_SNOOP_1_WIN,
  1025. MV64x60_PCI02MEM_SNOOP_2_WIN, MV64x60_PCI02MEM_SNOOP_3_WIN },
  1026. { MV64x60_PCI12MEM_SNOOP_0_WIN, MV64x60_PCI12MEM_SNOOP_1_WIN,
  1027. MV64x60_PCI12MEM_SNOOP_2_WIN, MV64x60_PCI12MEM_SNOOP_3_WIN }
  1028. };
  1029. static u32 pci_size_tab[2][4] __initdata = {
  1030. { MV64x60_PCI0_MEM_0_SIZE, MV64x60_PCI0_MEM_1_SIZE,
  1031. MV64x60_PCI0_MEM_2_SIZE, MV64x60_PCI0_MEM_3_SIZE },
  1032. { MV64x60_PCI1_MEM_0_SIZE, MV64x60_PCI1_MEM_1_SIZE,
  1033. MV64x60_PCI1_MEM_2_SIZE, MV64x60_PCI1_MEM_3_SIZE }
  1034. };
  1035. void __init
  1036. mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh,
  1037. struct pci_controller *hose, struct mv64x60_pci_info *pi,
  1038. u32 bus, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
  1039. {
  1040. u32 i, win;
  1041. /*
  1042. * Set the access control, snoop, BAR size, and window base addresses.
  1043. * PCI->MEM windows base addresses will match exactly what the
  1044. * CPU->MEM windows are.
  1045. */
  1046. for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
  1047. if (bh->ci->is_enabled_32bit(bh, win)) {
  1048. mv64x60_set_64bit_window(bh,
  1049. pci_acc_tab[bus][i], 0,
  1050. mem_windows[i][0], mem_windows[i][1],
  1051. pi->acc_cntl_options[i]);
  1052. bh->ci->enable_window_64bit(bh, pci_acc_tab[bus][i]);
  1053. if (bh->ci->window_tab_64bit[
  1054. pci_snoop_tab[bus][i]].base_lo_reg != 0) {
  1055. mv64x60_set_64bit_window(bh,
  1056. pci_snoop_tab[bus][i], 0,
  1057. mem_windows[i][0], mem_windows[i][1],
  1058. pi->snoop_options[i]);
  1059. bh->ci->enable_window_64bit(bh,
  1060. pci_snoop_tab[bus][i]);
  1061. }
  1062. bh->ci->set_pci2mem_window(hose, bus, i,
  1063. mem_windows[i][0]);
  1064. mv64x60_write(bh, pci_size_tab[bus][i],
  1065. mv64x60_mask(mem_windows[i][1] - 1, 20));
  1066. /* Enable the window */
  1067. mv64x60_clr_bits(bh, ((bus == 0) ?
  1068. MV64x60_PCI0_BAR_ENABLE :
  1069. MV64x60_PCI1_BAR_ENABLE), (1 << i));
  1070. }
  1071. }
  1072. /*
  1073. *****************************************************************************
  1074. *
  1075. * Hose & Resource Alloc/Init Routines
  1076. *
  1077. *****************************************************************************
  1078. */
  1079. /*
  1080. * mv64x60_alloc_hoses()
  1081. *
  1082. * Allocate the PCI hose structures for the bridge's PCI buses.
  1083. */
  1084. void __init
  1085. mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data,
  1086. struct pci_controller **hose)
  1087. {
  1088. *hose = pcibios_alloc_controller();
  1089. setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr,
  1090. bh->v_base + cfg_data);
  1091. }
  1092. /*
  1093. * mv64x60_config_resources()
  1094. *
  1095. * Calculate the offsets, etc. for the hose structures to reflect all of
  1096. * the address remapping that happens as you go from CPU->PCI and PCI->MEM.
  1097. */
  1098. void __init
  1099. mv64x60_config_resources(struct pci_controller *hose,
  1100. struct mv64x60_pci_info *pi, u32 io_base)
  1101. {
  1102. int i;
  1103. /* 2 hoses; 4 resources/hose; string <= 64 bytes */
  1104. static char s[2][4][64];
  1105. if (pi->pci_io.size != 0) {
  1106. sprintf(s[hose->index][0], "PCI hose %d I/O Space",
  1107. hose->index);
  1108. pci_init_resource(&hose->io_resource, io_base - isa_io_base,
  1109. io_base - isa_io_base + pi->pci_io.size - 1,
  1110. IORESOURCE_IO, s[hose->index][0]);
  1111. hose->io_space.start = pi->pci_io.pci_base_lo;
  1112. hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1;
  1113. hose->io_base_phys = pi->pci_io.cpu_base;
  1114. hose->io_base_virt = (void *)isa_io_base;
  1115. }
  1116. for (i=0; i<3; i++)
  1117. if (pi->pci_mem[i].size != 0) {
  1118. sprintf(s[hose->index][i+1], "PCI hose %d MEM Space %d",
  1119. hose->index, i);
  1120. pci_init_resource(&hose->mem_resources[i],
  1121. pi->pci_mem[i].cpu_base,
  1122. pi->pci_mem[i].cpu_base + pi->pci_mem[i].size-1,
  1123. IORESOURCE_MEM, s[hose->index][i+1]);
  1124. }
  1125. hose->mem_space.end = pi->pci_mem[0].pci_base_lo +
  1126. pi->pci_mem[0].size - 1;
  1127. hose->pci_mem_offset = pi->pci_mem[0].cpu_base -
  1128. pi->pci_mem[0].pci_base_lo;
  1129. }
  1130. /*
  1131. * mv64x60_config_pci_params()
  1132. *
  1133. * Configure a hose's PCI config space parameters.
  1134. */
  1135. void __init
  1136. mv64x60_config_pci_params(struct pci_controller *hose,
  1137. struct mv64x60_pci_info *pi)
  1138. {
  1139. u32 devfn;
  1140. u16 u16_val;
  1141. u8 save_exclude;
  1142. devfn = PCI_DEVFN(0,0);
  1143. save_exclude = mv64x60_pci_exclude_bridge;
  1144. mv64x60_pci_exclude_bridge = 0;
  1145. /* Set class code to indicate host bridge */
  1146. u16_val = PCI_CLASS_BRIDGE_HOST; /* 0x0600 (host bridge) */
  1147. early_write_config_word(hose, 0, devfn, PCI_CLASS_DEVICE, u16_val);
  1148. /* Enable bridge to be PCI master & respond to PCI MEM cycles */
  1149. early_read_config_word(hose, 0, devfn, PCI_COMMAND, &u16_val);
  1150. u16_val &= ~(PCI_COMMAND_IO | PCI_COMMAND_INVALIDATE |
  1151. PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
  1152. u16_val |= pi->pci_cmd_bits | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  1153. early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val);
  1154. /* Set latency timer, cache line size, clear BIST */
  1155. u16_val = (pi->latency_timer << 8) | (L1_CACHE_BYTES >> 2);
  1156. early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val);
  1157. mv64x60_pci_exclude_bridge = save_exclude;
  1158. }
  1159. /*
  1160. *****************************************************************************
  1161. *
  1162. * PCI Related Routine
  1163. *
  1164. *****************************************************************************
  1165. */
  1166. /*
  1167. * mv64x60_set_bus()
  1168. *
  1169. * Set the bus number for the hose directly under the bridge.
  1170. */
  1171. void __init
  1172. mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus)
  1173. {
  1174. struct pci_controller *hose;
  1175. u32 pci_mode, p2p_cfg, pci_cfg_offset, val;
  1176. u8 save_exclude;
  1177. if (bus == 0) {
  1178. pci_mode = bh->pci_mode_a;
  1179. p2p_cfg = MV64x60_PCI0_P2P_CONFIG;
  1180. pci_cfg_offset = 0x64;
  1181. hose = bh->hose_a;
  1182. } else {
  1183. pci_mode = bh->pci_mode_b;
  1184. p2p_cfg = MV64x60_PCI1_P2P_CONFIG;
  1185. pci_cfg_offset = 0xe4;
  1186. hose = bh->hose_b;
  1187. }
  1188. child_bus &= 0xff;
  1189. val = mv64x60_read(bh, p2p_cfg);
  1190. if (pci_mode == MV64x60_PCIMODE_CONVENTIONAL) {
  1191. val &= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */
  1192. val |= (child_bus << 16) | 0xff;
  1193. mv64x60_write(bh, p2p_cfg, val);
  1194. (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */
  1195. } else { /* PCI-X */
  1196. /*
  1197. * Need to use the current bus/dev number (that's in the
  1198. * P2P CONFIG reg) to access the bridge's pci config space.
  1199. */
  1200. save_exclude = mv64x60_pci_exclude_bridge;
  1201. mv64x60_pci_exclude_bridge = 0;
  1202. early_write_config_dword(hose, (val & 0x00ff0000) >> 16,
  1203. PCI_DEVFN(((val & 0x1f000000) >> 24), 0),
  1204. pci_cfg_offset, child_bus << 8);
  1205. mv64x60_pci_exclude_bridge = save_exclude;
  1206. }
  1207. }
  1208. /*
  1209. * mv64x60_pci_exclude_device()
  1210. *
  1211. * This routine is used to make the bridge not appear when the
  1212. * PCI subsystem is accessing PCI devices (in PCI config space).
  1213. */
  1214. int
  1215. mv64x60_pci_exclude_device(u8 bus, u8 devfn)
  1216. {
  1217. struct pci_controller *hose;
  1218. hose = pci_bus_to_hose(bus);
  1219. /* Skip slot 0 on both hoses */
  1220. if ((mv64x60_pci_exclude_bridge == 1) && (PCI_SLOT(devfn) == 0) &&
  1221. (hose->first_busno == bus))
  1222. return PCIBIOS_DEVICE_NOT_FOUND;
  1223. else
  1224. return PCIBIOS_SUCCESSFUL;
  1225. } /* mv64x60_pci_exclude_device() */
  1226. /*
  1227. *****************************************************************************
  1228. *
  1229. * Platform Device Routines
  1230. *
  1231. *****************************************************************************
  1232. */
  1233. /*
  1234. * mv64x60_pd_fixup()
  1235. *
  1236. * Need to add the base addr of where the bridge's regs are mapped in the
  1237. * physical addr space so drivers can ioremap() them.
  1238. */
  1239. void __init
  1240. mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[],
  1241. u32 entries)
  1242. {
  1243. struct resource *r;
  1244. u32 i, j;
  1245. for (i=0; i<entries; i++) {
  1246. j = 0;
  1247. while ((r = platform_get_resource(pd_devs[i],IORESOURCE_MEM,j))
  1248. != NULL) {
  1249. r->start += bh->p_base;
  1250. r->end += bh->p_base;
  1251. j++;
  1252. }
  1253. }
  1254. }
  1255. /*
  1256. * mv64x60_add_pds()
  1257. *
  1258. * Add the mv64x60 platform devices to the list of platform devices.
  1259. */
  1260. static int __init
  1261. mv64x60_add_pds(void)
  1262. {
  1263. return platform_add_devices(mv64x60_pd_devs,
  1264. ARRAY_SIZE(mv64x60_pd_devs));
  1265. }
  1266. arch_initcall(mv64x60_add_pds);
  1267. /*
  1268. *****************************************************************************
  1269. *
  1270. * GT64260-Specific Routines
  1271. *
  1272. *****************************************************************************
  1273. */
  1274. /*
  1275. * gt64260_translate_size()
  1276. *
  1277. * On the GT64260, the size register is really the "top" address of the window.
  1278. */
  1279. static u32 __init
  1280. gt64260_translate_size(u32 base, u32 size, u32 num_bits)
  1281. {
  1282. return base + mv64x60_mask(size - 1, num_bits);
  1283. }
  1284. /*
  1285. * gt64260_untranslate_size()
  1286. *
  1287. * Translate the top address of a window into a window size.
  1288. */
  1289. static u32 __init
  1290. gt64260_untranslate_size(u32 base, u32 size, u32 num_bits)
  1291. {
  1292. if (size >= base)
  1293. size = size - base + (1 << (32 - num_bits));
  1294. else
  1295. size = 0;
  1296. return size;
  1297. }
  1298. /*
  1299. * gt64260_set_pci2mem_window()
  1300. *
  1301. * The PCI->MEM window registers are actually in PCI config space so need
  1302. * to set them by setting the correct config space BARs.
  1303. */
  1304. static u32 gt64260_reg_addrs[2][4] __initdata = {
  1305. { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c }
  1306. };
  1307. static void __init
  1308. gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
  1309. u32 base)
  1310. {
  1311. u8 save_exclude;
  1312. pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
  1313. hose->index, base);
  1314. save_exclude = mv64x60_pci_exclude_bridge;
  1315. mv64x60_pci_exclude_bridge = 0;
  1316. early_write_config_dword(hose, 0, PCI_DEVFN(0, 0),
  1317. gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8);
  1318. mv64x60_pci_exclude_bridge = save_exclude;
  1319. }
  1320. /*
  1321. * gt64260_set_pci2regs_window()
  1322. *
  1323. * Set where the bridge's registers appear in PCI MEM space.
  1324. */
  1325. static u32 gt64260_offset[2] __initdata = {0x20, 0xa0};
  1326. static void __init
  1327. gt64260_set_pci2regs_window(struct mv64x60_handle *bh,
  1328. struct pci_controller *hose, u32 bus, u32 base)
  1329. {
  1330. u8 save_exclude;
  1331. pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
  1332. base);
  1333. save_exclude = mv64x60_pci_exclude_bridge;
  1334. mv64x60_pci_exclude_bridge = 0;
  1335. early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus],
  1336. (base << 16));
  1337. mv64x60_pci_exclude_bridge = save_exclude;
  1338. }
  1339. /*
  1340. * gt64260_is_enabled_32bit()
  1341. *
  1342. * On a GT64260, a window is enabled iff its top address is >= to its base
  1343. * address.
  1344. */
  1345. static u32 __init
  1346. gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
  1347. {
  1348. u32 rc = 0;
  1349. if ((gt64260_32bit_windows[window].base_reg != 0) &&
  1350. (gt64260_32bit_windows[window].size_reg != 0) &&
  1351. ((mv64x60_read(bh, gt64260_32bit_windows[window].size_reg) &
  1352. ((1 << gt64260_32bit_windows[window].size_bits) - 1)) >=
  1353. (mv64x60_read(bh, gt64260_32bit_windows[window].base_reg) &
  1354. ((1 << gt64260_32bit_windows[window].base_bits) - 1))))
  1355. rc = 1;
  1356. return rc;
  1357. }
  1358. /*
  1359. * gt64260_enable_window_32bit()
  1360. *
  1361. * On the GT64260, a window is enabled iff the top address is >= to the base
  1362. * address of the window. Since the window has already been configured by
  1363. * the time this routine is called, we have nothing to do here.
  1364. */
  1365. static void __init
  1366. gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
  1367. {
  1368. pr_debug("enable 32bit window: %d\n", window);
  1369. }
  1370. /*
  1371. * gt64260_disable_window_32bit()
  1372. *
  1373. * On a GT64260, you disable a window by setting its top address to be less
  1374. * than its base address.
  1375. */
  1376. static void __init
  1377. gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
  1378. {
  1379. pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
  1380. window, gt64260_32bit_windows[window].base_reg,
  1381. gt64260_32bit_windows[window].size_reg);
  1382. if ((gt64260_32bit_windows[window].base_reg != 0) &&
  1383. (gt64260_32bit_windows[window].size_reg != 0)) {
  1384. /* To disable, make bottom reg higher than top reg */
  1385. mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff);
  1386. mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0);
  1387. }
  1388. }
  1389. /*
  1390. * gt64260_enable_window_64bit()
  1391. *
  1392. * On the GT64260, a window is enabled iff the top address is >= to the base
  1393. * address of the window. Since the window has already been configured by
  1394. * the time this routine is called, we have nothing to do here.
  1395. */
  1396. static void __init
  1397. gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
  1398. {
  1399. pr_debug("enable 64bit window: %d\n", window);
  1400. }
  1401. /*
  1402. * gt64260_disable_window_64bit()
  1403. *
  1404. * On a GT64260, you disable a window by setting its top address to be less
  1405. * than its base address.
  1406. */
  1407. static void __init
  1408. gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
  1409. {
  1410. pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
  1411. window, gt64260_64bit_windows[window].base_lo_reg,
  1412. gt64260_64bit_windows[window].size_reg);
  1413. if ((gt64260_64bit_windows[window].base_lo_reg != 0) &&
  1414. (gt64260_64bit_windows[window].size_reg != 0)) {
  1415. /* To disable, make bottom reg higher than top reg */
  1416. mv64x60_write(bh, gt64260_64bit_windows[window].base_lo_reg,
  1417. 0xfff);
  1418. mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0);
  1419. mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0);
  1420. }
  1421. }
  1422. /*
  1423. * gt64260_disable_all_windows()
  1424. *
  1425. * The GT64260 has several windows that aren't represented in the table of
  1426. * windows at the top of this file. This routine turns all of them off
  1427. * except for the memory controller windows, of course.
  1428. */
  1429. static void __init
  1430. gt64260_disable_all_windows(struct mv64x60_handle *bh,
  1431. struct mv64x60_setup_info *si)
  1432. {
  1433. u32 i, preserve;
  1434. /* Disable 32bit windows (don't disable cpu->mem windows) */
  1435. for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
  1436. if (i < 32)
  1437. preserve = si->window_preserve_mask_32_lo & (1 << i);
  1438. else
  1439. preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
  1440. if (!preserve)
  1441. gt64260_disable_window_32bit(bh, i);
  1442. }
  1443. /* Disable 64bit windows */
  1444. for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
  1445. if (!(si->window_preserve_mask_64 & (1<<i)))
  1446. gt64260_disable_window_64bit(bh, i);
  1447. /* Turn off cpu protection windows not in gt64260_32bit_windows[] */
  1448. mv64x60_write(bh, GT64260_CPU_PROT_BASE_4, 0xfff);
  1449. mv64x60_write(bh, GT64260_CPU_PROT_SIZE_4, 0);
  1450. mv64x60_write(bh, GT64260_CPU_PROT_BASE_5, 0xfff);
  1451. mv64x60_write(bh, GT64260_CPU_PROT_SIZE_5, 0);
  1452. mv64x60_write(bh, GT64260_CPU_PROT_BASE_6, 0xfff);
  1453. mv64x60_write(bh, GT64260_CPU_PROT_SIZE_6, 0);
  1454. mv64x60_write(bh, GT64260_CPU_PROT_BASE_7, 0xfff);
  1455. mv64x60_write(bh, GT64260_CPU_PROT_SIZE_7, 0);
  1456. /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */
  1457. mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0xfff);
  1458. mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_HI, 0);
  1459. mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_SIZE, 0);
  1460. mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0xfff);
  1461. mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_HI, 0);
  1462. mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_SIZE, 0);
  1463. mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_LO, 0xfff);
  1464. mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_HI, 0);
  1465. mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_SIZE, 0);
  1466. mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_LO, 0xfff);
  1467. mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_HI, 0);
  1468. mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_SIZE, 0);
  1469. mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0xfff);
  1470. mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_HI, 0);
  1471. mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_SIZE, 0);
  1472. mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0xfff);
  1473. mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_HI, 0);
  1474. mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_SIZE, 0);
  1475. mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_LO, 0xfff);
  1476. mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_HI, 0);
  1477. mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_SIZE, 0);
  1478. mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_LO, 0xfff);
  1479. mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_HI, 0);
  1480. mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_SIZE, 0);
  1481. /* Disable all PCI-><whatever> windows */
  1482. mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x07fffdff);
  1483. mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x07fffdff);
  1484. /*
  1485. * Some firmwares enable a bunch of intr sources
  1486. * for the PCI INT output pins.
  1487. */
  1488. mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_LO, 0);
  1489. mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_HI, 0);
  1490. mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_LO, 0);
  1491. mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_HI, 0);
  1492. mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_LO, 0);
  1493. mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_HI, 0);
  1494. mv64x60_write(bh, GT64260_IC_CPU_INT_0_MASK, 0);
  1495. mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0);
  1496. mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0);
  1497. mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0);
  1498. }
  1499. /*
  1500. * gt64260a_chip_specific_init()
  1501. *
  1502. * Implement errata workarounds for the GT64260A.
  1503. */
  1504. static void __init
  1505. gt64260a_chip_specific_init(struct mv64x60_handle *bh,
  1506. struct mv64x60_setup_info *si)
  1507. {
  1508. #ifdef CONFIG_SERIAL_MPSC
  1509. struct resource *r;
  1510. #endif
  1511. #if !defined(CONFIG_NOT_COHERENT_CACHE)
  1512. u32 val;
  1513. u8 save_exclude;
  1514. #endif
  1515. if (si->pci_0.enable_bus)
  1516. mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
  1517. ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
  1518. if (si->pci_1.enable_bus)
  1519. mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
  1520. ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
  1521. /*
  1522. * Dave Wilhardt found that bit 4 in the PCI Command registers must
  1523. * be set if you are using cache coherency.
  1524. */
  1525. #if !defined(CONFIG_NOT_COHERENT_CACHE)
  1526. /* Res #MEM-4 -- cpu read buffer to buffer 1 */
  1527. if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
  1528. mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
  1529. save_exclude = mv64x60_pci_exclude_bridge;
  1530. mv64x60_pci_exclude_bridge = 0;
  1531. if (si->pci_0.enable_bus) {
  1532. early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
  1533. PCI_COMMAND, &val);
  1534. val |= PCI_COMMAND_INVALIDATE;
  1535. early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
  1536. PCI_COMMAND, val);
  1537. }
  1538. if (si->pci_1.enable_bus) {
  1539. early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
  1540. PCI_COMMAND, &val);
  1541. val |= PCI_COMMAND_INVALIDATE;
  1542. early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
  1543. PCI_COMMAND, val);
  1544. }
  1545. mv64x60_pci_exclude_bridge = save_exclude;
  1546. #endif
  1547. /* Disable buffer/descriptor snooping */
  1548. mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
  1549. mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
  1550. #ifdef CONFIG_SERIAL_MPSC
  1551. mv64x60_mpsc0_pdata.mirror_regs = 1;
  1552. mv64x60_mpsc0_pdata.cache_mgmt = 1;
  1553. mv64x60_mpsc1_pdata.mirror_regs = 1;
  1554. mv64x60_mpsc1_pdata.cache_mgmt = 1;
  1555. if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
  1556. != NULL) {
  1557. r->start = MV64x60_IRQ_SDMA_0;
  1558. r->end = MV64x60_IRQ_SDMA_0;
  1559. }
  1560. #endif
  1561. }
  1562. /*
  1563. * gt64260b_chip_specific_init()
  1564. *
  1565. * Implement errata workarounds for the GT64260B.
  1566. */
  1567. static void __init
  1568. gt64260b_chip_specific_init(struct mv64x60_handle *bh,
  1569. struct mv64x60_setup_info *si)
  1570. {
  1571. #ifdef CONFIG_SERIAL_MPSC
  1572. struct resource *r;
  1573. #endif
  1574. #if !defined(CONFIG_NOT_COHERENT_CACHE)
  1575. u32 val;
  1576. u8 save_exclude;
  1577. #endif
  1578. if (si->pci_0.enable_bus)
  1579. mv64x60_set_bits(bh, MV64x60_PCI0_CMD,
  1580. ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
  1581. if (si->pci_1.enable_bus)
  1582. mv64x60_set_bits(bh, MV64x60_PCI1_CMD,
  1583. ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
  1584. /*
  1585. * Dave Wilhardt found that bit 4 in the PCI Command registers must
  1586. * be set if you are using cache coherency.
  1587. */
  1588. #if !defined(CONFIG_NOT_COHERENT_CACHE)
  1589. mv64x60_set_bits(bh, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH, 0xf);
  1590. /* Res #MEM-4 -- cpu read buffer to buffer 1 */
  1591. if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40)
  1592. mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26));
  1593. save_exclude = mv64x60_pci_exclude_bridge;
  1594. mv64x60_pci_exclude_bridge = 0;
  1595. if (si->pci_0.enable_bus) {
  1596. early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
  1597. PCI_COMMAND, &val);
  1598. val |= PCI_COMMAND_INVALIDATE;
  1599. early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0),
  1600. PCI_COMMAND, val);
  1601. }
  1602. if (si->pci_1.enable_bus) {
  1603. early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
  1604. PCI_COMMAND, &val);
  1605. val |= PCI_COMMAND_INVALIDATE;
  1606. early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0),
  1607. PCI_COMMAND, val);
  1608. }
  1609. mv64x60_pci_exclude_bridge = save_exclude;
  1610. #endif
  1611. /* Disable buffer/descriptor snooping */
  1612. mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
  1613. mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
  1614. #ifdef CONFIG_SERIAL_MPSC
  1615. /*
  1616. * The 64260B is not supposed to have the bug where the MPSC & ENET
  1617. * can't access cache coherent regions. However, testing has shown
  1618. * that the MPSC, at least, still has this bug.
  1619. */
  1620. mv64x60_mpsc0_pdata.cache_mgmt = 1;
  1621. mv64x60_mpsc1_pdata.cache_mgmt = 1;
  1622. if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
  1623. != NULL) {
  1624. r->start = MV64x60_IRQ_SDMA_0;
  1625. r->end = MV64x60_IRQ_SDMA_0;
  1626. }
  1627. #endif
  1628. }
  1629. /*
  1630. *****************************************************************************
  1631. *
  1632. * MV64360-Specific Routines
  1633. *
  1634. *****************************************************************************
  1635. */
  1636. /*
  1637. * mv64360_translate_size()
  1638. *
  1639. * On the MV64360, the size register is set similar to the size you get
  1640. * from a pci config space BAR register. That is, programmed from LSB to MSB
  1641. * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the
  1642. * assumption that the size is a power of 2.
  1643. */
  1644. static u32 __init
  1645. mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits)
  1646. {
  1647. return mv64x60_mask(size - 1, num_bits);
  1648. }
  1649. /*
  1650. * mv64360_untranslate_size()
  1651. *
  1652. * Translate the size register value of a window into a window size.
  1653. */
  1654. static u32 __init
  1655. mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits)
  1656. {
  1657. if (size > 0) {
  1658. size >>= (32 - num_bits);
  1659. size++;
  1660. size <<= (32 - num_bits);
  1661. }
  1662. return size;
  1663. }
  1664. /*
  1665. * mv64360_set_pci2mem_window()
  1666. *
  1667. * The PCI->MEM window registers are actually in PCI config space so need
  1668. * to set them by setting the correct config space BARs.
  1669. */
  1670. struct {
  1671. u32 fcn;
  1672. u32 base_hi_bar;
  1673. u32 base_lo_bar;
  1674. } static mv64360_reg_addrs[2][4] __initdata = {
  1675. {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 },
  1676. { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }},
  1677. {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 },
  1678. { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }}
  1679. };
  1680. static void __init
  1681. mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window,
  1682. u32 base)
  1683. {
  1684. u8 save_exclude;
  1685. pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window,
  1686. hose->index, base);
  1687. save_exclude = mv64x60_pci_exclude_bridge;
  1688. mv64x60_pci_exclude_bridge = 0;
  1689. early_write_config_dword(hose, 0,
  1690. PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
  1691. mv64360_reg_addrs[bus][window].base_hi_bar, 0);
  1692. early_write_config_dword(hose, 0,
  1693. PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn),
  1694. mv64360_reg_addrs[bus][window].base_lo_bar,
  1695. mv64x60_mask(base,20) | 0xc);
  1696. mv64x60_pci_exclude_bridge = save_exclude;
  1697. }
  1698. /*
  1699. * mv64360_set_pci2regs_window()
  1700. *
  1701. * Set where the bridge's registers appear in PCI MEM space.
  1702. */
  1703. static u32 mv64360_offset[2][2] __initdata = {{0x20, 0x24}, {0xa0, 0xa4}};
  1704. static void __init
  1705. mv64360_set_pci2regs_window(struct mv64x60_handle *bh,
  1706. struct pci_controller *hose, u32 bus, u32 base)
  1707. {
  1708. u8 save_exclude;
  1709. pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index,
  1710. base);
  1711. save_exclude = mv64x60_pci_exclude_bridge;
  1712. mv64x60_pci_exclude_bridge = 0;
  1713. early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
  1714. mv64360_offset[bus][0], (base << 16));
  1715. early_write_config_dword(hose, 0, PCI_DEVFN(0,0),
  1716. mv64360_offset[bus][1], 0);
  1717. mv64x60_pci_exclude_bridge = save_exclude;
  1718. }
  1719. /*
  1720. * mv64360_is_enabled_32bit()
  1721. *
  1722. * On a MV64360, a window is enabled by either clearing a bit in the
  1723. * CPU BAR Enable reg or setting a bit in the window's base reg.
  1724. * Note that this doesn't work for windows on the PCI slave side but we don't
  1725. * check those so its okay.
  1726. */
  1727. static u32 __init
  1728. mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window)
  1729. {
  1730. u32 extra, rc = 0;
  1731. if (((mv64360_32bit_windows[window].base_reg != 0) &&
  1732. (mv64360_32bit_windows[window].size_reg != 0)) ||
  1733. (window == MV64x60_CPU2SRAM_WIN)) {
  1734. extra = mv64360_32bit_windows[window].extra;
  1735. switch (extra & MV64x60_EXTRA_MASK) {
  1736. case MV64x60_EXTRA_CPUWIN_ENAB:
  1737. rc = (mv64x60_read(bh, MV64360_CPU_BAR_ENABLE) &
  1738. (1 << (extra & 0x1f))) == 0;
  1739. break;
  1740. case MV64x60_EXTRA_CPUPROT_ENAB:
  1741. rc = (mv64x60_read(bh,
  1742. mv64360_32bit_windows[window].base_reg) &
  1743. (1 << (extra & 0x1f))) != 0;
  1744. break;
  1745. case MV64x60_EXTRA_ENET_ENAB:
  1746. rc = (mv64x60_read(bh, MV64360_ENET2MEM_BAR_ENABLE) &
  1747. (1 << (extra & 0x7))) == 0;
  1748. break;
  1749. case MV64x60_EXTRA_MPSC_ENAB:
  1750. rc = (mv64x60_read(bh, MV64360_MPSC2MEM_BAR_ENABLE) &
  1751. (1 << (extra & 0x3))) == 0;
  1752. break;
  1753. case MV64x60_EXTRA_IDMA_ENAB:
  1754. rc = (mv64x60_read(bh, MV64360_IDMA2MEM_BAR_ENABLE) &
  1755. (1 << (extra & 0x7))) == 0;
  1756. break;
  1757. default:
  1758. printk(KERN_ERR "mv64360_is_enabled: %s\n",
  1759. "32bit table corrupted");
  1760. }
  1761. }
  1762. return rc;
  1763. }
  1764. /*
  1765. * mv64360_enable_window_32bit()
  1766. *
  1767. * On a MV64360, a window is enabled by either clearing a bit in the
  1768. * CPU BAR Enable reg or setting a bit in the window's base reg.
  1769. */
  1770. static void __init
  1771. mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window)
  1772. {
  1773. u32 extra;
  1774. pr_debug("enable 32bit window: %d\n", window);
  1775. if (((mv64360_32bit_windows[window].base_reg != 0) &&
  1776. (mv64360_32bit_windows[window].size_reg != 0)) ||
  1777. (window == MV64x60_CPU2SRAM_WIN)) {
  1778. extra = mv64360_32bit_windows[window].extra;
  1779. switch (extra & MV64x60_EXTRA_MASK) {
  1780. case MV64x60_EXTRA_CPUWIN_ENAB:
  1781. mv64x60_clr_bits(bh, MV64360_CPU_BAR_ENABLE,
  1782. (1 << (extra & 0x1f)));
  1783. break;
  1784. case MV64x60_EXTRA_CPUPROT_ENAB:
  1785. mv64x60_set_bits(bh,
  1786. mv64360_32bit_windows[window].base_reg,
  1787. (1 << (extra & 0x1f)));
  1788. break;
  1789. case MV64x60_EXTRA_ENET_ENAB:
  1790. mv64x60_clr_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
  1791. (1 << (extra & 0x7)));
  1792. break;
  1793. case MV64x60_EXTRA_MPSC_ENAB:
  1794. mv64x60_clr_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
  1795. (1 << (extra & 0x3)));
  1796. break;
  1797. case MV64x60_EXTRA_IDMA_ENAB:
  1798. mv64x60_clr_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
  1799. (1 << (extra & 0x7)));
  1800. break;
  1801. default:
  1802. printk(KERN_ERR "mv64360_enable: %s\n",
  1803. "32bit table corrupted");
  1804. }
  1805. }
  1806. }
  1807. /*
  1808. * mv64360_disable_window_32bit()
  1809. *
  1810. * On a MV64360, a window is disabled by either setting a bit in the
  1811. * CPU BAR Enable reg or clearing a bit in the window's base reg.
  1812. */
  1813. static void __init
  1814. mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window)
  1815. {
  1816. u32 extra;
  1817. pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
  1818. window, mv64360_32bit_windows[window].base_reg,
  1819. mv64360_32bit_windows[window].size_reg);
  1820. if (((mv64360_32bit_windows[window].base_reg != 0) &&
  1821. (mv64360_32bit_windows[window].size_reg != 0)) ||
  1822. (window == MV64x60_CPU2SRAM_WIN)) {
  1823. extra = mv64360_32bit_windows[window].extra;
  1824. switch (extra & MV64x60_EXTRA_MASK) {
  1825. case MV64x60_EXTRA_CPUWIN_ENAB:
  1826. mv64x60_set_bits(bh, MV64360_CPU_BAR_ENABLE,
  1827. (1 << (extra & 0x1f)));
  1828. break;
  1829. case MV64x60_EXTRA_CPUPROT_ENAB:
  1830. mv64x60_clr_bits(bh,
  1831. mv64360_32bit_windows[window].base_reg,
  1832. (1 << (extra & 0x1f)));
  1833. break;
  1834. case MV64x60_EXTRA_ENET_ENAB:
  1835. mv64x60_set_bits(bh, MV64360_ENET2MEM_BAR_ENABLE,
  1836. (1 << (extra & 0x7)));
  1837. break;
  1838. case MV64x60_EXTRA_MPSC_ENAB:
  1839. mv64x60_set_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE,
  1840. (1 << (extra & 0x3)));
  1841. break;
  1842. case MV64x60_EXTRA_IDMA_ENAB:
  1843. mv64x60_set_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE,
  1844. (1 << (extra & 0x7)));
  1845. break;
  1846. default:
  1847. printk(KERN_ERR "mv64360_disable: %s\n",
  1848. "32bit table corrupted");
  1849. }
  1850. }
  1851. }
  1852. /*
  1853. * mv64360_enable_window_64bit()
  1854. *
  1855. * On the MV64360, a 64-bit window is enabled by setting a bit in the window's
  1856. * base reg.
  1857. */
  1858. static void __init
  1859. mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window)
  1860. {
  1861. pr_debug("enable 64bit window: %d\n", window);
  1862. if ((mv64360_64bit_windows[window].base_lo_reg!= 0) &&
  1863. (mv64360_64bit_windows[window].size_reg != 0)) {
  1864. if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
  1865. == MV64x60_EXTRA_PCIACC_ENAB)
  1866. mv64x60_set_bits(bh,
  1867. mv64360_64bit_windows[window].base_lo_reg,
  1868. (1 << (mv64360_64bit_windows[window].extra &
  1869. 0x1f)));
  1870. else
  1871. printk(KERN_ERR "mv64360_enable: %s\n",
  1872. "64bit table corrupted");
  1873. }
  1874. }
  1875. /*
  1876. * mv64360_disable_window_64bit()
  1877. *
  1878. * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's
  1879. * base reg.
  1880. */
  1881. static void __init
  1882. mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window)
  1883. {
  1884. pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
  1885. window, mv64360_64bit_windows[window].base_lo_reg,
  1886. mv64360_64bit_windows[window].size_reg);
  1887. if ((mv64360_64bit_windows[window].base_lo_reg != 0) &&
  1888. (mv64360_64bit_windows[window].size_reg != 0)) {
  1889. if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK)
  1890. == MV64x60_EXTRA_PCIACC_ENAB)
  1891. mv64x60_clr_bits(bh,
  1892. mv64360_64bit_windows[window].base_lo_reg,
  1893. (1 << (mv64360_64bit_windows[window].extra &
  1894. 0x1f)));
  1895. else
  1896. printk(KERN_ERR "mv64360_disable: %s\n",
  1897. "64bit table corrupted");
  1898. }
  1899. }
  1900. /*
  1901. * mv64360_disable_all_windows()
  1902. *
  1903. * The MV64360 has a few windows that aren't represented in the table of
  1904. * windows at the top of this file. This routine turns all of them off
  1905. * except for the memory controller windows, of course.
  1906. */
  1907. static void __init
  1908. mv64360_disable_all_windows(struct mv64x60_handle *bh,
  1909. struct mv64x60_setup_info *si)
  1910. {
  1911. u32 preserve, i;
  1912. /* Disable 32bit windows (don't disable cpu->mem windows) */
  1913. for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) {
  1914. if (i < 32)
  1915. preserve = si->window_preserve_mask_32_lo & (1 << i);
  1916. else
  1917. preserve = si->window_preserve_mask_32_hi & (1<<(i-32));
  1918. if (!preserve)
  1919. mv64360_disable_window_32bit(bh, i);
  1920. }
  1921. /* Disable 64bit windows */
  1922. for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++)
  1923. if (!(si->window_preserve_mask_64 & (1<<i)))
  1924. mv64360_disable_window_64bit(bh, i);
  1925. /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */
  1926. mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0);
  1927. mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0);
  1928. mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0);
  1929. mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0);
  1930. /* Disable all PCI-><whatever> windows */
  1931. mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff);
  1932. mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff);
  1933. }
  1934. /*
  1935. * mv64360_config_io2mem_windows()
  1936. *
  1937. * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that
  1938. * must be set up so that the respective ctlr can access system memory.
  1939. */
  1940. static u32 enet_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
  1941. MV64x60_ENET2MEM_0_WIN, MV64x60_ENET2MEM_1_WIN,
  1942. MV64x60_ENET2MEM_2_WIN, MV64x60_ENET2MEM_3_WIN,
  1943. };
  1944. static u32 mpsc_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
  1945. MV64x60_MPSC2MEM_0_WIN, MV64x60_MPSC2MEM_1_WIN,
  1946. MV64x60_MPSC2MEM_2_WIN, MV64x60_MPSC2MEM_3_WIN,
  1947. };
  1948. static u32 idma_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = {
  1949. MV64x60_IDMA2MEM_0_WIN, MV64x60_IDMA2MEM_1_WIN,
  1950. MV64x60_IDMA2MEM_2_WIN, MV64x60_IDMA2MEM_3_WIN,
  1951. };
  1952. static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] __initdata =
  1953. { 0xe, 0xd, 0xb, 0x7 };
  1954. static void __init
  1955. mv64360_config_io2mem_windows(struct mv64x60_handle *bh,
  1956. struct mv64x60_setup_info *si,
  1957. u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2])
  1958. {
  1959. u32 i, win;
  1960. pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n");
  1961. mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_0, 0);
  1962. mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_1, 0);
  1963. mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_2, 0);
  1964. mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_0, 0);
  1965. mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_1, 0);
  1966. mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_0, 0);
  1967. mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_1, 0);
  1968. mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_2, 0);
  1969. mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_3, 0);
  1970. /* Assume that mem ctlr has no more windows than embedded I/O ctlr */
  1971. for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++)
  1972. if (bh->ci->is_enabled_32bit(bh, win)) {
  1973. mv64x60_set_32bit_window(bh, enet_tab[i],
  1974. mem_windows[i][0], mem_windows[i][1],
  1975. (dram_selects[i] << 8) |
  1976. (si->enet_options[i] & 0x3000));
  1977. bh->ci->enable_window_32bit(bh, enet_tab[i]);
  1978. /* Give enet r/w access to memory region */
  1979. mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_0,
  1980. (0x3 << (i << 1)));
  1981. mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_1,
  1982. (0x3 << (i << 1)));
  1983. mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_2,
  1984. (0x3 << (i << 1)));
  1985. mv64x60_set_32bit_window(bh, mpsc_tab[i],
  1986. mem_windows[i][0], mem_windows[i][1],
  1987. (dram_selects[i] << 8) |
  1988. (si->mpsc_options[i] & 0x3000));
  1989. bh->ci->enable_window_32bit(bh, mpsc_tab[i]);
  1990. /* Give mpsc r/w access to memory region */
  1991. mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_0,
  1992. (0x3 << (i << 1)));
  1993. mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_1,
  1994. (0x3 << (i << 1)));
  1995. mv64x60_set_32bit_window(bh, idma_tab[i],
  1996. mem_windows[i][0], mem_windows[i][1],
  1997. (dram_selects[i] << 8) |
  1998. (si->idma_options[i] & 0x3000));
  1999. bh->ci->enable_window_32bit(bh, idma_tab[i]);
  2000. /* Give idma r/w access to memory region */
  2001. mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_0,
  2002. (0x3 << (i << 1)));
  2003. mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_1,
  2004. (0x3 << (i << 1)));
  2005. mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_2,
  2006. (0x3 << (i << 1)));
  2007. mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3,
  2008. (0x3 << (i << 1)));
  2009. }
  2010. }
  2011. /*
  2012. * mv64360_set_mpsc2regs_window()
  2013. *
  2014. * MPSC has a window to the bridge's internal registers. Call this routine
  2015. * to change that window so it doesn't conflict with the windows mapping the
  2016. * mpsc to system memory.
  2017. */
  2018. static void __init
  2019. mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base)
  2020. {
  2021. pr_debug("set mpsc->internal regs, base: 0x%x\n", base);
  2022. mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000);
  2023. }
  2024. /*
  2025. * mv64360_chip_specific_init()
  2026. *
  2027. * Implement errata workarounds for the MV64360.
  2028. */
  2029. static void __init
  2030. mv64360_chip_specific_init(struct mv64x60_handle *bh,
  2031. struct mv64x60_setup_info *si)
  2032. {
  2033. #if !defined(CONFIG_NOT_COHERENT_CACHE)
  2034. mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24));
  2035. #endif
  2036. #ifdef CONFIG_SERIAL_MPSC
  2037. mv64x60_mpsc0_pdata.brg_can_tune = 1;
  2038. mv64x60_mpsc0_pdata.cache_mgmt = 1;
  2039. mv64x60_mpsc1_pdata.brg_can_tune = 1;
  2040. mv64x60_mpsc1_pdata.cache_mgmt = 1;
  2041. #endif
  2042. }
  2043. /*
  2044. * mv64460_chip_specific_init()
  2045. *
  2046. * Implement errata workarounds for the MV64460.
  2047. */
  2048. static void __init
  2049. mv64460_chip_specific_init(struct mv64x60_handle *bh,
  2050. struct mv64x60_setup_info *si)
  2051. {
  2052. #if !defined(CONFIG_NOT_COHERENT_CACHE)
  2053. mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24) | (1<<25));
  2054. mv64x60_set_bits(bh, MV64460_D_UNIT_MMASK, (1<<1) | (1<<4));
  2055. #endif
  2056. #ifdef CONFIG_SERIAL_MPSC
  2057. mv64x60_mpsc0_pdata.brg_can_tune = 1;
  2058. mv64x60_mpsc0_pdata.cache_mgmt = 1;
  2059. mv64x60_mpsc1_pdata.brg_can_tune = 1;
  2060. mv64x60_mpsc1_pdata.cache_mgmt = 1;
  2061. #endif
  2062. }
  2063. #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
  2064. /* Export the hotswap register via sysfs for enum event monitoring */
  2065. #define VAL_LEN_MAX 11 /* 32-bit hex or dec stringified number + '\n' */
  2066. static DEFINE_MUTEX(mv64xxx_hs_lock);
  2067. static ssize_t
  2068. mv64xxx_hs_reg_read(struct kobject *kobj, char *buf, loff_t off, size_t count)
  2069. {
  2070. u32 v;
  2071. u8 save_exclude;
  2072. if (off > 0)
  2073. return 0;
  2074. if (count < VAL_LEN_MAX)
  2075. return -EINVAL;
  2076. if (mutex_lock_interruptible(&mv64xxx_hs_lock))
  2077. return -ERESTARTSYS;
  2078. save_exclude = mv64x60_pci_exclude_bridge;
  2079. mv64x60_pci_exclude_bridge = 0;
  2080. early_read_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
  2081. MV64360_PCICFG_CPCI_HOTSWAP, &v);
  2082. mv64x60_pci_exclude_bridge = save_exclude;
  2083. mutex_unlock(&mv64xxx_hs_lock);
  2084. return sprintf(buf, "0x%08x\n", v);
  2085. }
  2086. static ssize_t
  2087. mv64xxx_hs_reg_write(struct kobject *kobj, char *buf, loff_t off, size_t count)
  2088. {
  2089. u32 v;
  2090. u8 save_exclude;
  2091. if (off > 0)
  2092. return 0;
  2093. if (count <= 0)
  2094. return -EINVAL;
  2095. if (sscanf(buf, "%i", &v) == 1) {
  2096. if (mutex_lock_interruptible(&mv64xxx_hs_lock))
  2097. return -ERESTARTSYS;
  2098. save_exclude = mv64x60_pci_exclude_bridge;
  2099. mv64x60_pci_exclude_bridge = 0;
  2100. early_write_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0),
  2101. MV64360_PCICFG_CPCI_HOTSWAP, v);
  2102. mv64x60_pci_exclude_bridge = save_exclude;
  2103. mutex_unlock(&mv64xxx_hs_lock);
  2104. }
  2105. else
  2106. count = -EINVAL;
  2107. return count;
  2108. }
  2109. static struct bin_attribute mv64xxx_hs_reg_attr = { /* Hotswap register */
  2110. .attr = {
  2111. .name = "hs_reg",
  2112. .mode = S_IRUGO | S_IWUSR,
  2113. },
  2114. .size = VAL_LEN_MAX,
  2115. .read = mv64xxx_hs_reg_read,
  2116. .write = mv64xxx_hs_reg_write,
  2117. };
  2118. /* Provide sysfs file indicating if this platform supports the hs_reg */
  2119. static ssize_t
  2120. mv64xxx_hs_reg_valid_show(struct device *dev, struct device_attribute *attr,
  2121. char *buf)
  2122. {
  2123. struct platform_device *pdev;
  2124. struct mv64xxx_pdata *pdp;
  2125. u32 v;
  2126. pdev = container_of(dev, struct platform_device, dev);
  2127. pdp = (struct mv64xxx_pdata *)pdev->dev.platform_data;
  2128. if (mutex_lock_interruptible(&mv64xxx_hs_lock))
  2129. return -ERESTARTSYS;
  2130. v = pdp->hs_reg_valid;
  2131. mutex_unlock(&mv64xxx_hs_lock);
  2132. return sprintf(buf, "%i\n", v);
  2133. }
  2134. static DEVICE_ATTR(hs_reg_valid, S_IRUGO, mv64xxx_hs_reg_valid_show, NULL);
  2135. static int __init
  2136. mv64xxx_sysfs_init(void)
  2137. {
  2138. sysfs_create_bin_file(&mv64xxx_device.dev.kobj, &mv64xxx_hs_reg_attr);
  2139. sysfs_create_file(&mv64xxx_device.dev.kobj,&dev_attr_hs_reg_valid.attr);
  2140. return 0;
  2141. }
  2142. subsys_initcall(mv64xxx_sysfs_init);
  2143. #endif