mpc8544_ds.c 8.9 KB

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  1. /*
  2. * MPC8544 DS Board Setup
  3. *
  4. * Author Xianghua Xiao (x.xiao@freescale.com)
  5. * Roy Zang <tie-fei.zang@freescale.com>
  6. * - Add PCI/PCI Exprees support
  7. * Copyright 2007 Freescale Semiconductor Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/stddef.h>
  15. #include <linux/kernel.h>
  16. #include <linux/pci.h>
  17. #include <linux/kdev_t.h>
  18. #include <linux/delay.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/interrupt.h>
  21. #include <asm/system.h>
  22. #include <asm/time.h>
  23. #include <asm/machdep.h>
  24. #include <asm/pci-bridge.h>
  25. #include <asm/mpc85xx.h>
  26. #include <mm/mmu_decl.h>
  27. #include <asm/prom.h>
  28. #include <asm/udbg.h>
  29. #include <asm/mpic.h>
  30. #include <asm/i8259.h>
  31. #include <sysdev/fsl_soc.h>
  32. #include <sysdev/fsl_pci.h>
  33. #include "mpc85xx.h"
  34. #undef DEBUG
  35. #ifdef DEBUG
  36. #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
  37. #else
  38. #define DBG(fmt, args...)
  39. #endif
  40. #ifdef CONFIG_PPC_I8259
  41. static void mpc8544_8259_cascade(unsigned int irq, struct irq_desc *desc)
  42. {
  43. unsigned int cascade_irq = i8259_irq();
  44. if (cascade_irq != NO_IRQ) {
  45. generic_handle_irq(cascade_irq);
  46. }
  47. desc->chip->eoi(irq);
  48. }
  49. #endif /* CONFIG_PPC_I8259 */
  50. void __init mpc8544_ds_pic_init(void)
  51. {
  52. struct mpic *mpic;
  53. struct resource r;
  54. struct device_node *np = NULL;
  55. #ifdef CONFIG_PPC_I8259
  56. struct device_node *cascade_node = NULL;
  57. int cascade_irq;
  58. #endif
  59. np = of_find_node_by_type(np, "open-pic");
  60. if (np == NULL) {
  61. printk(KERN_ERR "Could not find open-pic node\n");
  62. return;
  63. }
  64. if (of_address_to_resource(np, 0, &r)) {
  65. printk(KERN_ERR "Failed to map mpic register space\n");
  66. of_node_put(np);
  67. return;
  68. }
  69. mpic = mpic_alloc(np, r.start,
  70. MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
  71. 0, 256, " OpenPIC ");
  72. BUG_ON(mpic == NULL);
  73. mpic_init(mpic);
  74. #ifdef CONFIG_PPC_I8259
  75. /* Initialize the i8259 controller */
  76. for_each_node_by_type(np, "interrupt-controller")
  77. if (of_device_is_compatible(np, "chrp,iic")) {
  78. cascade_node = np;
  79. break;
  80. }
  81. if (cascade_node == NULL) {
  82. printk(KERN_DEBUG "Could not find i8259 PIC\n");
  83. return;
  84. }
  85. cascade_irq = irq_of_parse_and_map(cascade_node, 0);
  86. if (cascade_irq == NO_IRQ) {
  87. printk(KERN_ERR "Failed to map cascade interrupt\n");
  88. return;
  89. }
  90. DBG("mpc8544ds: cascade mapped to irq %d\n", cascade_irq);
  91. i8259_init(cascade_node, 0);
  92. of_node_put(cascade_node);
  93. set_irq_chained_handler(cascade_irq, mpc8544_8259_cascade);
  94. #endif /* CONFIG_PPC_I8259 */
  95. }
  96. #ifdef CONFIG_PCI
  97. enum pirq { PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH };
  98. /*
  99. * Value in table -- IRQ number
  100. */
  101. const unsigned char uli1575_irq_route_table[16] = {
  102. 0, /* 0: Reserved */
  103. 0x8,
  104. 0, /* 2: Reserved */
  105. 0x2,
  106. 0x4,
  107. 0x5,
  108. 0x7,
  109. 0x6,
  110. 0, /* 8: Reserved */
  111. 0x1,
  112. 0x3,
  113. 0x9,
  114. 0xb,
  115. 0, /* 13: Reserved */
  116. 0xd,
  117. 0xf,
  118. };
  119. static int __devinit
  120. get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
  121. {
  122. struct of_irq oirq;
  123. u32 laddr[3];
  124. struct device_node *hosenode = hose ? hose->arch_data : NULL;
  125. if (!hosenode)
  126. return -EINVAL;
  127. laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
  128. laddr[1] = laddr[2] = 0;
  129. of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
  130. DBG("mpc8544_ds: pci irq addr %x, slot %d, pin %d, irq %d\n",
  131. laddr[0], slot, pin, oirq.specifier[0]);
  132. return oirq.specifier[0];
  133. }
  134. /*8259*/
  135. static void __devinit quirk_uli1575(struct pci_dev *dev)
  136. {
  137. unsigned short temp;
  138. struct pci_controller *hose = pci_bus_to_host(dev->bus);
  139. unsigned char irq2pin[16];
  140. unsigned long pirq_map_word = 0;
  141. u32 irq;
  142. int i;
  143. /*
  144. * ULI1575 interrupts route setup
  145. */
  146. memset(irq2pin, 0, 16); /* Initialize default value 0 */
  147. irq2pin[6]=PIRQA+3; /* enabled mapping for IRQ6 to PIRQD, used by SATA */
  148. /*
  149. * PIRQE -> PIRQF mapping set manually
  150. *
  151. * IRQ pin IRQ#
  152. * PIRQE ---- 9
  153. * PIRQF ---- 10
  154. * PIRQG ---- 11
  155. * PIRQH ---- 12
  156. */
  157. for (i = 0; i < 4; i++)
  158. irq2pin[i + 9] = PIRQE + i;
  159. /* Set IRQ-PIRQ Mapping to ULI1575 */
  160. for (i = 0; i < 16; i++)
  161. if (irq2pin[i])
  162. pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
  163. << ((irq2pin[i] - PIRQA) * 4);
  164. pirq_map_word |= 1<<26; /* disable INTx in EP mode*/
  165. /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
  166. DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
  167. (int)pirq_map_word);
  168. pci_write_config_dword(dev, 0x48, pirq_map_word);
  169. #define ULI1575_SET_DEV_IRQ(slot, pin, reg) \
  170. do { \
  171. int irq; \
  172. irq = get_pci_irq_from_of(hose, slot, pin); \
  173. if (irq > 0 && irq < 16) \
  174. pci_write_config_byte(dev, reg, irq2pin[irq]); \
  175. else \
  176. printk(KERN_WARNING "ULI1575 device" \
  177. "(slot %d, pin %d) irq %d is invalid.\n", \
  178. slot, pin, irq); \
  179. } while(0)
  180. /* USB 1.1 OHCI controller 1, slot 28, pin 1 */
  181. ULI1575_SET_DEV_IRQ(28, 1, 0x86);
  182. /* USB 1.1 OHCI controller 2, slot 28, pin 2 */
  183. ULI1575_SET_DEV_IRQ(28, 2, 0x87);
  184. /* USB 1.1 OHCI controller 3, slot 28, pin 3 */
  185. ULI1575_SET_DEV_IRQ(28, 3, 0x88);
  186. /* USB 2.0 controller, slot 28, pin 4 */
  187. irq = get_pci_irq_from_of(hose, 28, 4);
  188. if (irq >= 0 && irq <= 15)
  189. pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
  190. /* Audio controller, slot 29, pin 1 */
  191. ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
  192. /* Modem controller, slot 29, pin 2 */
  193. ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
  194. /* HD audio controller, slot 29, pin 3 */
  195. ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
  196. /* SMB interrupt: slot 30, pin 1 */
  197. ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
  198. /* PMU ACPI SCI interrupt: slot 30, pin 2 */
  199. ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
  200. /* Serial ATA interrupt: slot 31, pin 1 */
  201. ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
  202. /* Primary PATA IDE IRQ: 14
  203. * Secondary PATA IDE IRQ: 15
  204. */
  205. pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
  206. pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
  207. /* Set IRQ14 and IRQ15 to legacy IRQs */
  208. pci_read_config_word(dev, 0x46, &temp);
  209. temp |= 0xc000;
  210. pci_write_config_word(dev, 0x46, temp);
  211. /* Set i8259 interrupt trigger
  212. * IRQ 3: Level
  213. * IRQ 4: Level
  214. * IRQ 5: Level
  215. * IRQ 6: Level
  216. * IRQ 7: Level
  217. * IRQ 9: Level
  218. * IRQ 10: Level
  219. * IRQ 11: Level
  220. * IRQ 12: Level
  221. * IRQ 14: Edge
  222. * IRQ 15: Edge
  223. */
  224. outb(0xfa, 0x4d0);
  225. outb(0x1e, 0x4d1);
  226. #undef ULI1575_SET_DEV_IRQ
  227. }
  228. /* SATA */
  229. static void __devinit quirk_uli5288(struct pci_dev *dev)
  230. {
  231. unsigned char c;
  232. pci_read_config_byte(dev, 0x83, &c);
  233. c |= 0x80; /* read/write lock */
  234. pci_write_config_byte(dev, 0x83, c);
  235. pci_write_config_byte(dev, 0x09, 0x01); /* Base class code: storage */
  236. pci_write_config_byte(dev, 0x0a, 0x06); /* IDE disk */
  237. pci_read_config_byte(dev, 0x83, &c);
  238. c &= 0x7f;
  239. pci_write_config_byte(dev, 0x83, c);
  240. pci_read_config_byte(dev, 0x84, &c);
  241. c |= 0x01; /* emulated PATA mode enabled */
  242. pci_write_config_byte(dev, 0x84, c);
  243. }
  244. /* PATA */
  245. static void __devinit quirk_uli5229(struct pci_dev *dev)
  246. {
  247. unsigned short temp;
  248. pci_write_config_word(dev, 0x04, 0x0405); /* MEM IO MSI */
  249. pci_read_config_word(dev, 0x4a, &temp);
  250. temp |= 0x1000; /* Enable Native IRQ 14/15 */
  251. pci_write_config_word(dev, 0x4a, temp);
  252. }
  253. /*Bridge*/
  254. static void __devinit early_uli5249(struct pci_dev *dev)
  255. {
  256. unsigned char temp;
  257. pci_write_config_word(dev, 0x04, 0x0007); /* mem access */
  258. pci_read_config_byte(dev, 0x7c, &temp);
  259. pci_write_config_byte(dev, 0x7c, 0x80); /* R/W lock control */
  260. pci_write_config_byte(dev, 0x09, 0x01); /* set as pci-pci bridge */
  261. pci_write_config_byte(dev, 0x7c, temp); /* restore pci bus debug control */
  262. dev->class |= 0x1;
  263. }
  264. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
  265. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
  266. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
  267. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
  268. #endif /* CONFIG_PCI */
  269. /*
  270. * Setup the architecture
  271. */
  272. static void __init mpc8544_ds_setup_arch(void)
  273. {
  274. #ifdef CONFIG_PCI
  275. struct device_node *np;
  276. #endif
  277. if (ppc_md.progress)
  278. ppc_md.progress("mpc8544_ds_setup_arch()", 0);
  279. #ifdef CONFIG_PCI
  280. for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
  281. struct resource rsrc;
  282. of_address_to_resource(np, 0, &rsrc);
  283. if ((rsrc.start & 0xfffff) == 0xb000)
  284. fsl_add_bridge(np, 1);
  285. else
  286. fsl_add_bridge(np, 0);
  287. }
  288. #endif
  289. printk("MPC8544 DS board from Freescale Semiconductor\n");
  290. }
  291. /*
  292. * Called very early, device-tree isn't unflattened
  293. */
  294. static int __init mpc8544_ds_probe(void)
  295. {
  296. unsigned long root = of_get_flat_dt_root();
  297. return of_flat_dt_is_compatible(root, "MPC8544DS");
  298. }
  299. define_machine(mpc8544_ds) {
  300. .name = "MPC8544 DS",
  301. .probe = mpc8544_ds_probe,
  302. .setup_arch = mpc8544_ds_setup_arch,
  303. .init_IRQ = mpc8544_ds_pic_init,
  304. .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
  305. .get_irq = mpic_get_irq,
  306. .restart = mpc85xx_restart,
  307. .calibrate_decr = generic_calibrate_decr,
  308. .progress = udbg_progress,
  309. };