via82cxxx.c 14 KB

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  1. /*
  2. *
  3. * Version 3.40
  4. *
  5. * VIA IDE driver for Linux. Supported southbridges:
  6. *
  7. * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
  8. * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
  9. * vt8235, vt8237, vt8237a
  10. *
  11. * Copyright (c) 2000-2002 Vojtech Pavlik
  12. * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
  13. *
  14. * Based on the work of:
  15. * Michel Aubry
  16. * Jeff Garzik
  17. * Andre Hedrick
  18. *
  19. * Documentation:
  20. * Obsolete device documentation publically available from via.com.tw
  21. * Current device documentation available under NDA only
  22. */
  23. /*
  24. * This program is free software; you can redistribute it and/or modify it
  25. * under the terms of the GNU General Public License version 2 as published by
  26. * the Free Software Foundation.
  27. */
  28. #include <linux/module.h>
  29. #include <linux/kernel.h>
  30. #include <linux/ioport.h>
  31. #include <linux/blkdev.h>
  32. #include <linux/pci.h>
  33. #include <linux/init.h>
  34. #include <linux/ide.h>
  35. #include <asm/io.h>
  36. #ifdef CONFIG_PPC_CHRP
  37. #include <asm/processor.h>
  38. #endif
  39. #include "ide-timing.h"
  40. #define VIA_IDE_ENABLE 0x40
  41. #define VIA_IDE_CONFIG 0x41
  42. #define VIA_FIFO_CONFIG 0x43
  43. #define VIA_MISC_1 0x44
  44. #define VIA_MISC_2 0x45
  45. #define VIA_MISC_3 0x46
  46. #define VIA_DRIVE_TIMING 0x48
  47. #define VIA_8BIT_TIMING 0x4e
  48. #define VIA_ADDRESS_SETUP 0x4c
  49. #define VIA_UDMA_TIMING 0x50
  50. #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
  51. #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
  52. #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
  53. #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
  54. #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
  55. #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
  56. /*
  57. * VIA SouthBridge chips.
  58. */
  59. static struct via_isa_bridge {
  60. char *name;
  61. u16 id;
  62. u8 rev_min;
  63. u8 rev_max;
  64. u8 udma_mask;
  65. u8 flags;
  66. } via_isa_bridges[] = {
  67. { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  68. { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  69. { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  70. { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  71. { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  72. { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  73. { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  74. { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  75. { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
  76. { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
  77. { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
  78. { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
  79. { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
  80. { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
  81. { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
  82. { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
  83. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
  84. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
  85. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
  86. { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
  87. { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
  88. { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
  89. { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
  90. { NULL }
  91. };
  92. static unsigned int via_clock;
  93. static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
  94. struct via82cxxx_dev
  95. {
  96. struct via_isa_bridge *via_config;
  97. unsigned int via_80w;
  98. };
  99. /**
  100. * via_set_speed - write timing registers
  101. * @dev: PCI device
  102. * @dn: device
  103. * @timing: IDE timing data to use
  104. *
  105. * via_set_speed writes timing values to the chipset registers
  106. */
  107. static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
  108. {
  109. struct pci_dev *dev = hwif->pci_dev;
  110. struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
  111. u8 t;
  112. if (~vdev->via_config->flags & VIA_BAD_AST) {
  113. pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
  114. t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
  115. pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
  116. }
  117. pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
  118. ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
  119. pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
  120. ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
  121. switch (vdev->via_config->udma_mask) {
  122. case ATA_UDMA2: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
  123. case ATA_UDMA4: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
  124. case ATA_UDMA5: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
  125. case ATA_UDMA6: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
  126. default: return;
  127. }
  128. pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
  129. }
  130. /**
  131. * via_set_drive - configure transfer mode
  132. * @drive: Drive to set up
  133. * @speed: desired speed
  134. *
  135. * via_set_drive() computes timing values configures the drive and
  136. * the chipset to a desired transfer mode. It also can be called
  137. * by upper layers.
  138. */
  139. static int via_set_drive(ide_drive_t *drive, u8 speed)
  140. {
  141. ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
  142. struct via82cxxx_dev *vdev = pci_get_drvdata(drive->hwif->pci_dev);
  143. struct ide_timing t, p;
  144. unsigned int T, UT;
  145. if (speed != XFER_PIO_SLOW)
  146. ide_config_drive_speed(drive, speed);
  147. T = 1000000000 / via_clock;
  148. switch (vdev->via_config->udma_mask) {
  149. case ATA_UDMA2: UT = T; break;
  150. case ATA_UDMA4: UT = T/2; break;
  151. case ATA_UDMA5: UT = T/3; break;
  152. case ATA_UDMA6: UT = T/4; break;
  153. default: UT = T;
  154. }
  155. ide_timing_compute(drive, speed, &t, T, UT);
  156. if (peer->present) {
  157. ide_timing_compute(peer, peer->current_speed, &p, T, UT);
  158. ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
  159. }
  160. via_set_speed(HWIF(drive), drive->dn, &t);
  161. if (!drive->init_speed)
  162. drive->init_speed = speed;
  163. drive->current_speed = speed;
  164. return 0;
  165. }
  166. /**
  167. * via82cxxx_tune_drive - PIO setup
  168. * @drive: drive to set up
  169. * @pio: mode to use (255 for 'best possible')
  170. *
  171. * A callback from the upper layers for PIO-only tuning.
  172. */
  173. static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
  174. {
  175. if (pio == 255) {
  176. via_set_drive(drive, ide_find_best_pio_mode(drive));
  177. return;
  178. }
  179. via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
  180. }
  181. /**
  182. * via82cxxx_ide_dma_check - set up for DMA if possible
  183. * @drive: IDE drive to set up
  184. *
  185. * Set up the drive for the highest supported speed considering the
  186. * driver, controller and cable
  187. */
  188. static int via82cxxx_ide_dma_check (ide_drive_t *drive)
  189. {
  190. u8 speed = ide_max_dma_mode(drive);
  191. if (speed == 0)
  192. speed = ide_find_best_pio_mode(drive);
  193. via_set_drive(drive, speed);
  194. if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
  195. return 0;
  196. return -1;
  197. }
  198. static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
  199. {
  200. struct via_isa_bridge *via_config;
  201. u8 t;
  202. for (via_config = via_isa_bridges; via_config->id; via_config++)
  203. if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
  204. !!(via_config->flags & VIA_BAD_ID),
  205. via_config->id, NULL))) {
  206. pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
  207. if (t >= via_config->rev_min &&
  208. t <= via_config->rev_max)
  209. break;
  210. pci_dev_put(*isa);
  211. }
  212. return via_config;
  213. }
  214. /*
  215. * Check and handle 80-wire cable presence
  216. */
  217. static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
  218. {
  219. int i;
  220. switch (vdev->via_config->udma_mask) {
  221. case ATA_UDMA4:
  222. for (i = 24; i >= 0; i -= 8)
  223. if (((u >> (i & 16)) & 8) &&
  224. ((u >> i) & 0x20) &&
  225. (((u >> i) & 7) < 2)) {
  226. /*
  227. * 2x PCI clock and
  228. * UDMA w/ < 3T/cycle
  229. */
  230. vdev->via_80w |= (1 << (1 - (i >> 4)));
  231. }
  232. break;
  233. case ATA_UDMA5:
  234. for (i = 24; i >= 0; i -= 8)
  235. if (((u >> i) & 0x10) ||
  236. (((u >> i) & 0x20) &&
  237. (((u >> i) & 7) < 4))) {
  238. /* BIOS 80-wire bit or
  239. * UDMA w/ < 60ns/cycle
  240. */
  241. vdev->via_80w |= (1 << (1 - (i >> 4)));
  242. }
  243. break;
  244. case ATA_UDMA6:
  245. for (i = 24; i >= 0; i -= 8)
  246. if (((u >> i) & 0x10) ||
  247. (((u >> i) & 0x20) &&
  248. (((u >> i) & 7) < 6))) {
  249. /* BIOS 80-wire bit or
  250. * UDMA w/ < 60ns/cycle
  251. */
  252. vdev->via_80w |= (1 << (1 - (i >> 4)));
  253. }
  254. break;
  255. }
  256. }
  257. /**
  258. * init_chipset_via82cxxx - initialization handler
  259. * @dev: PCI device
  260. * @name: Name of interface
  261. *
  262. * The initialization callback. Here we determine the IDE chip type
  263. * and initialize its drive independent registers.
  264. */
  265. static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
  266. {
  267. struct pci_dev *isa = NULL;
  268. struct via82cxxx_dev *vdev;
  269. struct via_isa_bridge *via_config;
  270. u8 t, v;
  271. u32 u;
  272. vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
  273. if (!vdev) {
  274. printk(KERN_ERR "VP_IDE: out of memory :(\n");
  275. return -ENOMEM;
  276. }
  277. pci_set_drvdata(dev, vdev);
  278. /*
  279. * Find the ISA bridge to see how good the IDE is.
  280. */
  281. vdev->via_config = via_config = via_config_find(&isa);
  282. /* We checked this earlier so if it fails here deeep badness
  283. is involved */
  284. BUG_ON(!via_config->id);
  285. /*
  286. * Detect cable and configure Clk66
  287. */
  288. pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
  289. via_cable_detect(vdev, u);
  290. if (via_config->udma_mask == ATA_UDMA4) {
  291. /* Enable Clk66 */
  292. pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
  293. } else if (via_config->flags & VIA_BAD_CLK66) {
  294. /* Would cause trouble on 596a and 686 */
  295. pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
  296. }
  297. /*
  298. * Check whether interfaces are enabled.
  299. */
  300. pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
  301. /*
  302. * Set up FIFO sizes and thresholds.
  303. */
  304. pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
  305. /* Disable PREQ# till DDACK# */
  306. if (via_config->flags & VIA_BAD_PREQ) {
  307. /* Would crash on 586b rev 41 */
  308. t &= 0x7f;
  309. }
  310. /* Fix FIFO split between channels */
  311. if (via_config->flags & VIA_SET_FIFO) {
  312. t &= (t & 0x9f);
  313. switch (v & 3) {
  314. case 2: t |= 0x00; break; /* 16 on primary */
  315. case 1: t |= 0x60; break; /* 16 on secondary */
  316. case 3: t |= 0x20; break; /* 8 pri 8 sec */
  317. }
  318. }
  319. pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
  320. /*
  321. * Determine system bus clock.
  322. */
  323. via_clock = system_bus_clock() * 1000;
  324. switch (via_clock) {
  325. case 33000: via_clock = 33333; break;
  326. case 37000: via_clock = 37500; break;
  327. case 41000: via_clock = 41666; break;
  328. }
  329. if (via_clock < 20000 || via_clock > 50000) {
  330. printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
  331. "impossible (%d), using 33 MHz instead.\n", via_clock);
  332. printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
  333. "to assume 80-wire cable.\n");
  334. via_clock = 33333;
  335. }
  336. /*
  337. * Print the boot message.
  338. */
  339. pci_read_config_byte(isa, PCI_REVISION_ID, &t);
  340. printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
  341. "controller on pci%s\n",
  342. via_config->name, t,
  343. via_config->udma_mask ? "U" : "MW",
  344. via_dma[via_config->udma_mask ?
  345. (fls(via_config->udma_mask) - 1) : 0],
  346. pci_name(dev));
  347. pci_dev_put(isa);
  348. return 0;
  349. }
  350. static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
  351. {
  352. struct via82cxxx_dev *vdev = pci_get_drvdata(hwif->pci_dev);
  353. int i;
  354. hwif->autodma = 0;
  355. hwif->tuneproc = &via82cxxx_tune_drive;
  356. hwif->speedproc = &via_set_drive;
  357. #ifdef CONFIG_PPC_CHRP
  358. if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
  359. hwif->irq = hwif->channel ? 15 : 14;
  360. }
  361. #endif
  362. for (i = 0; i < 2; i++) {
  363. hwif->drives[i].io_32bit = 1;
  364. hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
  365. hwif->drives[i].autotune = 1;
  366. hwif->drives[i].dn = hwif->channel * 2 + i;
  367. }
  368. if (!hwif->dma_base)
  369. return;
  370. hwif->atapi_dma = 1;
  371. hwif->ultra_mask = vdev->via_config->udma_mask;
  372. hwif->mwdma_mask = 0x07;
  373. hwif->swdma_mask = 0x07;
  374. if (!hwif->udma_four)
  375. hwif->udma_four = (vdev->via_80w >> hwif->channel) & 1;
  376. hwif->ide_dma_check = &via82cxxx_ide_dma_check;
  377. if (!noautodma)
  378. hwif->autodma = 1;
  379. hwif->drives[0].autodma = hwif->autodma;
  380. hwif->drives[1].autodma = hwif->autodma;
  381. }
  382. static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
  383. { /* 0 */
  384. .name = "VP_IDE",
  385. .init_chipset = init_chipset_via82cxxx,
  386. .init_hwif = init_hwif_via82cxxx,
  387. .channels = 2,
  388. .autodma = NOAUTODMA,
  389. .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
  390. .bootable = ON_BOARD
  391. },{ /* 1 */
  392. .name = "VP_IDE",
  393. .init_chipset = init_chipset_via82cxxx,
  394. .init_hwif = init_hwif_via82cxxx,
  395. .channels = 2,
  396. .autodma = AUTODMA,
  397. .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
  398. .bootable = ON_BOARD,
  399. }
  400. };
  401. static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  402. {
  403. struct pci_dev *isa = NULL;
  404. struct via_isa_bridge *via_config;
  405. /*
  406. * Find the ISA bridge and check we know what it is.
  407. */
  408. via_config = via_config_find(&isa);
  409. pci_dev_put(isa);
  410. if (!via_config->id) {
  411. printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
  412. return -ENODEV;
  413. }
  414. return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
  415. }
  416. static struct pci_device_id via_pci_tbl[] = {
  417. { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  418. { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  419. { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
  420. { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_SATA_EIDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
  421. { 0, },
  422. };
  423. MODULE_DEVICE_TABLE(pci, via_pci_tbl);
  424. static struct pci_driver driver = {
  425. .name = "VIA_IDE",
  426. .id_table = via_pci_tbl,
  427. .probe = via_init_one,
  428. };
  429. static int __init via_ide_init(void)
  430. {
  431. return ide_pci_register_driver(&driver);
  432. }
  433. module_init(via_ide_init);
  434. MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
  435. MODULE_DESCRIPTION("PCI driver module for VIA IDE");
  436. MODULE_LICENSE("GPL");