dss_features.c 16 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/dss_features.c
  3. *
  4. * Copyright (C) 2010 Texas Instruments
  5. * Author: Archit Taneja <archit@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include <linux/err.h>
  22. #include <linux/slab.h>
  23. #include <video/omapdss.h>
  24. #include <plat/cpu.h>
  25. #include "dss.h"
  26. #include "dss_features.h"
  27. /* Defines a generic omap register field */
  28. struct dss_reg_field {
  29. u8 start, end;
  30. };
  31. struct dss_param_range {
  32. int min, max;
  33. };
  34. struct omap_dss_features {
  35. const struct dss_reg_field *reg_fields;
  36. const int num_reg_fields;
  37. const u32 has_feature;
  38. const int num_mgrs;
  39. const int num_ovls;
  40. const enum omap_display_type *supported_displays;
  41. const enum omap_color_mode *supported_color_modes;
  42. const enum omap_overlay_caps *overlay_caps;
  43. const char * const *clksrc_names;
  44. const struct dss_param_range *dss_params;
  45. const u32 buffer_size_unit;
  46. const u32 burst_size_unit;
  47. };
  48. /* This struct is assigned to one of the below during initialization */
  49. static const struct omap_dss_features *omap_current_dss_features;
  50. static const struct dss_reg_field omap2_dss_reg_fields[] = {
  51. [FEAT_REG_FIRHINC] = { 11, 0 },
  52. [FEAT_REG_FIRVINC] = { 27, 16 },
  53. [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
  54. [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
  55. [FEAT_REG_FIFOSIZE] = { 8, 0 },
  56. [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
  57. [FEAT_REG_VERTICALACCU] = { 25, 16 },
  58. [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
  59. [FEAT_REG_DSIPLL_REGN] = { 0, 0 },
  60. [FEAT_REG_DSIPLL_REGM] = { 0, 0 },
  61. [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 },
  62. [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 },
  63. };
  64. static const struct dss_reg_field omap3_dss_reg_fields[] = {
  65. [FEAT_REG_FIRHINC] = { 12, 0 },
  66. [FEAT_REG_FIRVINC] = { 28, 16 },
  67. [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
  68. [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
  69. [FEAT_REG_FIFOSIZE] = { 10, 0 },
  70. [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
  71. [FEAT_REG_VERTICALACCU] = { 25, 16 },
  72. [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
  73. [FEAT_REG_DSIPLL_REGN] = { 7, 1 },
  74. [FEAT_REG_DSIPLL_REGM] = { 18, 8 },
  75. [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 },
  76. [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
  77. };
  78. static const struct dss_reg_field omap4_dss_reg_fields[] = {
  79. [FEAT_REG_FIRHINC] = { 12, 0 },
  80. [FEAT_REG_FIRVINC] = { 28, 16 },
  81. [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
  82. [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
  83. [FEAT_REG_FIFOSIZE] = { 15, 0 },
  84. [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
  85. [FEAT_REG_VERTICALACCU] = { 26, 16 },
  86. [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
  87. [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
  88. [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
  89. [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
  90. [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
  91. };
  92. static const enum omap_display_type omap2_dss_supported_displays[] = {
  93. /* OMAP_DSS_CHANNEL_LCD */
  94. OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
  95. /* OMAP_DSS_CHANNEL_DIGIT */
  96. OMAP_DISPLAY_TYPE_VENC,
  97. };
  98. static const enum omap_display_type omap3430_dss_supported_displays[] = {
  99. /* OMAP_DSS_CHANNEL_LCD */
  100. OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
  101. OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
  102. /* OMAP_DSS_CHANNEL_DIGIT */
  103. OMAP_DISPLAY_TYPE_VENC,
  104. };
  105. static const enum omap_display_type omap3630_dss_supported_displays[] = {
  106. /* OMAP_DSS_CHANNEL_LCD */
  107. OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
  108. OMAP_DISPLAY_TYPE_DSI,
  109. /* OMAP_DSS_CHANNEL_DIGIT */
  110. OMAP_DISPLAY_TYPE_VENC,
  111. };
  112. static const enum omap_display_type omap4_dss_supported_displays[] = {
  113. /* OMAP_DSS_CHANNEL_LCD */
  114. OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
  115. /* OMAP_DSS_CHANNEL_DIGIT */
  116. OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
  117. /* OMAP_DSS_CHANNEL_LCD2 */
  118. OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
  119. OMAP_DISPLAY_TYPE_DSI,
  120. };
  121. static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
  122. /* OMAP_DSS_GFX */
  123. OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
  124. OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
  125. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
  126. OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
  127. /* OMAP_DSS_VIDEO1 */
  128. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  129. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
  130. OMAP_DSS_COLOR_UYVY,
  131. /* OMAP_DSS_VIDEO2 */
  132. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  133. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
  134. OMAP_DSS_COLOR_UYVY,
  135. };
  136. static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
  137. /* OMAP_DSS_GFX */
  138. OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
  139. OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
  140. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
  141. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  142. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
  143. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
  144. /* OMAP_DSS_VIDEO1 */
  145. OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
  146. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
  147. OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
  148. /* OMAP_DSS_VIDEO2 */
  149. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
  150. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  151. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
  152. OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
  153. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
  154. };
  155. static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
  156. /* OMAP_DSS_GFX */
  157. OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
  158. OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
  159. OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
  160. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
  161. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
  162. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
  163. OMAP_DSS_COLOR_ARGB16_1555,
  164. /* OMAP_DSS_VIDEO1 */
  165. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
  166. OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
  167. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
  168. OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
  169. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
  170. OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
  171. OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
  172. OMAP_DSS_COLOR_RGBX32,
  173. /* OMAP_DSS_VIDEO2 */
  174. OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
  175. OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
  176. OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
  177. OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
  178. OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
  179. OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
  180. OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
  181. OMAP_DSS_COLOR_RGBX32,
  182. };
  183. static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
  184. /* OMAP_DSS_GFX */
  185. 0,
  186. /* OMAP_DSS_VIDEO1 */
  187. OMAP_DSS_OVL_CAP_SCALE,
  188. /* OMAP_DSS_VIDEO2 */
  189. OMAP_DSS_OVL_CAP_SCALE,
  190. };
  191. static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
  192. /* OMAP_DSS_GFX */
  193. OMAP_DSS_OVL_CAP_GLOBAL_ALPHA,
  194. /* OMAP_DSS_VIDEO1 */
  195. OMAP_DSS_OVL_CAP_SCALE,
  196. /* OMAP_DSS_VIDEO2 */
  197. OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA,
  198. };
  199. static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
  200. /* OMAP_DSS_GFX */
  201. OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
  202. /* OMAP_DSS_VIDEO1 */
  203. OMAP_DSS_OVL_CAP_SCALE,
  204. /* OMAP_DSS_VIDEO2 */
  205. OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
  206. OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
  207. };
  208. static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
  209. /* OMAP_DSS_GFX */
  210. OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
  211. /* OMAP_DSS_VIDEO1 */
  212. OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
  213. OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
  214. /* OMAP_DSS_VIDEO2 */
  215. OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
  216. OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
  217. };
  218. static const char * const omap2_dss_clk_source_names[] = {
  219. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
  220. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
  221. [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
  222. };
  223. static const char * const omap3_dss_clk_source_names[] = {
  224. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
  225. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
  226. [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
  227. };
  228. static const char * const omap4_dss_clk_source_names[] = {
  229. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
  230. [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
  231. [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
  232. [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
  233. [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
  234. };
  235. static const struct dss_param_range omap2_dss_param_range[] = {
  236. [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
  237. [FEAT_PARAM_DSS_PCD] = { 2, 255 },
  238. [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 },
  239. [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 },
  240. [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 },
  241. [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 },
  242. [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 },
  243. [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 },
  244. };
  245. static const struct dss_param_range omap3_dss_param_range[] = {
  246. [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
  247. [FEAT_PARAM_DSS_PCD] = { 1, 255 },
  248. [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 },
  249. [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 },
  250. [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 },
  251. [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 },
  252. [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 },
  253. [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
  254. };
  255. static const struct dss_param_range omap4_dss_param_range[] = {
  256. [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
  257. [FEAT_PARAM_DSS_PCD] = { 1, 255 },
  258. [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
  259. [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
  260. [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
  261. [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
  262. [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
  263. [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
  264. };
  265. /* OMAP2 DSS Features */
  266. static const struct omap_dss_features omap2_dss_features = {
  267. .reg_fields = omap2_dss_reg_fields,
  268. .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
  269. .has_feature =
  270. FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL |
  271. FEAT_PCKFREEENABLE | FEAT_FUNCGATED |
  272. FEAT_ROWREPEATENABLE | FEAT_RESIZECONF,
  273. .num_mgrs = 2,
  274. .num_ovls = 3,
  275. .supported_displays = omap2_dss_supported_displays,
  276. .supported_color_modes = omap2_dss_supported_color_modes,
  277. .overlay_caps = omap2_dss_overlay_caps,
  278. .clksrc_names = omap2_dss_clk_source_names,
  279. .dss_params = omap2_dss_param_range,
  280. .buffer_size_unit = 1,
  281. .burst_size_unit = 8,
  282. };
  283. /* OMAP3 DSS Features */
  284. static const struct omap_dss_features omap3430_dss_features = {
  285. .reg_fields = omap3_dss_reg_fields,
  286. .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
  287. .has_feature =
  288. FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
  289. FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
  290. FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
  291. FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
  292. FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC |
  293. FEAT_VENC_REQUIRES_TV_DAC_CLK | FEAT_CPR | FEAT_PRELOAD |
  294. FEAT_FIR_COEF_V,
  295. .num_mgrs = 2,
  296. .num_ovls = 3,
  297. .supported_displays = omap3430_dss_supported_displays,
  298. .supported_color_modes = omap3_dss_supported_color_modes,
  299. .overlay_caps = omap3430_dss_overlay_caps,
  300. .clksrc_names = omap3_dss_clk_source_names,
  301. .dss_params = omap3_dss_param_range,
  302. .buffer_size_unit = 1,
  303. .burst_size_unit = 8,
  304. };
  305. static const struct omap_dss_features omap3630_dss_features = {
  306. .reg_fields = omap3_dss_reg_fields,
  307. .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
  308. .has_feature =
  309. FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
  310. FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
  311. FEAT_FUNCGATED |
  312. FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
  313. FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |
  314. FEAT_DSI_PLL_FREQSEL | FEAT_CPR | FEAT_PRELOAD |
  315. FEAT_FIR_COEF_V,
  316. .num_mgrs = 2,
  317. .num_ovls = 3,
  318. .supported_displays = omap3630_dss_supported_displays,
  319. .supported_color_modes = omap3_dss_supported_color_modes,
  320. .overlay_caps = omap3630_dss_overlay_caps,
  321. .clksrc_names = omap3_dss_clk_source_names,
  322. .dss_params = omap3_dss_param_range,
  323. .buffer_size_unit = 1,
  324. .burst_size_unit = 8,
  325. };
  326. /* OMAP4 DSS Features */
  327. /* For OMAP4430 ES 1.0 revision */
  328. static const struct omap_dss_features omap4430_es1_0_dss_features = {
  329. .reg_fields = omap4_dss_reg_fields,
  330. .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
  331. .has_feature =
  332. FEAT_GLOBAL_ALPHA |
  333. FEAT_MGR_LCD2 |
  334. FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
  335. FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
  336. FEAT_DSI_GNQ | FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 |
  337. FEAT_CPR | FEAT_PRELOAD | FEAT_FIR_COEF_V,
  338. .num_mgrs = 3,
  339. .num_ovls = 3,
  340. .supported_displays = omap4_dss_supported_displays,
  341. .supported_color_modes = omap4_dss_supported_color_modes,
  342. .overlay_caps = omap4_dss_overlay_caps,
  343. .clksrc_names = omap4_dss_clk_source_names,
  344. .dss_params = omap4_dss_param_range,
  345. .buffer_size_unit = 16,
  346. .burst_size_unit = 16,
  347. };
  348. /* For all the other OMAP4 versions */
  349. static const struct omap_dss_features omap4_dss_features = {
  350. .reg_fields = omap4_dss_reg_fields,
  351. .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
  352. .has_feature =
  353. FEAT_GLOBAL_ALPHA |
  354. FEAT_MGR_LCD2 |
  355. FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
  356. FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
  357. FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE |
  358. FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 | FEAT_CPR |
  359. FEAT_PRELOAD | FEAT_FIR_COEF_V,
  360. .num_mgrs = 3,
  361. .num_ovls = 3,
  362. .supported_displays = omap4_dss_supported_displays,
  363. .supported_color_modes = omap4_dss_supported_color_modes,
  364. .overlay_caps = omap4_dss_overlay_caps,
  365. .clksrc_names = omap4_dss_clk_source_names,
  366. .dss_params = omap4_dss_param_range,
  367. .buffer_size_unit = 16,
  368. .burst_size_unit = 16,
  369. };
  370. #if defined(CONFIG_OMAP4_DSS_HDMI)
  371. /* HDMI OMAP4 Functions*/
  372. static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
  373. .video_configure = ti_hdmi_4xxx_basic_configure,
  374. .phy_enable = ti_hdmi_4xxx_phy_enable,
  375. .phy_disable = ti_hdmi_4xxx_phy_disable,
  376. .read_edid = ti_hdmi_4xxx_read_edid,
  377. .detect = ti_hdmi_4xxx_detect,
  378. .pll_enable = ti_hdmi_4xxx_pll_enable,
  379. .pll_disable = ti_hdmi_4xxx_pll_disable,
  380. .video_enable = ti_hdmi_4xxx_wp_video_start,
  381. };
  382. void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data)
  383. {
  384. if (cpu_is_omap44xx())
  385. ip_data->ops = &omap4_hdmi_functions;
  386. }
  387. #endif
  388. /* Functions returning values related to a DSS feature */
  389. int dss_feat_get_num_mgrs(void)
  390. {
  391. return omap_current_dss_features->num_mgrs;
  392. }
  393. int dss_feat_get_num_ovls(void)
  394. {
  395. return omap_current_dss_features->num_ovls;
  396. }
  397. unsigned long dss_feat_get_param_min(enum dss_range_param param)
  398. {
  399. return omap_current_dss_features->dss_params[param].min;
  400. }
  401. unsigned long dss_feat_get_param_max(enum dss_range_param param)
  402. {
  403. return omap_current_dss_features->dss_params[param].max;
  404. }
  405. enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
  406. {
  407. return omap_current_dss_features->supported_displays[channel];
  408. }
  409. enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
  410. {
  411. return omap_current_dss_features->supported_color_modes[plane];
  412. }
  413. enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
  414. {
  415. return omap_current_dss_features->overlay_caps[plane];
  416. }
  417. bool dss_feat_color_mode_supported(enum omap_plane plane,
  418. enum omap_color_mode color_mode)
  419. {
  420. return omap_current_dss_features->supported_color_modes[plane] &
  421. color_mode;
  422. }
  423. const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
  424. {
  425. return omap_current_dss_features->clksrc_names[id];
  426. }
  427. u32 dss_feat_get_buffer_size_unit(void)
  428. {
  429. return omap_current_dss_features->buffer_size_unit;
  430. }
  431. u32 dss_feat_get_burst_size_unit(void)
  432. {
  433. return omap_current_dss_features->burst_size_unit;
  434. }
  435. /* DSS has_feature check */
  436. bool dss_has_feature(enum dss_feat_id id)
  437. {
  438. return omap_current_dss_features->has_feature & id;
  439. }
  440. void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
  441. {
  442. if (id >= omap_current_dss_features->num_reg_fields)
  443. BUG();
  444. *start = omap_current_dss_features->reg_fields[id].start;
  445. *end = omap_current_dss_features->reg_fields[id].end;
  446. }
  447. void dss_features_init(void)
  448. {
  449. if (cpu_is_omap24xx())
  450. omap_current_dss_features = &omap2_dss_features;
  451. else if (cpu_is_omap3630())
  452. omap_current_dss_features = &omap3630_dss_features;
  453. else if (cpu_is_omap34xx())
  454. omap_current_dss_features = &omap3430_dss_features;
  455. else if (omap_rev() == OMAP4430_REV_ES1_0)
  456. omap_current_dss_features = &omap4430_es1_0_dss_features;
  457. else if (cpu_is_omap44xx())
  458. omap_current_dss_features = &omap4_dss_features;
  459. else
  460. DSSWARN("Unsupported OMAP version");
  461. }