smp.c 12 KB

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  1. /*
  2. * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
  3. *
  4. * Copyright 2007-2009 Analog Devices Inc.
  5. * Philippe Gerum <rpm@xenomai.org>
  6. *
  7. * Licensed under the GPL-2.
  8. */
  9. #include <linux/module.h>
  10. #include <linux/delay.h>
  11. #include <linux/init.h>
  12. #include <linux/spinlock.h>
  13. #include <linux/sched.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/cache.h>
  16. #include <linux/profile.h>
  17. #include <linux/errno.h>
  18. #include <linux/mm.h>
  19. #include <linux/cpu.h>
  20. #include <linux/smp.h>
  21. #include <linux/cpumask.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/irq.h>
  24. #include <linux/slab.h>
  25. #include <asm/atomic.h>
  26. #include <asm/cacheflush.h>
  27. #include <asm/mmu_context.h>
  28. #include <asm/pgtable.h>
  29. #include <asm/pgalloc.h>
  30. #include <asm/processor.h>
  31. #include <asm/ptrace.h>
  32. #include <asm/cpu.h>
  33. #include <asm/time.h>
  34. #include <linux/err.h>
  35. /*
  36. * Anomaly notes:
  37. * 05000120 - we always define corelock as 32-bit integer in L2
  38. */
  39. struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
  40. void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
  41. *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
  42. *init_saved_dcplb_fault_addr_coreb;
  43. #define BFIN_IPI_RESCHEDULE 0
  44. #define BFIN_IPI_CALL_FUNC 1
  45. #define BFIN_IPI_CPU_STOP 2
  46. struct blackfin_flush_data {
  47. unsigned long start;
  48. unsigned long end;
  49. };
  50. void *secondary_stack;
  51. struct smp_call_struct {
  52. void (*func)(void *info);
  53. void *info;
  54. int wait;
  55. cpumask_t pending;
  56. cpumask_t waitmask;
  57. };
  58. static struct blackfin_flush_data smp_flush_data;
  59. static DEFINE_SPINLOCK(stop_lock);
  60. struct ipi_message {
  61. struct list_head list;
  62. unsigned long type;
  63. struct smp_call_struct call_struct;
  64. };
  65. struct ipi_message_queue {
  66. struct list_head head;
  67. spinlock_t lock;
  68. unsigned long count;
  69. };
  70. static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
  71. static void ipi_cpu_stop(unsigned int cpu)
  72. {
  73. spin_lock(&stop_lock);
  74. printk(KERN_CRIT "CPU%u: stopping\n", cpu);
  75. dump_stack();
  76. spin_unlock(&stop_lock);
  77. cpu_clear(cpu, cpu_online_map);
  78. local_irq_disable();
  79. while (1)
  80. SSYNC();
  81. }
  82. static void ipi_flush_icache(void *info)
  83. {
  84. struct blackfin_flush_data *fdata = info;
  85. /* Invalidate the memory holding the bounds of the flushed region. */
  86. blackfin_dcache_invalidate_range((unsigned long)fdata,
  87. (unsigned long)fdata + sizeof(*fdata));
  88. blackfin_icache_flush_range(fdata->start, fdata->end);
  89. }
  90. static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
  91. {
  92. int wait;
  93. void (*func)(void *info);
  94. void *info;
  95. func = msg->call_struct.func;
  96. info = msg->call_struct.info;
  97. wait = msg->call_struct.wait;
  98. cpu_clear(cpu, msg->call_struct.pending);
  99. func(info);
  100. if (wait) {
  101. #ifdef __ARCH_SYNC_CORE_DCACHE
  102. /*
  103. * 'wait' usually means synchronization between CPUs.
  104. * Invalidate D cache in case shared data was changed
  105. * by func() to ensure cache coherence.
  106. */
  107. resync_core_dcache();
  108. #endif
  109. cpu_clear(cpu, msg->call_struct.waitmask);
  110. } else
  111. kfree(msg);
  112. }
  113. static irqreturn_t ipi_handler(int irq, void *dev_instance)
  114. {
  115. struct ipi_message *msg;
  116. struct ipi_message_queue *msg_queue;
  117. unsigned int cpu = smp_processor_id();
  118. platform_clear_ipi(cpu);
  119. msg_queue = &__get_cpu_var(ipi_msg_queue);
  120. msg_queue->count++;
  121. spin_lock(&msg_queue->lock);
  122. while (!list_empty(&msg_queue->head)) {
  123. msg = list_entry(msg_queue->head.next, typeof(*msg), list);
  124. list_del(&msg->list);
  125. switch (msg->type) {
  126. case BFIN_IPI_RESCHEDULE:
  127. /* That's the easiest one; leave it to
  128. * return_from_int. */
  129. kfree(msg);
  130. break;
  131. case BFIN_IPI_CALL_FUNC:
  132. spin_unlock(&msg_queue->lock);
  133. ipi_call_function(cpu, msg);
  134. spin_lock(&msg_queue->lock);
  135. break;
  136. case BFIN_IPI_CPU_STOP:
  137. spin_unlock(&msg_queue->lock);
  138. ipi_cpu_stop(cpu);
  139. spin_lock(&msg_queue->lock);
  140. kfree(msg);
  141. break;
  142. default:
  143. printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
  144. cpu, msg->type);
  145. kfree(msg);
  146. break;
  147. }
  148. }
  149. spin_unlock(&msg_queue->lock);
  150. return IRQ_HANDLED;
  151. }
  152. static void ipi_queue_init(void)
  153. {
  154. unsigned int cpu;
  155. struct ipi_message_queue *msg_queue;
  156. for_each_possible_cpu(cpu) {
  157. msg_queue = &per_cpu(ipi_msg_queue, cpu);
  158. INIT_LIST_HEAD(&msg_queue->head);
  159. spin_lock_init(&msg_queue->lock);
  160. msg_queue->count = 0;
  161. }
  162. }
  163. int smp_call_function(void (*func)(void *info), void *info, int wait)
  164. {
  165. unsigned int cpu;
  166. cpumask_t callmap;
  167. unsigned long flags;
  168. struct ipi_message_queue *msg_queue;
  169. struct ipi_message *msg;
  170. callmap = cpu_online_map;
  171. cpu_clear(smp_processor_id(), callmap);
  172. if (cpus_empty(callmap))
  173. return 0;
  174. msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
  175. if (!msg)
  176. return -ENOMEM;
  177. INIT_LIST_HEAD(&msg->list);
  178. msg->call_struct.func = func;
  179. msg->call_struct.info = info;
  180. msg->call_struct.wait = wait;
  181. msg->call_struct.pending = callmap;
  182. msg->call_struct.waitmask = callmap;
  183. msg->type = BFIN_IPI_CALL_FUNC;
  184. for_each_cpu_mask(cpu, callmap) {
  185. msg_queue = &per_cpu(ipi_msg_queue, cpu);
  186. spin_lock_irqsave(&msg_queue->lock, flags);
  187. list_add_tail(&msg->list, &msg_queue->head);
  188. spin_unlock_irqrestore(&msg_queue->lock, flags);
  189. platform_send_ipi_cpu(cpu);
  190. }
  191. if (wait) {
  192. while (!cpus_empty(msg->call_struct.waitmask))
  193. blackfin_dcache_invalidate_range(
  194. (unsigned long)(&msg->call_struct.waitmask),
  195. (unsigned long)(&msg->call_struct.waitmask));
  196. #ifdef __ARCH_SYNC_CORE_DCACHE
  197. /*
  198. * Invalidate D cache in case shared data was changed by
  199. * other processors to ensure cache coherence.
  200. */
  201. resync_core_dcache();
  202. #endif
  203. kfree(msg);
  204. }
  205. return 0;
  206. }
  207. EXPORT_SYMBOL_GPL(smp_call_function);
  208. int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
  209. int wait)
  210. {
  211. unsigned int cpu = cpuid;
  212. cpumask_t callmap;
  213. unsigned long flags;
  214. struct ipi_message_queue *msg_queue;
  215. struct ipi_message *msg;
  216. if (cpu_is_offline(cpu))
  217. return 0;
  218. cpus_clear(callmap);
  219. cpu_set(cpu, callmap);
  220. msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
  221. if (!msg)
  222. return -ENOMEM;
  223. INIT_LIST_HEAD(&msg->list);
  224. msg->call_struct.func = func;
  225. msg->call_struct.info = info;
  226. msg->call_struct.wait = wait;
  227. msg->call_struct.pending = callmap;
  228. msg->call_struct.waitmask = callmap;
  229. msg->type = BFIN_IPI_CALL_FUNC;
  230. msg_queue = &per_cpu(ipi_msg_queue, cpu);
  231. spin_lock_irqsave(&msg_queue->lock, flags);
  232. list_add_tail(&msg->list, &msg_queue->head);
  233. spin_unlock_irqrestore(&msg_queue->lock, flags);
  234. platform_send_ipi_cpu(cpu);
  235. if (wait) {
  236. while (!cpus_empty(msg->call_struct.waitmask))
  237. blackfin_dcache_invalidate_range(
  238. (unsigned long)(&msg->call_struct.waitmask),
  239. (unsigned long)(&msg->call_struct.waitmask));
  240. #ifdef __ARCH_SYNC_CORE_DCACHE
  241. /*
  242. * Invalidate D cache in case shared data was changed by
  243. * other processors to ensure cache coherence.
  244. */
  245. resync_core_dcache();
  246. #endif
  247. kfree(msg);
  248. }
  249. return 0;
  250. }
  251. EXPORT_SYMBOL_GPL(smp_call_function_single);
  252. void smp_send_reschedule(int cpu)
  253. {
  254. unsigned long flags;
  255. struct ipi_message_queue *msg_queue;
  256. struct ipi_message *msg;
  257. if (cpu_is_offline(cpu))
  258. return;
  259. msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
  260. if (!msg)
  261. return;
  262. INIT_LIST_HEAD(&msg->list);
  263. msg->type = BFIN_IPI_RESCHEDULE;
  264. msg_queue = &per_cpu(ipi_msg_queue, cpu);
  265. spin_lock_irqsave(&msg_queue->lock, flags);
  266. list_add_tail(&msg->list, &msg_queue->head);
  267. spin_unlock_irqrestore(&msg_queue->lock, flags);
  268. platform_send_ipi_cpu(cpu);
  269. return;
  270. }
  271. void smp_send_stop(void)
  272. {
  273. unsigned int cpu;
  274. cpumask_t callmap;
  275. unsigned long flags;
  276. struct ipi_message_queue *msg_queue;
  277. struct ipi_message *msg;
  278. callmap = cpu_online_map;
  279. cpu_clear(smp_processor_id(), callmap);
  280. if (cpus_empty(callmap))
  281. return;
  282. msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
  283. if (!msg)
  284. return;
  285. INIT_LIST_HEAD(&msg->list);
  286. msg->type = BFIN_IPI_CPU_STOP;
  287. for_each_cpu_mask(cpu, callmap) {
  288. msg_queue = &per_cpu(ipi_msg_queue, cpu);
  289. spin_lock_irqsave(&msg_queue->lock, flags);
  290. list_add_tail(&msg->list, &msg_queue->head);
  291. spin_unlock_irqrestore(&msg_queue->lock, flags);
  292. platform_send_ipi_cpu(cpu);
  293. }
  294. return;
  295. }
  296. int __cpuinit __cpu_up(unsigned int cpu)
  297. {
  298. int ret;
  299. static struct task_struct *idle;
  300. if (idle)
  301. free_task(idle);
  302. idle = fork_idle(cpu);
  303. if (IS_ERR(idle)) {
  304. printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
  305. return PTR_ERR(idle);
  306. }
  307. secondary_stack = task_stack_page(idle) + THREAD_SIZE;
  308. ret = platform_boot_secondary(cpu, idle);
  309. secondary_stack = NULL;
  310. return ret;
  311. }
  312. static void __cpuinit setup_secondary(unsigned int cpu)
  313. {
  314. unsigned long ilat;
  315. bfin_write_IMASK(0);
  316. CSYNC();
  317. ilat = bfin_read_ILAT();
  318. CSYNC();
  319. bfin_write_ILAT(ilat);
  320. CSYNC();
  321. /* Enable interrupt levels IVG7-15. IARs have been already
  322. * programmed by the boot CPU. */
  323. bfin_irq_flags |= IMASK_IVG15 |
  324. IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
  325. IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
  326. }
  327. void __cpuinit secondary_start_kernel(void)
  328. {
  329. unsigned int cpu = smp_processor_id();
  330. struct mm_struct *mm = &init_mm;
  331. if (_bfin_swrst & SWRST_DBL_FAULT_B) {
  332. printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
  333. #ifdef CONFIG_DEBUG_DOUBLEFAULT
  334. printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
  335. (int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
  336. printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
  337. printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
  338. #endif
  339. printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
  340. init_retx_coreb);
  341. }
  342. /*
  343. * We want the D-cache to be enabled early, in case the atomic
  344. * support code emulates cache coherence (see
  345. * __ARCH_SYNC_CORE_DCACHE).
  346. */
  347. init_exception_vectors();
  348. bfin_setup_caches(cpu);
  349. local_irq_disable();
  350. /* Attach the new idle task to the global mm. */
  351. atomic_inc(&mm->mm_users);
  352. atomic_inc(&mm->mm_count);
  353. current->active_mm = mm;
  354. preempt_disable();
  355. setup_secondary(cpu);
  356. platform_secondary_init(cpu);
  357. /* setup local core timer */
  358. bfin_local_timer_setup();
  359. local_irq_enable();
  360. /*
  361. * Calibrate loops per jiffy value.
  362. * IRQs need to be enabled here - D-cache can be invalidated
  363. * in timer irq handler, so core B can read correct jiffies.
  364. */
  365. calibrate_delay();
  366. cpu_idle();
  367. }
  368. void __init smp_prepare_boot_cpu(void)
  369. {
  370. }
  371. void __init smp_prepare_cpus(unsigned int max_cpus)
  372. {
  373. platform_prepare_cpus(max_cpus);
  374. ipi_queue_init();
  375. platform_request_ipi(ipi_handler);
  376. }
  377. void __init smp_cpus_done(unsigned int max_cpus)
  378. {
  379. unsigned long bogosum = 0;
  380. unsigned int cpu;
  381. for_each_online_cpu(cpu)
  382. bogosum += loops_per_jiffy;
  383. printk(KERN_INFO "SMP: Total of %d processors activated "
  384. "(%lu.%02lu BogoMIPS).\n",
  385. num_online_cpus(),
  386. bogosum / (500000/HZ),
  387. (bogosum / (5000/HZ)) % 100);
  388. }
  389. void smp_icache_flush_range_others(unsigned long start, unsigned long end)
  390. {
  391. smp_flush_data.start = start;
  392. smp_flush_data.end = end;
  393. if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
  394. printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
  395. }
  396. EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
  397. #ifdef __ARCH_SYNC_CORE_ICACHE
  398. unsigned long icache_invld_count[NR_CPUS];
  399. void resync_core_icache(void)
  400. {
  401. unsigned int cpu = get_cpu();
  402. blackfin_invalidate_entire_icache();
  403. icache_invld_count[cpu]++;
  404. put_cpu();
  405. }
  406. EXPORT_SYMBOL(resync_core_icache);
  407. #endif
  408. #ifdef __ARCH_SYNC_CORE_DCACHE
  409. unsigned long dcache_invld_count[NR_CPUS];
  410. unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
  411. void resync_core_dcache(void)
  412. {
  413. unsigned int cpu = get_cpu();
  414. blackfin_invalidate_entire_dcache();
  415. dcache_invld_count[cpu]++;
  416. put_cpu();
  417. }
  418. EXPORT_SYMBOL(resync_core_dcache);
  419. #endif
  420. #ifdef CONFIG_HOTPLUG_CPU
  421. int __cpuexit __cpu_disable(void)
  422. {
  423. unsigned int cpu = smp_processor_id();
  424. if (cpu == 0)
  425. return -EPERM;
  426. set_cpu_online(cpu, false);
  427. return 0;
  428. }
  429. static DECLARE_COMPLETION(cpu_killed);
  430. int __cpuexit __cpu_die(unsigned int cpu)
  431. {
  432. return wait_for_completion_timeout(&cpu_killed, 5000);
  433. }
  434. void cpu_die(void)
  435. {
  436. complete(&cpu_killed);
  437. atomic_dec(&init_mm.mm_users);
  438. atomic_dec(&init_mm.mm_count);
  439. local_irq_disable();
  440. platform_cpu_die();
  441. }
  442. #endif