rv770.c 32 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/firmware.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "radeon.h"
  33. #include "radeon_asic.h"
  34. #include "radeon_drm.h"
  35. #include "rv770d.h"
  36. #include "atom.h"
  37. #include "avivod.h"
  38. #define R700_PFP_UCODE_SIZE 848
  39. #define R700_PM4_UCODE_SIZE 1360
  40. static void rv770_gpu_init(struct radeon_device *rdev);
  41. void rv770_fini(struct radeon_device *rdev);
  42. /*
  43. * GART
  44. */
  45. int rv770_pcie_gart_enable(struct radeon_device *rdev)
  46. {
  47. u32 tmp;
  48. int r, i;
  49. if (rdev->gart.table.vram.robj == NULL) {
  50. dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  51. return -EINVAL;
  52. }
  53. r = radeon_gart_table_vram_pin(rdev);
  54. if (r)
  55. return r;
  56. radeon_gart_restore(rdev);
  57. /* Setup L2 cache */
  58. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  59. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  60. EFFECTIVE_L2_QUEUE_SIZE(7));
  61. WREG32(VM_L2_CNTL2, 0);
  62. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  63. /* Setup TLB control */
  64. tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  65. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  66. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  67. EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  68. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  69. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  70. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  71. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  72. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  73. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  74. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  75. WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  76. WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
  77. WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  78. WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  79. RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
  80. WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  81. (u32)(rdev->dummy_page.addr >> 12));
  82. for (i = 1; i < 7; i++)
  83. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  84. r600_pcie_gart_tlb_flush(rdev);
  85. rdev->gart.ready = true;
  86. return 0;
  87. }
  88. void rv770_pcie_gart_disable(struct radeon_device *rdev)
  89. {
  90. u32 tmp;
  91. int i, r;
  92. /* Disable all tables */
  93. for (i = 0; i < 7; i++)
  94. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  95. /* Setup L2 cache */
  96. WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
  97. EFFECTIVE_L2_QUEUE_SIZE(7));
  98. WREG32(VM_L2_CNTL2, 0);
  99. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  100. /* Setup TLB control */
  101. tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  102. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  103. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  104. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  105. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  106. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  107. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  108. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  109. if (rdev->gart.table.vram.robj) {
  110. r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  111. if (likely(r == 0)) {
  112. radeon_bo_kunmap(rdev->gart.table.vram.robj);
  113. radeon_bo_unpin(rdev->gart.table.vram.robj);
  114. radeon_bo_unreserve(rdev->gart.table.vram.robj);
  115. }
  116. }
  117. }
  118. void rv770_pcie_gart_fini(struct radeon_device *rdev)
  119. {
  120. radeon_gart_fini(rdev);
  121. rv770_pcie_gart_disable(rdev);
  122. radeon_gart_table_vram_free(rdev);
  123. }
  124. void rv770_agp_enable(struct radeon_device *rdev)
  125. {
  126. u32 tmp;
  127. int i;
  128. /* Setup L2 cache */
  129. WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  130. ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  131. EFFECTIVE_L2_QUEUE_SIZE(7));
  132. WREG32(VM_L2_CNTL2, 0);
  133. WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  134. /* Setup TLB control */
  135. tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  136. SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  137. SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  138. EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  139. WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  140. WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  141. WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  142. WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  143. WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  144. WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  145. WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  146. for (i = 0; i < 7; i++)
  147. WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  148. }
  149. static void rv770_mc_program(struct radeon_device *rdev)
  150. {
  151. struct rv515_mc_save save;
  152. u32 tmp;
  153. int i, j;
  154. /* Initialize HDP */
  155. for (i = 0, j = 0; i < 32; i++, j += 0x18) {
  156. WREG32((0x2c14 + j), 0x00000000);
  157. WREG32((0x2c18 + j), 0x00000000);
  158. WREG32((0x2c1c + j), 0x00000000);
  159. WREG32((0x2c20 + j), 0x00000000);
  160. WREG32((0x2c24 + j), 0x00000000);
  161. }
  162. WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
  163. rv515_mc_stop(rdev, &save);
  164. if (r600_mc_wait_for_idle(rdev)) {
  165. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  166. }
  167. /* Lockout access through VGA aperture*/
  168. WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
  169. /* Update configuration */
  170. if (rdev->flags & RADEON_IS_AGP) {
  171. if (rdev->mc.vram_start < rdev->mc.gtt_start) {
  172. /* VRAM before AGP */
  173. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  174. rdev->mc.vram_start >> 12);
  175. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  176. rdev->mc.gtt_end >> 12);
  177. } else {
  178. /* VRAM after AGP */
  179. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  180. rdev->mc.gtt_start >> 12);
  181. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  182. rdev->mc.vram_end >> 12);
  183. }
  184. } else {
  185. WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
  186. rdev->mc.vram_start >> 12);
  187. WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  188. rdev->mc.vram_end >> 12);
  189. }
  190. WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
  191. tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
  192. tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
  193. WREG32(MC_VM_FB_LOCATION, tmp);
  194. WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
  195. WREG32(HDP_NONSURFACE_INFO, (2 << 7));
  196. WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
  197. if (rdev->flags & RADEON_IS_AGP) {
  198. WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
  199. WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
  200. WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
  201. } else {
  202. WREG32(MC_VM_AGP_BASE, 0);
  203. WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
  204. WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
  205. }
  206. if (r600_mc_wait_for_idle(rdev)) {
  207. dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
  208. }
  209. rv515_mc_resume(rdev, &save);
  210. /* we need to own VRAM, so turn off the VGA renderer here
  211. * to stop it overwriting our objects */
  212. rv515_vga_render_disable(rdev);
  213. }
  214. /*
  215. * CP.
  216. */
  217. void r700_cp_stop(struct radeon_device *rdev)
  218. {
  219. WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
  220. }
  221. static int rv770_cp_load_microcode(struct radeon_device *rdev)
  222. {
  223. const __be32 *fw_data;
  224. int i;
  225. if (!rdev->me_fw || !rdev->pfp_fw)
  226. return -EINVAL;
  227. r700_cp_stop(rdev);
  228. WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
  229. /* Reset cp */
  230. WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
  231. RREG32(GRBM_SOFT_RESET);
  232. mdelay(15);
  233. WREG32(GRBM_SOFT_RESET, 0);
  234. fw_data = (const __be32 *)rdev->pfp_fw->data;
  235. WREG32(CP_PFP_UCODE_ADDR, 0);
  236. for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
  237. WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
  238. WREG32(CP_PFP_UCODE_ADDR, 0);
  239. fw_data = (const __be32 *)rdev->me_fw->data;
  240. WREG32(CP_ME_RAM_WADDR, 0);
  241. for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
  242. WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
  243. WREG32(CP_PFP_UCODE_ADDR, 0);
  244. WREG32(CP_ME_RAM_WADDR, 0);
  245. WREG32(CP_ME_RAM_RADDR, 0);
  246. return 0;
  247. }
  248. void r700_cp_fini(struct radeon_device *rdev)
  249. {
  250. r700_cp_stop(rdev);
  251. radeon_ring_fini(rdev);
  252. }
  253. /*
  254. * Core functions
  255. */
  256. static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
  257. u32 num_tile_pipes,
  258. u32 num_backends,
  259. u32 backend_disable_mask)
  260. {
  261. u32 backend_map = 0;
  262. u32 enabled_backends_mask;
  263. u32 enabled_backends_count;
  264. u32 cur_pipe;
  265. u32 swizzle_pipe[R7XX_MAX_PIPES];
  266. u32 cur_backend;
  267. u32 i;
  268. bool force_no_swizzle;
  269. if (num_tile_pipes > R7XX_MAX_PIPES)
  270. num_tile_pipes = R7XX_MAX_PIPES;
  271. if (num_tile_pipes < 1)
  272. num_tile_pipes = 1;
  273. if (num_backends > R7XX_MAX_BACKENDS)
  274. num_backends = R7XX_MAX_BACKENDS;
  275. if (num_backends < 1)
  276. num_backends = 1;
  277. enabled_backends_mask = 0;
  278. enabled_backends_count = 0;
  279. for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
  280. if (((backend_disable_mask >> i) & 1) == 0) {
  281. enabled_backends_mask |= (1 << i);
  282. ++enabled_backends_count;
  283. }
  284. if (enabled_backends_count == num_backends)
  285. break;
  286. }
  287. if (enabled_backends_count == 0) {
  288. enabled_backends_mask = 1;
  289. enabled_backends_count = 1;
  290. }
  291. if (enabled_backends_count != num_backends)
  292. num_backends = enabled_backends_count;
  293. switch (rdev->family) {
  294. case CHIP_RV770:
  295. case CHIP_RV730:
  296. force_no_swizzle = false;
  297. break;
  298. case CHIP_RV710:
  299. case CHIP_RV740:
  300. default:
  301. force_no_swizzle = true;
  302. break;
  303. }
  304. memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
  305. switch (num_tile_pipes) {
  306. case 1:
  307. swizzle_pipe[0] = 0;
  308. break;
  309. case 2:
  310. swizzle_pipe[0] = 0;
  311. swizzle_pipe[1] = 1;
  312. break;
  313. case 3:
  314. if (force_no_swizzle) {
  315. swizzle_pipe[0] = 0;
  316. swizzle_pipe[1] = 1;
  317. swizzle_pipe[2] = 2;
  318. } else {
  319. swizzle_pipe[0] = 0;
  320. swizzle_pipe[1] = 2;
  321. swizzle_pipe[2] = 1;
  322. }
  323. break;
  324. case 4:
  325. if (force_no_swizzle) {
  326. swizzle_pipe[0] = 0;
  327. swizzle_pipe[1] = 1;
  328. swizzle_pipe[2] = 2;
  329. swizzle_pipe[3] = 3;
  330. } else {
  331. swizzle_pipe[0] = 0;
  332. swizzle_pipe[1] = 2;
  333. swizzle_pipe[2] = 3;
  334. swizzle_pipe[3] = 1;
  335. }
  336. break;
  337. case 5:
  338. if (force_no_swizzle) {
  339. swizzle_pipe[0] = 0;
  340. swizzle_pipe[1] = 1;
  341. swizzle_pipe[2] = 2;
  342. swizzle_pipe[3] = 3;
  343. swizzle_pipe[4] = 4;
  344. } else {
  345. swizzle_pipe[0] = 0;
  346. swizzle_pipe[1] = 2;
  347. swizzle_pipe[2] = 4;
  348. swizzle_pipe[3] = 1;
  349. swizzle_pipe[4] = 3;
  350. }
  351. break;
  352. case 6:
  353. if (force_no_swizzle) {
  354. swizzle_pipe[0] = 0;
  355. swizzle_pipe[1] = 1;
  356. swizzle_pipe[2] = 2;
  357. swizzle_pipe[3] = 3;
  358. swizzle_pipe[4] = 4;
  359. swizzle_pipe[5] = 5;
  360. } else {
  361. swizzle_pipe[0] = 0;
  362. swizzle_pipe[1] = 2;
  363. swizzle_pipe[2] = 4;
  364. swizzle_pipe[3] = 5;
  365. swizzle_pipe[4] = 3;
  366. swizzle_pipe[5] = 1;
  367. }
  368. break;
  369. case 7:
  370. if (force_no_swizzle) {
  371. swizzle_pipe[0] = 0;
  372. swizzle_pipe[1] = 1;
  373. swizzle_pipe[2] = 2;
  374. swizzle_pipe[3] = 3;
  375. swizzle_pipe[4] = 4;
  376. swizzle_pipe[5] = 5;
  377. swizzle_pipe[6] = 6;
  378. } else {
  379. swizzle_pipe[0] = 0;
  380. swizzle_pipe[1] = 2;
  381. swizzle_pipe[2] = 4;
  382. swizzle_pipe[3] = 6;
  383. swizzle_pipe[4] = 3;
  384. swizzle_pipe[5] = 1;
  385. swizzle_pipe[6] = 5;
  386. }
  387. break;
  388. case 8:
  389. if (force_no_swizzle) {
  390. swizzle_pipe[0] = 0;
  391. swizzle_pipe[1] = 1;
  392. swizzle_pipe[2] = 2;
  393. swizzle_pipe[3] = 3;
  394. swizzle_pipe[4] = 4;
  395. swizzle_pipe[5] = 5;
  396. swizzle_pipe[6] = 6;
  397. swizzle_pipe[7] = 7;
  398. } else {
  399. swizzle_pipe[0] = 0;
  400. swizzle_pipe[1] = 2;
  401. swizzle_pipe[2] = 4;
  402. swizzle_pipe[3] = 6;
  403. swizzle_pipe[4] = 3;
  404. swizzle_pipe[5] = 1;
  405. swizzle_pipe[6] = 7;
  406. swizzle_pipe[7] = 5;
  407. }
  408. break;
  409. }
  410. cur_backend = 0;
  411. for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
  412. while (((1 << cur_backend) & enabled_backends_mask) == 0)
  413. cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
  414. backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
  415. cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
  416. }
  417. return backend_map;
  418. }
  419. static void rv770_gpu_init(struct radeon_device *rdev)
  420. {
  421. int i, j, num_qd_pipes;
  422. u32 ta_aux_cntl;
  423. u32 sx_debug_1;
  424. u32 smx_dc_ctl0;
  425. u32 db_debug3;
  426. u32 num_gs_verts_per_thread;
  427. u32 vgt_gs_per_es;
  428. u32 gs_prim_buffer_depth = 0;
  429. u32 sq_ms_fifo_sizes;
  430. u32 sq_config;
  431. u32 sq_thread_resource_mgmt;
  432. u32 hdp_host_path_cntl;
  433. u32 sq_dyn_gpr_size_simd_ab_0;
  434. u32 backend_map;
  435. u32 gb_tiling_config = 0;
  436. u32 cc_rb_backend_disable = 0;
  437. u32 cc_gc_shader_pipe_config = 0;
  438. u32 mc_arb_ramcfg;
  439. u32 db_debug4;
  440. /* setup chip specs */
  441. switch (rdev->family) {
  442. case CHIP_RV770:
  443. rdev->config.rv770.max_pipes = 4;
  444. rdev->config.rv770.max_tile_pipes = 8;
  445. rdev->config.rv770.max_simds = 10;
  446. rdev->config.rv770.max_backends = 4;
  447. rdev->config.rv770.max_gprs = 256;
  448. rdev->config.rv770.max_threads = 248;
  449. rdev->config.rv770.max_stack_entries = 512;
  450. rdev->config.rv770.max_hw_contexts = 8;
  451. rdev->config.rv770.max_gs_threads = 16 * 2;
  452. rdev->config.rv770.sx_max_export_size = 128;
  453. rdev->config.rv770.sx_max_export_pos_size = 16;
  454. rdev->config.rv770.sx_max_export_smx_size = 112;
  455. rdev->config.rv770.sq_num_cf_insts = 2;
  456. rdev->config.rv770.sx_num_of_sets = 7;
  457. rdev->config.rv770.sc_prim_fifo_size = 0xF9;
  458. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  459. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  460. break;
  461. case CHIP_RV730:
  462. rdev->config.rv770.max_pipes = 2;
  463. rdev->config.rv770.max_tile_pipes = 4;
  464. rdev->config.rv770.max_simds = 8;
  465. rdev->config.rv770.max_backends = 2;
  466. rdev->config.rv770.max_gprs = 128;
  467. rdev->config.rv770.max_threads = 248;
  468. rdev->config.rv770.max_stack_entries = 256;
  469. rdev->config.rv770.max_hw_contexts = 8;
  470. rdev->config.rv770.max_gs_threads = 16 * 2;
  471. rdev->config.rv770.sx_max_export_size = 256;
  472. rdev->config.rv770.sx_max_export_pos_size = 32;
  473. rdev->config.rv770.sx_max_export_smx_size = 224;
  474. rdev->config.rv770.sq_num_cf_insts = 2;
  475. rdev->config.rv770.sx_num_of_sets = 7;
  476. rdev->config.rv770.sc_prim_fifo_size = 0xf9;
  477. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  478. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  479. if (rdev->config.rv770.sx_max_export_pos_size > 16) {
  480. rdev->config.rv770.sx_max_export_pos_size -= 16;
  481. rdev->config.rv770.sx_max_export_smx_size += 16;
  482. }
  483. break;
  484. case CHIP_RV710:
  485. rdev->config.rv770.max_pipes = 2;
  486. rdev->config.rv770.max_tile_pipes = 2;
  487. rdev->config.rv770.max_simds = 2;
  488. rdev->config.rv770.max_backends = 1;
  489. rdev->config.rv770.max_gprs = 256;
  490. rdev->config.rv770.max_threads = 192;
  491. rdev->config.rv770.max_stack_entries = 256;
  492. rdev->config.rv770.max_hw_contexts = 4;
  493. rdev->config.rv770.max_gs_threads = 8 * 2;
  494. rdev->config.rv770.sx_max_export_size = 128;
  495. rdev->config.rv770.sx_max_export_pos_size = 16;
  496. rdev->config.rv770.sx_max_export_smx_size = 112;
  497. rdev->config.rv770.sq_num_cf_insts = 1;
  498. rdev->config.rv770.sx_num_of_sets = 7;
  499. rdev->config.rv770.sc_prim_fifo_size = 0x40;
  500. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  501. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  502. break;
  503. case CHIP_RV740:
  504. rdev->config.rv770.max_pipes = 4;
  505. rdev->config.rv770.max_tile_pipes = 4;
  506. rdev->config.rv770.max_simds = 8;
  507. rdev->config.rv770.max_backends = 4;
  508. rdev->config.rv770.max_gprs = 256;
  509. rdev->config.rv770.max_threads = 248;
  510. rdev->config.rv770.max_stack_entries = 512;
  511. rdev->config.rv770.max_hw_contexts = 8;
  512. rdev->config.rv770.max_gs_threads = 16 * 2;
  513. rdev->config.rv770.sx_max_export_size = 256;
  514. rdev->config.rv770.sx_max_export_pos_size = 32;
  515. rdev->config.rv770.sx_max_export_smx_size = 224;
  516. rdev->config.rv770.sq_num_cf_insts = 2;
  517. rdev->config.rv770.sx_num_of_sets = 7;
  518. rdev->config.rv770.sc_prim_fifo_size = 0x100;
  519. rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
  520. rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
  521. if (rdev->config.rv770.sx_max_export_pos_size > 16) {
  522. rdev->config.rv770.sx_max_export_pos_size -= 16;
  523. rdev->config.rv770.sx_max_export_smx_size += 16;
  524. }
  525. break;
  526. default:
  527. break;
  528. }
  529. /* Initialize HDP */
  530. j = 0;
  531. for (i = 0; i < 32; i++) {
  532. WREG32((0x2c14 + j), 0x00000000);
  533. WREG32((0x2c18 + j), 0x00000000);
  534. WREG32((0x2c1c + j), 0x00000000);
  535. WREG32((0x2c20 + j), 0x00000000);
  536. WREG32((0x2c24 + j), 0x00000000);
  537. j += 0x18;
  538. }
  539. WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
  540. /* setup tiling, simd, pipe config */
  541. mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
  542. switch (rdev->config.rv770.max_tile_pipes) {
  543. case 1:
  544. default:
  545. gb_tiling_config |= PIPE_TILING(0);
  546. break;
  547. case 2:
  548. gb_tiling_config |= PIPE_TILING(1);
  549. break;
  550. case 4:
  551. gb_tiling_config |= PIPE_TILING(2);
  552. break;
  553. case 8:
  554. gb_tiling_config |= PIPE_TILING(3);
  555. break;
  556. }
  557. rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
  558. if (rdev->family == CHIP_RV770)
  559. gb_tiling_config |= BANK_TILING(1);
  560. else
  561. gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
  562. rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
  563. gb_tiling_config |= GROUP_SIZE(0);
  564. rdev->config.rv770.tiling_group_size = 256;
  565. if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
  566. gb_tiling_config |= ROW_TILING(3);
  567. gb_tiling_config |= SAMPLE_SPLIT(3);
  568. } else {
  569. gb_tiling_config |=
  570. ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
  571. gb_tiling_config |=
  572. SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
  573. }
  574. gb_tiling_config |= BANK_SWAPS(1);
  575. cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
  576. cc_rb_backend_disable |=
  577. BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
  578. cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
  579. cc_gc_shader_pipe_config |=
  580. INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
  581. cc_gc_shader_pipe_config |=
  582. INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
  583. if (rdev->family == CHIP_RV740)
  584. backend_map = 0x28;
  585. else
  586. backend_map = r700_get_tile_pipe_to_backend_map(rdev,
  587. rdev->config.rv770.max_tile_pipes,
  588. (R7XX_MAX_BACKENDS -
  589. r600_count_pipe_bits((cc_rb_backend_disable &
  590. R7XX_MAX_BACKENDS_MASK) >> 16)),
  591. (cc_rb_backend_disable >> 16));
  592. gb_tiling_config |= BACKEND_MAP(backend_map);
  593. WREG32(GB_TILING_CONFIG, gb_tiling_config);
  594. WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
  595. WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
  596. WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
  597. WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
  598. WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
  599. WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
  600. WREG32(CGTS_SYS_TCC_DISABLE, 0);
  601. WREG32(CGTS_TCC_DISABLE, 0);
  602. WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
  603. WREG32(CGTS_USER_TCC_DISABLE, 0);
  604. num_qd_pipes =
  605. R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
  606. WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
  607. WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
  608. /* set HW defaults for 3D engine */
  609. WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
  610. ROQ_IB2_START(0x2b)));
  611. WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
  612. ta_aux_cntl = RREG32(TA_CNTL_AUX);
  613. WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
  614. sx_debug_1 = RREG32(SX_DEBUG_1);
  615. sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
  616. WREG32(SX_DEBUG_1, sx_debug_1);
  617. smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
  618. smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
  619. smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
  620. WREG32(SMX_DC_CTL0, smx_dc_ctl0);
  621. if (rdev->family != CHIP_RV740)
  622. WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
  623. GS_FLUSH_CTL(4) |
  624. ACK_FLUSH_CTL(3) |
  625. SYNC_FLUSH_CTL));
  626. db_debug3 = RREG32(DB_DEBUG3);
  627. db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
  628. switch (rdev->family) {
  629. case CHIP_RV770:
  630. case CHIP_RV740:
  631. db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
  632. break;
  633. case CHIP_RV710:
  634. case CHIP_RV730:
  635. default:
  636. db_debug3 |= DB_CLK_OFF_DELAY(2);
  637. break;
  638. }
  639. WREG32(DB_DEBUG3, db_debug3);
  640. if (rdev->family != CHIP_RV770) {
  641. db_debug4 = RREG32(DB_DEBUG4);
  642. db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
  643. WREG32(DB_DEBUG4, db_debug4);
  644. }
  645. WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
  646. POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
  647. SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
  648. WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
  649. SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
  650. SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
  651. WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
  652. WREG32(VGT_NUM_INSTANCES, 1);
  653. WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
  654. WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
  655. WREG32(CP_PERFMON_CNTL, 0);
  656. sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
  657. DONE_FIFO_HIWATER(0xe0) |
  658. ALU_UPDATE_FIFO_HIWATER(0x8));
  659. switch (rdev->family) {
  660. case CHIP_RV770:
  661. case CHIP_RV730:
  662. case CHIP_RV710:
  663. sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
  664. break;
  665. case CHIP_RV740:
  666. default:
  667. sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
  668. break;
  669. }
  670. WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
  671. /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
  672. * should be adjusted as needed by the 2D/3D drivers. This just sets default values
  673. */
  674. sq_config = RREG32(SQ_CONFIG);
  675. sq_config &= ~(PS_PRIO(3) |
  676. VS_PRIO(3) |
  677. GS_PRIO(3) |
  678. ES_PRIO(3));
  679. sq_config |= (DX9_CONSTS |
  680. VC_ENABLE |
  681. EXPORT_SRC_C |
  682. PS_PRIO(0) |
  683. VS_PRIO(1) |
  684. GS_PRIO(2) |
  685. ES_PRIO(3));
  686. if (rdev->family == CHIP_RV710)
  687. /* no vertex cache */
  688. sq_config &= ~VC_ENABLE;
  689. WREG32(SQ_CONFIG, sq_config);
  690. WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
  691. NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
  692. NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
  693. WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
  694. NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
  695. sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
  696. NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
  697. NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
  698. if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
  699. sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
  700. else
  701. sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
  702. WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
  703. WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
  704. NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
  705. WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
  706. NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
  707. sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
  708. SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
  709. SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
  710. SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
  711. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
  712. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
  713. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
  714. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
  715. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
  716. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
  717. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
  718. WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
  719. WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
  720. FORCE_EOV_MAX_REZ_CNT(255)));
  721. if (rdev->family == CHIP_RV710)
  722. WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
  723. AUTO_INVLD_EN(ES_AND_GS_AUTO)));
  724. else
  725. WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
  726. AUTO_INVLD_EN(ES_AND_GS_AUTO)));
  727. switch (rdev->family) {
  728. case CHIP_RV770:
  729. case CHIP_RV730:
  730. case CHIP_RV740:
  731. gs_prim_buffer_depth = 384;
  732. break;
  733. case CHIP_RV710:
  734. gs_prim_buffer_depth = 128;
  735. break;
  736. default:
  737. break;
  738. }
  739. num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
  740. vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
  741. /* Max value for this is 256 */
  742. if (vgt_gs_per_es > 256)
  743. vgt_gs_per_es = 256;
  744. WREG32(VGT_ES_PER_GS, 128);
  745. WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
  746. WREG32(VGT_GS_PER_VS, 2);
  747. /* more default values. 2D/3D driver should adjust as needed */
  748. WREG32(VGT_GS_VERTEX_REUSE, 16);
  749. WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
  750. WREG32(VGT_STRMOUT_EN, 0);
  751. WREG32(SX_MISC, 0);
  752. WREG32(PA_SC_MODE_CNTL, 0);
  753. WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
  754. WREG32(PA_SC_AA_CONFIG, 0);
  755. WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
  756. WREG32(PA_SC_LINE_STIPPLE, 0);
  757. WREG32(SPI_INPUT_Z, 0);
  758. WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
  759. WREG32(CB_COLOR7_FRAG, 0);
  760. /* clear render buffer base addresses */
  761. WREG32(CB_COLOR0_BASE, 0);
  762. WREG32(CB_COLOR1_BASE, 0);
  763. WREG32(CB_COLOR2_BASE, 0);
  764. WREG32(CB_COLOR3_BASE, 0);
  765. WREG32(CB_COLOR4_BASE, 0);
  766. WREG32(CB_COLOR5_BASE, 0);
  767. WREG32(CB_COLOR6_BASE, 0);
  768. WREG32(CB_COLOR7_BASE, 0);
  769. WREG32(TCP_CNTL, 0);
  770. hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
  771. WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
  772. WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
  773. WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
  774. NUM_CLIP_SEQ(3)));
  775. }
  776. int rv770_mc_init(struct radeon_device *rdev)
  777. {
  778. u32 tmp;
  779. int chansize, numchan;
  780. /* Get VRAM informations */
  781. rdev->mc.vram_is_ddr = true;
  782. tmp = RREG32(MC_ARB_RAMCFG);
  783. if (tmp & CHANSIZE_OVERRIDE) {
  784. chansize = 16;
  785. } else if (tmp & CHANSIZE_MASK) {
  786. chansize = 64;
  787. } else {
  788. chansize = 32;
  789. }
  790. tmp = RREG32(MC_SHARED_CHMAP);
  791. switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
  792. case 0:
  793. default:
  794. numchan = 1;
  795. break;
  796. case 1:
  797. numchan = 2;
  798. break;
  799. case 2:
  800. numchan = 4;
  801. break;
  802. case 3:
  803. numchan = 8;
  804. break;
  805. }
  806. rdev->mc.vram_width = numchan * chansize;
  807. /* Could aper size report 0 ? */
  808. rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
  809. rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
  810. /* Setup GPU memory space */
  811. rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
  812. rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
  813. rdev->mc.visible_vram_size = rdev->mc.aper_size;
  814. r600_vram_gtt_location(rdev, &rdev->mc);
  815. radeon_update_bandwidth_info(rdev);
  816. return 0;
  817. }
  818. static int rv770_startup(struct radeon_device *rdev)
  819. {
  820. int r;
  821. if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
  822. r = r600_init_microcode(rdev);
  823. if (r) {
  824. DRM_ERROR("Failed to load firmware!\n");
  825. return r;
  826. }
  827. }
  828. rv770_mc_program(rdev);
  829. if (rdev->flags & RADEON_IS_AGP) {
  830. rv770_agp_enable(rdev);
  831. } else {
  832. r = rv770_pcie_gart_enable(rdev);
  833. if (r)
  834. return r;
  835. }
  836. rv770_gpu_init(rdev);
  837. r = r600_blit_init(rdev);
  838. if (r) {
  839. r600_blit_fini(rdev);
  840. rdev->asic->copy = NULL;
  841. dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
  842. }
  843. /* pin copy shader into vram */
  844. if (rdev->r600_blit.shader_obj) {
  845. r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
  846. if (unlikely(r != 0))
  847. return r;
  848. r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
  849. &rdev->r600_blit.shader_gpu_addr);
  850. radeon_bo_unreserve(rdev->r600_blit.shader_obj);
  851. if (r) {
  852. DRM_ERROR("failed to pin blit object %d\n", r);
  853. return r;
  854. }
  855. }
  856. /* Enable IRQ */
  857. r = r600_irq_init(rdev);
  858. if (r) {
  859. DRM_ERROR("radeon: IH init failed (%d).\n", r);
  860. radeon_irq_kms_fini(rdev);
  861. return r;
  862. }
  863. r600_irq_set(rdev);
  864. r = radeon_ring_init(rdev, rdev->cp.ring_size);
  865. if (r)
  866. return r;
  867. r = rv770_cp_load_microcode(rdev);
  868. if (r)
  869. return r;
  870. r = r600_cp_resume(rdev);
  871. if (r)
  872. return r;
  873. /* write back buffer are not vital so don't worry about failure */
  874. r600_wb_enable(rdev);
  875. return 0;
  876. }
  877. int rv770_resume(struct radeon_device *rdev)
  878. {
  879. int r;
  880. /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
  881. * posting will perform necessary task to bring back GPU into good
  882. * shape.
  883. */
  884. /* post card */
  885. atom_asic_init(rdev->mode_info.atom_context);
  886. /* Initialize clocks */
  887. r = radeon_clocks_init(rdev);
  888. if (r) {
  889. return r;
  890. }
  891. r = rv770_startup(rdev);
  892. if (r) {
  893. DRM_ERROR("r600 startup failed on resume\n");
  894. return r;
  895. }
  896. r = r600_ib_test(rdev);
  897. if (r) {
  898. DRM_ERROR("radeon: failled testing IB (%d).\n", r);
  899. return r;
  900. }
  901. r = r600_audio_init(rdev);
  902. if (r) {
  903. dev_err(rdev->dev, "radeon: audio init failed\n");
  904. return r;
  905. }
  906. return r;
  907. }
  908. int rv770_suspend(struct radeon_device *rdev)
  909. {
  910. int r;
  911. r600_audio_fini(rdev);
  912. /* FIXME: we should wait for ring to be empty */
  913. r700_cp_stop(rdev);
  914. rdev->cp.ready = false;
  915. r600_irq_suspend(rdev);
  916. r600_wb_disable(rdev);
  917. rv770_pcie_gart_disable(rdev);
  918. /* unpin shaders bo */
  919. if (rdev->r600_blit.shader_obj) {
  920. r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
  921. if (likely(r == 0)) {
  922. radeon_bo_unpin(rdev->r600_blit.shader_obj);
  923. radeon_bo_unreserve(rdev->r600_blit.shader_obj);
  924. }
  925. }
  926. return 0;
  927. }
  928. /* Plan is to move initialization in that function and use
  929. * helper function so that radeon_device_init pretty much
  930. * do nothing more than calling asic specific function. This
  931. * should also allow to remove a bunch of callback function
  932. * like vram_info.
  933. */
  934. int rv770_init(struct radeon_device *rdev)
  935. {
  936. int r;
  937. r = radeon_dummy_page_init(rdev);
  938. if (r)
  939. return r;
  940. /* This don't do much */
  941. r = radeon_gem_init(rdev);
  942. if (r)
  943. return r;
  944. /* Read BIOS */
  945. if (!radeon_get_bios(rdev)) {
  946. if (ASIC_IS_AVIVO(rdev))
  947. return -EINVAL;
  948. }
  949. /* Must be an ATOMBIOS */
  950. if (!rdev->is_atom_bios) {
  951. dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
  952. return -EINVAL;
  953. }
  954. r = radeon_atombios_init(rdev);
  955. if (r)
  956. return r;
  957. /* Post card if necessary */
  958. if (!r600_card_posted(rdev)) {
  959. if (!rdev->bios) {
  960. dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  961. return -EINVAL;
  962. }
  963. DRM_INFO("GPU not posted. posting now...\n");
  964. atom_asic_init(rdev->mode_info.atom_context);
  965. }
  966. /* Initialize scratch registers */
  967. r600_scratch_init(rdev);
  968. /* Initialize surface registers */
  969. radeon_surface_init(rdev);
  970. /* Initialize clocks */
  971. radeon_get_clock_info(rdev->ddev);
  972. r = radeon_clocks_init(rdev);
  973. if (r)
  974. return r;
  975. /* Initialize power management */
  976. radeon_pm_init(rdev);
  977. /* Fence driver */
  978. r = radeon_fence_driver_init(rdev);
  979. if (r)
  980. return r;
  981. /* initialize AGP */
  982. if (rdev->flags & RADEON_IS_AGP) {
  983. r = radeon_agp_init(rdev);
  984. if (r)
  985. radeon_agp_disable(rdev);
  986. }
  987. r = rv770_mc_init(rdev);
  988. if (r)
  989. return r;
  990. /* Memory manager */
  991. r = radeon_bo_init(rdev);
  992. if (r)
  993. return r;
  994. r = radeon_irq_kms_init(rdev);
  995. if (r)
  996. return r;
  997. rdev->cp.ring_obj = NULL;
  998. r600_ring_init(rdev, 1024 * 1024);
  999. rdev->ih.ring_obj = NULL;
  1000. r600_ih_ring_init(rdev, 64 * 1024);
  1001. r = r600_pcie_gart_init(rdev);
  1002. if (r)
  1003. return r;
  1004. rdev->accel_working = true;
  1005. r = rv770_startup(rdev);
  1006. if (r) {
  1007. dev_err(rdev->dev, "disabling GPU acceleration\n");
  1008. r700_cp_fini(rdev);
  1009. r600_wb_fini(rdev);
  1010. r600_irq_fini(rdev);
  1011. radeon_irq_kms_fini(rdev);
  1012. rv770_pcie_gart_fini(rdev);
  1013. rdev->accel_working = false;
  1014. }
  1015. if (rdev->accel_working) {
  1016. r = radeon_ib_pool_init(rdev);
  1017. if (r) {
  1018. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  1019. rdev->accel_working = false;
  1020. } else {
  1021. r = r600_ib_test(rdev);
  1022. if (r) {
  1023. dev_err(rdev->dev, "IB test failed (%d).\n", r);
  1024. rdev->accel_working = false;
  1025. }
  1026. }
  1027. }
  1028. r = r600_audio_init(rdev);
  1029. if (r) {
  1030. dev_err(rdev->dev, "radeon: audio init failed\n");
  1031. return r;
  1032. }
  1033. return 0;
  1034. }
  1035. void rv770_fini(struct radeon_device *rdev)
  1036. {
  1037. radeon_pm_fini(rdev);
  1038. r600_blit_fini(rdev);
  1039. r700_cp_fini(rdev);
  1040. r600_wb_fini(rdev);
  1041. r600_irq_fini(rdev);
  1042. radeon_irq_kms_fini(rdev);
  1043. rv770_pcie_gart_fini(rdev);
  1044. radeon_gem_fini(rdev);
  1045. radeon_fence_driver_fini(rdev);
  1046. radeon_clocks_fini(rdev);
  1047. radeon_agp_fini(rdev);
  1048. radeon_bo_fini(rdev);
  1049. radeon_atombios_fini(rdev);
  1050. kfree(rdev->bios);
  1051. rdev->bios = NULL;
  1052. radeon_dummy_page_fini(rdev);
  1053. }