events.c 37 KB

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  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is recieved, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #include <linux/linkage.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/module.h>
  27. #include <linux/string.h>
  28. #include <linux/bootmem.h>
  29. #include <linux/slab.h>
  30. #include <linux/irqnr.h>
  31. #include <linux/pci.h>
  32. #include <asm/desc.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/irq.h>
  35. #include <asm/idle.h>
  36. #include <asm/io_apic.h>
  37. #include <asm/sync_bitops.h>
  38. #include <asm/xen/pci.h>
  39. #include <asm/xen/hypercall.h>
  40. #include <asm/xen/hypervisor.h>
  41. #include <xen/xen.h>
  42. #include <xen/hvm.h>
  43. #include <xen/xen-ops.h>
  44. #include <xen/events.h>
  45. #include <xen/interface/xen.h>
  46. #include <xen/interface/event_channel.h>
  47. #include <xen/interface/hvm/hvm_op.h>
  48. #include <xen/interface/hvm/params.h>
  49. /*
  50. * This lock protects updates to the following mapping and reference-count
  51. * arrays. The lock does not need to be acquired to read the mapping tables.
  52. */
  53. static DEFINE_SPINLOCK(irq_mapping_update_lock);
  54. /* IRQ <-> VIRQ mapping. */
  55. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  56. /* IRQ <-> IPI mapping */
  57. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  58. /* Interrupt types. */
  59. enum xen_irq_type {
  60. IRQT_UNBOUND = 0,
  61. IRQT_PIRQ,
  62. IRQT_VIRQ,
  63. IRQT_IPI,
  64. IRQT_EVTCHN
  65. };
  66. /*
  67. * Packed IRQ information:
  68. * type - enum xen_irq_type
  69. * event channel - irq->event channel mapping
  70. * cpu - cpu this event channel is bound to
  71. * index - type-specific information:
  72. * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
  73. * guest, or GSI (real passthrough IRQ) of the device.
  74. * VIRQ - virq number
  75. * IPI - IPI vector
  76. * EVTCHN -
  77. */
  78. struct irq_info
  79. {
  80. enum xen_irq_type type; /* type */
  81. unsigned short evtchn; /* event channel */
  82. unsigned short cpu; /* cpu bound */
  83. union {
  84. unsigned short virq;
  85. enum ipi_vector ipi;
  86. struct {
  87. unsigned short pirq;
  88. unsigned short gsi;
  89. unsigned char vector;
  90. unsigned char flags;
  91. } pirq;
  92. } u;
  93. };
  94. #define PIRQ_NEEDS_EOI (1 << 0)
  95. #define PIRQ_SHAREABLE (1 << 1)
  96. static struct irq_info *irq_info;
  97. static int *pirq_to_irq;
  98. static int *evtchn_to_irq;
  99. struct cpu_evtchn_s {
  100. unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
  101. };
  102. static __initdata struct cpu_evtchn_s init_evtchn_mask = {
  103. .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
  104. };
  105. static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
  106. static inline unsigned long *cpu_evtchn_mask(int cpu)
  107. {
  108. return cpu_evtchn_mask_p[cpu].bits;
  109. }
  110. /* Xen will never allocate port zero for any purpose. */
  111. #define VALID_EVTCHN(chn) ((chn) != 0)
  112. static struct irq_chip xen_dynamic_chip;
  113. static struct irq_chip xen_percpu_chip;
  114. static struct irq_chip xen_pirq_chip;
  115. /* Constructor for packed IRQ information. */
  116. static struct irq_info mk_unbound_info(void)
  117. {
  118. return (struct irq_info) { .type = IRQT_UNBOUND };
  119. }
  120. static struct irq_info mk_evtchn_info(unsigned short evtchn)
  121. {
  122. return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
  123. .cpu = 0 };
  124. }
  125. static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
  126. {
  127. return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
  128. .cpu = 0, .u.ipi = ipi };
  129. }
  130. static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
  131. {
  132. return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
  133. .cpu = 0, .u.virq = virq };
  134. }
  135. static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
  136. unsigned short gsi, unsigned short vector)
  137. {
  138. return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
  139. .cpu = 0,
  140. .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
  141. }
  142. /*
  143. * Accessors for packed IRQ information.
  144. */
  145. static struct irq_info *info_for_irq(unsigned irq)
  146. {
  147. return &irq_info[irq];
  148. }
  149. static unsigned int evtchn_from_irq(unsigned irq)
  150. {
  151. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  152. return 0;
  153. return info_for_irq(irq)->evtchn;
  154. }
  155. unsigned irq_from_evtchn(unsigned int evtchn)
  156. {
  157. return evtchn_to_irq[evtchn];
  158. }
  159. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  160. static enum ipi_vector ipi_from_irq(unsigned irq)
  161. {
  162. struct irq_info *info = info_for_irq(irq);
  163. BUG_ON(info == NULL);
  164. BUG_ON(info->type != IRQT_IPI);
  165. return info->u.ipi;
  166. }
  167. static unsigned virq_from_irq(unsigned irq)
  168. {
  169. struct irq_info *info = info_for_irq(irq);
  170. BUG_ON(info == NULL);
  171. BUG_ON(info->type != IRQT_VIRQ);
  172. return info->u.virq;
  173. }
  174. static unsigned pirq_from_irq(unsigned irq)
  175. {
  176. struct irq_info *info = info_for_irq(irq);
  177. BUG_ON(info == NULL);
  178. BUG_ON(info->type != IRQT_PIRQ);
  179. return info->u.pirq.pirq;
  180. }
  181. static unsigned gsi_from_irq(unsigned irq)
  182. {
  183. struct irq_info *info = info_for_irq(irq);
  184. BUG_ON(info == NULL);
  185. BUG_ON(info->type != IRQT_PIRQ);
  186. return info->u.pirq.gsi;
  187. }
  188. static unsigned vector_from_irq(unsigned irq)
  189. {
  190. struct irq_info *info = info_for_irq(irq);
  191. BUG_ON(info == NULL);
  192. BUG_ON(info->type != IRQT_PIRQ);
  193. return info->u.pirq.vector;
  194. }
  195. static enum xen_irq_type type_from_irq(unsigned irq)
  196. {
  197. return info_for_irq(irq)->type;
  198. }
  199. static unsigned cpu_from_irq(unsigned irq)
  200. {
  201. return info_for_irq(irq)->cpu;
  202. }
  203. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  204. {
  205. int irq = evtchn_to_irq[evtchn];
  206. unsigned ret = 0;
  207. if (irq != -1)
  208. ret = cpu_from_irq(irq);
  209. return ret;
  210. }
  211. static bool pirq_needs_eoi(unsigned irq)
  212. {
  213. struct irq_info *info = info_for_irq(irq);
  214. BUG_ON(info->type != IRQT_PIRQ);
  215. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  216. }
  217. static inline unsigned long active_evtchns(unsigned int cpu,
  218. struct shared_info *sh,
  219. unsigned int idx)
  220. {
  221. return (sh->evtchn_pending[idx] &
  222. cpu_evtchn_mask(cpu)[idx] &
  223. ~sh->evtchn_mask[idx]);
  224. }
  225. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  226. {
  227. int irq = evtchn_to_irq[chn];
  228. BUG_ON(irq == -1);
  229. #ifdef CONFIG_SMP
  230. cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu));
  231. #endif
  232. clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
  233. set_bit(chn, cpu_evtchn_mask(cpu));
  234. irq_info[irq].cpu = cpu;
  235. }
  236. static void init_evtchn_cpu_bindings(void)
  237. {
  238. int i;
  239. #ifdef CONFIG_SMP
  240. struct irq_desc *desc;
  241. /* By default all event channels notify CPU#0. */
  242. for_each_irq_desc(i, desc) {
  243. cpumask_copy(desc->affinity, cpumask_of(0));
  244. }
  245. #endif
  246. for_each_possible_cpu(i)
  247. memset(cpu_evtchn_mask(i),
  248. (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
  249. }
  250. static inline void clear_evtchn(int port)
  251. {
  252. struct shared_info *s = HYPERVISOR_shared_info;
  253. sync_clear_bit(port, &s->evtchn_pending[0]);
  254. }
  255. static inline void set_evtchn(int port)
  256. {
  257. struct shared_info *s = HYPERVISOR_shared_info;
  258. sync_set_bit(port, &s->evtchn_pending[0]);
  259. }
  260. static inline int test_evtchn(int port)
  261. {
  262. struct shared_info *s = HYPERVISOR_shared_info;
  263. return sync_test_bit(port, &s->evtchn_pending[0]);
  264. }
  265. /**
  266. * notify_remote_via_irq - send event to remote end of event channel via irq
  267. * @irq: irq of event channel to send event to
  268. *
  269. * Unlike notify_remote_via_evtchn(), this is safe to use across
  270. * save/restore. Notifications on a broken connection are silently
  271. * dropped.
  272. */
  273. void notify_remote_via_irq(int irq)
  274. {
  275. int evtchn = evtchn_from_irq(irq);
  276. if (VALID_EVTCHN(evtchn))
  277. notify_remote_via_evtchn(evtchn);
  278. }
  279. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  280. static void mask_evtchn(int port)
  281. {
  282. struct shared_info *s = HYPERVISOR_shared_info;
  283. sync_set_bit(port, &s->evtchn_mask[0]);
  284. }
  285. static void unmask_evtchn(int port)
  286. {
  287. struct shared_info *s = HYPERVISOR_shared_info;
  288. unsigned int cpu = get_cpu();
  289. BUG_ON(!irqs_disabled());
  290. /* Slow path (hypercall) if this is a non-local port. */
  291. if (unlikely(cpu != cpu_from_evtchn(port))) {
  292. struct evtchn_unmask unmask = { .port = port };
  293. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  294. } else {
  295. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  296. sync_clear_bit(port, &s->evtchn_mask[0]);
  297. /*
  298. * The following is basically the equivalent of
  299. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  300. * the interrupt edge' if the channel is masked.
  301. */
  302. if (sync_test_bit(port, &s->evtchn_pending[0]) &&
  303. !sync_test_and_set_bit(port / BITS_PER_LONG,
  304. &vcpu_info->evtchn_pending_sel))
  305. vcpu_info->evtchn_upcall_pending = 1;
  306. }
  307. put_cpu();
  308. }
  309. static int get_nr_hw_irqs(void)
  310. {
  311. int ret = 1;
  312. #ifdef CONFIG_X86_IO_APIC
  313. ret = get_nr_irqs_gsi();
  314. #endif
  315. return ret;
  316. }
  317. static int find_unbound_pirq(int type)
  318. {
  319. int rc, i;
  320. struct physdev_get_free_pirq op_get_free_pirq;
  321. op_get_free_pirq.type = type;
  322. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  323. if (!rc)
  324. return op_get_free_pirq.pirq;
  325. for (i = 0; i < nr_irqs; i++) {
  326. if (pirq_to_irq[i] < 0)
  327. return i;
  328. }
  329. return -1;
  330. }
  331. static int find_unbound_irq(void)
  332. {
  333. struct irq_data *data;
  334. int irq, res;
  335. int bottom = get_nr_hw_irqs();
  336. int top = nr_irqs-1;
  337. if (bottom == nr_irqs)
  338. goto no_irqs;
  339. /* This loop starts from the top of IRQ space and goes down.
  340. * We need this b/c if we have a PCI device in a Xen PV guest
  341. * we do not have an IO-APIC (though the backend might have them)
  342. * mapped in. To not have a collision of physical IRQs with the Xen
  343. * event channels start at the top of the IRQ space for virtual IRQs.
  344. */
  345. for (irq = top; irq > bottom; irq--) {
  346. data = irq_get_irq_data(irq);
  347. /* only 15->0 have init'd desc; handle irq > 16 */
  348. if (!data)
  349. break;
  350. if (data->chip == &no_irq_chip)
  351. break;
  352. if (data->chip != &xen_dynamic_chip)
  353. continue;
  354. if (irq_info[irq].type == IRQT_UNBOUND)
  355. return irq;
  356. }
  357. if (irq == bottom)
  358. goto no_irqs;
  359. res = irq_alloc_desc_at(irq, -1);
  360. if (WARN_ON(res != irq))
  361. return -1;
  362. return irq;
  363. no_irqs:
  364. panic("No available IRQ to bind to: increase nr_irqs!\n");
  365. }
  366. static bool identity_mapped_irq(unsigned irq)
  367. {
  368. /* identity map all the hardware irqs */
  369. return irq < get_nr_hw_irqs();
  370. }
  371. static void pirq_unmask_notify(int irq)
  372. {
  373. struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
  374. if (unlikely(pirq_needs_eoi(irq))) {
  375. int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  376. WARN_ON(rc);
  377. }
  378. }
  379. static void pirq_query_unmask(int irq)
  380. {
  381. struct physdev_irq_status_query irq_status;
  382. struct irq_info *info = info_for_irq(irq);
  383. BUG_ON(info->type != IRQT_PIRQ);
  384. irq_status.irq = pirq_from_irq(irq);
  385. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  386. irq_status.flags = 0;
  387. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  388. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  389. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  390. }
  391. static bool probing_irq(int irq)
  392. {
  393. struct irq_desc *desc = irq_to_desc(irq);
  394. return desc && desc->action == NULL;
  395. }
  396. static unsigned int startup_pirq(unsigned int irq)
  397. {
  398. struct evtchn_bind_pirq bind_pirq;
  399. struct irq_info *info = info_for_irq(irq);
  400. int evtchn = evtchn_from_irq(irq);
  401. int rc;
  402. BUG_ON(info->type != IRQT_PIRQ);
  403. if (VALID_EVTCHN(evtchn))
  404. goto out;
  405. bind_pirq.pirq = pirq_from_irq(irq);
  406. /* NB. We are happy to share unless we are probing. */
  407. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  408. BIND_PIRQ__WILL_SHARE : 0;
  409. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  410. if (rc != 0) {
  411. if (!probing_irq(irq))
  412. printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
  413. irq);
  414. return 0;
  415. }
  416. evtchn = bind_pirq.port;
  417. pirq_query_unmask(irq);
  418. evtchn_to_irq[evtchn] = irq;
  419. bind_evtchn_to_cpu(evtchn, 0);
  420. info->evtchn = evtchn;
  421. out:
  422. unmask_evtchn(evtchn);
  423. pirq_unmask_notify(irq);
  424. return 0;
  425. }
  426. static void shutdown_pirq(unsigned int irq)
  427. {
  428. struct evtchn_close close;
  429. struct irq_info *info = info_for_irq(irq);
  430. int evtchn = evtchn_from_irq(irq);
  431. BUG_ON(info->type != IRQT_PIRQ);
  432. if (!VALID_EVTCHN(evtchn))
  433. return;
  434. mask_evtchn(evtchn);
  435. close.port = evtchn;
  436. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  437. BUG();
  438. bind_evtchn_to_cpu(evtchn, 0);
  439. evtchn_to_irq[evtchn] = -1;
  440. info->evtchn = 0;
  441. }
  442. static void enable_pirq(unsigned int irq)
  443. {
  444. startup_pirq(irq);
  445. }
  446. static void disable_pirq(unsigned int irq)
  447. {
  448. }
  449. static void ack_pirq(unsigned int irq)
  450. {
  451. int evtchn = evtchn_from_irq(irq);
  452. move_native_irq(irq);
  453. if (VALID_EVTCHN(evtchn)) {
  454. mask_evtchn(evtchn);
  455. clear_evtchn(evtchn);
  456. }
  457. }
  458. static void end_pirq(unsigned int irq)
  459. {
  460. int evtchn = evtchn_from_irq(irq);
  461. struct irq_desc *desc = irq_to_desc(irq);
  462. if (WARN_ON(!desc))
  463. return;
  464. if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) ==
  465. (IRQ_DISABLED|IRQ_PENDING)) {
  466. shutdown_pirq(irq);
  467. } else if (VALID_EVTCHN(evtchn)) {
  468. unmask_evtchn(evtchn);
  469. pirq_unmask_notify(irq);
  470. }
  471. }
  472. static int find_irq_by_gsi(unsigned gsi)
  473. {
  474. int irq;
  475. for (irq = 0; irq < nr_irqs; irq++) {
  476. struct irq_info *info = info_for_irq(irq);
  477. if (info == NULL || info->type != IRQT_PIRQ)
  478. continue;
  479. if (gsi_from_irq(irq) == gsi)
  480. return irq;
  481. }
  482. return -1;
  483. }
  484. int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
  485. {
  486. return xen_map_pirq_gsi(gsi, gsi, shareable, name);
  487. }
  488. /* xen_map_pirq_gsi might allocate irqs from the top down, as a
  489. * consequence don't assume that the irq number returned has a low value
  490. * or can be used as a pirq number unless you know otherwise.
  491. *
  492. * One notable exception is when xen_map_pirq_gsi is called passing an
  493. * hardware gsi as argument, in that case the irq number returned
  494. * matches the gsi number passed as second argument.
  495. *
  496. * Note: We don't assign an event channel until the irq actually started
  497. * up. Return an existing irq if we've already got one for the gsi.
  498. */
  499. int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
  500. {
  501. int irq = 0;
  502. struct physdev_irq irq_op;
  503. spin_lock(&irq_mapping_update_lock);
  504. if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
  505. printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
  506. pirq > nr_irqs ? "pirq" :"",
  507. gsi > nr_irqs ? "gsi" : "");
  508. goto out;
  509. }
  510. irq = find_irq_by_gsi(gsi);
  511. if (irq != -1) {
  512. printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
  513. irq, gsi);
  514. goto out; /* XXX need refcount? */
  515. }
  516. /* If we are a PV guest, we don't have GSIs (no ACPI passed). Therefore
  517. * we are using the !xen_initial_domain() to drop in the function.*/
  518. if (identity_mapped_irq(gsi) || (!xen_initial_domain() &&
  519. xen_pv_domain())) {
  520. irq = gsi;
  521. irq_alloc_desc_at(irq, -1);
  522. } else
  523. irq = find_unbound_irq();
  524. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  525. handle_level_irq, name);
  526. irq_op.irq = irq;
  527. irq_op.vector = 0;
  528. /* Only the privileged domain can do this. For non-priv, the pcifront
  529. * driver provides a PCI bus that does the call to do exactly
  530. * this in the priv domain. */
  531. if (xen_initial_domain() &&
  532. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  533. irq_free_desc(irq);
  534. irq = -ENOSPC;
  535. goto out;
  536. }
  537. irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
  538. irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
  539. pirq_to_irq[pirq] = irq;
  540. out:
  541. spin_unlock(&irq_mapping_update_lock);
  542. return irq;
  543. }
  544. #ifdef CONFIG_PCI_MSI
  545. #include <linux/msi.h>
  546. #include "../pci/msi.h"
  547. void xen_allocate_pirq_msi(char *name, int *irq, int *pirq, int alloc)
  548. {
  549. spin_lock(&irq_mapping_update_lock);
  550. if (alloc & XEN_ALLOC_IRQ) {
  551. *irq = find_unbound_irq();
  552. if (*irq == -1)
  553. goto out;
  554. }
  555. if (alloc & XEN_ALLOC_PIRQ) {
  556. *pirq = find_unbound_pirq(MAP_PIRQ_TYPE_MSI);
  557. if (*pirq == -1)
  558. goto out;
  559. }
  560. set_irq_chip_and_handler_name(*irq, &xen_pirq_chip,
  561. handle_level_irq, name);
  562. irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0);
  563. pirq_to_irq[*pirq] = *irq;
  564. out:
  565. spin_unlock(&irq_mapping_update_lock);
  566. }
  567. int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
  568. {
  569. int irq = -1;
  570. struct physdev_map_pirq map_irq;
  571. int rc;
  572. int pos;
  573. u32 table_offset, bir;
  574. memset(&map_irq, 0, sizeof(map_irq));
  575. map_irq.domid = DOMID_SELF;
  576. map_irq.type = MAP_PIRQ_TYPE_MSI;
  577. map_irq.index = -1;
  578. map_irq.pirq = -1;
  579. map_irq.bus = dev->bus->number;
  580. map_irq.devfn = dev->devfn;
  581. if (type == PCI_CAP_ID_MSIX) {
  582. pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  583. pci_read_config_dword(dev, msix_table_offset_reg(pos),
  584. &table_offset);
  585. bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
  586. map_irq.table_base = pci_resource_start(dev, bir);
  587. map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
  588. }
  589. spin_lock(&irq_mapping_update_lock);
  590. irq = find_unbound_irq();
  591. if (irq == -1)
  592. goto out;
  593. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  594. if (rc) {
  595. printk(KERN_WARNING "xen map irq failed %d\n", rc);
  596. irq_free_desc(irq);
  597. irq = -1;
  598. goto out;
  599. }
  600. irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
  601. set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
  602. handle_level_irq,
  603. (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
  604. out:
  605. spin_unlock(&irq_mapping_update_lock);
  606. return irq;
  607. }
  608. #endif
  609. int xen_destroy_irq(int irq)
  610. {
  611. struct irq_desc *desc;
  612. struct physdev_unmap_pirq unmap_irq;
  613. struct irq_info *info = info_for_irq(irq);
  614. int rc = -ENOENT;
  615. spin_lock(&irq_mapping_update_lock);
  616. desc = irq_to_desc(irq);
  617. if (!desc)
  618. goto out;
  619. if (xen_initial_domain()) {
  620. unmap_irq.pirq = info->u.pirq.pirq;
  621. unmap_irq.domid = DOMID_SELF;
  622. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  623. if (rc) {
  624. printk(KERN_WARNING "unmap irq failed %d\n", rc);
  625. goto out;
  626. }
  627. pirq_to_irq[info->u.pirq.pirq] = -1;
  628. }
  629. irq_info[irq] = mk_unbound_info();
  630. irq_free_desc(irq);
  631. out:
  632. spin_unlock(&irq_mapping_update_lock);
  633. return rc;
  634. }
  635. int xen_vector_from_irq(unsigned irq)
  636. {
  637. return vector_from_irq(irq);
  638. }
  639. int xen_gsi_from_irq(unsigned irq)
  640. {
  641. return gsi_from_irq(irq);
  642. }
  643. int xen_irq_from_pirq(unsigned pirq)
  644. {
  645. return pirq_to_irq[pirq];
  646. }
  647. int bind_evtchn_to_irq(unsigned int evtchn)
  648. {
  649. int irq;
  650. spin_lock(&irq_mapping_update_lock);
  651. irq = evtchn_to_irq[evtchn];
  652. if (irq == -1) {
  653. irq = find_unbound_irq();
  654. set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
  655. handle_fasteoi_irq, "event");
  656. evtchn_to_irq[evtchn] = irq;
  657. irq_info[irq] = mk_evtchn_info(evtchn);
  658. }
  659. spin_unlock(&irq_mapping_update_lock);
  660. return irq;
  661. }
  662. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  663. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  664. {
  665. struct evtchn_bind_ipi bind_ipi;
  666. int evtchn, irq;
  667. spin_lock(&irq_mapping_update_lock);
  668. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  669. if (irq == -1) {
  670. irq = find_unbound_irq();
  671. if (irq < 0)
  672. goto out;
  673. set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
  674. handle_percpu_irq, "ipi");
  675. bind_ipi.vcpu = cpu;
  676. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  677. &bind_ipi) != 0)
  678. BUG();
  679. evtchn = bind_ipi.port;
  680. evtchn_to_irq[evtchn] = irq;
  681. irq_info[irq] = mk_ipi_info(evtchn, ipi);
  682. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  683. bind_evtchn_to_cpu(evtchn, cpu);
  684. }
  685. out:
  686. spin_unlock(&irq_mapping_update_lock);
  687. return irq;
  688. }
  689. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  690. {
  691. struct evtchn_bind_virq bind_virq;
  692. int evtchn, irq;
  693. spin_lock(&irq_mapping_update_lock);
  694. irq = per_cpu(virq_to_irq, cpu)[virq];
  695. if (irq == -1) {
  696. irq = find_unbound_irq();
  697. set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
  698. handle_percpu_irq, "virq");
  699. bind_virq.virq = virq;
  700. bind_virq.vcpu = cpu;
  701. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  702. &bind_virq) != 0)
  703. BUG();
  704. evtchn = bind_virq.port;
  705. evtchn_to_irq[evtchn] = irq;
  706. irq_info[irq] = mk_virq_info(evtchn, virq);
  707. per_cpu(virq_to_irq, cpu)[virq] = irq;
  708. bind_evtchn_to_cpu(evtchn, cpu);
  709. }
  710. spin_unlock(&irq_mapping_update_lock);
  711. return irq;
  712. }
  713. static void unbind_from_irq(unsigned int irq)
  714. {
  715. struct evtchn_close close;
  716. int evtchn = evtchn_from_irq(irq);
  717. spin_lock(&irq_mapping_update_lock);
  718. if (VALID_EVTCHN(evtchn)) {
  719. close.port = evtchn;
  720. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  721. BUG();
  722. switch (type_from_irq(irq)) {
  723. case IRQT_VIRQ:
  724. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  725. [virq_from_irq(irq)] = -1;
  726. break;
  727. case IRQT_IPI:
  728. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  729. [ipi_from_irq(irq)] = -1;
  730. break;
  731. default:
  732. break;
  733. }
  734. /* Closed ports are implicitly re-bound to VCPU0. */
  735. bind_evtchn_to_cpu(evtchn, 0);
  736. evtchn_to_irq[evtchn] = -1;
  737. }
  738. if (irq_info[irq].type != IRQT_UNBOUND) {
  739. irq_info[irq] = mk_unbound_info();
  740. irq_free_desc(irq);
  741. }
  742. spin_unlock(&irq_mapping_update_lock);
  743. }
  744. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  745. irq_handler_t handler,
  746. unsigned long irqflags,
  747. const char *devname, void *dev_id)
  748. {
  749. unsigned int irq;
  750. int retval;
  751. irq = bind_evtchn_to_irq(evtchn);
  752. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  753. if (retval != 0) {
  754. unbind_from_irq(irq);
  755. return retval;
  756. }
  757. return irq;
  758. }
  759. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  760. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  761. irq_handler_t handler,
  762. unsigned long irqflags, const char *devname, void *dev_id)
  763. {
  764. unsigned int irq;
  765. int retval;
  766. irq = bind_virq_to_irq(virq, cpu);
  767. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  768. if (retval != 0) {
  769. unbind_from_irq(irq);
  770. return retval;
  771. }
  772. return irq;
  773. }
  774. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  775. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  776. unsigned int cpu,
  777. irq_handler_t handler,
  778. unsigned long irqflags,
  779. const char *devname,
  780. void *dev_id)
  781. {
  782. int irq, retval;
  783. irq = bind_ipi_to_irq(ipi, cpu);
  784. if (irq < 0)
  785. return irq;
  786. irqflags |= IRQF_NO_SUSPEND;
  787. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  788. if (retval != 0) {
  789. unbind_from_irq(irq);
  790. return retval;
  791. }
  792. return irq;
  793. }
  794. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  795. {
  796. free_irq(irq, dev_id);
  797. unbind_from_irq(irq);
  798. }
  799. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  800. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  801. {
  802. int irq = per_cpu(ipi_to_irq, cpu)[vector];
  803. BUG_ON(irq < 0);
  804. notify_remote_via_irq(irq);
  805. }
  806. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  807. {
  808. struct shared_info *sh = HYPERVISOR_shared_info;
  809. int cpu = smp_processor_id();
  810. unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
  811. int i;
  812. unsigned long flags;
  813. static DEFINE_SPINLOCK(debug_lock);
  814. struct vcpu_info *v;
  815. spin_lock_irqsave(&debug_lock, flags);
  816. printk("\nvcpu %d\n ", cpu);
  817. for_each_online_cpu(i) {
  818. int pending;
  819. v = per_cpu(xen_vcpu, i);
  820. pending = (get_irq_regs() && i == cpu)
  821. ? xen_irqs_disabled(get_irq_regs())
  822. : v->evtchn_upcall_mask;
  823. printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
  824. pending, v->evtchn_upcall_pending,
  825. (int)(sizeof(v->evtchn_pending_sel)*2),
  826. v->evtchn_pending_sel);
  827. }
  828. v = per_cpu(xen_vcpu, cpu);
  829. printk("\npending:\n ");
  830. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  831. printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
  832. sh->evtchn_pending[i],
  833. i % 8 == 0 ? "\n " : " ");
  834. printk("\nglobal mask:\n ");
  835. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  836. printk("%0*lx%s",
  837. (int)(sizeof(sh->evtchn_mask[0])*2),
  838. sh->evtchn_mask[i],
  839. i % 8 == 0 ? "\n " : " ");
  840. printk("\nglobally unmasked:\n ");
  841. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  842. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  843. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  844. i % 8 == 0 ? "\n " : " ");
  845. printk("\nlocal cpu%d mask:\n ", cpu);
  846. for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
  847. printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
  848. cpu_evtchn[i],
  849. i % 8 == 0 ? "\n " : " ");
  850. printk("\nlocally unmasked:\n ");
  851. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  852. unsigned long pending = sh->evtchn_pending[i]
  853. & ~sh->evtchn_mask[i]
  854. & cpu_evtchn[i];
  855. printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
  856. pending, i % 8 == 0 ? "\n " : " ");
  857. }
  858. printk("\npending list:\n");
  859. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  860. if (sync_test_bit(i, sh->evtchn_pending)) {
  861. int word_idx = i / BITS_PER_LONG;
  862. printk(" %d: event %d -> irq %d%s%s%s\n",
  863. cpu_from_evtchn(i), i,
  864. evtchn_to_irq[i],
  865. sync_test_bit(word_idx, &v->evtchn_pending_sel)
  866. ? "" : " l2-clear",
  867. !sync_test_bit(i, sh->evtchn_mask)
  868. ? "" : " globally-masked",
  869. sync_test_bit(i, cpu_evtchn)
  870. ? "" : " locally-masked");
  871. }
  872. }
  873. spin_unlock_irqrestore(&debug_lock, flags);
  874. return IRQ_HANDLED;
  875. }
  876. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  877. /*
  878. * Search the CPUs pending events bitmasks. For each one found, map
  879. * the event number to an irq, and feed it into do_IRQ() for
  880. * handling.
  881. *
  882. * Xen uses a two-level bitmap to speed searching. The first level is
  883. * a bitset of words which contain pending event bits. The second
  884. * level is a bitset of pending events themselves.
  885. */
  886. static void __xen_evtchn_do_upcall(void)
  887. {
  888. int cpu = get_cpu();
  889. struct shared_info *s = HYPERVISOR_shared_info;
  890. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  891. unsigned count;
  892. do {
  893. unsigned long pending_words;
  894. vcpu_info->evtchn_upcall_pending = 0;
  895. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  896. goto out;
  897. #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
  898. /* Clear master flag /before/ clearing selector flag. */
  899. wmb();
  900. #endif
  901. pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
  902. while (pending_words != 0) {
  903. unsigned long pending_bits;
  904. int word_idx = __ffs(pending_words);
  905. pending_words &= ~(1UL << word_idx);
  906. while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
  907. int bit_idx = __ffs(pending_bits);
  908. int port = (word_idx * BITS_PER_LONG) + bit_idx;
  909. int irq = evtchn_to_irq[port];
  910. struct irq_desc *desc;
  911. mask_evtchn(port);
  912. clear_evtchn(port);
  913. if (irq != -1) {
  914. desc = irq_to_desc(irq);
  915. if (desc)
  916. generic_handle_irq_desc(irq, desc);
  917. }
  918. }
  919. }
  920. BUG_ON(!irqs_disabled());
  921. count = __this_cpu_read(xed_nesting_count);
  922. __this_cpu_write(xed_nesting_count, 0);
  923. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  924. out:
  925. put_cpu();
  926. }
  927. void xen_evtchn_do_upcall(struct pt_regs *regs)
  928. {
  929. struct pt_regs *old_regs = set_irq_regs(regs);
  930. exit_idle();
  931. irq_enter();
  932. __xen_evtchn_do_upcall();
  933. irq_exit();
  934. set_irq_regs(old_regs);
  935. }
  936. void xen_hvm_evtchn_do_upcall(void)
  937. {
  938. __xen_evtchn_do_upcall();
  939. }
  940. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  941. /* Rebind a new event channel to an existing irq. */
  942. void rebind_evtchn_irq(int evtchn, int irq)
  943. {
  944. struct irq_info *info = info_for_irq(irq);
  945. /* Make sure the irq is masked, since the new event channel
  946. will also be masked. */
  947. disable_irq(irq);
  948. spin_lock(&irq_mapping_update_lock);
  949. /* After resume the irq<->evtchn mappings are all cleared out */
  950. BUG_ON(evtchn_to_irq[evtchn] != -1);
  951. /* Expect irq to have been bound before,
  952. so there should be a proper type */
  953. BUG_ON(info->type == IRQT_UNBOUND);
  954. evtchn_to_irq[evtchn] = irq;
  955. irq_info[irq] = mk_evtchn_info(evtchn);
  956. spin_unlock(&irq_mapping_update_lock);
  957. /* new event channels are always bound to cpu 0 */
  958. irq_set_affinity(irq, cpumask_of(0));
  959. /* Unmask the event channel. */
  960. enable_irq(irq);
  961. }
  962. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  963. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  964. {
  965. struct evtchn_bind_vcpu bind_vcpu;
  966. int evtchn = evtchn_from_irq(irq);
  967. /* events delivered via platform PCI interrupts are always
  968. * routed to vcpu 0 */
  969. if (!VALID_EVTCHN(evtchn) ||
  970. (xen_hvm_domain() && !xen_have_vector_callback))
  971. return -1;
  972. /* Send future instances of this interrupt to other vcpu. */
  973. bind_vcpu.port = evtchn;
  974. bind_vcpu.vcpu = tcpu;
  975. /*
  976. * If this fails, it usually just indicates that we're dealing with a
  977. * virq or IPI channel, which don't actually need to be rebound. Ignore
  978. * it, but don't do the xenlinux-level rebind in that case.
  979. */
  980. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  981. bind_evtchn_to_cpu(evtchn, tcpu);
  982. return 0;
  983. }
  984. static int set_affinity_irq(unsigned irq, const struct cpumask *dest)
  985. {
  986. unsigned tcpu = cpumask_first(dest);
  987. return rebind_irq_to_cpu(irq, tcpu);
  988. }
  989. int resend_irq_on_evtchn(unsigned int irq)
  990. {
  991. int masked, evtchn = evtchn_from_irq(irq);
  992. struct shared_info *s = HYPERVISOR_shared_info;
  993. if (!VALID_EVTCHN(evtchn))
  994. return 1;
  995. masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
  996. sync_set_bit(evtchn, s->evtchn_pending);
  997. if (!masked)
  998. unmask_evtchn(evtchn);
  999. return 1;
  1000. }
  1001. static void enable_dynirq(unsigned int irq)
  1002. {
  1003. int evtchn = evtchn_from_irq(irq);
  1004. if (VALID_EVTCHN(evtchn))
  1005. unmask_evtchn(evtchn);
  1006. }
  1007. static void disable_dynirq(unsigned int irq)
  1008. {
  1009. int evtchn = evtchn_from_irq(irq);
  1010. if (VALID_EVTCHN(evtchn))
  1011. mask_evtchn(evtchn);
  1012. }
  1013. static void ack_dynirq(unsigned int irq)
  1014. {
  1015. int evtchn = evtchn_from_irq(irq);
  1016. move_masked_irq(irq);
  1017. if (VALID_EVTCHN(evtchn))
  1018. unmask_evtchn(evtchn);
  1019. }
  1020. static int retrigger_dynirq(unsigned int irq)
  1021. {
  1022. int evtchn = evtchn_from_irq(irq);
  1023. struct shared_info *sh = HYPERVISOR_shared_info;
  1024. int ret = 0;
  1025. if (VALID_EVTCHN(evtchn)) {
  1026. int masked;
  1027. masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
  1028. sync_set_bit(evtchn, sh->evtchn_pending);
  1029. if (!masked)
  1030. unmask_evtchn(evtchn);
  1031. ret = 1;
  1032. }
  1033. return ret;
  1034. }
  1035. static void restore_cpu_pirqs(void)
  1036. {
  1037. int pirq, rc, irq, gsi;
  1038. struct physdev_map_pirq map_irq;
  1039. for (pirq = 0; pirq < nr_irqs; pirq++) {
  1040. irq = pirq_to_irq[pirq];
  1041. if (irq == -1)
  1042. continue;
  1043. /* save/restore of PT devices doesn't work, so at this point the
  1044. * only devices present are GSI based emulated devices */
  1045. gsi = gsi_from_irq(irq);
  1046. if (!gsi)
  1047. continue;
  1048. map_irq.domid = DOMID_SELF;
  1049. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1050. map_irq.index = gsi;
  1051. map_irq.pirq = pirq;
  1052. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1053. if (rc) {
  1054. printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1055. gsi, irq, pirq, rc);
  1056. irq_info[irq] = mk_unbound_info();
  1057. pirq_to_irq[pirq] = -1;
  1058. continue;
  1059. }
  1060. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1061. startup_pirq(irq);
  1062. }
  1063. }
  1064. static void restore_cpu_virqs(unsigned int cpu)
  1065. {
  1066. struct evtchn_bind_virq bind_virq;
  1067. int virq, irq, evtchn;
  1068. for (virq = 0; virq < NR_VIRQS; virq++) {
  1069. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1070. continue;
  1071. BUG_ON(virq_from_irq(irq) != virq);
  1072. /* Get a new binding from Xen. */
  1073. bind_virq.virq = virq;
  1074. bind_virq.vcpu = cpu;
  1075. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1076. &bind_virq) != 0)
  1077. BUG();
  1078. evtchn = bind_virq.port;
  1079. /* Record the new mapping. */
  1080. evtchn_to_irq[evtchn] = irq;
  1081. irq_info[irq] = mk_virq_info(evtchn, virq);
  1082. bind_evtchn_to_cpu(evtchn, cpu);
  1083. }
  1084. }
  1085. static void restore_cpu_ipis(unsigned int cpu)
  1086. {
  1087. struct evtchn_bind_ipi bind_ipi;
  1088. int ipi, irq, evtchn;
  1089. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1090. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1091. continue;
  1092. BUG_ON(ipi_from_irq(irq) != ipi);
  1093. /* Get a new binding from Xen. */
  1094. bind_ipi.vcpu = cpu;
  1095. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1096. &bind_ipi) != 0)
  1097. BUG();
  1098. evtchn = bind_ipi.port;
  1099. /* Record the new mapping. */
  1100. evtchn_to_irq[evtchn] = irq;
  1101. irq_info[irq] = mk_ipi_info(evtchn, ipi);
  1102. bind_evtchn_to_cpu(evtchn, cpu);
  1103. }
  1104. }
  1105. /* Clear an irq's pending state, in preparation for polling on it */
  1106. void xen_clear_irq_pending(int irq)
  1107. {
  1108. int evtchn = evtchn_from_irq(irq);
  1109. if (VALID_EVTCHN(evtchn))
  1110. clear_evtchn(evtchn);
  1111. }
  1112. EXPORT_SYMBOL(xen_clear_irq_pending);
  1113. void xen_set_irq_pending(int irq)
  1114. {
  1115. int evtchn = evtchn_from_irq(irq);
  1116. if (VALID_EVTCHN(evtchn))
  1117. set_evtchn(evtchn);
  1118. }
  1119. bool xen_test_irq_pending(int irq)
  1120. {
  1121. int evtchn = evtchn_from_irq(irq);
  1122. bool ret = false;
  1123. if (VALID_EVTCHN(evtchn))
  1124. ret = test_evtchn(evtchn);
  1125. return ret;
  1126. }
  1127. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1128. * the irq will be disabled so it won't deliver an interrupt. */
  1129. void xen_poll_irq_timeout(int irq, u64 timeout)
  1130. {
  1131. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1132. if (VALID_EVTCHN(evtchn)) {
  1133. struct sched_poll poll;
  1134. poll.nr_ports = 1;
  1135. poll.timeout = timeout;
  1136. set_xen_guest_handle(poll.ports, &evtchn);
  1137. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1138. BUG();
  1139. }
  1140. }
  1141. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1142. /* Poll waiting for an irq to become pending. In the usual case, the
  1143. * irq will be disabled so it won't deliver an interrupt. */
  1144. void xen_poll_irq(int irq)
  1145. {
  1146. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1147. }
  1148. void xen_irq_resume(void)
  1149. {
  1150. unsigned int cpu, irq, evtchn;
  1151. struct irq_desc *desc;
  1152. init_evtchn_cpu_bindings();
  1153. /* New event-channel space is not 'live' yet. */
  1154. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1155. mask_evtchn(evtchn);
  1156. /* No IRQ <-> event-channel mappings. */
  1157. for (irq = 0; irq < nr_irqs; irq++)
  1158. irq_info[irq].evtchn = 0; /* zap event-channel binding */
  1159. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1160. evtchn_to_irq[evtchn] = -1;
  1161. for_each_possible_cpu(cpu) {
  1162. restore_cpu_virqs(cpu);
  1163. restore_cpu_ipis(cpu);
  1164. }
  1165. /*
  1166. * Unmask any IRQF_NO_SUSPEND IRQs which are enabled. These
  1167. * are not handled by the IRQ core.
  1168. */
  1169. for_each_irq_desc(irq, desc) {
  1170. if (!desc->action || !(desc->action->flags & IRQF_NO_SUSPEND))
  1171. continue;
  1172. if (desc->status & IRQ_DISABLED)
  1173. continue;
  1174. evtchn = evtchn_from_irq(irq);
  1175. if (evtchn == -1)
  1176. continue;
  1177. unmask_evtchn(evtchn);
  1178. }
  1179. restore_cpu_pirqs();
  1180. }
  1181. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1182. .name = "xen-dyn",
  1183. .disable = disable_dynirq,
  1184. .mask = disable_dynirq,
  1185. .unmask = enable_dynirq,
  1186. .eoi = ack_dynirq,
  1187. .set_affinity = set_affinity_irq,
  1188. .retrigger = retrigger_dynirq,
  1189. };
  1190. static struct irq_chip xen_pirq_chip __read_mostly = {
  1191. .name = "xen-pirq",
  1192. .startup = startup_pirq,
  1193. .shutdown = shutdown_pirq,
  1194. .enable = enable_pirq,
  1195. .unmask = enable_pirq,
  1196. .disable = disable_pirq,
  1197. .mask = disable_pirq,
  1198. .ack = ack_pirq,
  1199. .end = end_pirq,
  1200. .set_affinity = set_affinity_irq,
  1201. .retrigger = retrigger_dynirq,
  1202. };
  1203. static struct irq_chip xen_percpu_chip __read_mostly = {
  1204. .name = "xen-percpu",
  1205. .disable = disable_dynirq,
  1206. .mask = disable_dynirq,
  1207. .unmask = enable_dynirq,
  1208. .ack = ack_dynirq,
  1209. };
  1210. int xen_set_callback_via(uint64_t via)
  1211. {
  1212. struct xen_hvm_param a;
  1213. a.domid = DOMID_SELF;
  1214. a.index = HVM_PARAM_CALLBACK_IRQ;
  1215. a.value = via;
  1216. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1217. }
  1218. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1219. #ifdef CONFIG_XEN_PVHVM
  1220. /* Vector callbacks are better than PCI interrupts to receive event
  1221. * channel notifications because we can receive vector callbacks on any
  1222. * vcpu and we don't need PCI support or APIC interactions. */
  1223. void xen_callback_vector(void)
  1224. {
  1225. int rc;
  1226. uint64_t callback_via;
  1227. if (xen_have_vector_callback) {
  1228. callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
  1229. rc = xen_set_callback_via(callback_via);
  1230. if (rc) {
  1231. printk(KERN_ERR "Request for Xen HVM callback vector"
  1232. " failed.\n");
  1233. xen_have_vector_callback = 0;
  1234. return;
  1235. }
  1236. printk(KERN_INFO "Xen HVM callback vector for event delivery is "
  1237. "enabled\n");
  1238. /* in the restore case the vector has already been allocated */
  1239. if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
  1240. alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
  1241. }
  1242. }
  1243. #else
  1244. void xen_callback_vector(void) {}
  1245. #endif
  1246. void __init xen_init_IRQ(void)
  1247. {
  1248. int i;
  1249. cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
  1250. GFP_KERNEL);
  1251. irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
  1252. /* We are using nr_irqs as the maximum number of pirq available but
  1253. * that number is actually chosen by Xen and we don't know exactly
  1254. * what it is. Be careful choosing high pirq numbers. */
  1255. pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
  1256. for (i = 0; i < nr_irqs; i++)
  1257. pirq_to_irq[i] = -1;
  1258. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1259. GFP_KERNEL);
  1260. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1261. evtchn_to_irq[i] = -1;
  1262. init_evtchn_cpu_bindings();
  1263. /* No event channels are 'live' right now. */
  1264. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1265. mask_evtchn(i);
  1266. if (xen_hvm_domain()) {
  1267. xen_callback_vector();
  1268. native_init_IRQ();
  1269. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1270. * __acpi_register_gsi can point at the right function */
  1271. pci_xen_hvm_init();
  1272. } else {
  1273. irq_ctx_init(smp_processor_id());
  1274. if (xen_initial_domain())
  1275. xen_setup_pirqs();
  1276. }
  1277. }