iwl3945-base.c 122 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/wireless.h>
  42. #include <linux/firmware.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/if_arp.h>
  45. #include <net/ieee80211_radiotap.h>
  46. #include <net/mac80211.h>
  47. #include <asm/div64.h>
  48. #define DRV_NAME "iwl3945"
  49. #include "iwl-fh.h"
  50. #include "iwl-3945-fh.h"
  51. #include "iwl-commands.h"
  52. #include "iwl-sta.h"
  53. #include "iwl-3945.h"
  54. #include "iwl-core.h"
  55. #include "iwl-helpers.h"
  56. #include "iwl-dev.h"
  57. #include "iwl-spectrum.h"
  58. #include "iwl-legacy.h"
  59. /*
  60. * module name, copyright, version, etc.
  61. */
  62. #define DRV_DESCRIPTION \
  63. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  64. #ifdef CONFIG_IWLWIFI_DEBUG
  65. #define VD "d"
  66. #else
  67. #define VD
  68. #endif
  69. /*
  70. * add "s" to indicate spectrum measurement included.
  71. * we add it here to be consistent with previous releases in which
  72. * this was configurable.
  73. */
  74. #define DRV_VERSION IWLWIFI_VERSION VD "s"
  75. #define DRV_COPYRIGHT "Copyright(c) 2003-2010 Intel Corporation"
  76. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  77. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  78. MODULE_VERSION(DRV_VERSION);
  79. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  80. MODULE_LICENSE("GPL");
  81. /* module parameters */
  82. struct iwl_mod_params iwl3945_mod_params = {
  83. .sw_crypto = 1,
  84. .restart_fw = 1,
  85. /* the rest are 0 by default */
  86. };
  87. /**
  88. * iwl3945_get_antenna_flags - Get antenna flags for RXON command
  89. * @priv: eeprom and antenna fields are used to determine antenna flags
  90. *
  91. * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
  92. * iwl3945_mod_params.antenna specifies the antenna diversity mode:
  93. *
  94. * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
  95. * IWL_ANTENNA_MAIN - Force MAIN antenna
  96. * IWL_ANTENNA_AUX - Force AUX antenna
  97. */
  98. __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
  99. {
  100. struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  101. switch (iwl3945_mod_params.antenna) {
  102. case IWL_ANTENNA_DIVERSITY:
  103. return 0;
  104. case IWL_ANTENNA_MAIN:
  105. if (eeprom->antenna_switch_type)
  106. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  107. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  108. case IWL_ANTENNA_AUX:
  109. if (eeprom->antenna_switch_type)
  110. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
  111. return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
  112. }
  113. /* bad antenna selector value */
  114. IWL_ERR(priv, "Bad antenna selector value (0x%x)\n",
  115. iwl3945_mod_params.antenna);
  116. return 0; /* "diversity" is default if error */
  117. }
  118. static int iwl3945_set_ccmp_dynamic_key_info(struct iwl_priv *priv,
  119. struct ieee80211_key_conf *keyconf,
  120. u8 sta_id)
  121. {
  122. unsigned long flags;
  123. __le16 key_flags = 0;
  124. int ret;
  125. key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
  126. key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  127. if (sta_id == priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id)
  128. key_flags |= STA_KEY_MULTICAST_MSK;
  129. keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  130. keyconf->hw_key_idx = keyconf->keyidx;
  131. key_flags &= ~STA_KEY_FLG_INVALID;
  132. spin_lock_irqsave(&priv->sta_lock, flags);
  133. priv->stations[sta_id].keyinfo.cipher = keyconf->cipher;
  134. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  135. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  136. keyconf->keylen);
  137. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  138. keyconf->keylen);
  139. if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
  140. == STA_KEY_FLG_NO_ENC)
  141. priv->stations[sta_id].sta.key.key_offset =
  142. iwl_get_free_ucode_key_index(priv);
  143. /* else, we are overriding an existing key => no need to allocated room
  144. * in uCode. */
  145. WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
  146. "no space for a new key");
  147. priv->stations[sta_id].sta.key.key_flags = key_flags;
  148. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  149. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  150. IWL_DEBUG_INFO(priv, "hwcrypto: modify ucode station key info\n");
  151. ret = iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  152. spin_unlock_irqrestore(&priv->sta_lock, flags);
  153. return ret;
  154. }
  155. static int iwl3945_set_tkip_dynamic_key_info(struct iwl_priv *priv,
  156. struct ieee80211_key_conf *keyconf,
  157. u8 sta_id)
  158. {
  159. return -EOPNOTSUPP;
  160. }
  161. static int iwl3945_set_wep_dynamic_key_info(struct iwl_priv *priv,
  162. struct ieee80211_key_conf *keyconf,
  163. u8 sta_id)
  164. {
  165. return -EOPNOTSUPP;
  166. }
  167. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  168. {
  169. unsigned long flags;
  170. struct iwl_addsta_cmd sta_cmd;
  171. spin_lock_irqsave(&priv->sta_lock, flags);
  172. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl_hw_key));
  173. memset(&priv->stations[sta_id].sta.key, 0,
  174. sizeof(struct iwl4965_keyinfo));
  175. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  176. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  177. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  178. memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(struct iwl_addsta_cmd));
  179. spin_unlock_irqrestore(&priv->sta_lock, flags);
  180. IWL_DEBUG_INFO(priv, "hwcrypto: clear ucode station key info\n");
  181. return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC);
  182. }
  183. static int iwl3945_set_dynamic_key(struct iwl_priv *priv,
  184. struct ieee80211_key_conf *keyconf, u8 sta_id)
  185. {
  186. int ret = 0;
  187. keyconf->hw_key_idx = HW_KEY_DYNAMIC;
  188. switch (keyconf->cipher) {
  189. case WLAN_CIPHER_SUITE_CCMP:
  190. ret = iwl3945_set_ccmp_dynamic_key_info(priv, keyconf, sta_id);
  191. break;
  192. case WLAN_CIPHER_SUITE_TKIP:
  193. ret = iwl3945_set_tkip_dynamic_key_info(priv, keyconf, sta_id);
  194. break;
  195. case WLAN_CIPHER_SUITE_WEP40:
  196. case WLAN_CIPHER_SUITE_WEP104:
  197. ret = iwl3945_set_wep_dynamic_key_info(priv, keyconf, sta_id);
  198. break;
  199. default:
  200. IWL_ERR(priv, "Unknown alg: %s alg=%x\n", __func__,
  201. keyconf->cipher);
  202. ret = -EINVAL;
  203. }
  204. IWL_DEBUG_WEP(priv, "Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
  205. keyconf->cipher, keyconf->keylen, keyconf->keyidx,
  206. sta_id, ret);
  207. return ret;
  208. }
  209. static int iwl3945_remove_static_key(struct iwl_priv *priv)
  210. {
  211. int ret = -EOPNOTSUPP;
  212. return ret;
  213. }
  214. static int iwl3945_set_static_key(struct iwl_priv *priv,
  215. struct ieee80211_key_conf *key)
  216. {
  217. if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  218. key->cipher == WLAN_CIPHER_SUITE_WEP104)
  219. return -EOPNOTSUPP;
  220. IWL_ERR(priv, "Static key invalid: cipher %x\n", key->cipher);
  221. return -EINVAL;
  222. }
  223. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  224. {
  225. struct list_head *element;
  226. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  227. priv->frames_count);
  228. while (!list_empty(&priv->free_frames)) {
  229. element = priv->free_frames.next;
  230. list_del(element);
  231. kfree(list_entry(element, struct iwl3945_frame, list));
  232. priv->frames_count--;
  233. }
  234. if (priv->frames_count) {
  235. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  236. priv->frames_count);
  237. priv->frames_count = 0;
  238. }
  239. }
  240. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  241. {
  242. struct iwl3945_frame *frame;
  243. struct list_head *element;
  244. if (list_empty(&priv->free_frames)) {
  245. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  246. if (!frame) {
  247. IWL_ERR(priv, "Could not allocate frame!\n");
  248. return NULL;
  249. }
  250. priv->frames_count++;
  251. return frame;
  252. }
  253. element = priv->free_frames.next;
  254. list_del(element);
  255. return list_entry(element, struct iwl3945_frame, list);
  256. }
  257. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  258. {
  259. memset(frame, 0, sizeof(*frame));
  260. list_add(&frame->list, &priv->free_frames);
  261. }
  262. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  263. struct ieee80211_hdr *hdr,
  264. int left)
  265. {
  266. if (!iwl_is_associated(priv, IWL_RXON_CTX_BSS) || !priv->beacon_skb)
  267. return 0;
  268. if (priv->beacon_skb->len > left)
  269. return 0;
  270. memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
  271. return priv->beacon_skb->len;
  272. }
  273. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  274. {
  275. struct iwl3945_frame *frame;
  276. unsigned int frame_size;
  277. int rc;
  278. u8 rate;
  279. frame = iwl3945_get_free_frame(priv);
  280. if (!frame) {
  281. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  282. "command.\n");
  283. return -ENOMEM;
  284. }
  285. rate = iwl_rate_get_lowest_plcp(priv,
  286. &priv->contexts[IWL_RXON_CTX_BSS]);
  287. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  288. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  289. &frame->u.cmd[0]);
  290. iwl3945_free_frame(priv, frame);
  291. return rc;
  292. }
  293. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  294. {
  295. if (priv->_3945.shared_virt)
  296. dma_free_coherent(&priv->pci_dev->dev,
  297. sizeof(struct iwl3945_shared),
  298. priv->_3945.shared_virt,
  299. priv->_3945.shared_phys);
  300. }
  301. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  302. struct ieee80211_tx_info *info,
  303. struct iwl_device_cmd *cmd,
  304. struct sk_buff *skb_frag,
  305. int sta_id)
  306. {
  307. struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  308. struct iwl_hw_key *keyinfo = &priv->stations[sta_id].keyinfo;
  309. tx_cmd->sec_ctl = 0;
  310. switch (keyinfo->cipher) {
  311. case WLAN_CIPHER_SUITE_CCMP:
  312. tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
  313. memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
  314. IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
  315. break;
  316. case WLAN_CIPHER_SUITE_TKIP:
  317. break;
  318. case WLAN_CIPHER_SUITE_WEP104:
  319. tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
  320. /* fall through */
  321. case WLAN_CIPHER_SUITE_WEP40:
  322. tx_cmd->sec_ctl |= TX_CMD_SEC_WEP |
  323. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  324. memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
  325. IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
  326. "with key %d\n", info->control.hw_key->hw_key_idx);
  327. break;
  328. default:
  329. IWL_ERR(priv, "Unknown encode cipher %x\n", keyinfo->cipher);
  330. break;
  331. }
  332. }
  333. /*
  334. * handle build REPLY_TX command notification.
  335. */
  336. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  337. struct iwl_device_cmd *cmd,
  338. struct ieee80211_tx_info *info,
  339. struct ieee80211_hdr *hdr, u8 std_id)
  340. {
  341. struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  342. __le32 tx_flags = tx_cmd->tx_flags;
  343. __le16 fc = hdr->frame_control;
  344. tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  345. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  346. tx_flags |= TX_CMD_FLG_ACK_MSK;
  347. if (ieee80211_is_mgmt(fc))
  348. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  349. if (ieee80211_is_probe_resp(fc) &&
  350. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  351. tx_flags |= TX_CMD_FLG_TSF_MSK;
  352. } else {
  353. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  354. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  355. }
  356. tx_cmd->sta_id = std_id;
  357. if (ieee80211_has_morefrags(fc))
  358. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  359. if (ieee80211_is_data_qos(fc)) {
  360. u8 *qc = ieee80211_get_qos_ctl(hdr);
  361. tx_cmd->tid_tspec = qc[0] & 0xf;
  362. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  363. } else {
  364. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  365. }
  366. priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags);
  367. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  368. if (ieee80211_is_mgmt(fc)) {
  369. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  370. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
  371. else
  372. tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
  373. } else {
  374. tx_cmd->timeout.pm_frame_timeout = 0;
  375. }
  376. tx_cmd->driver_txop = 0;
  377. tx_cmd->tx_flags = tx_flags;
  378. tx_cmd->next_frame_len = 0;
  379. }
  380. /*
  381. * start REPLY_TX command process
  382. */
  383. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  384. {
  385. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  386. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  387. struct iwl3945_tx_cmd *tx_cmd;
  388. struct iwl_tx_queue *txq = NULL;
  389. struct iwl_queue *q = NULL;
  390. struct iwl_device_cmd *out_cmd;
  391. struct iwl_cmd_meta *out_meta;
  392. dma_addr_t phys_addr;
  393. dma_addr_t txcmd_phys;
  394. int txq_id = skb_get_queue_mapping(skb);
  395. u16 len, idx, hdr_len;
  396. u8 id;
  397. u8 unicast;
  398. u8 sta_id;
  399. u8 tid = 0;
  400. __le16 fc;
  401. u8 wait_write_ptr = 0;
  402. unsigned long flags;
  403. spin_lock_irqsave(&priv->lock, flags);
  404. if (iwl_is_rfkill(priv)) {
  405. IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
  406. goto drop_unlock;
  407. }
  408. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  409. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  410. goto drop_unlock;
  411. }
  412. unicast = !is_multicast_ether_addr(hdr->addr1);
  413. id = 0;
  414. fc = hdr->frame_control;
  415. #ifdef CONFIG_IWLWIFI_DEBUG
  416. if (ieee80211_is_auth(fc))
  417. IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
  418. else if (ieee80211_is_assoc_req(fc))
  419. IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
  420. else if (ieee80211_is_reassoc_req(fc))
  421. IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
  422. #endif
  423. spin_unlock_irqrestore(&priv->lock, flags);
  424. hdr_len = ieee80211_hdrlen(fc);
  425. /* Find index into station table for destination station */
  426. sta_id = iwl_sta_id_or_broadcast(
  427. priv, &priv->contexts[IWL_RXON_CTX_BSS],
  428. info->control.sta);
  429. if (sta_id == IWL_INVALID_STATION) {
  430. IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
  431. hdr->addr1);
  432. goto drop;
  433. }
  434. IWL_DEBUG_RATE(priv, "station Id %d\n", sta_id);
  435. if (ieee80211_is_data_qos(fc)) {
  436. u8 *qc = ieee80211_get_qos_ctl(hdr);
  437. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  438. if (unlikely(tid >= MAX_TID_COUNT))
  439. goto drop;
  440. }
  441. /* Descriptor for chosen Tx queue */
  442. txq = &priv->txq[txq_id];
  443. q = &txq->q;
  444. if ((iwl_queue_space(q) < q->high_mark))
  445. goto drop;
  446. spin_lock_irqsave(&priv->lock, flags);
  447. idx = get_cmd_index(q, q->write_ptr, 0);
  448. /* Set up driver data for this TFD */
  449. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
  450. txq->txb[q->write_ptr].skb = skb;
  451. txq->txb[q->write_ptr].ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  452. /* Init first empty entry in queue's array of Tx/cmd buffers */
  453. out_cmd = txq->cmd[idx];
  454. out_meta = &txq->meta[idx];
  455. tx_cmd = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
  456. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  457. memset(tx_cmd, 0, sizeof(*tx_cmd));
  458. /*
  459. * Set up the Tx-command (not MAC!) header.
  460. * Store the chosen Tx queue and TFD index within the sequence field;
  461. * after Tx, uCode's Tx response will return this value so driver can
  462. * locate the frame within the tx queue and do post-tx processing.
  463. */
  464. out_cmd->hdr.cmd = REPLY_TX;
  465. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  466. INDEX_TO_SEQ(q->write_ptr)));
  467. /* Copy MAC header from skb into command buffer */
  468. memcpy(tx_cmd->hdr, hdr, hdr_len);
  469. if (info->control.hw_key)
  470. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, sta_id);
  471. /* TODO need this for burst mode later on */
  472. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
  473. /* set is_hcca to 0; it probably will never be implemented */
  474. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  475. /* Total # bytes to be transmitted */
  476. len = (u16)skb->len;
  477. tx_cmd->len = cpu_to_le16(len);
  478. iwl_dbg_log_tx_data_frame(priv, len, hdr);
  479. iwl_update_stats(priv, true, fc, len);
  480. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  481. tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  482. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  483. txq->need_update = 1;
  484. } else {
  485. wait_write_ptr = 1;
  486. txq->need_update = 0;
  487. }
  488. IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
  489. le16_to_cpu(out_cmd->hdr.sequence));
  490. IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
  491. iwl_print_hex_dump(priv, IWL_DL_TX, tx_cmd, sizeof(*tx_cmd));
  492. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr,
  493. ieee80211_hdrlen(fc));
  494. /*
  495. * Use the first empty entry in this queue's command buffer array
  496. * to contain the Tx command and MAC header concatenated together
  497. * (payload data will be in another buffer).
  498. * Size of this varies, due to varying MAC header length.
  499. * If end is not dword aligned, we'll have 2 extra bytes at the end
  500. * of the MAC header (device reads on dword boundaries).
  501. * We'll tell device about this padding later.
  502. */
  503. len = sizeof(struct iwl3945_tx_cmd) +
  504. sizeof(struct iwl_cmd_header) + hdr_len;
  505. len = (len + 3) & ~3;
  506. /* Physical address of this Tx command's header (not MAC header!),
  507. * within command buffer array. */
  508. txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
  509. len, PCI_DMA_TODEVICE);
  510. /* we do not map meta data ... so we can safely access address to
  511. * provide to unmap command*/
  512. dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
  513. dma_unmap_len_set(out_meta, len, len);
  514. /* Add buffer containing Tx command and MAC(!) header to TFD's
  515. * first entry */
  516. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  517. txcmd_phys, len, 1, 0);
  518. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  519. * if any (802.11 null frames have no payload). */
  520. len = skb->len - hdr_len;
  521. if (len) {
  522. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  523. len, PCI_DMA_TODEVICE);
  524. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  525. phys_addr, len,
  526. 0, U32_PAD(len));
  527. }
  528. /* Tell device the write index *just past* this latest filled TFD */
  529. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  530. iwl_txq_update_write_ptr(priv, txq);
  531. spin_unlock_irqrestore(&priv->lock, flags);
  532. if ((iwl_queue_space(q) < q->high_mark)
  533. && priv->mac80211_registered) {
  534. if (wait_write_ptr) {
  535. spin_lock_irqsave(&priv->lock, flags);
  536. txq->need_update = 1;
  537. iwl_txq_update_write_ptr(priv, txq);
  538. spin_unlock_irqrestore(&priv->lock, flags);
  539. }
  540. iwl_stop_queue(priv, txq);
  541. }
  542. return 0;
  543. drop_unlock:
  544. spin_unlock_irqrestore(&priv->lock, flags);
  545. drop:
  546. return -1;
  547. }
  548. static int iwl3945_get_measurement(struct iwl_priv *priv,
  549. struct ieee80211_measurement_params *params,
  550. u8 type)
  551. {
  552. struct iwl_spectrum_cmd spectrum;
  553. struct iwl_rx_packet *pkt;
  554. struct iwl_host_cmd cmd = {
  555. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  556. .data = (void *)&spectrum,
  557. .flags = CMD_WANT_SKB,
  558. };
  559. u32 add_time = le64_to_cpu(params->start_time);
  560. int rc;
  561. int spectrum_resp_status;
  562. int duration = le16_to_cpu(params->duration);
  563. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  564. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS))
  565. add_time = iwl_usecs_to_beacons(priv,
  566. le64_to_cpu(params->start_time) - priv->_3945.last_tsf,
  567. le16_to_cpu(ctx->timing.beacon_interval));
  568. memset(&spectrum, 0, sizeof(spectrum));
  569. spectrum.channel_count = cpu_to_le16(1);
  570. spectrum.flags =
  571. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  572. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  573. cmd.len = sizeof(spectrum);
  574. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  575. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS))
  576. spectrum.start_time =
  577. iwl_add_beacon_time(priv,
  578. priv->_3945.last_beacon_time, add_time,
  579. le16_to_cpu(ctx->timing.beacon_interval));
  580. else
  581. spectrum.start_time = 0;
  582. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  583. spectrum.channels[0].channel = params->channel;
  584. spectrum.channels[0].type = type;
  585. if (ctx->active.flags & RXON_FLG_BAND_24G_MSK)
  586. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  587. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  588. rc = iwl_send_cmd_sync(priv, &cmd);
  589. if (rc)
  590. return rc;
  591. pkt = (struct iwl_rx_packet *)cmd.reply_page;
  592. if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
  593. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  594. rc = -EIO;
  595. }
  596. spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
  597. switch (spectrum_resp_status) {
  598. case 0: /* Command will be handled */
  599. if (pkt->u.spectrum.id != 0xff) {
  600. IWL_DEBUG_INFO(priv, "Replaced existing measurement: %d\n",
  601. pkt->u.spectrum.id);
  602. priv->measurement_status &= ~MEASUREMENT_READY;
  603. }
  604. priv->measurement_status |= MEASUREMENT_ACTIVE;
  605. rc = 0;
  606. break;
  607. case 1: /* Command will not be handled */
  608. rc = -EAGAIN;
  609. break;
  610. }
  611. iwl_free_pages(priv, cmd.reply_page);
  612. return rc;
  613. }
  614. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  615. struct iwl_rx_mem_buffer *rxb)
  616. {
  617. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  618. struct iwl_alive_resp *palive;
  619. struct delayed_work *pwork;
  620. palive = &pkt->u.alive_frame;
  621. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  622. "0x%01X 0x%01X\n",
  623. palive->is_valid, palive->ver_type,
  624. palive->ver_subtype);
  625. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  626. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  627. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  628. sizeof(struct iwl_alive_resp));
  629. pwork = &priv->init_alive_start;
  630. } else {
  631. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  632. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  633. sizeof(struct iwl_alive_resp));
  634. pwork = &priv->alive_start;
  635. iwl3945_disable_events(priv);
  636. }
  637. /* We delay the ALIVE response by 5ms to
  638. * give the HW RF Kill time to activate... */
  639. if (palive->is_valid == UCODE_VALID_OK)
  640. queue_delayed_work(priv->workqueue, pwork,
  641. msecs_to_jiffies(5));
  642. else
  643. IWL_WARN(priv, "uCode did not respond OK.\n");
  644. }
  645. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  646. struct iwl_rx_mem_buffer *rxb)
  647. {
  648. #ifdef CONFIG_IWLWIFI_DEBUG
  649. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  650. #endif
  651. IWL_DEBUG_RX(priv, "Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  652. }
  653. static void iwl3945_bg_beacon_update(struct work_struct *work)
  654. {
  655. struct iwl_priv *priv =
  656. container_of(work, struct iwl_priv, beacon_update);
  657. struct sk_buff *beacon;
  658. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  659. beacon = ieee80211_beacon_get(priv->hw,
  660. priv->contexts[IWL_RXON_CTX_BSS].vif);
  661. if (!beacon) {
  662. IWL_ERR(priv, "update beacon failed\n");
  663. return;
  664. }
  665. mutex_lock(&priv->mutex);
  666. /* new beacon skb is allocated every time; dispose previous.*/
  667. if (priv->beacon_skb)
  668. dev_kfree_skb(priv->beacon_skb);
  669. priv->beacon_skb = beacon;
  670. mutex_unlock(&priv->mutex);
  671. iwl3945_send_beacon_cmd(priv);
  672. }
  673. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  674. struct iwl_rx_mem_buffer *rxb)
  675. {
  676. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  677. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  678. #ifdef CONFIG_IWLWIFI_DEBUG
  679. u8 rate = beacon->beacon_notify_hdr.rate;
  680. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  681. "tsf %d %d rate %d\n",
  682. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  683. beacon->beacon_notify_hdr.failure_frame,
  684. le32_to_cpu(beacon->ibss_mgr_status),
  685. le32_to_cpu(beacon->high_tsf),
  686. le32_to_cpu(beacon->low_tsf), rate);
  687. #endif
  688. priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
  689. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  690. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  691. queue_work(priv->workqueue, &priv->beacon_update);
  692. }
  693. /* Handle notification from uCode that card's power state is changing
  694. * due to software, hardware, or critical temperature RFKILL */
  695. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  696. struct iwl_rx_mem_buffer *rxb)
  697. {
  698. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  699. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  700. unsigned long status = priv->status;
  701. IWL_WARN(priv, "Card state received: HW:%s SW:%s\n",
  702. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  703. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  704. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  705. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  706. if (flags & HW_CARD_DISABLED)
  707. set_bit(STATUS_RF_KILL_HW, &priv->status);
  708. else
  709. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  710. iwl_scan_cancel(priv);
  711. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  712. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  713. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  714. test_bit(STATUS_RF_KILL_HW, &priv->status));
  715. else
  716. wake_up_interruptible(&priv->wait_command_queue);
  717. }
  718. /**
  719. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  720. *
  721. * Setup the RX handlers for each of the reply types sent from the uCode
  722. * to the host.
  723. *
  724. * This function chains into the hardware specific files for them to setup
  725. * any hardware specific handlers as well.
  726. */
  727. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  728. {
  729. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  730. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  731. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  732. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  733. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  734. iwl_rx_spectrum_measure_notif;
  735. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  736. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  737. iwl_rx_pm_debug_statistics_notif;
  738. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  739. /*
  740. * The same handler is used for both the REPLY to a discrete
  741. * statistics request from the host as well as for the periodic
  742. * statistics notifications (after received beacons) from the uCode.
  743. */
  744. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_reply_statistics;
  745. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  746. iwl_setup_rx_scan_handlers(priv);
  747. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  748. /* Set up hardware specific Rx handlers */
  749. iwl3945_hw_rx_handler_setup(priv);
  750. }
  751. /************************** RX-FUNCTIONS ****************************/
  752. /*
  753. * Rx theory of operation
  754. *
  755. * The host allocates 32 DMA target addresses and passes the host address
  756. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  757. * 0 to 31
  758. *
  759. * Rx Queue Indexes
  760. * The host/firmware share two index registers for managing the Rx buffers.
  761. *
  762. * The READ index maps to the first position that the firmware may be writing
  763. * to -- the driver can read up to (but not including) this position and get
  764. * good data.
  765. * The READ index is managed by the firmware once the card is enabled.
  766. *
  767. * The WRITE index maps to the last position the driver has read from -- the
  768. * position preceding WRITE is the last slot the firmware can place a packet.
  769. *
  770. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  771. * WRITE = READ.
  772. *
  773. * During initialization, the host sets up the READ queue position to the first
  774. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  775. *
  776. * When the firmware places a packet in a buffer, it will advance the READ index
  777. * and fire the RX interrupt. The driver can then query the READ index and
  778. * process as many packets as possible, moving the WRITE index forward as it
  779. * resets the Rx queue buffers with new memory.
  780. *
  781. * The management in the driver is as follows:
  782. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  783. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  784. * to replenish the iwl->rxq->rx_free.
  785. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  786. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  787. * 'processed' and 'read' driver indexes as well)
  788. * + A received packet is processed and handed to the kernel network stack,
  789. * detached from the iwl->rxq. The driver 'processed' index is updated.
  790. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  791. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  792. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  793. * were enough free buffers and RX_STALLED is set it is cleared.
  794. *
  795. *
  796. * Driver sequence:
  797. *
  798. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  799. * iwl3945_rx_queue_restock
  800. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  801. * queue, updates firmware pointers, and updates
  802. * the WRITE index. If insufficient rx_free buffers
  803. * are available, schedules iwl3945_rx_replenish
  804. *
  805. * -- enable interrupts --
  806. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  807. * READ INDEX, detaching the SKB from the pool.
  808. * Moves the packet buffer from queue to rx_used.
  809. * Calls iwl3945_rx_queue_restock to refill any empty
  810. * slots.
  811. * ...
  812. *
  813. */
  814. /**
  815. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  816. */
  817. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  818. dma_addr_t dma_addr)
  819. {
  820. return cpu_to_le32((u32)dma_addr);
  821. }
  822. /**
  823. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  824. *
  825. * If there are slots in the RX queue that need to be restocked,
  826. * and we have free pre-allocated buffers, fill the ranks as much
  827. * as we can, pulling from rx_free.
  828. *
  829. * This moves the 'write' index forward to catch up with 'processed', and
  830. * also updates the memory address in the firmware to reference the new
  831. * target buffer.
  832. */
  833. static void iwl3945_rx_queue_restock(struct iwl_priv *priv)
  834. {
  835. struct iwl_rx_queue *rxq = &priv->rxq;
  836. struct list_head *element;
  837. struct iwl_rx_mem_buffer *rxb;
  838. unsigned long flags;
  839. int write;
  840. spin_lock_irqsave(&rxq->lock, flags);
  841. write = rxq->write & ~0x7;
  842. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  843. /* Get next free Rx buffer, remove from free list */
  844. element = rxq->rx_free.next;
  845. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  846. list_del(element);
  847. /* Point to Rx buffer via next RBD in circular buffer */
  848. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->page_dma);
  849. rxq->queue[rxq->write] = rxb;
  850. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  851. rxq->free_count--;
  852. }
  853. spin_unlock_irqrestore(&rxq->lock, flags);
  854. /* If the pre-allocated buffer pool is dropping low, schedule to
  855. * refill it */
  856. if (rxq->free_count <= RX_LOW_WATERMARK)
  857. queue_work(priv->workqueue, &priv->rx_replenish);
  858. /* If we've added more space for the firmware to place data, tell it.
  859. * Increment device's write pointer in multiples of 8. */
  860. if ((rxq->write_actual != (rxq->write & ~0x7))
  861. || (abs(rxq->write - rxq->read) > 7)) {
  862. spin_lock_irqsave(&rxq->lock, flags);
  863. rxq->need_update = 1;
  864. spin_unlock_irqrestore(&rxq->lock, flags);
  865. iwl_rx_queue_update_write_ptr(priv, rxq);
  866. }
  867. }
  868. /**
  869. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  870. *
  871. * When moving to rx_free an SKB is allocated for the slot.
  872. *
  873. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  874. * This is called as a scheduled work item (except for during initialization)
  875. */
  876. static void iwl3945_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  877. {
  878. struct iwl_rx_queue *rxq = &priv->rxq;
  879. struct list_head *element;
  880. struct iwl_rx_mem_buffer *rxb;
  881. struct page *page;
  882. unsigned long flags;
  883. gfp_t gfp_mask = priority;
  884. while (1) {
  885. spin_lock_irqsave(&rxq->lock, flags);
  886. if (list_empty(&rxq->rx_used)) {
  887. spin_unlock_irqrestore(&rxq->lock, flags);
  888. return;
  889. }
  890. spin_unlock_irqrestore(&rxq->lock, flags);
  891. if (rxq->free_count > RX_LOW_WATERMARK)
  892. gfp_mask |= __GFP_NOWARN;
  893. if (priv->hw_params.rx_page_order > 0)
  894. gfp_mask |= __GFP_COMP;
  895. /* Alloc a new receive buffer */
  896. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  897. if (!page) {
  898. if (net_ratelimit())
  899. IWL_DEBUG_INFO(priv, "Failed to allocate SKB buffer.\n");
  900. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  901. net_ratelimit())
  902. IWL_CRIT(priv, "Failed to allocate SKB buffer with %s. Only %u free buffers remaining.\n",
  903. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  904. rxq->free_count);
  905. /* We don't reschedule replenish work here -- we will
  906. * call the restock method and if it still needs
  907. * more buffers it will schedule replenish */
  908. break;
  909. }
  910. spin_lock_irqsave(&rxq->lock, flags);
  911. if (list_empty(&rxq->rx_used)) {
  912. spin_unlock_irqrestore(&rxq->lock, flags);
  913. __free_pages(page, priv->hw_params.rx_page_order);
  914. return;
  915. }
  916. element = rxq->rx_used.next;
  917. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  918. list_del(element);
  919. spin_unlock_irqrestore(&rxq->lock, flags);
  920. rxb->page = page;
  921. /* Get physical address of RB/SKB */
  922. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  923. PAGE_SIZE << priv->hw_params.rx_page_order,
  924. PCI_DMA_FROMDEVICE);
  925. spin_lock_irqsave(&rxq->lock, flags);
  926. list_add_tail(&rxb->list, &rxq->rx_free);
  927. rxq->free_count++;
  928. priv->alloc_rxb_page++;
  929. spin_unlock_irqrestore(&rxq->lock, flags);
  930. }
  931. }
  932. void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  933. {
  934. unsigned long flags;
  935. int i;
  936. spin_lock_irqsave(&rxq->lock, flags);
  937. INIT_LIST_HEAD(&rxq->rx_free);
  938. INIT_LIST_HEAD(&rxq->rx_used);
  939. /* Fill the rx_used queue with _all_ of the Rx buffers */
  940. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  941. /* In the reset function, these buffers may have been allocated
  942. * to an SKB, so we need to unmap and free potential storage */
  943. if (rxq->pool[i].page != NULL) {
  944. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  945. PAGE_SIZE << priv->hw_params.rx_page_order,
  946. PCI_DMA_FROMDEVICE);
  947. __iwl_free_pages(priv, rxq->pool[i].page);
  948. rxq->pool[i].page = NULL;
  949. }
  950. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  951. }
  952. /* Set us so that we have processed and used all buffers, but have
  953. * not restocked the Rx queue with fresh buffers */
  954. rxq->read = rxq->write = 0;
  955. rxq->write_actual = 0;
  956. rxq->free_count = 0;
  957. spin_unlock_irqrestore(&rxq->lock, flags);
  958. }
  959. void iwl3945_rx_replenish(void *data)
  960. {
  961. struct iwl_priv *priv = data;
  962. unsigned long flags;
  963. iwl3945_rx_allocate(priv, GFP_KERNEL);
  964. spin_lock_irqsave(&priv->lock, flags);
  965. iwl3945_rx_queue_restock(priv);
  966. spin_unlock_irqrestore(&priv->lock, flags);
  967. }
  968. static void iwl3945_rx_replenish_now(struct iwl_priv *priv)
  969. {
  970. iwl3945_rx_allocate(priv, GFP_ATOMIC);
  971. iwl3945_rx_queue_restock(priv);
  972. }
  973. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  974. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  975. * This free routine walks the list of POOL entries and if SKB is set to
  976. * non NULL it is unmapped and freed
  977. */
  978. static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  979. {
  980. int i;
  981. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  982. if (rxq->pool[i].page != NULL) {
  983. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  984. PAGE_SIZE << priv->hw_params.rx_page_order,
  985. PCI_DMA_FROMDEVICE);
  986. __iwl_free_pages(priv, rxq->pool[i].page);
  987. rxq->pool[i].page = NULL;
  988. }
  989. }
  990. dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  991. rxq->bd_dma);
  992. dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
  993. rxq->rb_stts, rxq->rb_stts_dma);
  994. rxq->bd = NULL;
  995. rxq->rb_stts = NULL;
  996. }
  997. /* Convert linear signal-to-noise ratio into dB */
  998. static u8 ratio2dB[100] = {
  999. /* 0 1 2 3 4 5 6 7 8 9 */
  1000. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  1001. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  1002. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  1003. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  1004. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  1005. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  1006. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  1007. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  1008. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  1009. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  1010. };
  1011. /* Calculates a relative dB value from a ratio of linear
  1012. * (i.e. not dB) signal levels.
  1013. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  1014. int iwl3945_calc_db_from_ratio(int sig_ratio)
  1015. {
  1016. /* 1000:1 or higher just report as 60 dB */
  1017. if (sig_ratio >= 1000)
  1018. return 60;
  1019. /* 100:1 or higher, divide by 10 and use table,
  1020. * add 20 dB to make up for divide by 10 */
  1021. if (sig_ratio >= 100)
  1022. return 20 + (int)ratio2dB[sig_ratio/10];
  1023. /* We shouldn't see this */
  1024. if (sig_ratio < 1)
  1025. return 0;
  1026. /* Use table for ratios 1:1 - 99:1 */
  1027. return (int)ratio2dB[sig_ratio];
  1028. }
  1029. /**
  1030. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  1031. *
  1032. * Uses the priv->rx_handlers callback function array to invoke
  1033. * the appropriate handlers, including command responses,
  1034. * frame-received notifications, and other notifications.
  1035. */
  1036. static void iwl3945_rx_handle(struct iwl_priv *priv)
  1037. {
  1038. struct iwl_rx_mem_buffer *rxb;
  1039. struct iwl_rx_packet *pkt;
  1040. struct iwl_rx_queue *rxq = &priv->rxq;
  1041. u32 r, i;
  1042. int reclaim;
  1043. unsigned long flags;
  1044. u8 fill_rx = 0;
  1045. u32 count = 8;
  1046. int total_empty = 0;
  1047. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  1048. * buffer that the driver may process (last buffer filled by ucode). */
  1049. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  1050. i = rxq->read;
  1051. /* calculate total frames need to be restock after handling RX */
  1052. total_empty = r - rxq->write_actual;
  1053. if (total_empty < 0)
  1054. total_empty += RX_QUEUE_SIZE;
  1055. if (total_empty > (RX_QUEUE_SIZE / 2))
  1056. fill_rx = 1;
  1057. /* Rx interrupt, but nothing sent from uCode */
  1058. if (i == r)
  1059. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  1060. while (i != r) {
  1061. int len;
  1062. rxb = rxq->queue[i];
  1063. /* If an RXB doesn't have a Rx queue slot associated with it,
  1064. * then a bug has been introduced in the queue refilling
  1065. * routines -- catch it here */
  1066. BUG_ON(rxb == NULL);
  1067. rxq->queue[i] = NULL;
  1068. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  1069. PAGE_SIZE << priv->hw_params.rx_page_order,
  1070. PCI_DMA_FROMDEVICE);
  1071. pkt = rxb_addr(rxb);
  1072. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1073. len += sizeof(u32); /* account for status word */
  1074. trace_iwlwifi_dev_rx(priv, pkt, len);
  1075. /* Reclaim a command buffer only if this packet is a response
  1076. * to a (driver-originated) command.
  1077. * If the packet (e.g. Rx frame) originated from uCode,
  1078. * there is no command buffer to reclaim.
  1079. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  1080. * but apparently a few don't get set; catch them here. */
  1081. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  1082. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  1083. (pkt->hdr.cmd != REPLY_TX);
  1084. /* Based on type of command response or notification,
  1085. * handle those that need handling via function in
  1086. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  1087. if (priv->rx_handlers[pkt->hdr.cmd]) {
  1088. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, i,
  1089. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  1090. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  1091. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  1092. } else {
  1093. /* No handling needed */
  1094. IWL_DEBUG_RX(priv,
  1095. "r %d i %d No handler needed for %s, 0x%02x\n",
  1096. r, i, get_cmd_string(pkt->hdr.cmd),
  1097. pkt->hdr.cmd);
  1098. }
  1099. /*
  1100. * XXX: After here, we should always check rxb->page
  1101. * against NULL before touching it or its virtual
  1102. * memory (pkt). Because some rx_handler might have
  1103. * already taken or freed the pages.
  1104. */
  1105. if (reclaim) {
  1106. /* Invoke any callbacks, transfer the buffer to caller,
  1107. * and fire off the (possibly) blocking iwl_send_cmd()
  1108. * as we reclaim the driver command queue */
  1109. if (rxb->page)
  1110. iwl_tx_cmd_complete(priv, rxb);
  1111. else
  1112. IWL_WARN(priv, "Claim null rxb?\n");
  1113. }
  1114. /* Reuse the page if possible. For notification packets and
  1115. * SKBs that fail to Rx correctly, add them back into the
  1116. * rx_free list for reuse later. */
  1117. spin_lock_irqsave(&rxq->lock, flags);
  1118. if (rxb->page != NULL) {
  1119. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  1120. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  1121. PCI_DMA_FROMDEVICE);
  1122. list_add_tail(&rxb->list, &rxq->rx_free);
  1123. rxq->free_count++;
  1124. } else
  1125. list_add_tail(&rxb->list, &rxq->rx_used);
  1126. spin_unlock_irqrestore(&rxq->lock, flags);
  1127. i = (i + 1) & RX_QUEUE_MASK;
  1128. /* If there are a lot of unused frames,
  1129. * restock the Rx queue so ucode won't assert. */
  1130. if (fill_rx) {
  1131. count++;
  1132. if (count >= 8) {
  1133. rxq->read = i;
  1134. iwl3945_rx_replenish_now(priv);
  1135. count = 0;
  1136. }
  1137. }
  1138. }
  1139. /* Backtrack one entry */
  1140. rxq->read = i;
  1141. if (fill_rx)
  1142. iwl3945_rx_replenish_now(priv);
  1143. else
  1144. iwl3945_rx_queue_restock(priv);
  1145. }
  1146. /* call this function to flush any scheduled tasklet */
  1147. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  1148. {
  1149. /* wait to make sure we flush pending tasklet*/
  1150. synchronize_irq(priv->pci_dev->irq);
  1151. tasklet_kill(&priv->irq_tasklet);
  1152. }
  1153. static const char *desc_lookup(int i)
  1154. {
  1155. switch (i) {
  1156. case 1:
  1157. return "FAIL";
  1158. case 2:
  1159. return "BAD_PARAM";
  1160. case 3:
  1161. return "BAD_CHECKSUM";
  1162. case 4:
  1163. return "NMI_INTERRUPT";
  1164. case 5:
  1165. return "SYSASSERT";
  1166. case 6:
  1167. return "FATAL_ERROR";
  1168. }
  1169. return "UNKNOWN";
  1170. }
  1171. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1172. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1173. void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  1174. {
  1175. u32 i;
  1176. u32 desc, time, count, base, data1;
  1177. u32 blink1, blink2, ilink1, ilink2;
  1178. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1179. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  1180. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1181. return;
  1182. }
  1183. count = iwl_read_targ_mem(priv, base);
  1184. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1185. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1186. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1187. priv->status, count);
  1188. }
  1189. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  1190. "ilink1 nmiPC Line\n");
  1191. for (i = ERROR_START_OFFSET;
  1192. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  1193. i += ERROR_ELEM_SIZE) {
  1194. desc = iwl_read_targ_mem(priv, base + i);
  1195. time =
  1196. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  1197. blink1 =
  1198. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  1199. blink2 =
  1200. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  1201. ilink1 =
  1202. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  1203. ilink2 =
  1204. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  1205. data1 =
  1206. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  1207. IWL_ERR(priv,
  1208. "%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  1209. desc_lookup(desc), desc, time, blink1, blink2,
  1210. ilink1, ilink2, data1);
  1211. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, 0,
  1212. 0, blink1, blink2, ilink1, ilink2);
  1213. }
  1214. }
  1215. #define EVENT_START_OFFSET (6 * sizeof(u32))
  1216. /**
  1217. * iwl3945_print_event_log - Dump error event log to syslog
  1218. *
  1219. */
  1220. static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1221. u32 num_events, u32 mode,
  1222. int pos, char **buf, size_t bufsz)
  1223. {
  1224. u32 i;
  1225. u32 base; /* SRAM byte address of event log header */
  1226. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1227. u32 ptr; /* SRAM byte address of log data */
  1228. u32 ev, time, data; /* event log data */
  1229. unsigned long reg_flags;
  1230. if (num_events == 0)
  1231. return pos;
  1232. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1233. if (mode == 0)
  1234. event_size = 2 * sizeof(u32);
  1235. else
  1236. event_size = 3 * sizeof(u32);
  1237. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1238. /* Make sure device is powered up for SRAM reads */
  1239. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1240. iwl_grab_nic_access(priv);
  1241. /* Set starting address; reads will auto-increment */
  1242. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1243. rmb();
  1244. /* "time" is actually "data" for mode 0 (no timestamp).
  1245. * place event id # at far right for easier visual parsing. */
  1246. for (i = 0; i < num_events; i++) {
  1247. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1248. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1249. if (mode == 0) {
  1250. /* data, ev */
  1251. if (bufsz) {
  1252. pos += scnprintf(*buf + pos, bufsz - pos,
  1253. "0x%08x:%04u\n",
  1254. time, ev);
  1255. } else {
  1256. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  1257. trace_iwlwifi_dev_ucode_event(priv, 0,
  1258. time, ev);
  1259. }
  1260. } else {
  1261. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1262. if (bufsz) {
  1263. pos += scnprintf(*buf + pos, bufsz - pos,
  1264. "%010u:0x%08x:%04u\n",
  1265. time, data, ev);
  1266. } else {
  1267. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
  1268. time, data, ev);
  1269. trace_iwlwifi_dev_ucode_event(priv, time,
  1270. data, ev);
  1271. }
  1272. }
  1273. }
  1274. /* Allow device to power down */
  1275. iwl_release_nic_access(priv);
  1276. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1277. return pos;
  1278. }
  1279. /**
  1280. * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
  1281. */
  1282. static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1283. u32 num_wraps, u32 next_entry,
  1284. u32 size, u32 mode,
  1285. int pos, char **buf, size_t bufsz)
  1286. {
  1287. /*
  1288. * display the newest DEFAULT_LOG_ENTRIES entries
  1289. * i.e the entries just before the next ont that uCode would fill.
  1290. */
  1291. if (num_wraps) {
  1292. if (next_entry < size) {
  1293. pos = iwl3945_print_event_log(priv,
  1294. capacity - (size - next_entry),
  1295. size - next_entry, mode,
  1296. pos, buf, bufsz);
  1297. pos = iwl3945_print_event_log(priv, 0,
  1298. next_entry, mode,
  1299. pos, buf, bufsz);
  1300. } else
  1301. pos = iwl3945_print_event_log(priv, next_entry - size,
  1302. size, mode,
  1303. pos, buf, bufsz);
  1304. } else {
  1305. if (next_entry < size)
  1306. pos = iwl3945_print_event_log(priv, 0,
  1307. next_entry, mode,
  1308. pos, buf, bufsz);
  1309. else
  1310. pos = iwl3945_print_event_log(priv, next_entry - size,
  1311. size, mode,
  1312. pos, buf, bufsz);
  1313. }
  1314. return pos;
  1315. }
  1316. #define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
  1317. int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1318. char **buf, bool display)
  1319. {
  1320. u32 base; /* SRAM byte address of event log header */
  1321. u32 capacity; /* event log capacity in # entries */
  1322. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1323. u32 num_wraps; /* # times uCode wrapped to top of log */
  1324. u32 next_entry; /* index of next entry to be written by uCode */
  1325. u32 size; /* # entries that we'll print */
  1326. int pos = 0;
  1327. size_t bufsz = 0;
  1328. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1329. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  1330. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1331. return -EINVAL;
  1332. }
  1333. /* event log header */
  1334. capacity = iwl_read_targ_mem(priv, base);
  1335. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1336. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1337. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1338. if (capacity > priv->cfg->base_params->max_event_log_size) {
  1339. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1340. capacity, priv->cfg->base_params->max_event_log_size);
  1341. capacity = priv->cfg->base_params->max_event_log_size;
  1342. }
  1343. if (next_entry > priv->cfg->base_params->max_event_log_size) {
  1344. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1345. next_entry, priv->cfg->base_params->max_event_log_size);
  1346. next_entry = priv->cfg->base_params->max_event_log_size;
  1347. }
  1348. size = num_wraps ? capacity : next_entry;
  1349. /* bail out if nothing in log */
  1350. if (size == 0) {
  1351. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1352. return pos;
  1353. }
  1354. #ifdef CONFIG_IWLWIFI_DEBUG
  1355. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1356. size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
  1357. ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
  1358. #else
  1359. size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
  1360. ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
  1361. #endif
  1362. IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
  1363. size);
  1364. #ifdef CONFIG_IWLWIFI_DEBUG
  1365. if (display) {
  1366. if (full_log)
  1367. bufsz = capacity * 48;
  1368. else
  1369. bufsz = size * 48;
  1370. *buf = kmalloc(bufsz, GFP_KERNEL);
  1371. if (!*buf)
  1372. return -ENOMEM;
  1373. }
  1374. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1375. /* if uCode has wrapped back to top of log,
  1376. * start at the oldest entry,
  1377. * i.e the next one that uCode would fill.
  1378. */
  1379. if (num_wraps)
  1380. pos = iwl3945_print_event_log(priv, next_entry,
  1381. capacity - next_entry, mode,
  1382. pos, buf, bufsz);
  1383. /* (then/else) start at top of log */
  1384. pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
  1385. pos, buf, bufsz);
  1386. } else
  1387. pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
  1388. next_entry, size, mode,
  1389. pos, buf, bufsz);
  1390. #else
  1391. pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
  1392. next_entry, size, mode,
  1393. pos, buf, bufsz);
  1394. #endif
  1395. return pos;
  1396. }
  1397. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  1398. {
  1399. u32 inta, handled = 0;
  1400. u32 inta_fh;
  1401. unsigned long flags;
  1402. #ifdef CONFIG_IWLWIFI_DEBUG
  1403. u32 inta_mask;
  1404. #endif
  1405. spin_lock_irqsave(&priv->lock, flags);
  1406. /* Ack/clear/reset pending uCode interrupts.
  1407. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1408. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  1409. inta = iwl_read32(priv, CSR_INT);
  1410. iwl_write32(priv, CSR_INT, inta);
  1411. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  1412. * Any new interrupts that happen after this, either while we're
  1413. * in this tasklet, or later, will show up in next ISR/tasklet. */
  1414. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1415. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  1416. #ifdef CONFIG_IWLWIFI_DEBUG
  1417. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1418. /* just for debug */
  1419. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1420. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1421. inta, inta_mask, inta_fh);
  1422. }
  1423. #endif
  1424. spin_unlock_irqrestore(&priv->lock, flags);
  1425. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  1426. * atomic, make sure that inta covers all the interrupts that
  1427. * we've discovered, even if FH interrupt came in just after
  1428. * reading CSR_INT. */
  1429. if (inta_fh & CSR39_FH_INT_RX_MASK)
  1430. inta |= CSR_INT_BIT_FH_RX;
  1431. if (inta_fh & CSR39_FH_INT_TX_MASK)
  1432. inta |= CSR_INT_BIT_FH_TX;
  1433. /* Now service all interrupt bits discovered above. */
  1434. if (inta & CSR_INT_BIT_HW_ERR) {
  1435. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1436. /* Tell the device to stop sending interrupts */
  1437. iwl_disable_interrupts(priv);
  1438. priv->isr_stats.hw++;
  1439. iwl_irq_handle_error(priv);
  1440. handled |= CSR_INT_BIT_HW_ERR;
  1441. return;
  1442. }
  1443. #ifdef CONFIG_IWLWIFI_DEBUG
  1444. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1445. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1446. if (inta & CSR_INT_BIT_SCD) {
  1447. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1448. "the frame/frames.\n");
  1449. priv->isr_stats.sch++;
  1450. }
  1451. /* Alive notification via Rx interrupt will do the real work */
  1452. if (inta & CSR_INT_BIT_ALIVE) {
  1453. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1454. priv->isr_stats.alive++;
  1455. }
  1456. }
  1457. #endif
  1458. /* Safely ignore these bits for debug checks below */
  1459. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1460. /* Error detected by uCode */
  1461. if (inta & CSR_INT_BIT_SW_ERR) {
  1462. IWL_ERR(priv, "Microcode SW error detected. "
  1463. "Restarting 0x%X.\n", inta);
  1464. priv->isr_stats.sw++;
  1465. iwl_irq_handle_error(priv);
  1466. handled |= CSR_INT_BIT_SW_ERR;
  1467. }
  1468. /* uCode wakes up after power-down sleep */
  1469. if (inta & CSR_INT_BIT_WAKEUP) {
  1470. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1471. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1472. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  1473. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  1474. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  1475. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  1476. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  1477. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  1478. priv->isr_stats.wakeup++;
  1479. handled |= CSR_INT_BIT_WAKEUP;
  1480. }
  1481. /* All uCode command responses, including Tx command responses,
  1482. * Rx "responses" (frame-received notification), and other
  1483. * notifications from uCode come through here*/
  1484. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1485. iwl3945_rx_handle(priv);
  1486. priv->isr_stats.rx++;
  1487. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1488. }
  1489. if (inta & CSR_INT_BIT_FH_TX) {
  1490. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1491. priv->isr_stats.tx++;
  1492. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  1493. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  1494. (FH39_SRVC_CHNL), 0x0);
  1495. handled |= CSR_INT_BIT_FH_TX;
  1496. }
  1497. if (inta & ~handled) {
  1498. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1499. priv->isr_stats.unhandled++;
  1500. }
  1501. if (inta & ~priv->inta_mask) {
  1502. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1503. inta & ~priv->inta_mask);
  1504. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1505. }
  1506. /* Re-enable all interrupts */
  1507. /* only Re-enable if disabled by irq */
  1508. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1509. iwl_enable_interrupts(priv);
  1510. #ifdef CONFIG_IWLWIFI_DEBUG
  1511. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1512. inta = iwl_read32(priv, CSR_INT);
  1513. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1514. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1515. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1516. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1517. }
  1518. #endif
  1519. }
  1520. static int iwl3945_get_single_channel_for_scan(struct iwl_priv *priv,
  1521. struct ieee80211_vif *vif,
  1522. enum ieee80211_band band,
  1523. struct iwl3945_scan_channel *scan_ch)
  1524. {
  1525. const struct ieee80211_supported_band *sband;
  1526. u16 passive_dwell = 0;
  1527. u16 active_dwell = 0;
  1528. int added = 0;
  1529. u8 channel = 0;
  1530. sband = iwl_get_hw_mode(priv, band);
  1531. if (!sband) {
  1532. IWL_ERR(priv, "invalid band\n");
  1533. return added;
  1534. }
  1535. active_dwell = iwl_get_active_dwell_time(priv, band, 0);
  1536. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1537. if (passive_dwell <= active_dwell)
  1538. passive_dwell = active_dwell + 1;
  1539. channel = iwl_get_single_channel_number(priv, band);
  1540. if (channel) {
  1541. scan_ch->channel = channel;
  1542. scan_ch->type = 0; /* passive */
  1543. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1544. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1545. /* Set txpower levels to defaults */
  1546. scan_ch->tpc.dsp_atten = 110;
  1547. if (band == IEEE80211_BAND_5GHZ)
  1548. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1549. else
  1550. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1551. added++;
  1552. } else
  1553. IWL_ERR(priv, "no valid channel found\n");
  1554. return added;
  1555. }
  1556. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  1557. enum ieee80211_band band,
  1558. u8 is_active, u8 n_probes,
  1559. struct iwl3945_scan_channel *scan_ch,
  1560. struct ieee80211_vif *vif)
  1561. {
  1562. struct ieee80211_channel *chan;
  1563. const struct ieee80211_supported_band *sband;
  1564. const struct iwl_channel_info *ch_info;
  1565. u16 passive_dwell = 0;
  1566. u16 active_dwell = 0;
  1567. int added, i;
  1568. sband = iwl_get_hw_mode(priv, band);
  1569. if (!sband)
  1570. return 0;
  1571. active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
  1572. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1573. if (passive_dwell <= active_dwell)
  1574. passive_dwell = active_dwell + 1;
  1575. for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
  1576. chan = priv->scan_request->channels[i];
  1577. if (chan->band != band)
  1578. continue;
  1579. scan_ch->channel = chan->hw_value;
  1580. ch_info = iwl_get_channel_info(priv, band, scan_ch->channel);
  1581. if (!is_channel_valid(ch_info)) {
  1582. IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
  1583. scan_ch->channel);
  1584. continue;
  1585. }
  1586. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1587. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1588. /* If passive , set up for auto-switch
  1589. * and use long active_dwell time.
  1590. */
  1591. if (!is_active || is_channel_passive(ch_info) ||
  1592. (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  1593. scan_ch->type = 0; /* passive */
  1594. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  1595. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  1596. } else {
  1597. scan_ch->type = 1; /* active */
  1598. }
  1599. /* Set direct probe bits. These may be used both for active
  1600. * scan channels (probes gets sent right away),
  1601. * or for passive channels (probes get se sent only after
  1602. * hearing clear Rx packet).*/
  1603. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  1604. if (n_probes)
  1605. scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
  1606. } else {
  1607. /* uCode v1 does not allow setting direct probe bits on
  1608. * passive channel. */
  1609. if ((scan_ch->type & 1) && n_probes)
  1610. scan_ch->type |= IWL39_SCAN_PROBE_MASK(n_probes);
  1611. }
  1612. /* Set txpower levels to defaults */
  1613. scan_ch->tpc.dsp_atten = 110;
  1614. /* scan_pwr_info->tpc.dsp_atten; */
  1615. /*scan_pwr_info->tpc.tx_gain; */
  1616. if (band == IEEE80211_BAND_5GHZ)
  1617. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1618. else {
  1619. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  1620. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  1621. * power level:
  1622. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  1623. */
  1624. }
  1625. IWL_DEBUG_SCAN(priv, "Scanning %d [%s %d]\n",
  1626. scan_ch->channel,
  1627. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  1628. (scan_ch->type & 1) ?
  1629. active_dwell : passive_dwell);
  1630. scan_ch++;
  1631. added++;
  1632. }
  1633. IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
  1634. return added;
  1635. }
  1636. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  1637. struct ieee80211_rate *rates)
  1638. {
  1639. int i;
  1640. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  1641. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  1642. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  1643. rates[i].hw_value_short = i;
  1644. rates[i].flags = 0;
  1645. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  1646. /*
  1647. * If CCK != 1M then set short preamble rate flag.
  1648. */
  1649. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  1650. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  1651. }
  1652. }
  1653. }
  1654. /******************************************************************************
  1655. *
  1656. * uCode download functions
  1657. *
  1658. ******************************************************************************/
  1659. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  1660. {
  1661. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1662. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1663. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1664. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1665. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1666. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1667. }
  1668. /**
  1669. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  1670. * looking at all data.
  1671. */
  1672. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  1673. {
  1674. u32 val;
  1675. u32 save_len = len;
  1676. int rc = 0;
  1677. u32 errcnt;
  1678. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1679. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1680. IWL39_RTC_INST_LOWER_BOUND);
  1681. errcnt = 0;
  1682. for (; len > 0; len -= sizeof(u32), image++) {
  1683. /* read data comes through single port, auto-incr addr */
  1684. /* NOTE: Use the debugless read so we don't flood kernel log
  1685. * if IWL_DL_IO is set */
  1686. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1687. if (val != le32_to_cpu(*image)) {
  1688. IWL_ERR(priv, "uCode INST section is invalid at "
  1689. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1690. save_len - len, val, le32_to_cpu(*image));
  1691. rc = -EIO;
  1692. errcnt++;
  1693. if (errcnt >= 20)
  1694. break;
  1695. }
  1696. }
  1697. if (!errcnt)
  1698. IWL_DEBUG_INFO(priv,
  1699. "ucode image in INSTRUCTION memory is good\n");
  1700. return rc;
  1701. }
  1702. /**
  1703. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1704. * using sample data 100 bytes apart. If these sample points are good,
  1705. * it's a pretty good bet that everything between them is good, too.
  1706. */
  1707. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1708. {
  1709. u32 val;
  1710. int rc = 0;
  1711. u32 errcnt = 0;
  1712. u32 i;
  1713. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1714. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1715. /* read data comes through single port, auto-incr addr */
  1716. /* NOTE: Use the debugless read so we don't flood kernel log
  1717. * if IWL_DL_IO is set */
  1718. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1719. i + IWL39_RTC_INST_LOWER_BOUND);
  1720. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1721. if (val != le32_to_cpu(*image)) {
  1722. #if 0 /* Enable this if you want to see details */
  1723. IWL_ERR(priv, "uCode INST section is invalid at "
  1724. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1725. i, val, *image);
  1726. #endif
  1727. rc = -EIO;
  1728. errcnt++;
  1729. if (errcnt >= 3)
  1730. break;
  1731. }
  1732. }
  1733. return rc;
  1734. }
  1735. /**
  1736. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  1737. * and verify its contents
  1738. */
  1739. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  1740. {
  1741. __le32 *image;
  1742. u32 len;
  1743. int rc = 0;
  1744. /* Try bootstrap */
  1745. image = (__le32 *)priv->ucode_boot.v_addr;
  1746. len = priv->ucode_boot.len;
  1747. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1748. if (rc == 0) {
  1749. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1750. return 0;
  1751. }
  1752. /* Try initialize */
  1753. image = (__le32 *)priv->ucode_init.v_addr;
  1754. len = priv->ucode_init.len;
  1755. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1756. if (rc == 0) {
  1757. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1758. return 0;
  1759. }
  1760. /* Try runtime/protocol */
  1761. image = (__le32 *)priv->ucode_code.v_addr;
  1762. len = priv->ucode_code.len;
  1763. rc = iwl3945_verify_inst_sparse(priv, image, len);
  1764. if (rc == 0) {
  1765. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1766. return 0;
  1767. }
  1768. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1769. /* Since nothing seems to match, show first several data entries in
  1770. * instruction SRAM, so maybe visual inspection will give a clue.
  1771. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1772. image = (__le32 *)priv->ucode_boot.v_addr;
  1773. len = priv->ucode_boot.len;
  1774. rc = iwl3945_verify_inst_full(priv, image, len);
  1775. return rc;
  1776. }
  1777. static void iwl3945_nic_start(struct iwl_priv *priv)
  1778. {
  1779. /* Remove all resets to allow NIC to operate */
  1780. iwl_write32(priv, CSR_RESET, 0);
  1781. }
  1782. #define IWL3945_UCODE_GET(item) \
  1783. static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode)\
  1784. { \
  1785. return le32_to_cpu(ucode->u.v1.item); \
  1786. }
  1787. static u32 iwl3945_ucode_get_header_size(u32 api_ver)
  1788. {
  1789. return 24;
  1790. }
  1791. static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode)
  1792. {
  1793. return (u8 *) ucode->u.v1.data;
  1794. }
  1795. IWL3945_UCODE_GET(inst_size);
  1796. IWL3945_UCODE_GET(data_size);
  1797. IWL3945_UCODE_GET(init_size);
  1798. IWL3945_UCODE_GET(init_data_size);
  1799. IWL3945_UCODE_GET(boot_size);
  1800. /**
  1801. * iwl3945_read_ucode - Read uCode images from disk file.
  1802. *
  1803. * Copy into buffers for card to fetch via bus-mastering
  1804. */
  1805. static int iwl3945_read_ucode(struct iwl_priv *priv)
  1806. {
  1807. const struct iwl_ucode_header *ucode;
  1808. int ret = -EINVAL, index;
  1809. const struct firmware *ucode_raw;
  1810. /* firmware file name contains uCode/driver compatibility version */
  1811. const char *name_pre = priv->cfg->fw_name_pre;
  1812. const unsigned int api_max = priv->cfg->ucode_api_max;
  1813. const unsigned int api_min = priv->cfg->ucode_api_min;
  1814. char buf[25];
  1815. u8 *src;
  1816. size_t len;
  1817. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  1818. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1819. * request_firmware() is synchronous, file is in memory on return. */
  1820. for (index = api_max; index >= api_min; index--) {
  1821. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  1822. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1823. if (ret < 0) {
  1824. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1825. buf, ret);
  1826. if (ret == -ENOENT)
  1827. continue;
  1828. else
  1829. goto error;
  1830. } else {
  1831. if (index < api_max)
  1832. IWL_ERR(priv, "Loaded firmware %s, "
  1833. "which is deprecated. "
  1834. " Please use API v%u instead.\n",
  1835. buf, api_max);
  1836. IWL_DEBUG_INFO(priv, "Got firmware '%s' file "
  1837. "(%zd bytes) from disk\n",
  1838. buf, ucode_raw->size);
  1839. break;
  1840. }
  1841. }
  1842. if (ret < 0)
  1843. goto error;
  1844. /* Make sure that we got at least our header! */
  1845. if (ucode_raw->size < iwl3945_ucode_get_header_size(1)) {
  1846. IWL_ERR(priv, "File size way too small!\n");
  1847. ret = -EINVAL;
  1848. goto err_release;
  1849. }
  1850. /* Data from ucode file: header followed by uCode images */
  1851. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1852. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1853. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1854. inst_size = iwl3945_ucode_get_inst_size(ucode);
  1855. data_size = iwl3945_ucode_get_data_size(ucode);
  1856. init_size = iwl3945_ucode_get_init_size(ucode);
  1857. init_data_size = iwl3945_ucode_get_init_data_size(ucode);
  1858. boot_size = iwl3945_ucode_get_boot_size(ucode);
  1859. src = iwl3945_ucode_get_data(ucode);
  1860. /* api_ver should match the api version forming part of the
  1861. * firmware filename ... but we don't check for that and only rely
  1862. * on the API version read from firmware header from here on forward */
  1863. if (api_ver < api_min || api_ver > api_max) {
  1864. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1865. "Driver supports v%u, firmware is v%u.\n",
  1866. api_max, api_ver);
  1867. priv->ucode_ver = 0;
  1868. ret = -EINVAL;
  1869. goto err_release;
  1870. }
  1871. if (api_ver != api_max)
  1872. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  1873. "got %u. New firmware can be obtained "
  1874. "from http://www.intellinuxwireless.org.\n",
  1875. api_max, api_ver);
  1876. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1877. IWL_UCODE_MAJOR(priv->ucode_ver),
  1878. IWL_UCODE_MINOR(priv->ucode_ver),
  1879. IWL_UCODE_API(priv->ucode_ver),
  1880. IWL_UCODE_SERIAL(priv->ucode_ver));
  1881. snprintf(priv->hw->wiphy->fw_version,
  1882. sizeof(priv->hw->wiphy->fw_version),
  1883. "%u.%u.%u.%u",
  1884. IWL_UCODE_MAJOR(priv->ucode_ver),
  1885. IWL_UCODE_MINOR(priv->ucode_ver),
  1886. IWL_UCODE_API(priv->ucode_ver),
  1887. IWL_UCODE_SERIAL(priv->ucode_ver));
  1888. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1889. priv->ucode_ver);
  1890. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1891. inst_size);
  1892. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1893. data_size);
  1894. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1895. init_size);
  1896. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1897. init_data_size);
  1898. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1899. boot_size);
  1900. /* Verify size of file vs. image size info in file's header */
  1901. if (ucode_raw->size != iwl3945_ucode_get_header_size(api_ver) +
  1902. inst_size + data_size + init_size +
  1903. init_data_size + boot_size) {
  1904. IWL_DEBUG_INFO(priv,
  1905. "uCode file size %zd does not match expected size\n",
  1906. ucode_raw->size);
  1907. ret = -EINVAL;
  1908. goto err_release;
  1909. }
  1910. /* Verify that uCode images will fit in card's SRAM */
  1911. if (inst_size > IWL39_MAX_INST_SIZE) {
  1912. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1913. inst_size);
  1914. ret = -EINVAL;
  1915. goto err_release;
  1916. }
  1917. if (data_size > IWL39_MAX_DATA_SIZE) {
  1918. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1919. data_size);
  1920. ret = -EINVAL;
  1921. goto err_release;
  1922. }
  1923. if (init_size > IWL39_MAX_INST_SIZE) {
  1924. IWL_DEBUG_INFO(priv,
  1925. "uCode init instr len %d too large to fit in\n",
  1926. init_size);
  1927. ret = -EINVAL;
  1928. goto err_release;
  1929. }
  1930. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  1931. IWL_DEBUG_INFO(priv,
  1932. "uCode init data len %d too large to fit in\n",
  1933. init_data_size);
  1934. ret = -EINVAL;
  1935. goto err_release;
  1936. }
  1937. if (boot_size > IWL39_MAX_BSM_SIZE) {
  1938. IWL_DEBUG_INFO(priv,
  1939. "uCode boot instr len %d too large to fit in\n",
  1940. boot_size);
  1941. ret = -EINVAL;
  1942. goto err_release;
  1943. }
  1944. /* Allocate ucode buffers for card's bus-master loading ... */
  1945. /* Runtime instructions and 2 copies of data:
  1946. * 1) unmodified from disk
  1947. * 2) backup cache for save/restore during power-downs */
  1948. priv->ucode_code.len = inst_size;
  1949. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1950. priv->ucode_data.len = data_size;
  1951. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1952. priv->ucode_data_backup.len = data_size;
  1953. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1954. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1955. !priv->ucode_data_backup.v_addr)
  1956. goto err_pci_alloc;
  1957. /* Initialization instructions and data */
  1958. if (init_size && init_data_size) {
  1959. priv->ucode_init.len = init_size;
  1960. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1961. priv->ucode_init_data.len = init_data_size;
  1962. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1963. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1964. goto err_pci_alloc;
  1965. }
  1966. /* Bootstrap (instructions only, no data) */
  1967. if (boot_size) {
  1968. priv->ucode_boot.len = boot_size;
  1969. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1970. if (!priv->ucode_boot.v_addr)
  1971. goto err_pci_alloc;
  1972. }
  1973. /* Copy images into buffers for card's bus-master reads ... */
  1974. /* Runtime instructions (first block of data in file) */
  1975. len = inst_size;
  1976. IWL_DEBUG_INFO(priv,
  1977. "Copying (but not loading) uCode instr len %zd\n", len);
  1978. memcpy(priv->ucode_code.v_addr, src, len);
  1979. src += len;
  1980. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1981. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1982. /* Runtime data (2nd block)
  1983. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  1984. len = data_size;
  1985. IWL_DEBUG_INFO(priv,
  1986. "Copying (but not loading) uCode data len %zd\n", len);
  1987. memcpy(priv->ucode_data.v_addr, src, len);
  1988. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1989. src += len;
  1990. /* Initialization instructions (3rd block) */
  1991. if (init_size) {
  1992. len = init_size;
  1993. IWL_DEBUG_INFO(priv,
  1994. "Copying (but not loading) init instr len %zd\n", len);
  1995. memcpy(priv->ucode_init.v_addr, src, len);
  1996. src += len;
  1997. }
  1998. /* Initialization data (4th block) */
  1999. if (init_data_size) {
  2000. len = init_data_size;
  2001. IWL_DEBUG_INFO(priv,
  2002. "Copying (but not loading) init data len %zd\n", len);
  2003. memcpy(priv->ucode_init_data.v_addr, src, len);
  2004. src += len;
  2005. }
  2006. /* Bootstrap instructions (5th block) */
  2007. len = boot_size;
  2008. IWL_DEBUG_INFO(priv,
  2009. "Copying (but not loading) boot instr len %zd\n", len);
  2010. memcpy(priv->ucode_boot.v_addr, src, len);
  2011. /* We have our copies now, allow OS release its copies */
  2012. release_firmware(ucode_raw);
  2013. return 0;
  2014. err_pci_alloc:
  2015. IWL_ERR(priv, "failed to allocate pci memory\n");
  2016. ret = -ENOMEM;
  2017. iwl3945_dealloc_ucode_pci(priv);
  2018. err_release:
  2019. release_firmware(ucode_raw);
  2020. error:
  2021. return ret;
  2022. }
  2023. /**
  2024. * iwl3945_set_ucode_ptrs - Set uCode address location
  2025. *
  2026. * Tell initialization uCode where to find runtime uCode.
  2027. *
  2028. * BSM registers initially contain pointers to initialization uCode.
  2029. * We need to replace them to load runtime uCode inst and data,
  2030. * and to save runtime data when powering down.
  2031. */
  2032. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  2033. {
  2034. dma_addr_t pinst;
  2035. dma_addr_t pdata;
  2036. /* bits 31:0 for 3945 */
  2037. pinst = priv->ucode_code.p_addr;
  2038. pdata = priv->ucode_data_backup.p_addr;
  2039. /* Tell bootstrap uCode where to find image to load */
  2040. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  2041. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  2042. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  2043. priv->ucode_data.len);
  2044. /* Inst byte count must be last to set up, bit 31 signals uCode
  2045. * that all new ptr/size info is in place */
  2046. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  2047. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  2048. IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
  2049. return 0;
  2050. }
  2051. /**
  2052. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  2053. *
  2054. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  2055. *
  2056. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  2057. */
  2058. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  2059. {
  2060. /* Check alive response for "valid" sign from uCode */
  2061. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  2062. /* We had an error bringing up the hardware, so take it
  2063. * all the way back down so we can try again */
  2064. IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
  2065. goto restart;
  2066. }
  2067. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  2068. * This is a paranoid check, because we would not have gotten the
  2069. * "initialize" alive if code weren't properly loaded. */
  2070. if (iwl3945_verify_ucode(priv)) {
  2071. /* Runtime instruction load was bad;
  2072. * take it all the way back down so we can try again */
  2073. IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
  2074. goto restart;
  2075. }
  2076. /* Send pointers to protocol/runtime uCode image ... init code will
  2077. * load and launch runtime uCode, which will send us another "Alive"
  2078. * notification. */
  2079. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  2080. if (iwl3945_set_ucode_ptrs(priv)) {
  2081. /* Runtime instruction load won't happen;
  2082. * take it all the way back down so we can try again */
  2083. IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
  2084. goto restart;
  2085. }
  2086. return;
  2087. restart:
  2088. queue_work(priv->workqueue, &priv->restart);
  2089. }
  2090. /**
  2091. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  2092. * from protocol/runtime uCode (initialization uCode's
  2093. * Alive gets handled by iwl3945_init_alive_start()).
  2094. */
  2095. static void iwl3945_alive_start(struct iwl_priv *priv)
  2096. {
  2097. int thermal_spin = 0;
  2098. u32 rfkill;
  2099. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2100. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  2101. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  2102. /* We had an error bringing up the hardware, so take it
  2103. * all the way back down so we can try again */
  2104. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  2105. goto restart;
  2106. }
  2107. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  2108. * This is a paranoid check, because we would not have gotten the
  2109. * "runtime" alive if code weren't properly loaded. */
  2110. if (iwl3945_verify_ucode(priv)) {
  2111. /* Runtime instruction load was bad;
  2112. * take it all the way back down so we can try again */
  2113. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  2114. goto restart;
  2115. }
  2116. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  2117. IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
  2118. if (rfkill & 0x1) {
  2119. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2120. /* if RFKILL is not on, then wait for thermal
  2121. * sensor in adapter to kick in */
  2122. while (iwl3945_hw_get_temperature(priv) == 0) {
  2123. thermal_spin++;
  2124. udelay(10);
  2125. }
  2126. if (thermal_spin)
  2127. IWL_DEBUG_INFO(priv, "Thermal calibration took %dus\n",
  2128. thermal_spin * 10);
  2129. } else
  2130. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2131. /* After the ALIVE response, we can send commands to 3945 uCode */
  2132. set_bit(STATUS_ALIVE, &priv->status);
  2133. /* Enable watchdog to monitor the driver tx queues */
  2134. iwl_setup_watchdog(priv);
  2135. if (iwl_is_rfkill(priv))
  2136. return;
  2137. ieee80211_wake_queues(priv->hw);
  2138. priv->active_rate = IWL_RATES_MASK;
  2139. iwl_power_update_mode(priv, true);
  2140. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
  2141. struct iwl3945_rxon_cmd *active_rxon =
  2142. (struct iwl3945_rxon_cmd *)(&ctx->active);
  2143. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2144. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2145. } else {
  2146. /* Initialize our rx_config data */
  2147. iwl_connection_init_rx_config(priv, ctx);
  2148. }
  2149. /* Configure Bluetooth device coexistence support */
  2150. priv->cfg->ops->hcmd->send_bt_config(priv);
  2151. /* Configure the adapter for unassociated operation */
  2152. iwl3945_commit_rxon(priv, ctx);
  2153. iwl3945_reg_txpower_periodic(priv);
  2154. iwl_leds_init(priv);
  2155. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2156. set_bit(STATUS_READY, &priv->status);
  2157. wake_up_interruptible(&priv->wait_command_queue);
  2158. return;
  2159. restart:
  2160. queue_work(priv->workqueue, &priv->restart);
  2161. }
  2162. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  2163. static void __iwl3945_down(struct iwl_priv *priv)
  2164. {
  2165. unsigned long flags;
  2166. int exit_pending;
  2167. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2168. iwl_scan_cancel_timeout(priv, 200);
  2169. exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
  2170. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  2171. * to prevent rearm timer */
  2172. del_timer_sync(&priv->watchdog);
  2173. /* Station information will now be cleared in device */
  2174. iwl_clear_ucode_stations(priv, NULL);
  2175. iwl_dealloc_bcast_stations(priv);
  2176. iwl_clear_driver_stations(priv);
  2177. /* Unblock any waiting calls */
  2178. wake_up_interruptible_all(&priv->wait_command_queue);
  2179. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2180. * exiting the module */
  2181. if (!exit_pending)
  2182. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2183. /* stop and reset the on-board processor */
  2184. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2185. /* tell the device to stop sending interrupts */
  2186. spin_lock_irqsave(&priv->lock, flags);
  2187. iwl_disable_interrupts(priv);
  2188. spin_unlock_irqrestore(&priv->lock, flags);
  2189. iwl_synchronize_irq(priv);
  2190. if (priv->mac80211_registered)
  2191. ieee80211_stop_queues(priv->hw);
  2192. /* If we have not previously called iwl3945_init() then
  2193. * clear all bits but the RF Kill bits and return */
  2194. if (!iwl_is_init(priv)) {
  2195. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2196. STATUS_RF_KILL_HW |
  2197. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2198. STATUS_GEO_CONFIGURED |
  2199. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2200. STATUS_EXIT_PENDING;
  2201. goto exit;
  2202. }
  2203. /* ...otherwise clear out all the status bits but the RF Kill
  2204. * bit and continue taking the NIC down. */
  2205. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2206. STATUS_RF_KILL_HW |
  2207. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2208. STATUS_GEO_CONFIGURED |
  2209. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2210. STATUS_FW_ERROR |
  2211. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2212. STATUS_EXIT_PENDING;
  2213. iwl3945_hw_txq_ctx_stop(priv);
  2214. iwl3945_hw_rxq_stop(priv);
  2215. /* Power-down device's busmaster DMA clocks */
  2216. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2217. udelay(5);
  2218. /* Stop the device, and put it in low power state */
  2219. iwl_apm_stop(priv);
  2220. exit:
  2221. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2222. if (priv->beacon_skb)
  2223. dev_kfree_skb(priv->beacon_skb);
  2224. priv->beacon_skb = NULL;
  2225. /* clear out any free frames */
  2226. iwl3945_clear_free_frames(priv);
  2227. }
  2228. static void iwl3945_down(struct iwl_priv *priv)
  2229. {
  2230. mutex_lock(&priv->mutex);
  2231. __iwl3945_down(priv);
  2232. mutex_unlock(&priv->mutex);
  2233. iwl3945_cancel_deferred_work(priv);
  2234. }
  2235. #define MAX_HW_RESTARTS 5
  2236. static int iwl3945_alloc_bcast_station(struct iwl_priv *priv)
  2237. {
  2238. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2239. unsigned long flags;
  2240. u8 sta_id;
  2241. spin_lock_irqsave(&priv->sta_lock, flags);
  2242. sta_id = iwl_prep_station(priv, ctx, iwl_bcast_addr, false, NULL);
  2243. if (sta_id == IWL_INVALID_STATION) {
  2244. IWL_ERR(priv, "Unable to prepare broadcast station\n");
  2245. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2246. return -EINVAL;
  2247. }
  2248. priv->stations[sta_id].used |= IWL_STA_DRIVER_ACTIVE;
  2249. priv->stations[sta_id].used |= IWL_STA_BCAST;
  2250. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2251. return 0;
  2252. }
  2253. static int __iwl3945_up(struct iwl_priv *priv)
  2254. {
  2255. int rc, i;
  2256. rc = iwl3945_alloc_bcast_station(priv);
  2257. if (rc)
  2258. return rc;
  2259. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2260. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2261. return -EIO;
  2262. }
  2263. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2264. IWL_ERR(priv, "ucode not available for device bring up\n");
  2265. return -EIO;
  2266. }
  2267. /* If platform's RF_KILL switch is NOT set to KILL */
  2268. if (iwl_read32(priv, CSR_GP_CNTRL) &
  2269. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2270. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2271. else {
  2272. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2273. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2274. return -ENODEV;
  2275. }
  2276. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2277. rc = iwl3945_hw_nic_init(priv);
  2278. if (rc) {
  2279. IWL_ERR(priv, "Unable to int nic\n");
  2280. return rc;
  2281. }
  2282. /* make sure rfkill handshake bits are cleared */
  2283. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2284. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2285. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2286. /* clear (again), then enable host interrupts */
  2287. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2288. iwl_enable_interrupts(priv);
  2289. /* really make sure rfkill handshake bits are cleared */
  2290. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2291. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2292. /* Copy original ucode data image from disk into backup cache.
  2293. * This will be used to initialize the on-board processor's
  2294. * data SRAM for a clean start when the runtime program first loads. */
  2295. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2296. priv->ucode_data.len);
  2297. /* We return success when we resume from suspend and rf_kill is on. */
  2298. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  2299. return 0;
  2300. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2301. /* load bootstrap state machine,
  2302. * load bootstrap program into processor's memory,
  2303. * prepare to load the "initialize" uCode */
  2304. rc = priv->cfg->ops->lib->load_ucode(priv);
  2305. if (rc) {
  2306. IWL_ERR(priv,
  2307. "Unable to set up bootstrap uCode: %d\n", rc);
  2308. continue;
  2309. }
  2310. /* start card; "initialize" will load runtime ucode */
  2311. iwl3945_nic_start(priv);
  2312. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2313. return 0;
  2314. }
  2315. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2316. __iwl3945_down(priv);
  2317. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2318. /* tried to restart and config the device for as long as our
  2319. * patience could withstand */
  2320. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2321. return -EIO;
  2322. }
  2323. /*****************************************************************************
  2324. *
  2325. * Workqueue callbacks
  2326. *
  2327. *****************************************************************************/
  2328. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  2329. {
  2330. struct iwl_priv *priv =
  2331. container_of(data, struct iwl_priv, init_alive_start.work);
  2332. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2333. return;
  2334. mutex_lock(&priv->mutex);
  2335. iwl3945_init_alive_start(priv);
  2336. mutex_unlock(&priv->mutex);
  2337. }
  2338. static void iwl3945_bg_alive_start(struct work_struct *data)
  2339. {
  2340. struct iwl_priv *priv =
  2341. container_of(data, struct iwl_priv, alive_start.work);
  2342. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2343. return;
  2344. mutex_lock(&priv->mutex);
  2345. iwl3945_alive_start(priv);
  2346. mutex_unlock(&priv->mutex);
  2347. }
  2348. /*
  2349. * 3945 cannot interrupt driver when hardware rf kill switch toggles;
  2350. * driver must poll CSR_GP_CNTRL_REG register for change. This register
  2351. * *is* readable even when device has been SW_RESET into low power mode
  2352. * (e.g. during RF KILL).
  2353. */
  2354. static void iwl3945_rfkill_poll(struct work_struct *data)
  2355. {
  2356. struct iwl_priv *priv =
  2357. container_of(data, struct iwl_priv, _3945.rfkill_poll.work);
  2358. bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &priv->status);
  2359. bool new_rfkill = !(iwl_read32(priv, CSR_GP_CNTRL)
  2360. & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
  2361. if (new_rfkill != old_rfkill) {
  2362. if (new_rfkill)
  2363. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2364. else
  2365. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2366. wiphy_rfkill_set_hw_state(priv->hw->wiphy, new_rfkill);
  2367. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  2368. new_rfkill ? "disable radio" : "enable radio");
  2369. }
  2370. /* Keep this running, even if radio now enabled. This will be
  2371. * cancelled in mac_start() if system decides to start again */
  2372. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  2373. round_jiffies_relative(2 * HZ));
  2374. }
  2375. int iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2376. {
  2377. struct iwl_host_cmd cmd = {
  2378. .id = REPLY_SCAN_CMD,
  2379. .len = sizeof(struct iwl3945_scan_cmd),
  2380. .flags = CMD_SIZE_HUGE,
  2381. };
  2382. struct iwl3945_scan_cmd *scan;
  2383. u8 n_probes = 0;
  2384. enum ieee80211_band band;
  2385. bool is_active = false;
  2386. int ret;
  2387. lockdep_assert_held(&priv->mutex);
  2388. if (!priv->scan_cmd) {
  2389. priv->scan_cmd = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  2390. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  2391. if (!priv->scan_cmd) {
  2392. IWL_DEBUG_SCAN(priv, "Fail to allocate scan memory\n");
  2393. return -ENOMEM;
  2394. }
  2395. }
  2396. scan = priv->scan_cmd;
  2397. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  2398. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  2399. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  2400. if (iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
  2401. u16 interval = 0;
  2402. u32 extra;
  2403. u32 suspend_time = 100;
  2404. u32 scan_suspend_time = 100;
  2405. unsigned long flags;
  2406. IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
  2407. spin_lock_irqsave(&priv->lock, flags);
  2408. if (priv->is_internal_short_scan)
  2409. interval = 0;
  2410. else
  2411. interval = vif->bss_conf.beacon_int;
  2412. spin_unlock_irqrestore(&priv->lock, flags);
  2413. scan->suspend_time = 0;
  2414. scan->max_out_time = cpu_to_le32(200 * 1024);
  2415. if (!interval)
  2416. interval = suspend_time;
  2417. /*
  2418. * suspend time format:
  2419. * 0-19: beacon interval in usec (time before exec.)
  2420. * 20-23: 0
  2421. * 24-31: number of beacons (suspend between channels)
  2422. */
  2423. extra = (suspend_time / interval) << 24;
  2424. scan_suspend_time = 0xFF0FFFFF &
  2425. (extra | ((suspend_time % interval) * 1024));
  2426. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  2427. IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
  2428. scan_suspend_time, interval);
  2429. }
  2430. if (priv->is_internal_short_scan) {
  2431. IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
  2432. } else if (priv->scan_request->n_ssids) {
  2433. int i, p = 0;
  2434. IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
  2435. for (i = 0; i < priv->scan_request->n_ssids; i++) {
  2436. /* always does wildcard anyway */
  2437. if (!priv->scan_request->ssids[i].ssid_len)
  2438. continue;
  2439. scan->direct_scan[p].id = WLAN_EID_SSID;
  2440. scan->direct_scan[p].len =
  2441. priv->scan_request->ssids[i].ssid_len;
  2442. memcpy(scan->direct_scan[p].ssid,
  2443. priv->scan_request->ssids[i].ssid,
  2444. priv->scan_request->ssids[i].ssid_len);
  2445. n_probes++;
  2446. p++;
  2447. }
  2448. is_active = true;
  2449. } else
  2450. IWL_DEBUG_SCAN(priv, "Kicking off passive scan.\n");
  2451. /* We don't build a direct scan probe request; the uCode will do
  2452. * that based on the direct_mask added to each channel entry */
  2453. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  2454. scan->tx_cmd.sta_id = priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
  2455. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2456. /* flags + rate selection */
  2457. switch (priv->scan_band) {
  2458. case IEEE80211_BAND_2GHZ:
  2459. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  2460. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  2461. band = IEEE80211_BAND_2GHZ;
  2462. break;
  2463. case IEEE80211_BAND_5GHZ:
  2464. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  2465. band = IEEE80211_BAND_5GHZ;
  2466. break;
  2467. default:
  2468. IWL_WARN(priv, "Invalid scan band\n");
  2469. return -EIO;
  2470. }
  2471. /*
  2472. * If active scaning is requested but a certain channel
  2473. * is marked passive, we can do active scanning if we
  2474. * detect transmissions.
  2475. */
  2476. scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
  2477. IWL_GOOD_CRC_TH_DISABLED;
  2478. if (!priv->is_internal_short_scan) {
  2479. scan->tx_cmd.len = cpu_to_le16(
  2480. iwl_fill_probe_req(priv,
  2481. (struct ieee80211_mgmt *)scan->data,
  2482. vif->addr,
  2483. priv->scan_request->ie,
  2484. priv->scan_request->ie_len,
  2485. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  2486. } else {
  2487. /* use bcast addr, will not be transmitted but must be valid */
  2488. scan->tx_cmd.len = cpu_to_le16(
  2489. iwl_fill_probe_req(priv,
  2490. (struct ieee80211_mgmt *)scan->data,
  2491. iwl_bcast_addr, NULL, 0,
  2492. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  2493. }
  2494. /* select Rx antennas */
  2495. scan->flags |= iwl3945_get_antenna_flags(priv);
  2496. if (priv->is_internal_short_scan) {
  2497. scan->channel_count =
  2498. iwl3945_get_single_channel_for_scan(priv, vif, band,
  2499. (void *)&scan->data[le16_to_cpu(
  2500. scan->tx_cmd.len)]);
  2501. } else {
  2502. scan->channel_count =
  2503. iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
  2504. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)], vif);
  2505. }
  2506. if (scan->channel_count == 0) {
  2507. IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
  2508. return -EIO;
  2509. }
  2510. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  2511. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  2512. cmd.data = scan;
  2513. scan->len = cpu_to_le16(cmd.len);
  2514. set_bit(STATUS_SCAN_HW, &priv->status);
  2515. ret = iwl_send_cmd_sync(priv, &cmd);
  2516. if (ret)
  2517. clear_bit(STATUS_SCAN_HW, &priv->status);
  2518. return ret;
  2519. }
  2520. void iwl3945_post_scan(struct iwl_priv *priv)
  2521. {
  2522. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2523. /*
  2524. * Since setting the RXON may have been deferred while
  2525. * performing the scan, fire one off if needed
  2526. */
  2527. if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
  2528. iwl3945_commit_rxon(priv, ctx);
  2529. }
  2530. static void iwl3945_bg_restart(struct work_struct *data)
  2531. {
  2532. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2533. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2534. return;
  2535. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2536. struct iwl_rxon_context *ctx;
  2537. mutex_lock(&priv->mutex);
  2538. for_each_context(priv, ctx)
  2539. ctx->vif = NULL;
  2540. priv->is_open = 0;
  2541. mutex_unlock(&priv->mutex);
  2542. iwl3945_down(priv);
  2543. ieee80211_restart_hw(priv->hw);
  2544. } else {
  2545. iwl3945_down(priv);
  2546. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2547. return;
  2548. mutex_lock(&priv->mutex);
  2549. __iwl3945_up(priv);
  2550. mutex_unlock(&priv->mutex);
  2551. }
  2552. }
  2553. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  2554. {
  2555. struct iwl_priv *priv =
  2556. container_of(data, struct iwl_priv, rx_replenish);
  2557. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2558. return;
  2559. mutex_lock(&priv->mutex);
  2560. iwl3945_rx_replenish(priv);
  2561. mutex_unlock(&priv->mutex);
  2562. }
  2563. void iwl3945_post_associate(struct iwl_priv *priv)
  2564. {
  2565. int rc = 0;
  2566. struct ieee80211_conf *conf = NULL;
  2567. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2568. if (!ctx->vif || !priv->is_open)
  2569. return;
  2570. if (ctx->vif->type == NL80211_IFTYPE_AP) {
  2571. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2572. return;
  2573. }
  2574. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2575. ctx->vif->bss_conf.aid, ctx->active.bssid_addr);
  2576. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2577. return;
  2578. iwl_scan_cancel_timeout(priv, 200);
  2579. conf = ieee80211_get_hw_conf(priv->hw);
  2580. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2581. iwl3945_commit_rxon(priv, ctx);
  2582. rc = iwl_send_rxon_timing(priv, ctx);
  2583. if (rc)
  2584. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2585. "Attempting to continue.\n");
  2586. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2587. ctx->staging.assoc_id = cpu_to_le16(ctx->vif->bss_conf.aid);
  2588. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2589. ctx->vif->bss_conf.aid, ctx->vif->bss_conf.beacon_int);
  2590. if (ctx->vif->bss_conf.use_short_preamble)
  2591. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2592. else
  2593. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2594. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2595. if (ctx->vif->bss_conf.use_short_slot)
  2596. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2597. else
  2598. ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2599. }
  2600. iwl3945_commit_rxon(priv, ctx);
  2601. switch (ctx->vif->type) {
  2602. case NL80211_IFTYPE_STATION:
  2603. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  2604. break;
  2605. case NL80211_IFTYPE_ADHOC:
  2606. iwl3945_send_beacon_cmd(priv);
  2607. break;
  2608. default:
  2609. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2610. __func__, ctx->vif->type);
  2611. break;
  2612. }
  2613. }
  2614. /*****************************************************************************
  2615. *
  2616. * mac80211 entry point functions
  2617. *
  2618. *****************************************************************************/
  2619. #define UCODE_READY_TIMEOUT (2 * HZ)
  2620. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  2621. {
  2622. struct iwl_priv *priv = hw->priv;
  2623. int ret;
  2624. IWL_DEBUG_MAC80211(priv, "enter\n");
  2625. /* we should be verifying the device is ready to be opened */
  2626. mutex_lock(&priv->mutex);
  2627. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2628. * ucode filename and max sizes are card-specific. */
  2629. if (!priv->ucode_code.len) {
  2630. ret = iwl3945_read_ucode(priv);
  2631. if (ret) {
  2632. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2633. mutex_unlock(&priv->mutex);
  2634. goto out_release_irq;
  2635. }
  2636. }
  2637. ret = __iwl3945_up(priv);
  2638. mutex_unlock(&priv->mutex);
  2639. if (ret)
  2640. goto out_release_irq;
  2641. IWL_DEBUG_INFO(priv, "Start UP work.\n");
  2642. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  2643. * mac80211 will not be run successfully. */
  2644. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2645. test_bit(STATUS_READY, &priv->status),
  2646. UCODE_READY_TIMEOUT);
  2647. if (!ret) {
  2648. if (!test_bit(STATUS_READY, &priv->status)) {
  2649. IWL_ERR(priv,
  2650. "Wait for START_ALIVE timeout after %dms.\n",
  2651. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2652. ret = -ETIMEDOUT;
  2653. goto out_release_irq;
  2654. }
  2655. }
  2656. /* ucode is running and will send rfkill notifications,
  2657. * no need to poll the killswitch state anymore */
  2658. cancel_delayed_work(&priv->_3945.rfkill_poll);
  2659. iwl_led_start(priv);
  2660. priv->is_open = 1;
  2661. IWL_DEBUG_MAC80211(priv, "leave\n");
  2662. return 0;
  2663. out_release_irq:
  2664. priv->is_open = 0;
  2665. IWL_DEBUG_MAC80211(priv, "leave - failed\n");
  2666. return ret;
  2667. }
  2668. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  2669. {
  2670. struct iwl_priv *priv = hw->priv;
  2671. IWL_DEBUG_MAC80211(priv, "enter\n");
  2672. if (!priv->is_open) {
  2673. IWL_DEBUG_MAC80211(priv, "leave - skip\n");
  2674. return;
  2675. }
  2676. priv->is_open = 0;
  2677. iwl3945_down(priv);
  2678. flush_workqueue(priv->workqueue);
  2679. /* start polling the killswitch state again */
  2680. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  2681. round_jiffies_relative(2 * HZ));
  2682. IWL_DEBUG_MAC80211(priv, "leave\n");
  2683. }
  2684. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2685. {
  2686. struct iwl_priv *priv = hw->priv;
  2687. IWL_DEBUG_MAC80211(priv, "enter\n");
  2688. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2689. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2690. if (iwl3945_tx_skb(priv, skb))
  2691. dev_kfree_skb_any(skb);
  2692. IWL_DEBUG_MAC80211(priv, "leave\n");
  2693. return NETDEV_TX_OK;
  2694. }
  2695. void iwl3945_config_ap(struct iwl_priv *priv)
  2696. {
  2697. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2698. struct ieee80211_vif *vif = ctx->vif;
  2699. int rc = 0;
  2700. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2701. return;
  2702. /* The following should be done only at AP bring up */
  2703. if (!(iwl_is_associated(priv, IWL_RXON_CTX_BSS))) {
  2704. /* RXON - unassoc (to set timing command) */
  2705. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2706. iwl3945_commit_rxon(priv, ctx);
  2707. /* RXON Timing */
  2708. rc = iwl_send_rxon_timing(priv, ctx);
  2709. if (rc)
  2710. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2711. "Attempting to continue.\n");
  2712. ctx->staging.assoc_id = 0;
  2713. if (vif->bss_conf.use_short_preamble)
  2714. ctx->staging.flags |=
  2715. RXON_FLG_SHORT_PREAMBLE_MSK;
  2716. else
  2717. ctx->staging.flags &=
  2718. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2719. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
  2720. if (vif->bss_conf.use_short_slot)
  2721. ctx->staging.flags |=
  2722. RXON_FLG_SHORT_SLOT_MSK;
  2723. else
  2724. ctx->staging.flags &=
  2725. ~RXON_FLG_SHORT_SLOT_MSK;
  2726. }
  2727. /* restore RXON assoc */
  2728. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2729. iwl3945_commit_rxon(priv, ctx);
  2730. }
  2731. iwl3945_send_beacon_cmd(priv);
  2732. /* FIXME - we need to add code here to detect a totally new
  2733. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2734. * clear sta table, add BCAST sta... */
  2735. }
  2736. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2737. struct ieee80211_vif *vif,
  2738. struct ieee80211_sta *sta,
  2739. struct ieee80211_key_conf *key)
  2740. {
  2741. struct iwl_priv *priv = hw->priv;
  2742. int ret = 0;
  2743. u8 sta_id = IWL_INVALID_STATION;
  2744. u8 static_key;
  2745. IWL_DEBUG_MAC80211(priv, "enter\n");
  2746. if (iwl3945_mod_params.sw_crypto) {
  2747. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2748. return -EOPNOTSUPP;
  2749. }
  2750. static_key = !iwl_is_associated(priv, IWL_RXON_CTX_BSS);
  2751. if (!static_key) {
  2752. sta_id = iwl_sta_id_or_broadcast(
  2753. priv, &priv->contexts[IWL_RXON_CTX_BSS], sta);
  2754. if (sta_id == IWL_INVALID_STATION)
  2755. return -EINVAL;
  2756. }
  2757. mutex_lock(&priv->mutex);
  2758. iwl_scan_cancel_timeout(priv, 100);
  2759. switch (cmd) {
  2760. case SET_KEY:
  2761. if (static_key)
  2762. ret = iwl3945_set_static_key(priv, key);
  2763. else
  2764. ret = iwl3945_set_dynamic_key(priv, key, sta_id);
  2765. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2766. break;
  2767. case DISABLE_KEY:
  2768. if (static_key)
  2769. ret = iwl3945_remove_static_key(priv);
  2770. else
  2771. ret = iwl3945_clear_sta_key_info(priv, sta_id);
  2772. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2773. break;
  2774. default:
  2775. ret = -EINVAL;
  2776. }
  2777. mutex_unlock(&priv->mutex);
  2778. IWL_DEBUG_MAC80211(priv, "leave\n");
  2779. return ret;
  2780. }
  2781. static int iwl3945_mac_sta_add(struct ieee80211_hw *hw,
  2782. struct ieee80211_vif *vif,
  2783. struct ieee80211_sta *sta)
  2784. {
  2785. struct iwl_priv *priv = hw->priv;
  2786. struct iwl3945_sta_priv *sta_priv = (void *)sta->drv_priv;
  2787. int ret;
  2788. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2789. u8 sta_id;
  2790. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2791. sta->addr);
  2792. mutex_lock(&priv->mutex);
  2793. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2794. sta->addr);
  2795. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2796. ret = iwl_add_station_common(priv, &priv->contexts[IWL_RXON_CTX_BSS],
  2797. sta->addr, is_ap, sta, &sta_id);
  2798. if (ret) {
  2799. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2800. sta->addr, ret);
  2801. /* Should we return success if return code is EEXIST ? */
  2802. mutex_unlock(&priv->mutex);
  2803. return ret;
  2804. }
  2805. sta_priv->common.sta_id = sta_id;
  2806. /* Initialize rate scaling */
  2807. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2808. sta->addr);
  2809. iwl3945_rs_rate_init(priv, sta, sta_id);
  2810. mutex_unlock(&priv->mutex);
  2811. return 0;
  2812. }
  2813. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  2814. unsigned int changed_flags,
  2815. unsigned int *total_flags,
  2816. u64 multicast)
  2817. {
  2818. struct iwl_priv *priv = hw->priv;
  2819. __le32 filter_or = 0, filter_nand = 0;
  2820. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2821. #define CHK(test, flag) do { \
  2822. if (*total_flags & (test)) \
  2823. filter_or |= (flag); \
  2824. else \
  2825. filter_nand |= (flag); \
  2826. } while (0)
  2827. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  2828. changed_flags, *total_flags);
  2829. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2830. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
  2831. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2832. #undef CHK
  2833. mutex_lock(&priv->mutex);
  2834. ctx->staging.filter_flags &= ~filter_nand;
  2835. ctx->staging.filter_flags |= filter_or;
  2836. /*
  2837. * Not committing directly because hardware can perform a scan,
  2838. * but even if hw is ready, committing here breaks for some reason,
  2839. * we'll eventually commit the filter flags change anyway.
  2840. */
  2841. mutex_unlock(&priv->mutex);
  2842. /*
  2843. * Receiving all multicast frames is always enabled by the
  2844. * default flags setup in iwl_connection_init_rx_config()
  2845. * since we currently do not support programming multicast
  2846. * filters into the device.
  2847. */
  2848. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2849. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2850. }
  2851. /*****************************************************************************
  2852. *
  2853. * sysfs attributes
  2854. *
  2855. *****************************************************************************/
  2856. #ifdef CONFIG_IWLWIFI_DEBUG
  2857. /*
  2858. * The following adds a new attribute to the sysfs representation
  2859. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  2860. * used for controlling the debug level.
  2861. *
  2862. * See the level definitions in iwl for details.
  2863. *
  2864. * The debug_level being managed using sysfs below is a per device debug
  2865. * level that is used instead of the global debug level if it (the per
  2866. * device debug level) is set.
  2867. */
  2868. static ssize_t show_debug_level(struct device *d,
  2869. struct device_attribute *attr, char *buf)
  2870. {
  2871. struct iwl_priv *priv = dev_get_drvdata(d);
  2872. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2873. }
  2874. static ssize_t store_debug_level(struct device *d,
  2875. struct device_attribute *attr,
  2876. const char *buf, size_t count)
  2877. {
  2878. struct iwl_priv *priv = dev_get_drvdata(d);
  2879. unsigned long val;
  2880. int ret;
  2881. ret = strict_strtoul(buf, 0, &val);
  2882. if (ret)
  2883. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  2884. else {
  2885. priv->debug_level = val;
  2886. if (iwl_alloc_traffic_mem(priv))
  2887. IWL_ERR(priv,
  2888. "Not enough memory to generate traffic log\n");
  2889. }
  2890. return strnlen(buf, count);
  2891. }
  2892. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2893. show_debug_level, store_debug_level);
  2894. #endif /* CONFIG_IWLWIFI_DEBUG */
  2895. static ssize_t show_temperature(struct device *d,
  2896. struct device_attribute *attr, char *buf)
  2897. {
  2898. struct iwl_priv *priv = dev_get_drvdata(d);
  2899. if (!iwl_is_alive(priv))
  2900. return -EAGAIN;
  2901. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  2902. }
  2903. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2904. static ssize_t show_tx_power(struct device *d,
  2905. struct device_attribute *attr, char *buf)
  2906. {
  2907. struct iwl_priv *priv = dev_get_drvdata(d);
  2908. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2909. }
  2910. static ssize_t store_tx_power(struct device *d,
  2911. struct device_attribute *attr,
  2912. const char *buf, size_t count)
  2913. {
  2914. struct iwl_priv *priv = dev_get_drvdata(d);
  2915. char *p = (char *)buf;
  2916. u32 val;
  2917. val = simple_strtoul(p, &p, 10);
  2918. if (p == buf)
  2919. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  2920. else
  2921. iwl3945_hw_reg_set_txpower(priv, val);
  2922. return count;
  2923. }
  2924. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2925. static ssize_t show_flags(struct device *d,
  2926. struct device_attribute *attr, char *buf)
  2927. {
  2928. struct iwl_priv *priv = dev_get_drvdata(d);
  2929. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2930. return sprintf(buf, "0x%04X\n", ctx->active.flags);
  2931. }
  2932. static ssize_t store_flags(struct device *d,
  2933. struct device_attribute *attr,
  2934. const char *buf, size_t count)
  2935. {
  2936. struct iwl_priv *priv = dev_get_drvdata(d);
  2937. u32 flags = simple_strtoul(buf, NULL, 0);
  2938. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2939. mutex_lock(&priv->mutex);
  2940. if (le32_to_cpu(ctx->staging.flags) != flags) {
  2941. /* Cancel any currently running scans... */
  2942. if (iwl_scan_cancel_timeout(priv, 100))
  2943. IWL_WARN(priv, "Could not cancel scan.\n");
  2944. else {
  2945. IWL_DEBUG_INFO(priv, "Committing rxon.flags = 0x%04X\n",
  2946. flags);
  2947. ctx->staging.flags = cpu_to_le32(flags);
  2948. iwl3945_commit_rxon(priv, ctx);
  2949. }
  2950. }
  2951. mutex_unlock(&priv->mutex);
  2952. return count;
  2953. }
  2954. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2955. static ssize_t show_filter_flags(struct device *d,
  2956. struct device_attribute *attr, char *buf)
  2957. {
  2958. struct iwl_priv *priv = dev_get_drvdata(d);
  2959. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2960. return sprintf(buf, "0x%04X\n",
  2961. le32_to_cpu(ctx->active.filter_flags));
  2962. }
  2963. static ssize_t store_filter_flags(struct device *d,
  2964. struct device_attribute *attr,
  2965. const char *buf, size_t count)
  2966. {
  2967. struct iwl_priv *priv = dev_get_drvdata(d);
  2968. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2969. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  2970. mutex_lock(&priv->mutex);
  2971. if (le32_to_cpu(ctx->staging.filter_flags) != filter_flags) {
  2972. /* Cancel any currently running scans... */
  2973. if (iwl_scan_cancel_timeout(priv, 100))
  2974. IWL_WARN(priv, "Could not cancel scan.\n");
  2975. else {
  2976. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2977. "0x%04X\n", filter_flags);
  2978. ctx->staging.filter_flags =
  2979. cpu_to_le32(filter_flags);
  2980. iwl3945_commit_rxon(priv, ctx);
  2981. }
  2982. }
  2983. mutex_unlock(&priv->mutex);
  2984. return count;
  2985. }
  2986. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2987. store_filter_flags);
  2988. static ssize_t show_measurement(struct device *d,
  2989. struct device_attribute *attr, char *buf)
  2990. {
  2991. struct iwl_priv *priv = dev_get_drvdata(d);
  2992. struct iwl_spectrum_notification measure_report;
  2993. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  2994. u8 *data = (u8 *)&measure_report;
  2995. unsigned long flags;
  2996. spin_lock_irqsave(&priv->lock, flags);
  2997. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  2998. spin_unlock_irqrestore(&priv->lock, flags);
  2999. return 0;
  3000. }
  3001. memcpy(&measure_report, &priv->measure_report, size);
  3002. priv->measurement_status = 0;
  3003. spin_unlock_irqrestore(&priv->lock, flags);
  3004. while (size && (PAGE_SIZE - len)) {
  3005. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  3006. PAGE_SIZE - len, 1);
  3007. len = strlen(buf);
  3008. if (PAGE_SIZE - len)
  3009. buf[len++] = '\n';
  3010. ofs += 16;
  3011. size -= min(size, 16U);
  3012. }
  3013. return len;
  3014. }
  3015. static ssize_t store_measurement(struct device *d,
  3016. struct device_attribute *attr,
  3017. const char *buf, size_t count)
  3018. {
  3019. struct iwl_priv *priv = dev_get_drvdata(d);
  3020. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  3021. struct ieee80211_measurement_params params = {
  3022. .channel = le16_to_cpu(ctx->active.channel),
  3023. .start_time = cpu_to_le64(priv->_3945.last_tsf),
  3024. .duration = cpu_to_le16(1),
  3025. };
  3026. u8 type = IWL_MEASURE_BASIC;
  3027. u8 buffer[32];
  3028. u8 channel;
  3029. if (count) {
  3030. char *p = buffer;
  3031. strncpy(buffer, buf, min(sizeof(buffer), count));
  3032. channel = simple_strtoul(p, NULL, 0);
  3033. if (channel)
  3034. params.channel = channel;
  3035. p = buffer;
  3036. while (*p && *p != ' ')
  3037. p++;
  3038. if (*p)
  3039. type = simple_strtoul(p + 1, NULL, 0);
  3040. }
  3041. IWL_DEBUG_INFO(priv, "Invoking measurement of type %d on "
  3042. "channel %d (for '%s')\n", type, params.channel, buf);
  3043. iwl3945_get_measurement(priv, &params, type);
  3044. return count;
  3045. }
  3046. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  3047. show_measurement, store_measurement);
  3048. static ssize_t store_retry_rate(struct device *d,
  3049. struct device_attribute *attr,
  3050. const char *buf, size_t count)
  3051. {
  3052. struct iwl_priv *priv = dev_get_drvdata(d);
  3053. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  3054. if (priv->retry_rate <= 0)
  3055. priv->retry_rate = 1;
  3056. return count;
  3057. }
  3058. static ssize_t show_retry_rate(struct device *d,
  3059. struct device_attribute *attr, char *buf)
  3060. {
  3061. struct iwl_priv *priv = dev_get_drvdata(d);
  3062. return sprintf(buf, "%d", priv->retry_rate);
  3063. }
  3064. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  3065. store_retry_rate);
  3066. static ssize_t show_channels(struct device *d,
  3067. struct device_attribute *attr, char *buf)
  3068. {
  3069. /* all this shit doesn't belong into sysfs anyway */
  3070. return 0;
  3071. }
  3072. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  3073. static ssize_t show_antenna(struct device *d,
  3074. struct device_attribute *attr, char *buf)
  3075. {
  3076. struct iwl_priv *priv = dev_get_drvdata(d);
  3077. if (!iwl_is_alive(priv))
  3078. return -EAGAIN;
  3079. return sprintf(buf, "%d\n", iwl3945_mod_params.antenna);
  3080. }
  3081. static ssize_t store_antenna(struct device *d,
  3082. struct device_attribute *attr,
  3083. const char *buf, size_t count)
  3084. {
  3085. struct iwl_priv *priv __maybe_unused = dev_get_drvdata(d);
  3086. int ant;
  3087. if (count == 0)
  3088. return 0;
  3089. if (sscanf(buf, "%1i", &ant) != 1) {
  3090. IWL_DEBUG_INFO(priv, "not in hex or decimal form.\n");
  3091. return count;
  3092. }
  3093. if ((ant >= 0) && (ant <= 2)) {
  3094. IWL_DEBUG_INFO(priv, "Setting antenna select to %d.\n", ant);
  3095. iwl3945_mod_params.antenna = (enum iwl3945_antenna)ant;
  3096. } else
  3097. IWL_DEBUG_INFO(priv, "Bad antenna select value %d.\n", ant);
  3098. return count;
  3099. }
  3100. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  3101. static ssize_t show_status(struct device *d,
  3102. struct device_attribute *attr, char *buf)
  3103. {
  3104. struct iwl_priv *priv = dev_get_drvdata(d);
  3105. if (!iwl_is_alive(priv))
  3106. return -EAGAIN;
  3107. return sprintf(buf, "0x%08x\n", (int)priv->status);
  3108. }
  3109. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  3110. static ssize_t dump_error_log(struct device *d,
  3111. struct device_attribute *attr,
  3112. const char *buf, size_t count)
  3113. {
  3114. struct iwl_priv *priv = dev_get_drvdata(d);
  3115. char *p = (char *)buf;
  3116. if (p[0] == '1')
  3117. iwl3945_dump_nic_error_log(priv);
  3118. return strnlen(buf, count);
  3119. }
  3120. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  3121. /*****************************************************************************
  3122. *
  3123. * driver setup and tear down
  3124. *
  3125. *****************************************************************************/
  3126. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  3127. {
  3128. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  3129. init_waitqueue_head(&priv->wait_command_queue);
  3130. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  3131. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  3132. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  3133. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  3134. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  3135. INIT_DELAYED_WORK(&priv->_3945.rfkill_poll, iwl3945_rfkill_poll);
  3136. iwl_setup_scan_deferred_work(priv);
  3137. iwl3945_hw_setup_deferred_work(priv);
  3138. init_timer(&priv->watchdog);
  3139. priv->watchdog.data = (unsigned long)priv;
  3140. priv->watchdog.function = iwl_bg_watchdog;
  3141. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  3142. iwl3945_irq_tasklet, (unsigned long)priv);
  3143. }
  3144. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  3145. {
  3146. iwl3945_hw_cancel_deferred_work(priv);
  3147. cancel_delayed_work_sync(&priv->init_alive_start);
  3148. cancel_delayed_work(&priv->alive_start);
  3149. cancel_work_sync(&priv->beacon_update);
  3150. iwl_cancel_scan_deferred_work(priv);
  3151. }
  3152. static struct attribute *iwl3945_sysfs_entries[] = {
  3153. &dev_attr_antenna.attr,
  3154. &dev_attr_channels.attr,
  3155. &dev_attr_dump_errors.attr,
  3156. &dev_attr_flags.attr,
  3157. &dev_attr_filter_flags.attr,
  3158. &dev_attr_measurement.attr,
  3159. &dev_attr_retry_rate.attr,
  3160. &dev_attr_status.attr,
  3161. &dev_attr_temperature.attr,
  3162. &dev_attr_tx_power.attr,
  3163. #ifdef CONFIG_IWLWIFI_DEBUG
  3164. &dev_attr_debug_level.attr,
  3165. #endif
  3166. NULL
  3167. };
  3168. static struct attribute_group iwl3945_attribute_group = {
  3169. .name = NULL, /* put in device directory */
  3170. .attrs = iwl3945_sysfs_entries,
  3171. };
  3172. struct ieee80211_ops iwl3945_hw_ops = {
  3173. .tx = iwl3945_mac_tx,
  3174. .start = iwl3945_mac_start,
  3175. .stop = iwl3945_mac_stop,
  3176. .add_interface = iwl_mac_add_interface,
  3177. .remove_interface = iwl_mac_remove_interface,
  3178. .change_interface = iwl_mac_change_interface,
  3179. .config = iwl_legacy_mac_config,
  3180. .configure_filter = iwl3945_configure_filter,
  3181. .set_key = iwl3945_mac_set_key,
  3182. .conf_tx = iwl_mac_conf_tx,
  3183. .reset_tsf = iwl_legacy_mac_reset_tsf,
  3184. .bss_info_changed = iwl_legacy_mac_bss_info_changed,
  3185. .hw_scan = iwl_mac_hw_scan,
  3186. .sta_add = iwl3945_mac_sta_add,
  3187. .sta_remove = iwl_mac_sta_remove,
  3188. .tx_last_beacon = iwl_mac_tx_last_beacon,
  3189. };
  3190. static int iwl3945_init_drv(struct iwl_priv *priv)
  3191. {
  3192. int ret;
  3193. struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  3194. priv->retry_rate = 1;
  3195. priv->beacon_skb = NULL;
  3196. spin_lock_init(&priv->sta_lock);
  3197. spin_lock_init(&priv->hcmd_lock);
  3198. INIT_LIST_HEAD(&priv->free_frames);
  3199. mutex_init(&priv->mutex);
  3200. mutex_init(&priv->sync_cmd_mutex);
  3201. priv->ieee_channels = NULL;
  3202. priv->ieee_rates = NULL;
  3203. priv->band = IEEE80211_BAND_2GHZ;
  3204. priv->iw_mode = NL80211_IFTYPE_STATION;
  3205. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  3206. /* initialize force reset */
  3207. priv->force_reset[IWL_RF_RESET].reset_duration =
  3208. IWL_DELAY_NEXT_FORCE_RF_RESET;
  3209. priv->force_reset[IWL_FW_RESET].reset_duration =
  3210. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  3211. priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
  3212. priv->tx_power_next = IWL_DEFAULT_TX_POWER;
  3213. if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
  3214. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3215. eeprom->version);
  3216. ret = -EINVAL;
  3217. goto err;
  3218. }
  3219. ret = iwl_init_channel_map(priv);
  3220. if (ret) {
  3221. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  3222. goto err;
  3223. }
  3224. /* Set up txpower settings in driver for all channels */
  3225. if (iwl3945_txpower_set_from_eeprom(priv)) {
  3226. ret = -EIO;
  3227. goto err_free_channel_map;
  3228. }
  3229. ret = iwlcore_init_geos(priv);
  3230. if (ret) {
  3231. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  3232. goto err_free_channel_map;
  3233. }
  3234. iwl3945_init_hw_rates(priv, priv->ieee_rates);
  3235. return 0;
  3236. err_free_channel_map:
  3237. iwl_free_channel_map(priv);
  3238. err:
  3239. return ret;
  3240. }
  3241. #define IWL3945_MAX_PROBE_REQUEST 200
  3242. static int iwl3945_setup_mac(struct iwl_priv *priv)
  3243. {
  3244. int ret;
  3245. struct ieee80211_hw *hw = priv->hw;
  3246. hw->rate_control_algorithm = "iwl-3945-rs";
  3247. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  3248. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  3249. /* Tell mac80211 our characteristics */
  3250. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  3251. IEEE80211_HW_SPECTRUM_MGMT;
  3252. if (!priv->cfg->base_params->broken_powersave)
  3253. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  3254. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  3255. hw->wiphy->interface_modes =
  3256. priv->contexts[IWL_RXON_CTX_BSS].interface_modes;
  3257. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  3258. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  3259. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
  3260. /* we create the 802.11 header and a zero-length SSID element */
  3261. hw->wiphy->max_scan_ie_len = IWL3945_MAX_PROBE_REQUEST - 24 - 2;
  3262. /* Default value; 4 EDCA QOS priorities */
  3263. hw->queues = 4;
  3264. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3265. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3266. &priv->bands[IEEE80211_BAND_2GHZ];
  3267. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3268. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3269. &priv->bands[IEEE80211_BAND_5GHZ];
  3270. ret = ieee80211_register_hw(priv->hw);
  3271. if (ret) {
  3272. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  3273. return ret;
  3274. }
  3275. priv->mac80211_registered = 1;
  3276. return 0;
  3277. }
  3278. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  3279. {
  3280. int err = 0, i;
  3281. struct iwl_priv *priv;
  3282. struct ieee80211_hw *hw;
  3283. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  3284. struct iwl3945_eeprom *eeprom;
  3285. unsigned long flags;
  3286. /***********************
  3287. * 1. Allocating HW data
  3288. * ********************/
  3289. /* mac80211 allocates memory for this device instance, including
  3290. * space for this driver's private structure */
  3291. hw = iwl_alloc_all(cfg);
  3292. if (hw == NULL) {
  3293. pr_err("Can not allocate network device\n");
  3294. err = -ENOMEM;
  3295. goto out;
  3296. }
  3297. priv = hw->priv;
  3298. SET_IEEE80211_DEV(hw, &pdev->dev);
  3299. priv->cmd_queue = IWL39_CMD_QUEUE_NUM;
  3300. /* 3945 has only one valid context */
  3301. priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
  3302. for (i = 0; i < NUM_IWL_RXON_CTX; i++)
  3303. priv->contexts[i].ctxid = i;
  3304. priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
  3305. priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
  3306. priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
  3307. priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
  3308. priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
  3309. priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
  3310. priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
  3311. BIT(NL80211_IFTYPE_STATION) |
  3312. BIT(NL80211_IFTYPE_ADHOC);
  3313. priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
  3314. priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
  3315. priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
  3316. /*
  3317. * Disabling hardware scan means that mac80211 will perform scans
  3318. * "the hard way", rather than using device's scan.
  3319. */
  3320. if (iwl3945_mod_params.disable_hw_scan) {
  3321. dev_printk(KERN_DEBUG, &(pdev->dev),
  3322. "sw scan support is deprecated\n");
  3323. iwl3945_hw_ops.hw_scan = NULL;
  3324. }
  3325. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3326. priv->cfg = cfg;
  3327. priv->pci_dev = pdev;
  3328. priv->inta_mask = CSR_INI_SET_MASK;
  3329. if (iwl_alloc_traffic_mem(priv))
  3330. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3331. /***************************
  3332. * 2. Initializing PCI bus
  3333. * *************************/
  3334. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  3335. PCIE_LINK_STATE_CLKPM);
  3336. if (pci_enable_device(pdev)) {
  3337. err = -ENODEV;
  3338. goto out_ieee80211_free_hw;
  3339. }
  3340. pci_set_master(pdev);
  3341. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3342. if (!err)
  3343. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3344. if (err) {
  3345. IWL_WARN(priv, "No suitable DMA available.\n");
  3346. goto out_pci_disable_device;
  3347. }
  3348. pci_set_drvdata(pdev, priv);
  3349. err = pci_request_regions(pdev, DRV_NAME);
  3350. if (err)
  3351. goto out_pci_disable_device;
  3352. /***********************
  3353. * 3. Read REV Register
  3354. * ********************/
  3355. priv->hw_base = pci_iomap(pdev, 0, 0);
  3356. if (!priv->hw_base) {
  3357. err = -ENODEV;
  3358. goto out_pci_release_regions;
  3359. }
  3360. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3361. (unsigned long long) pci_resource_len(pdev, 0));
  3362. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3363. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3364. * PCI Tx retries from interfering with C3 CPU state */
  3365. pci_write_config_byte(pdev, 0x41, 0x00);
  3366. /* these spin locks will be used in apm_ops.init and EEPROM access
  3367. * we should init now
  3368. */
  3369. spin_lock_init(&priv->reg_lock);
  3370. spin_lock_init(&priv->lock);
  3371. /*
  3372. * stop and reset the on-board processor just in case it is in a
  3373. * strange state ... like being left stranded by a primary kernel
  3374. * and this is now the kdump kernel trying to start up
  3375. */
  3376. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3377. /***********************
  3378. * 4. Read EEPROM
  3379. * ********************/
  3380. /* Read the EEPROM */
  3381. err = iwl_eeprom_init(priv);
  3382. if (err) {
  3383. IWL_ERR(priv, "Unable to init EEPROM\n");
  3384. goto out_iounmap;
  3385. }
  3386. /* MAC Address location in EEPROM same for 3945/4965 */
  3387. eeprom = (struct iwl3945_eeprom *)priv->eeprom;
  3388. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", eeprom->mac_address);
  3389. SET_IEEE80211_PERM_ADDR(priv->hw, eeprom->mac_address);
  3390. /***********************
  3391. * 5. Setup HW Constants
  3392. * ********************/
  3393. /* Device-specific setup */
  3394. if (iwl3945_hw_set_hw_params(priv)) {
  3395. IWL_ERR(priv, "failed to set hw settings\n");
  3396. goto out_eeprom_free;
  3397. }
  3398. /***********************
  3399. * 6. Setup priv
  3400. * ********************/
  3401. err = iwl3945_init_drv(priv);
  3402. if (err) {
  3403. IWL_ERR(priv, "initializing driver failed\n");
  3404. goto out_unset_hw_params;
  3405. }
  3406. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  3407. priv->cfg->name);
  3408. /***********************
  3409. * 7. Setup Services
  3410. * ********************/
  3411. spin_lock_irqsave(&priv->lock, flags);
  3412. iwl_disable_interrupts(priv);
  3413. spin_unlock_irqrestore(&priv->lock, flags);
  3414. pci_enable_msi(priv->pci_dev);
  3415. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
  3416. IRQF_SHARED, DRV_NAME, priv);
  3417. if (err) {
  3418. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3419. goto out_disable_msi;
  3420. }
  3421. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3422. if (err) {
  3423. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  3424. goto out_release_irq;
  3425. }
  3426. iwl_set_rxon_channel(priv,
  3427. &priv->bands[IEEE80211_BAND_2GHZ].channels[5],
  3428. &priv->contexts[IWL_RXON_CTX_BSS]);
  3429. iwl3945_setup_deferred_work(priv);
  3430. iwl3945_setup_rx_handlers(priv);
  3431. iwl_power_initialize(priv);
  3432. /*********************************
  3433. * 8. Setup and Register mac80211
  3434. * *******************************/
  3435. iwl_enable_interrupts(priv);
  3436. err = iwl3945_setup_mac(priv);
  3437. if (err)
  3438. goto out_remove_sysfs;
  3439. err = iwl_dbgfs_register(priv, DRV_NAME);
  3440. if (err)
  3441. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  3442. /* Start monitoring the killswitch */
  3443. queue_delayed_work(priv->workqueue, &priv->_3945.rfkill_poll,
  3444. 2 * HZ);
  3445. return 0;
  3446. out_remove_sysfs:
  3447. destroy_workqueue(priv->workqueue);
  3448. priv->workqueue = NULL;
  3449. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3450. out_release_irq:
  3451. free_irq(priv->pci_dev->irq, priv);
  3452. out_disable_msi:
  3453. pci_disable_msi(priv->pci_dev);
  3454. iwlcore_free_geos(priv);
  3455. iwl_free_channel_map(priv);
  3456. out_unset_hw_params:
  3457. iwl3945_unset_hw_params(priv);
  3458. out_eeprom_free:
  3459. iwl_eeprom_free(priv);
  3460. out_iounmap:
  3461. pci_iounmap(pdev, priv->hw_base);
  3462. out_pci_release_regions:
  3463. pci_release_regions(pdev);
  3464. out_pci_disable_device:
  3465. pci_set_drvdata(pdev, NULL);
  3466. pci_disable_device(pdev);
  3467. out_ieee80211_free_hw:
  3468. iwl_free_traffic_mem(priv);
  3469. ieee80211_free_hw(priv->hw);
  3470. out:
  3471. return err;
  3472. }
  3473. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  3474. {
  3475. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3476. unsigned long flags;
  3477. if (!priv)
  3478. return;
  3479. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3480. iwl_dbgfs_unregister(priv);
  3481. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3482. if (priv->mac80211_registered) {
  3483. ieee80211_unregister_hw(priv->hw);
  3484. priv->mac80211_registered = 0;
  3485. } else {
  3486. iwl3945_down(priv);
  3487. }
  3488. /*
  3489. * Make sure device is reset to low power before unloading driver.
  3490. * This may be redundant with iwl_down(), but there are paths to
  3491. * run iwl_down() without calling apm_ops.stop(), and there are
  3492. * paths to avoid running iwl_down() at all before leaving driver.
  3493. * This (inexpensive) call *makes sure* device is reset.
  3494. */
  3495. iwl_apm_stop(priv);
  3496. /* make sure we flush any pending irq or
  3497. * tasklet for the driver
  3498. */
  3499. spin_lock_irqsave(&priv->lock, flags);
  3500. iwl_disable_interrupts(priv);
  3501. spin_unlock_irqrestore(&priv->lock, flags);
  3502. iwl_synchronize_irq(priv);
  3503. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  3504. cancel_delayed_work_sync(&priv->_3945.rfkill_poll);
  3505. iwl3945_dealloc_ucode_pci(priv);
  3506. if (priv->rxq.bd)
  3507. iwl3945_rx_queue_free(priv, &priv->rxq);
  3508. iwl3945_hw_txq_ctx_free(priv);
  3509. iwl3945_unset_hw_params(priv);
  3510. /*netif_stop_queue(dev); */
  3511. flush_workqueue(priv->workqueue);
  3512. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  3513. * priv->workqueue... so we can't take down the workqueue
  3514. * until now... */
  3515. destroy_workqueue(priv->workqueue);
  3516. priv->workqueue = NULL;
  3517. iwl_free_traffic_mem(priv);
  3518. free_irq(pdev->irq, priv);
  3519. pci_disable_msi(pdev);
  3520. pci_iounmap(pdev, priv->hw_base);
  3521. pci_release_regions(pdev);
  3522. pci_disable_device(pdev);
  3523. pci_set_drvdata(pdev, NULL);
  3524. iwl_free_channel_map(priv);
  3525. iwlcore_free_geos(priv);
  3526. kfree(priv->scan_cmd);
  3527. if (priv->beacon_skb)
  3528. dev_kfree_skb(priv->beacon_skb);
  3529. ieee80211_free_hw(priv->hw);
  3530. }
  3531. /*****************************************************************************
  3532. *
  3533. * driver and module entry point
  3534. *
  3535. *****************************************************************************/
  3536. static struct pci_driver iwl3945_driver = {
  3537. .name = DRV_NAME,
  3538. .id_table = iwl3945_hw_card_ids,
  3539. .probe = iwl3945_pci_probe,
  3540. .remove = __devexit_p(iwl3945_pci_remove),
  3541. .driver.pm = IWL_PM_OPS,
  3542. };
  3543. static int __init iwl3945_init(void)
  3544. {
  3545. int ret;
  3546. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3547. pr_info(DRV_COPYRIGHT "\n");
  3548. ret = iwl3945_rate_control_register();
  3549. if (ret) {
  3550. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3551. return ret;
  3552. }
  3553. ret = pci_register_driver(&iwl3945_driver);
  3554. if (ret) {
  3555. pr_err("Unable to initialize PCI module\n");
  3556. goto error_register;
  3557. }
  3558. return ret;
  3559. error_register:
  3560. iwl3945_rate_control_unregister();
  3561. return ret;
  3562. }
  3563. static void __exit iwl3945_exit(void)
  3564. {
  3565. pci_unregister_driver(&iwl3945_driver);
  3566. iwl3945_rate_control_unregister();
  3567. }
  3568. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  3569. module_param_named(antenna, iwl3945_mod_params.antenna, int, S_IRUGO);
  3570. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  3571. module_param_named(swcrypto, iwl3945_mod_params.sw_crypto, int, S_IRUGO);
  3572. MODULE_PARM_DESC(swcrypto,
  3573. "using software crypto (default 1 [software])\n");
  3574. #ifdef CONFIG_IWLWIFI_DEBUG
  3575. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3576. MODULE_PARM_DESC(debug, "debug output mask");
  3577. #endif
  3578. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan,
  3579. int, S_IRUGO);
  3580. MODULE_PARM_DESC(disable_hw_scan,
  3581. "disable hardware scanning (default 0) (deprecated)");
  3582. module_param_named(fw_restart3945, iwl3945_mod_params.restart_fw, int, S_IRUGO);
  3583. MODULE_PARM_DESC(fw_restart3945, "restart firmware in case of error");
  3584. module_exit(iwl3945_exit);
  3585. module_init(iwl3945_init);