phy.c 90 KB

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  1. /*
  2. * PHY functions
  3. *
  4. * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
  5. * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
  6. * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
  7. * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
  8. *
  9. * Permission to use, copy, modify, and distribute this software for any
  10. * purpose with or without fee is hereby granted, provided that the above
  11. * copyright notice and this permission notice appear in all copies.
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20. *
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/slab.h>
  24. #include "ath5k.h"
  25. #include "reg.h"
  26. #include "base.h"
  27. #include "rfbuffer.h"
  28. #include "rfgain.h"
  29. /******************\
  30. * Helper functions *
  31. \******************/
  32. /*
  33. * Get the PHY Chip revision
  34. */
  35. u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
  36. {
  37. unsigned int i;
  38. u32 srev;
  39. u16 ret;
  40. /*
  41. * Set the radio chip access register
  42. */
  43. switch (chan) {
  44. case CHANNEL_2GHZ:
  45. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
  46. break;
  47. case CHANNEL_5GHZ:
  48. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
  49. break;
  50. default:
  51. return 0;
  52. }
  53. mdelay(2);
  54. /* ...wait until PHY is ready and read the selected radio revision */
  55. ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
  56. for (i = 0; i < 8; i++)
  57. ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
  58. if (ah->ah_version == AR5K_AR5210) {
  59. srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
  60. ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
  61. } else {
  62. srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
  63. ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
  64. ((srev & 0x0f) << 4), 8);
  65. }
  66. /* Reset to the 5GHz mode */
  67. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
  68. return ret;
  69. }
  70. /*
  71. * Check if a channel is supported
  72. */
  73. bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
  74. {
  75. /* Check if the channel is in our supported range */
  76. if (flags & CHANNEL_2GHZ) {
  77. if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
  78. (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
  79. return true;
  80. } else if (flags & CHANNEL_5GHZ)
  81. if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
  82. (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
  83. return true;
  84. return false;
  85. }
  86. bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
  87. struct ieee80211_channel *channel)
  88. {
  89. u8 refclk_freq;
  90. if ((ah->ah_radio == AR5K_RF5112) ||
  91. (ah->ah_radio == AR5K_RF5413) ||
  92. (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
  93. refclk_freq = 40;
  94. else
  95. refclk_freq = 32;
  96. if ((channel->center_freq % refclk_freq != 0) &&
  97. ((channel->center_freq % refclk_freq < 10) ||
  98. (channel->center_freq % refclk_freq > 22)))
  99. return true;
  100. else
  101. return false;
  102. }
  103. /*
  104. * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
  105. */
  106. static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
  107. const struct ath5k_rf_reg *rf_regs,
  108. u32 val, u8 reg_id, bool set)
  109. {
  110. const struct ath5k_rf_reg *rfreg = NULL;
  111. u8 offset, bank, num_bits, col, position;
  112. u16 entry;
  113. u32 mask, data, last_bit, bits_shifted, first_bit;
  114. u32 *rfb;
  115. s32 bits_left;
  116. int i;
  117. data = 0;
  118. rfb = ah->ah_rf_banks;
  119. for (i = 0; i < ah->ah_rf_regs_count; i++) {
  120. if (rf_regs[i].index == reg_id) {
  121. rfreg = &rf_regs[i];
  122. break;
  123. }
  124. }
  125. if (rfb == NULL || rfreg == NULL) {
  126. ATH5K_PRINTF("Rf register not found!\n");
  127. /* should not happen */
  128. return 0;
  129. }
  130. bank = rfreg->bank;
  131. num_bits = rfreg->field.len;
  132. first_bit = rfreg->field.pos;
  133. col = rfreg->field.col;
  134. /* first_bit is an offset from bank's
  135. * start. Since we have all banks on
  136. * the same array, we use this offset
  137. * to mark each bank's start */
  138. offset = ah->ah_offset[bank];
  139. /* Boundary check */
  140. if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
  141. ATH5K_PRINTF("invalid values at offset %u\n", offset);
  142. return 0;
  143. }
  144. entry = ((first_bit - 1) / 8) + offset;
  145. position = (first_bit - 1) % 8;
  146. if (set)
  147. data = ath5k_hw_bitswap(val, num_bits);
  148. for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
  149. position = 0, entry++) {
  150. last_bit = (position + bits_left > 8) ? 8 :
  151. position + bits_left;
  152. mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
  153. (col * 8);
  154. if (set) {
  155. rfb[entry] &= ~mask;
  156. rfb[entry] |= ((data << position) << (col * 8)) & mask;
  157. data >>= (8 - position);
  158. } else {
  159. data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
  160. << bits_shifted;
  161. bits_shifted += last_bit - position;
  162. }
  163. bits_left -= 8 - position;
  164. }
  165. data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
  166. return data;
  167. }
  168. /**
  169. * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
  170. *
  171. * @ah: the &struct ath5k_hw
  172. * @channel: the currently set channel upon reset
  173. *
  174. * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
  175. * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
  176. *
  177. * Since delta slope is floating point we split it on its exponent and
  178. * mantissa and provide these values on hw.
  179. *
  180. * For more infos i think this patent is related
  181. * http://www.freepatentsonline.com/7184495.html
  182. */
  183. static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
  184. struct ieee80211_channel *channel)
  185. {
  186. /* Get exponent and mantissa and set it */
  187. u32 coef_scaled, coef_exp, coef_man,
  188. ds_coef_exp, ds_coef_man, clock;
  189. BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
  190. !(channel->hw_value & CHANNEL_OFDM));
  191. /* Get coefficient
  192. * ALGO: coef = (5 * clock / carrier_freq) / 2
  193. * we scale coef by shifting clock value by 24 for
  194. * better precision since we use integers */
  195. switch (ah->ah_bwmode) {
  196. case AR5K_BWMODE_40MHZ:
  197. clock = 40 * 2;
  198. break;
  199. case AR5K_BWMODE_10MHZ:
  200. clock = 40 / 2;
  201. break;
  202. case AR5K_BWMODE_5MHZ:
  203. clock = 40 / 4;
  204. break;
  205. default:
  206. clock = 40;
  207. break;
  208. }
  209. coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
  210. /* Get exponent
  211. * ALGO: coef_exp = 14 - highest set bit position */
  212. coef_exp = ilog2(coef_scaled);
  213. /* Doesn't make sense if it's zero*/
  214. if (!coef_scaled || !coef_exp)
  215. return -EINVAL;
  216. /* Note: we've shifted coef_scaled by 24 */
  217. coef_exp = 14 - (coef_exp - 24);
  218. /* Get mantissa (significant digits)
  219. * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
  220. coef_man = coef_scaled +
  221. (1 << (24 - coef_exp - 1));
  222. /* Calculate delta slope coefficient exponent
  223. * and mantissa (remove scaling) and set them on hw */
  224. ds_coef_man = coef_man >> (24 - coef_exp);
  225. ds_coef_exp = coef_exp - 16;
  226. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
  227. AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
  228. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
  229. AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
  230. return 0;
  231. }
  232. int ath5k_hw_phy_disable(struct ath5k_hw *ah)
  233. {
  234. /*Just a try M.F.*/
  235. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
  236. return 0;
  237. }
  238. /**********************\
  239. * RF Gain optimization *
  240. \**********************/
  241. /*
  242. * This code is used to optimize RF gain on different environments
  243. * (temperature mostly) based on feedback from a power detector.
  244. *
  245. * It's only used on RF5111 and RF5112, later RF chips seem to have
  246. * auto adjustment on hw -notice they have a much smaller BANK 7 and
  247. * no gain optimization ladder-.
  248. *
  249. * For more infos check out this patent doc
  250. * http://www.freepatentsonline.com/7400691.html
  251. *
  252. * This paper describes power drops as seen on the receiver due to
  253. * probe packets
  254. * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
  255. * %20of%20Power%20Control.pdf
  256. *
  257. * And this is the MadWiFi bug entry related to the above
  258. * http://madwifi-project.org/ticket/1659
  259. * with various measurements and diagrams
  260. *
  261. * TODO: Deal with power drops due to probes by setting an apropriate
  262. * tx power on the probe packets ! Make this part of the calibration process.
  263. */
  264. /* Initialize ah_gain durring attach */
  265. int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
  266. {
  267. /* Initialize the gain optimization values */
  268. switch (ah->ah_radio) {
  269. case AR5K_RF5111:
  270. ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
  271. ah->ah_gain.g_low = 20;
  272. ah->ah_gain.g_high = 35;
  273. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  274. break;
  275. case AR5K_RF5112:
  276. ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
  277. ah->ah_gain.g_low = 20;
  278. ah->ah_gain.g_high = 85;
  279. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  280. break;
  281. default:
  282. return -EINVAL;
  283. }
  284. return 0;
  285. }
  286. /* Schedule a gain probe check on the next transmited packet.
  287. * That means our next packet is going to be sent with lower
  288. * tx power and a Peak to Average Power Detector (PAPD) will try
  289. * to measure the gain.
  290. *
  291. * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
  292. * just after we enable the probe so that we don't mess with
  293. * standard traffic ? Maybe it's time to use sw interrupts and
  294. * a probe tasklet !!!
  295. */
  296. static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
  297. {
  298. /* Skip if gain calibration is inactive or
  299. * we already handle a probe request */
  300. if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
  301. return;
  302. /* Send the packet with 2dB below max power as
  303. * patent doc suggest */
  304. ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
  305. AR5K_PHY_PAPD_PROBE_TXPOWER) |
  306. AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
  307. ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
  308. }
  309. /* Calculate gain_F measurement correction
  310. * based on the current step for RF5112 rev. 2 */
  311. static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
  312. {
  313. u32 mix, step;
  314. u32 *rf;
  315. const struct ath5k_gain_opt *go;
  316. const struct ath5k_gain_opt_step *g_step;
  317. const struct ath5k_rf_reg *rf_regs;
  318. /* Only RF5112 Rev. 2 supports it */
  319. if ((ah->ah_radio != AR5K_RF5112) ||
  320. (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
  321. return 0;
  322. go = &rfgain_opt_5112;
  323. rf_regs = rf_regs_5112a;
  324. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
  325. g_step = &go->go_step[ah->ah_gain.g_step_idx];
  326. if (ah->ah_rf_banks == NULL)
  327. return 0;
  328. rf = ah->ah_rf_banks;
  329. ah->ah_gain.g_f_corr = 0;
  330. /* No VGA (Variable Gain Amplifier) override, skip */
  331. if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
  332. return 0;
  333. /* Mix gain stepping */
  334. step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
  335. /* Mix gain override */
  336. mix = g_step->gos_param[0];
  337. switch (mix) {
  338. case 3:
  339. ah->ah_gain.g_f_corr = step * 2;
  340. break;
  341. case 2:
  342. ah->ah_gain.g_f_corr = (step - 5) * 2;
  343. break;
  344. case 1:
  345. ah->ah_gain.g_f_corr = step;
  346. break;
  347. default:
  348. ah->ah_gain.g_f_corr = 0;
  349. break;
  350. }
  351. return ah->ah_gain.g_f_corr;
  352. }
  353. /* Check if current gain_F measurement is in the range of our
  354. * power detector windows. If we get a measurement outside range
  355. * we know it's not accurate (detectors can't measure anything outside
  356. * their detection window) so we must ignore it */
  357. static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
  358. {
  359. const struct ath5k_rf_reg *rf_regs;
  360. u32 step, mix_ovr, level[4];
  361. u32 *rf;
  362. if (ah->ah_rf_banks == NULL)
  363. return false;
  364. rf = ah->ah_rf_banks;
  365. if (ah->ah_radio == AR5K_RF5111) {
  366. rf_regs = rf_regs_5111;
  367. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
  368. step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
  369. false);
  370. level[0] = 0;
  371. level[1] = (step == 63) ? 50 : step + 4;
  372. level[2] = (step != 63) ? 64 : level[0];
  373. level[3] = level[2] + 50 ;
  374. ah->ah_gain.g_high = level[3] -
  375. (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
  376. ah->ah_gain.g_low = level[0] +
  377. (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
  378. } else {
  379. rf_regs = rf_regs_5112;
  380. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
  381. mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
  382. false);
  383. level[0] = level[2] = 0;
  384. if (mix_ovr == 1) {
  385. level[1] = level[3] = 83;
  386. } else {
  387. level[1] = level[3] = 107;
  388. ah->ah_gain.g_high = 55;
  389. }
  390. }
  391. return (ah->ah_gain.g_current >= level[0] &&
  392. ah->ah_gain.g_current <= level[1]) ||
  393. (ah->ah_gain.g_current >= level[2] &&
  394. ah->ah_gain.g_current <= level[3]);
  395. }
  396. /* Perform gain_F adjustment by choosing the right set
  397. * of parameters from RF gain optimization ladder */
  398. static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
  399. {
  400. const struct ath5k_gain_opt *go;
  401. const struct ath5k_gain_opt_step *g_step;
  402. int ret = 0;
  403. switch (ah->ah_radio) {
  404. case AR5K_RF5111:
  405. go = &rfgain_opt_5111;
  406. break;
  407. case AR5K_RF5112:
  408. go = &rfgain_opt_5112;
  409. break;
  410. default:
  411. return 0;
  412. }
  413. g_step = &go->go_step[ah->ah_gain.g_step_idx];
  414. if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
  415. /* Reached maximum */
  416. if (ah->ah_gain.g_step_idx == 0)
  417. return -1;
  418. for (ah->ah_gain.g_target = ah->ah_gain.g_current;
  419. ah->ah_gain.g_target >= ah->ah_gain.g_high &&
  420. ah->ah_gain.g_step_idx > 0;
  421. g_step = &go->go_step[ah->ah_gain.g_step_idx])
  422. ah->ah_gain.g_target -= 2 *
  423. (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
  424. g_step->gos_gain);
  425. ret = 1;
  426. goto done;
  427. }
  428. if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
  429. /* Reached minimum */
  430. if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
  431. return -2;
  432. for (ah->ah_gain.g_target = ah->ah_gain.g_current;
  433. ah->ah_gain.g_target <= ah->ah_gain.g_low &&
  434. ah->ah_gain.g_step_idx < go->go_steps_count-1;
  435. g_step = &go->go_step[ah->ah_gain.g_step_idx])
  436. ah->ah_gain.g_target -= 2 *
  437. (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
  438. g_step->gos_gain);
  439. ret = 2;
  440. goto done;
  441. }
  442. done:
  443. ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
  444. "ret %d, gain step %u, current gain %u, target gain %u\n",
  445. ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
  446. ah->ah_gain.g_target);
  447. return ret;
  448. }
  449. /* Main callback for thermal RF gain calibration engine
  450. * Check for a new gain reading and schedule an adjustment
  451. * if needed.
  452. *
  453. * TODO: Use sw interrupt to schedule reset if gain_F needs
  454. * adjustment */
  455. enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
  456. {
  457. u32 data, type;
  458. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  459. if (ah->ah_rf_banks == NULL ||
  460. ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
  461. return AR5K_RFGAIN_INACTIVE;
  462. /* No check requested, either engine is inactive
  463. * or an adjustment is already requested */
  464. if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
  465. goto done;
  466. /* Read the PAPD (Peak to Average Power Detector)
  467. * register */
  468. data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
  469. /* No probe is scheduled, read gain_F measurement */
  470. if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
  471. ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
  472. type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
  473. /* If tx packet is CCK correct the gain_F measurement
  474. * by cck ofdm gain delta */
  475. if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
  476. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
  477. ah->ah_gain.g_current +=
  478. ee->ee_cck_ofdm_gain_delta;
  479. else
  480. ah->ah_gain.g_current +=
  481. AR5K_GAIN_CCK_PROBE_CORR;
  482. }
  483. /* Further correct gain_F measurement for
  484. * RF5112A radios */
  485. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
  486. ath5k_hw_rf_gainf_corr(ah);
  487. ah->ah_gain.g_current =
  488. ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
  489. (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
  490. 0;
  491. }
  492. /* Check if measurement is ok and if we need
  493. * to adjust gain, schedule a gain adjustment,
  494. * else switch back to the acive state */
  495. if (ath5k_hw_rf_check_gainf_readback(ah) &&
  496. AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
  497. ath5k_hw_rf_gainf_adjust(ah)) {
  498. ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
  499. } else {
  500. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  501. }
  502. }
  503. done:
  504. return ah->ah_gain.g_state;
  505. }
  506. /* Write initial RF gain table to set the RF sensitivity
  507. * this one works on all RF chips and has nothing to do
  508. * with gain_F calibration */
  509. static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
  510. {
  511. const struct ath5k_ini_rfgain *ath5k_rfg;
  512. unsigned int i, size, index;
  513. switch (ah->ah_radio) {
  514. case AR5K_RF5111:
  515. ath5k_rfg = rfgain_5111;
  516. size = ARRAY_SIZE(rfgain_5111);
  517. break;
  518. case AR5K_RF5112:
  519. ath5k_rfg = rfgain_5112;
  520. size = ARRAY_SIZE(rfgain_5112);
  521. break;
  522. case AR5K_RF2413:
  523. ath5k_rfg = rfgain_2413;
  524. size = ARRAY_SIZE(rfgain_2413);
  525. break;
  526. case AR5K_RF2316:
  527. ath5k_rfg = rfgain_2316;
  528. size = ARRAY_SIZE(rfgain_2316);
  529. break;
  530. case AR5K_RF5413:
  531. ath5k_rfg = rfgain_5413;
  532. size = ARRAY_SIZE(rfgain_5413);
  533. break;
  534. case AR5K_RF2317:
  535. case AR5K_RF2425:
  536. ath5k_rfg = rfgain_2425;
  537. size = ARRAY_SIZE(rfgain_2425);
  538. break;
  539. default:
  540. return -EINVAL;
  541. }
  542. index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0;
  543. for (i = 0; i < size; i++) {
  544. AR5K_REG_WAIT(i);
  545. ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index],
  546. (u32)ath5k_rfg[i].rfg_register);
  547. }
  548. return 0;
  549. }
  550. /********************\
  551. * RF Registers setup *
  552. \********************/
  553. /*
  554. * Setup RF registers by writing RF buffer on hw
  555. */
  556. static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
  557. struct ieee80211_channel *channel, unsigned int mode)
  558. {
  559. const struct ath5k_rf_reg *rf_regs;
  560. const struct ath5k_ini_rfbuffer *ini_rfb;
  561. const struct ath5k_gain_opt *go = NULL;
  562. const struct ath5k_gain_opt_step *g_step;
  563. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  564. u8 ee_mode = 0;
  565. u32 *rfb;
  566. int i, obdb = -1, bank = -1;
  567. switch (ah->ah_radio) {
  568. case AR5K_RF5111:
  569. rf_regs = rf_regs_5111;
  570. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
  571. ini_rfb = rfb_5111;
  572. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
  573. go = &rfgain_opt_5111;
  574. break;
  575. case AR5K_RF5112:
  576. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
  577. rf_regs = rf_regs_5112a;
  578. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
  579. ini_rfb = rfb_5112a;
  580. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
  581. } else {
  582. rf_regs = rf_regs_5112;
  583. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
  584. ini_rfb = rfb_5112;
  585. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
  586. }
  587. go = &rfgain_opt_5112;
  588. break;
  589. case AR5K_RF2413:
  590. rf_regs = rf_regs_2413;
  591. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
  592. ini_rfb = rfb_2413;
  593. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
  594. break;
  595. case AR5K_RF2316:
  596. rf_regs = rf_regs_2316;
  597. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
  598. ini_rfb = rfb_2316;
  599. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
  600. break;
  601. case AR5K_RF5413:
  602. rf_regs = rf_regs_5413;
  603. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
  604. ini_rfb = rfb_5413;
  605. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
  606. break;
  607. case AR5K_RF2317:
  608. rf_regs = rf_regs_2425;
  609. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
  610. ini_rfb = rfb_2317;
  611. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
  612. break;
  613. case AR5K_RF2425:
  614. rf_regs = rf_regs_2425;
  615. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
  616. if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
  617. ini_rfb = rfb_2425;
  618. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
  619. } else {
  620. ini_rfb = rfb_2417;
  621. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
  622. }
  623. break;
  624. default:
  625. return -EINVAL;
  626. }
  627. /* If it's the first time we set RF buffer, allocate
  628. * ah->ah_rf_banks based on ah->ah_rf_banks_size
  629. * we set above */
  630. if (ah->ah_rf_banks == NULL) {
  631. ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
  632. GFP_KERNEL);
  633. if (ah->ah_rf_banks == NULL) {
  634. ATH5K_ERR(ah->ah_sc, "out of memory\n");
  635. return -ENOMEM;
  636. }
  637. }
  638. /* Copy values to modify them */
  639. rfb = ah->ah_rf_banks;
  640. for (i = 0; i < ah->ah_rf_banks_size; i++) {
  641. if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
  642. ATH5K_ERR(ah->ah_sc, "invalid bank\n");
  643. return -EINVAL;
  644. }
  645. /* Bank changed, write down the offset */
  646. if (bank != ini_rfb[i].rfb_bank) {
  647. bank = ini_rfb[i].rfb_bank;
  648. ah->ah_offset[bank] = i;
  649. }
  650. rfb[i] = ini_rfb[i].rfb_mode_data[mode];
  651. }
  652. /* Set Output and Driver bias current (OB/DB) */
  653. if (channel->hw_value & CHANNEL_2GHZ) {
  654. if (channel->hw_value & CHANNEL_CCK)
  655. ee_mode = AR5K_EEPROM_MODE_11B;
  656. else
  657. ee_mode = AR5K_EEPROM_MODE_11G;
  658. /* For RF511X/RF211X combination we
  659. * use b_OB and b_DB parameters stored
  660. * in eeprom on ee->ee_ob[ee_mode][0]
  661. *
  662. * For all other chips we use OB/DB for 2Ghz
  663. * stored in the b/g modal section just like
  664. * 802.11a on ee->ee_ob[ee_mode][1] */
  665. if ((ah->ah_radio == AR5K_RF5111) ||
  666. (ah->ah_radio == AR5K_RF5112))
  667. obdb = 0;
  668. else
  669. obdb = 1;
  670. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
  671. AR5K_RF_OB_2GHZ, true);
  672. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
  673. AR5K_RF_DB_2GHZ, true);
  674. /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
  675. } else if ((channel->hw_value & CHANNEL_5GHZ) ||
  676. (ah->ah_radio == AR5K_RF5111)) {
  677. /* For 11a, Turbo and XR we need to choose
  678. * OB/DB based on frequency range */
  679. ee_mode = AR5K_EEPROM_MODE_11A;
  680. obdb = channel->center_freq >= 5725 ? 3 :
  681. (channel->center_freq >= 5500 ? 2 :
  682. (channel->center_freq >= 5260 ? 1 :
  683. (channel->center_freq > 4000 ? 0 : -1)));
  684. if (obdb < 0)
  685. return -EINVAL;
  686. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
  687. AR5K_RF_OB_5GHZ, true);
  688. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
  689. AR5K_RF_DB_5GHZ, true);
  690. }
  691. g_step = &go->go_step[ah->ah_gain.g_step_idx];
  692. /* Set turbo mode (N/A on RF5413) */
  693. if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
  694. (ah->ah_radio != AR5K_RF5413))
  695. ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
  696. /* Bank Modifications (chip-specific) */
  697. if (ah->ah_radio == AR5K_RF5111) {
  698. /* Set gain_F settings according to current step */
  699. if (channel->hw_value & CHANNEL_OFDM) {
  700. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
  701. AR5K_PHY_FRAME_CTL_TX_CLIP,
  702. g_step->gos_param[0]);
  703. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
  704. AR5K_RF_PWD_90, true);
  705. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
  706. AR5K_RF_PWD_84, true);
  707. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
  708. AR5K_RF_RFGAIN_SEL, true);
  709. /* We programmed gain_F parameters, switch back
  710. * to active state */
  711. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  712. }
  713. /* Bank 6/7 setup */
  714. ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
  715. AR5K_RF_PWD_XPD, true);
  716. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
  717. AR5K_RF_XPD_GAIN, true);
  718. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
  719. AR5K_RF_GAIN_I, true);
  720. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
  721. AR5K_RF_PLO_SEL, true);
  722. /* Tweak power detectors for half/quarter rate support */
  723. if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
  724. ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
  725. u8 wait_i;
  726. ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
  727. AR5K_RF_WAIT_S, true);
  728. wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
  729. 0x1f : 0x10;
  730. ath5k_hw_rfb_op(ah, rf_regs, wait_i,
  731. AR5K_RF_WAIT_I, true);
  732. ath5k_hw_rfb_op(ah, rf_regs, 3,
  733. AR5K_RF_MAX_TIME, true);
  734. }
  735. }
  736. if (ah->ah_radio == AR5K_RF5112) {
  737. /* Set gain_F settings according to current step */
  738. if (channel->hw_value & CHANNEL_OFDM) {
  739. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
  740. AR5K_RF_MIXGAIN_OVR, true);
  741. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
  742. AR5K_RF_PWD_138, true);
  743. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
  744. AR5K_RF_PWD_137, true);
  745. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
  746. AR5K_RF_PWD_136, true);
  747. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
  748. AR5K_RF_PWD_132, true);
  749. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
  750. AR5K_RF_PWD_131, true);
  751. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
  752. AR5K_RF_PWD_130, true);
  753. /* We programmed gain_F parameters, switch back
  754. * to active state */
  755. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  756. }
  757. /* Bank 6/7 setup */
  758. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
  759. AR5K_RF_XPD_SEL, true);
  760. if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
  761. /* Rev. 1 supports only one xpd */
  762. ath5k_hw_rfb_op(ah, rf_regs,
  763. ee->ee_x_gain[ee_mode],
  764. AR5K_RF_XPD_GAIN, true);
  765. } else {
  766. u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
  767. if (ee->ee_pd_gains[ee_mode] > 1) {
  768. ath5k_hw_rfb_op(ah, rf_regs,
  769. pdg_curve_to_idx[0],
  770. AR5K_RF_PD_GAIN_LO, true);
  771. ath5k_hw_rfb_op(ah, rf_regs,
  772. pdg_curve_to_idx[1],
  773. AR5K_RF_PD_GAIN_HI, true);
  774. } else {
  775. ath5k_hw_rfb_op(ah, rf_regs,
  776. pdg_curve_to_idx[0],
  777. AR5K_RF_PD_GAIN_LO, true);
  778. ath5k_hw_rfb_op(ah, rf_regs,
  779. pdg_curve_to_idx[0],
  780. AR5K_RF_PD_GAIN_HI, true);
  781. }
  782. /* Lower synth voltage on Rev 2 */
  783. ath5k_hw_rfb_op(ah, rf_regs, 2,
  784. AR5K_RF_HIGH_VC_CP, true);
  785. ath5k_hw_rfb_op(ah, rf_regs, 2,
  786. AR5K_RF_MID_VC_CP, true);
  787. ath5k_hw_rfb_op(ah, rf_regs, 2,
  788. AR5K_RF_LOW_VC_CP, true);
  789. ath5k_hw_rfb_op(ah, rf_regs, 2,
  790. AR5K_RF_PUSH_UP, true);
  791. /* Decrease power consumption on 5213+ BaseBand */
  792. if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
  793. ath5k_hw_rfb_op(ah, rf_regs, 1,
  794. AR5K_RF_PAD2GND, true);
  795. ath5k_hw_rfb_op(ah, rf_regs, 1,
  796. AR5K_RF_XB2_LVL, true);
  797. ath5k_hw_rfb_op(ah, rf_regs, 1,
  798. AR5K_RF_XB5_LVL, true);
  799. ath5k_hw_rfb_op(ah, rf_regs, 1,
  800. AR5K_RF_PWD_167, true);
  801. ath5k_hw_rfb_op(ah, rf_regs, 1,
  802. AR5K_RF_PWD_166, true);
  803. }
  804. }
  805. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
  806. AR5K_RF_GAIN_I, true);
  807. /* Tweak power detector for half/quarter rates */
  808. if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
  809. ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
  810. u8 pd_delay;
  811. pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
  812. 0xf : 0x8;
  813. ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
  814. AR5K_RF_PD_PERIOD_A, true);
  815. ath5k_hw_rfb_op(ah, rf_regs, 0xf,
  816. AR5K_RF_PD_DELAY_A, true);
  817. }
  818. }
  819. if (ah->ah_radio == AR5K_RF5413 &&
  820. channel->hw_value & CHANNEL_2GHZ) {
  821. ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
  822. true);
  823. /* Set optimum value for early revisions (on pci-e chips) */
  824. if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
  825. ah->ah_mac_srev < AR5K_SREV_AR5413)
  826. ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
  827. AR5K_RF_PWD_ICLOBUF_2G, true);
  828. }
  829. /* Write RF banks on hw */
  830. for (i = 0; i < ah->ah_rf_banks_size; i++) {
  831. AR5K_REG_WAIT(i);
  832. ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
  833. }
  834. return 0;
  835. }
  836. /**************************\
  837. PHY/RF channel functions
  838. \**************************/
  839. /*
  840. * Convertion needed for RF5110
  841. */
  842. static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
  843. {
  844. u32 athchan;
  845. /*
  846. * Convert IEEE channel/MHz to an internal channel value used
  847. * by the AR5210 chipset. This has not been verified with
  848. * newer chipsets like the AR5212A who have a completely
  849. * different RF/PHY part.
  850. */
  851. athchan = (ath5k_hw_bitswap(
  852. (ieee80211_frequency_to_channel(
  853. channel->center_freq) - 24) / 2, 5)
  854. << 1) | (1 << 6) | 0x1;
  855. return athchan;
  856. }
  857. /*
  858. * Set channel on RF5110
  859. */
  860. static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
  861. struct ieee80211_channel *channel)
  862. {
  863. u32 data;
  864. /*
  865. * Set the channel and wait
  866. */
  867. data = ath5k_hw_rf5110_chan2athchan(channel);
  868. ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
  869. ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
  870. mdelay(1);
  871. return 0;
  872. }
  873. /*
  874. * Convertion needed for 5111
  875. */
  876. static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
  877. struct ath5k_athchan_2ghz *athchan)
  878. {
  879. int channel;
  880. /* Cast this value to catch negative channel numbers (>= -19) */
  881. channel = (int)ieee;
  882. /*
  883. * Map 2GHz IEEE channel to 5GHz Atheros channel
  884. */
  885. if (channel <= 13) {
  886. athchan->a2_athchan = 115 + channel;
  887. athchan->a2_flags = 0x46;
  888. } else if (channel == 14) {
  889. athchan->a2_athchan = 124;
  890. athchan->a2_flags = 0x44;
  891. } else if (channel >= 15 && channel <= 26) {
  892. athchan->a2_athchan = ((channel - 14) * 4) + 132;
  893. athchan->a2_flags = 0x46;
  894. } else
  895. return -EINVAL;
  896. return 0;
  897. }
  898. /*
  899. * Set channel on 5111
  900. */
  901. static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
  902. struct ieee80211_channel *channel)
  903. {
  904. struct ath5k_athchan_2ghz ath5k_channel_2ghz;
  905. unsigned int ath5k_channel =
  906. ieee80211_frequency_to_channel(channel->center_freq);
  907. u32 data0, data1, clock;
  908. int ret;
  909. /*
  910. * Set the channel on the RF5111 radio
  911. */
  912. data0 = data1 = 0;
  913. if (channel->hw_value & CHANNEL_2GHZ) {
  914. /* Map 2GHz channel to 5GHz Atheros channel ID */
  915. ret = ath5k_hw_rf5111_chan2athchan(
  916. ieee80211_frequency_to_channel(channel->center_freq),
  917. &ath5k_channel_2ghz);
  918. if (ret)
  919. return ret;
  920. ath5k_channel = ath5k_channel_2ghz.a2_athchan;
  921. data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
  922. << 5) | (1 << 4);
  923. }
  924. if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
  925. clock = 1;
  926. data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
  927. (clock << 1) | (1 << 10) | 1;
  928. } else {
  929. clock = 0;
  930. data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
  931. << 2) | (clock << 1) | (1 << 10) | 1;
  932. }
  933. ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
  934. AR5K_RF_BUFFER);
  935. ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
  936. AR5K_RF_BUFFER_CONTROL_3);
  937. return 0;
  938. }
  939. /*
  940. * Set channel on 5112 and newer
  941. */
  942. static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
  943. struct ieee80211_channel *channel)
  944. {
  945. u32 data, data0, data1, data2;
  946. u16 c;
  947. data = data0 = data1 = data2 = 0;
  948. c = channel->center_freq;
  949. if (c < 4800) {
  950. if (!((c - 2224) % 5)) {
  951. data0 = ((2 * (c - 704)) - 3040) / 10;
  952. data1 = 1;
  953. } else if (!((c - 2192) % 5)) {
  954. data0 = ((2 * (c - 672)) - 3040) / 10;
  955. data1 = 0;
  956. } else
  957. return -EINVAL;
  958. data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
  959. } else if ((c % 5) != 2 || c > 5435) {
  960. if (!(c % 20) && c >= 5120) {
  961. data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
  962. data2 = ath5k_hw_bitswap(3, 2);
  963. } else if (!(c % 10)) {
  964. data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
  965. data2 = ath5k_hw_bitswap(2, 2);
  966. } else if (!(c % 5)) {
  967. data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
  968. data2 = ath5k_hw_bitswap(1, 2);
  969. } else
  970. return -EINVAL;
  971. } else {
  972. data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
  973. data2 = ath5k_hw_bitswap(0, 2);
  974. }
  975. data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
  976. ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
  977. ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
  978. return 0;
  979. }
  980. /*
  981. * Set the channel on the RF2425
  982. */
  983. static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
  984. struct ieee80211_channel *channel)
  985. {
  986. u32 data, data0, data2;
  987. u16 c;
  988. data = data0 = data2 = 0;
  989. c = channel->center_freq;
  990. if (c < 4800) {
  991. data0 = ath5k_hw_bitswap((c - 2272), 8);
  992. data2 = 0;
  993. /* ? 5GHz ? */
  994. } else if ((c % 5) != 2 || c > 5435) {
  995. if (!(c % 20) && c < 5120)
  996. data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
  997. else if (!(c % 10))
  998. data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
  999. else if (!(c % 5))
  1000. data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
  1001. else
  1002. return -EINVAL;
  1003. data2 = ath5k_hw_bitswap(1, 2);
  1004. } else {
  1005. data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
  1006. data2 = ath5k_hw_bitswap(0, 2);
  1007. }
  1008. data = (data0 << 4) | data2 << 2 | 0x1001;
  1009. ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
  1010. ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
  1011. return 0;
  1012. }
  1013. /*
  1014. * Set a channel on the radio chip
  1015. */
  1016. static int ath5k_hw_channel(struct ath5k_hw *ah,
  1017. struct ieee80211_channel *channel)
  1018. {
  1019. int ret;
  1020. /*
  1021. * Check bounds supported by the PHY (we don't care about regultory
  1022. * restrictions at this point). Note: hw_value already has the band
  1023. * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
  1024. * of the band by that */
  1025. if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
  1026. ATH5K_ERR(ah->ah_sc,
  1027. "channel frequency (%u MHz) out of supported "
  1028. "band range\n",
  1029. channel->center_freq);
  1030. return -EINVAL;
  1031. }
  1032. /*
  1033. * Set the channel and wait
  1034. */
  1035. switch (ah->ah_radio) {
  1036. case AR5K_RF5110:
  1037. ret = ath5k_hw_rf5110_channel(ah, channel);
  1038. break;
  1039. case AR5K_RF5111:
  1040. ret = ath5k_hw_rf5111_channel(ah, channel);
  1041. break;
  1042. case AR5K_RF2425:
  1043. ret = ath5k_hw_rf2425_channel(ah, channel);
  1044. break;
  1045. default:
  1046. ret = ath5k_hw_rf5112_channel(ah, channel);
  1047. break;
  1048. }
  1049. if (ret)
  1050. return ret;
  1051. /* Set JAPAN setting for channel 14 */
  1052. if (channel->center_freq == 2484) {
  1053. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
  1054. AR5K_PHY_CCKTXCTL_JAPAN);
  1055. } else {
  1056. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
  1057. AR5K_PHY_CCKTXCTL_WORLD);
  1058. }
  1059. ah->ah_current_channel = channel;
  1060. return 0;
  1061. }
  1062. /*****************\
  1063. PHY calibration
  1064. \*****************/
  1065. static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
  1066. {
  1067. s32 val;
  1068. val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
  1069. return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
  1070. }
  1071. void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
  1072. {
  1073. int i;
  1074. ah->ah_nfcal_hist.index = 0;
  1075. for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
  1076. ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
  1077. }
  1078. static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
  1079. {
  1080. struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
  1081. hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
  1082. hist->nfval[hist->index] = noise_floor;
  1083. }
  1084. static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
  1085. {
  1086. s16 sort[ATH5K_NF_CAL_HIST_MAX];
  1087. s16 tmp;
  1088. int i, j;
  1089. memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
  1090. for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
  1091. for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
  1092. if (sort[j] > sort[j-1]) {
  1093. tmp = sort[j];
  1094. sort[j] = sort[j-1];
  1095. sort[j-1] = tmp;
  1096. }
  1097. }
  1098. }
  1099. for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
  1100. ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
  1101. "cal %d:%d\n", i, sort[i]);
  1102. }
  1103. return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
  1104. }
  1105. /*
  1106. * When we tell the hardware to perform a noise floor calibration
  1107. * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
  1108. * sample-and-hold the minimum noise level seen at the antennas.
  1109. * This value is then stored in a ring buffer of recently measured
  1110. * noise floor values so we have a moving window of the last few
  1111. * samples.
  1112. *
  1113. * The median of the values in the history is then loaded into the
  1114. * hardware for its own use for RSSI and CCA measurements.
  1115. */
  1116. void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
  1117. {
  1118. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1119. u32 val;
  1120. s16 nf, threshold;
  1121. u8 ee_mode;
  1122. /* keep last value if calibration hasn't completed */
  1123. if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
  1124. ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
  1125. "NF did not complete in calibration window\n");
  1126. return;
  1127. }
  1128. ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel);
  1129. /* completed NF calibration, test threshold */
  1130. nf = ath5k_hw_read_measured_noise_floor(ah);
  1131. threshold = ee->ee_noise_floor_thr[ee_mode];
  1132. if (nf > threshold) {
  1133. ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
  1134. "noise floor failure detected; "
  1135. "read %d, threshold %d\n",
  1136. nf, threshold);
  1137. nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
  1138. }
  1139. ath5k_hw_update_nfcal_hist(ah, nf);
  1140. nf = ath5k_hw_get_median_noise_floor(ah);
  1141. /* load noise floor (in .5 dBm) so the hardware will use it */
  1142. val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
  1143. val |= (nf * 2) & AR5K_PHY_NF_M;
  1144. ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
  1145. AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
  1146. ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
  1147. ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
  1148. 0, false);
  1149. /*
  1150. * Load a high max CCA Power value (-50 dBm in .5 dBm units)
  1151. * so that we're not capped by the median we just loaded.
  1152. * This will be used as the initial value for the next noise
  1153. * floor calibration.
  1154. */
  1155. val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
  1156. ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
  1157. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1158. AR5K_PHY_AGCCTL_NF_EN |
  1159. AR5K_PHY_AGCCTL_NF_NOUPDATE |
  1160. AR5K_PHY_AGCCTL_NF);
  1161. ah->ah_noise_floor = nf;
  1162. ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
  1163. "noise floor calibrated: %d\n", nf);
  1164. }
  1165. /*
  1166. * Perform a PHY calibration on RF5110
  1167. * -Fix BPSK/QAM Constellation (I/Q correction)
  1168. */
  1169. static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
  1170. struct ieee80211_channel *channel)
  1171. {
  1172. u32 phy_sig, phy_agc, phy_sat, beacon;
  1173. int ret;
  1174. /*
  1175. * Disable beacons and RX/TX queues, wait
  1176. */
  1177. AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
  1178. AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
  1179. beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
  1180. ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
  1181. mdelay(2);
  1182. /*
  1183. * Set the channel (with AGC turned off)
  1184. */
  1185. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1186. udelay(10);
  1187. ret = ath5k_hw_channel(ah, channel);
  1188. /*
  1189. * Activate PHY and wait
  1190. */
  1191. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
  1192. mdelay(1);
  1193. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1194. if (ret)
  1195. return ret;
  1196. /*
  1197. * Calibrate the radio chip
  1198. */
  1199. /* Remember normal state */
  1200. phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
  1201. phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
  1202. phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
  1203. /* Update radio registers */
  1204. ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
  1205. AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
  1206. ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
  1207. AR5K_PHY_AGCCOARSE_LO)) |
  1208. AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
  1209. AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
  1210. ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
  1211. AR5K_PHY_ADCSAT_THR)) |
  1212. AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
  1213. AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
  1214. udelay(20);
  1215. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1216. udelay(10);
  1217. ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
  1218. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1219. mdelay(1);
  1220. /*
  1221. * Enable calibration and wait until completion
  1222. */
  1223. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
  1224. ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
  1225. AR5K_PHY_AGCCTL_CAL, 0, false);
  1226. /* Reset to normal state */
  1227. ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
  1228. ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
  1229. ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
  1230. if (ret) {
  1231. ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
  1232. channel->center_freq);
  1233. return ret;
  1234. }
  1235. /*
  1236. * Re-enable RX/TX and beacons
  1237. */
  1238. AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
  1239. AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
  1240. ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
  1241. return 0;
  1242. }
  1243. /*
  1244. * Perform I/Q calibration on RF5111/5112 and newer chips
  1245. */
  1246. static int
  1247. ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
  1248. {
  1249. u32 i_pwr, q_pwr;
  1250. s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
  1251. int i;
  1252. if (!ah->ah_calibration ||
  1253. ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
  1254. return 0;
  1255. /* Calibration has finished, get the results and re-run */
  1256. /* work around empty results which can apparently happen on 5212 */
  1257. for (i = 0; i <= 10; i++) {
  1258. iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
  1259. i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
  1260. q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
  1261. ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
  1262. "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
  1263. if (i_pwr && q_pwr)
  1264. break;
  1265. }
  1266. i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
  1267. if (ah->ah_version == AR5K_AR5211)
  1268. q_coffd = q_pwr >> 6;
  1269. else
  1270. q_coffd = q_pwr >> 7;
  1271. /* protect against divide by 0 and loss of sign bits */
  1272. if (i_coffd == 0 || q_coffd < 2)
  1273. return 0;
  1274. i_coff = (-iq_corr) / i_coffd;
  1275. i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
  1276. if (ah->ah_version == AR5K_AR5211)
  1277. q_coff = (i_pwr / q_coffd) - 64;
  1278. else
  1279. q_coff = (i_pwr / q_coffd) - 128;
  1280. q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
  1281. ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
  1282. "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
  1283. i_coff, q_coff, i_coffd, q_coffd);
  1284. /* Commit new I/Q values (set enable bit last to match HAL sources) */
  1285. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
  1286. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
  1287. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
  1288. /* Re-enable calibration -if we don't we'll commit
  1289. * the same values again and again */
  1290. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
  1291. AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
  1292. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
  1293. return 0;
  1294. }
  1295. /*
  1296. * Perform a PHY calibration
  1297. */
  1298. int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
  1299. struct ieee80211_channel *channel)
  1300. {
  1301. int ret;
  1302. if (ah->ah_radio == AR5K_RF5110)
  1303. ret = ath5k_hw_rf5110_calibrate(ah, channel);
  1304. else {
  1305. ret = ath5k_hw_rf511x_iq_calibrate(ah);
  1306. ath5k_hw_request_rfgain_probe(ah);
  1307. }
  1308. return ret;
  1309. }
  1310. /***************************\
  1311. * Spur mitigation functions *
  1312. \***************************/
  1313. static void
  1314. ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
  1315. struct ieee80211_channel *channel)
  1316. {
  1317. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1318. u32 mag_mask[4] = {0, 0, 0, 0};
  1319. u32 pilot_mask[2] = {0, 0};
  1320. /* Note: fbin values are scaled up by 2 */
  1321. u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
  1322. s32 spur_delta_phase, spur_freq_sigma_delta;
  1323. s32 spur_offset, num_symbols_x16;
  1324. u8 num_symbol_offsets, i, freq_band;
  1325. /* Convert current frequency to fbin value (the same way channels
  1326. * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
  1327. * up by 2 so we can compare it later */
  1328. if (channel->hw_value & CHANNEL_2GHZ) {
  1329. chan_fbin = (channel->center_freq - 2300) * 10;
  1330. freq_band = AR5K_EEPROM_BAND_2GHZ;
  1331. } else {
  1332. chan_fbin = (channel->center_freq - 4900) * 10;
  1333. freq_band = AR5K_EEPROM_BAND_5GHZ;
  1334. }
  1335. /* Check if any spur_chan_fbin from EEPROM is
  1336. * within our current channel's spur detection range */
  1337. spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
  1338. spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
  1339. /* XXX: Half/Quarter channels ?*/
  1340. if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
  1341. spur_detection_window *= 2;
  1342. for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
  1343. spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
  1344. /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
  1345. * so it's zero if we got nothing from EEPROM */
  1346. if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
  1347. spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
  1348. break;
  1349. }
  1350. if ((chan_fbin - spur_detection_window <=
  1351. (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
  1352. (chan_fbin + spur_detection_window >=
  1353. (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
  1354. spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
  1355. break;
  1356. }
  1357. }
  1358. /* We need to enable spur filter for this channel */
  1359. if (spur_chan_fbin) {
  1360. spur_offset = spur_chan_fbin - chan_fbin;
  1361. /*
  1362. * Calculate deltas:
  1363. * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
  1364. * spur_delta_phase -> spur_offset / chip_freq << 11
  1365. * Note: Both values have 100Hz resolution
  1366. */
  1367. switch (ah->ah_bwmode) {
  1368. case AR5K_BWMODE_40MHZ:
  1369. /* Both sample_freq and chip_freq are 80MHz */
  1370. spur_delta_phase = (spur_offset << 16) / 25;
  1371. spur_freq_sigma_delta = (spur_delta_phase >> 10);
  1372. symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
  1373. break;
  1374. case AR5K_BWMODE_10MHZ:
  1375. /* Both sample_freq and chip_freq are 20MHz (?) */
  1376. spur_delta_phase = (spur_offset << 18) / 25;
  1377. spur_freq_sigma_delta = (spur_delta_phase >> 10);
  1378. symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
  1379. case AR5K_BWMODE_5MHZ:
  1380. /* Both sample_freq and chip_freq are 10MHz (?) */
  1381. spur_delta_phase = (spur_offset << 19) / 25;
  1382. spur_freq_sigma_delta = (spur_delta_phase >> 10);
  1383. symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
  1384. default:
  1385. if (channel->hw_value == CHANNEL_A) {
  1386. /* Both sample_freq and chip_freq are 40MHz */
  1387. spur_delta_phase = (spur_offset << 17) / 25;
  1388. spur_freq_sigma_delta =
  1389. (spur_delta_phase >> 10);
  1390. symbol_width =
  1391. AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
  1392. } else {
  1393. /* sample_freq -> 40MHz chip_freq -> 44MHz
  1394. * (for b compatibility) */
  1395. spur_delta_phase = (spur_offset << 17) / 25;
  1396. spur_freq_sigma_delta =
  1397. (spur_offset << 8) / 55;
  1398. symbol_width =
  1399. AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
  1400. }
  1401. break;
  1402. }
  1403. /* Calculate pilot and magnitude masks */
  1404. /* Scale up spur_offset by 1000 to switch to 100HZ resolution
  1405. * and divide by symbol_width to find how many symbols we have
  1406. * Note: number of symbols is scaled up by 16 */
  1407. num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
  1408. /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
  1409. if (!(num_symbols_x16 & 0xF))
  1410. /* _X_ */
  1411. num_symbol_offsets = 3;
  1412. else
  1413. /* _xx_ */
  1414. num_symbol_offsets = 4;
  1415. for (i = 0; i < num_symbol_offsets; i++) {
  1416. /* Calculate pilot mask */
  1417. s32 curr_sym_off =
  1418. (num_symbols_x16 / 16) + i + 25;
  1419. /* Pilot magnitude mask seems to be a way to
  1420. * declare the boundaries for our detection
  1421. * window or something, it's 2 for the middle
  1422. * value(s) where the symbol is expected to be
  1423. * and 1 on the boundary values */
  1424. u8 plt_mag_map =
  1425. (i == 0 || i == (num_symbol_offsets - 1))
  1426. ? 1 : 2;
  1427. if (curr_sym_off >= 0 && curr_sym_off <= 32) {
  1428. if (curr_sym_off <= 25)
  1429. pilot_mask[0] |= 1 << curr_sym_off;
  1430. else if (curr_sym_off >= 27)
  1431. pilot_mask[0] |= 1 << (curr_sym_off - 1);
  1432. } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
  1433. pilot_mask[1] |= 1 << (curr_sym_off - 33);
  1434. /* Calculate magnitude mask (for viterbi decoder) */
  1435. if (curr_sym_off >= -1 && curr_sym_off <= 14)
  1436. mag_mask[0] |=
  1437. plt_mag_map << (curr_sym_off + 1) * 2;
  1438. else if (curr_sym_off >= 15 && curr_sym_off <= 30)
  1439. mag_mask[1] |=
  1440. plt_mag_map << (curr_sym_off - 15) * 2;
  1441. else if (curr_sym_off >= 31 && curr_sym_off <= 46)
  1442. mag_mask[2] |=
  1443. plt_mag_map << (curr_sym_off - 31) * 2;
  1444. else if (curr_sym_off >= 47 && curr_sym_off <= 53)
  1445. mag_mask[3] |=
  1446. plt_mag_map << (curr_sym_off - 47) * 2;
  1447. }
  1448. /* Write settings on hw to enable spur filter */
  1449. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1450. AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
  1451. /* XXX: Self correlator also ? */
  1452. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
  1453. AR5K_PHY_IQ_PILOT_MASK_EN |
  1454. AR5K_PHY_IQ_CHAN_MASK_EN |
  1455. AR5K_PHY_IQ_SPUR_FILT_EN);
  1456. /* Set delta phase and freq sigma delta */
  1457. ath5k_hw_reg_write(ah,
  1458. AR5K_REG_SM(spur_delta_phase,
  1459. AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
  1460. AR5K_REG_SM(spur_freq_sigma_delta,
  1461. AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
  1462. AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
  1463. AR5K_PHY_TIMING_11);
  1464. /* Write pilot masks */
  1465. ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
  1466. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
  1467. AR5K_PHY_TIMING_8_PILOT_MASK_2,
  1468. pilot_mask[1]);
  1469. ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
  1470. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
  1471. AR5K_PHY_TIMING_10_PILOT_MASK_2,
  1472. pilot_mask[1]);
  1473. /* Write magnitude masks */
  1474. ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
  1475. ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
  1476. ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
  1477. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1478. AR5K_PHY_BIN_MASK_CTL_MASK_4,
  1479. mag_mask[3]);
  1480. ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
  1481. ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
  1482. ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
  1483. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
  1484. AR5K_PHY_BIN_MASK2_4_MASK_4,
  1485. mag_mask[3]);
  1486. } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
  1487. AR5K_PHY_IQ_SPUR_FILT_EN) {
  1488. /* Clean up spur mitigation settings and disable fliter */
  1489. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1490. AR5K_PHY_BIN_MASK_CTL_RATE, 0);
  1491. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
  1492. AR5K_PHY_IQ_PILOT_MASK_EN |
  1493. AR5K_PHY_IQ_CHAN_MASK_EN |
  1494. AR5K_PHY_IQ_SPUR_FILT_EN);
  1495. ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
  1496. /* Clear pilot masks */
  1497. ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
  1498. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
  1499. AR5K_PHY_TIMING_8_PILOT_MASK_2,
  1500. 0);
  1501. ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
  1502. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
  1503. AR5K_PHY_TIMING_10_PILOT_MASK_2,
  1504. 0);
  1505. /* Clear magnitude masks */
  1506. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
  1507. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
  1508. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
  1509. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1510. AR5K_PHY_BIN_MASK_CTL_MASK_4,
  1511. 0);
  1512. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
  1513. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
  1514. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
  1515. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
  1516. AR5K_PHY_BIN_MASK2_4_MASK_4,
  1517. 0);
  1518. }
  1519. }
  1520. /*****************\
  1521. * Antenna control *
  1522. \*****************/
  1523. static void /*TODO:Boundary check*/
  1524. ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
  1525. {
  1526. if (ah->ah_version != AR5K_AR5210)
  1527. ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
  1528. }
  1529. /*
  1530. * Enable/disable fast rx antenna diversity
  1531. */
  1532. static void
  1533. ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
  1534. {
  1535. switch (ee_mode) {
  1536. case AR5K_EEPROM_MODE_11G:
  1537. /* XXX: This is set to
  1538. * disabled on initvals !!! */
  1539. case AR5K_EEPROM_MODE_11A:
  1540. if (enable)
  1541. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1542. AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
  1543. else
  1544. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1545. AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
  1546. break;
  1547. case AR5K_EEPROM_MODE_11B:
  1548. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1549. AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
  1550. break;
  1551. default:
  1552. return;
  1553. }
  1554. if (enable) {
  1555. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
  1556. AR5K_PHY_RESTART_DIV_GC, 4);
  1557. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
  1558. AR5K_PHY_FAST_ANT_DIV_EN);
  1559. } else {
  1560. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
  1561. AR5K_PHY_RESTART_DIV_GC, 0);
  1562. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
  1563. AR5K_PHY_FAST_ANT_DIV_EN);
  1564. }
  1565. }
  1566. void
  1567. ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
  1568. {
  1569. u8 ant0, ant1;
  1570. /*
  1571. * In case a fixed antenna was set as default
  1572. * use the same switch table twice.
  1573. */
  1574. if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
  1575. ant0 = ant1 = AR5K_ANT_SWTABLE_A;
  1576. else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
  1577. ant0 = ant1 = AR5K_ANT_SWTABLE_B;
  1578. else {
  1579. ant0 = AR5K_ANT_SWTABLE_A;
  1580. ant1 = AR5K_ANT_SWTABLE_B;
  1581. }
  1582. /* Set antenna idle switch table */
  1583. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
  1584. AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
  1585. (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
  1586. AR5K_PHY_ANT_CTL_TXRX_EN));
  1587. /* Set antenna switch tables */
  1588. ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
  1589. AR5K_PHY_ANT_SWITCH_TABLE_0);
  1590. ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
  1591. AR5K_PHY_ANT_SWITCH_TABLE_1);
  1592. }
  1593. /*
  1594. * Set antenna operating mode
  1595. */
  1596. void
  1597. ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
  1598. {
  1599. struct ieee80211_channel *channel = ah->ah_current_channel;
  1600. bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
  1601. bool use_def_for_sg;
  1602. int ee_mode;
  1603. u8 def_ant, tx_ant;
  1604. u32 sta_id1 = 0;
  1605. /* if channel is not initialized yet we can't set the antennas
  1606. * so just store the mode. it will be set on the next reset */
  1607. if (channel == NULL) {
  1608. ah->ah_ant_mode = ant_mode;
  1609. return;
  1610. }
  1611. def_ant = ah->ah_def_ant;
  1612. ee_mode = ath5k_eeprom_mode_from_channel(channel);
  1613. if (ee_mode < 0) {
  1614. ATH5K_ERR(ah->ah_sc,
  1615. "invalid channel: %d\n", channel->center_freq);
  1616. return;
  1617. }
  1618. switch (ant_mode) {
  1619. case AR5K_ANTMODE_DEFAULT:
  1620. tx_ant = 0;
  1621. use_def_for_tx = false;
  1622. update_def_on_tx = false;
  1623. use_def_for_rts = false;
  1624. use_def_for_sg = false;
  1625. fast_div = true;
  1626. break;
  1627. case AR5K_ANTMODE_FIXED_A:
  1628. def_ant = 1;
  1629. tx_ant = 1;
  1630. use_def_for_tx = true;
  1631. update_def_on_tx = false;
  1632. use_def_for_rts = true;
  1633. use_def_for_sg = true;
  1634. fast_div = false;
  1635. break;
  1636. case AR5K_ANTMODE_FIXED_B:
  1637. def_ant = 2;
  1638. tx_ant = 2;
  1639. use_def_for_tx = true;
  1640. update_def_on_tx = false;
  1641. use_def_for_rts = true;
  1642. use_def_for_sg = true;
  1643. fast_div = false;
  1644. break;
  1645. case AR5K_ANTMODE_SINGLE_AP:
  1646. def_ant = 1; /* updated on tx */
  1647. tx_ant = 0;
  1648. use_def_for_tx = true;
  1649. update_def_on_tx = true;
  1650. use_def_for_rts = true;
  1651. use_def_for_sg = true;
  1652. fast_div = true;
  1653. break;
  1654. case AR5K_ANTMODE_SECTOR_AP:
  1655. tx_ant = 1; /* variable */
  1656. use_def_for_tx = false;
  1657. update_def_on_tx = false;
  1658. use_def_for_rts = true;
  1659. use_def_for_sg = false;
  1660. fast_div = false;
  1661. break;
  1662. case AR5K_ANTMODE_SECTOR_STA:
  1663. tx_ant = 1; /* variable */
  1664. use_def_for_tx = true;
  1665. update_def_on_tx = false;
  1666. use_def_for_rts = true;
  1667. use_def_for_sg = false;
  1668. fast_div = true;
  1669. break;
  1670. case AR5K_ANTMODE_DEBUG:
  1671. def_ant = 1;
  1672. tx_ant = 2;
  1673. use_def_for_tx = false;
  1674. update_def_on_tx = false;
  1675. use_def_for_rts = false;
  1676. use_def_for_sg = false;
  1677. fast_div = false;
  1678. break;
  1679. default:
  1680. return;
  1681. }
  1682. ah->ah_tx_ant = tx_ant;
  1683. ah->ah_ant_mode = ant_mode;
  1684. ah->ah_def_ant = def_ant;
  1685. sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
  1686. sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
  1687. sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
  1688. sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
  1689. AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
  1690. if (sta_id1)
  1691. AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
  1692. ath5k_hw_set_antenna_switch(ah, ee_mode);
  1693. /* Note: set diversity before default antenna
  1694. * because it won't work correctly */
  1695. ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
  1696. ath5k_hw_set_def_antenna(ah, def_ant);
  1697. }
  1698. /****************\
  1699. * TX power setup *
  1700. \****************/
  1701. /*
  1702. * Helper functions
  1703. */
  1704. /*
  1705. * Do linear interpolation between two given (x, y) points
  1706. */
  1707. static s16
  1708. ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
  1709. s16 y_left, s16 y_right)
  1710. {
  1711. s16 ratio, result;
  1712. /* Avoid divide by zero and skip interpolation
  1713. * if we have the same point */
  1714. if ((x_left == x_right) || (y_left == y_right))
  1715. return y_left;
  1716. /*
  1717. * Since we use ints and not fps, we need to scale up in
  1718. * order to get a sane ratio value (or else we 'll eg. get
  1719. * always 1 instead of 1.25, 1.75 etc). We scale up by 100
  1720. * to have some accuracy both for 0.5 and 0.25 steps.
  1721. */
  1722. ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
  1723. /* Now scale down to be in range */
  1724. result = y_left + (ratio * (target - x_left) / 100);
  1725. return result;
  1726. }
  1727. /*
  1728. * Find vertical boundary (min pwr) for the linear PCDAC curve.
  1729. *
  1730. * Since we have the top of the curve and we draw the line below
  1731. * until we reach 1 (1 pcdac step) we need to know which point
  1732. * (x value) that is so that we don't go below y axis and have negative
  1733. * pcdac values when creating the curve, or fill the table with zeroes.
  1734. */
  1735. static s16
  1736. ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
  1737. const s16 *pwrL, const s16 *pwrR)
  1738. {
  1739. s8 tmp;
  1740. s16 min_pwrL, min_pwrR;
  1741. s16 pwr_i;
  1742. /* Some vendors write the same pcdac value twice !!! */
  1743. if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
  1744. return max(pwrL[0], pwrR[0]);
  1745. if (pwrL[0] == pwrL[1])
  1746. min_pwrL = pwrL[0];
  1747. else {
  1748. pwr_i = pwrL[0];
  1749. do {
  1750. pwr_i--;
  1751. tmp = (s8) ath5k_get_interpolated_value(pwr_i,
  1752. pwrL[0], pwrL[1],
  1753. stepL[0], stepL[1]);
  1754. } while (tmp > 1);
  1755. min_pwrL = pwr_i;
  1756. }
  1757. if (pwrR[0] == pwrR[1])
  1758. min_pwrR = pwrR[0];
  1759. else {
  1760. pwr_i = pwrR[0];
  1761. do {
  1762. pwr_i--;
  1763. tmp = (s8) ath5k_get_interpolated_value(pwr_i,
  1764. pwrR[0], pwrR[1],
  1765. stepR[0], stepR[1]);
  1766. } while (tmp > 1);
  1767. min_pwrR = pwr_i;
  1768. }
  1769. /* Keep the right boundary so that it works for both curves */
  1770. return max(min_pwrL, min_pwrR);
  1771. }
  1772. /*
  1773. * Interpolate (pwr,vpd) points to create a Power to PDADC or a
  1774. * Power to PCDAC curve.
  1775. *
  1776. * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
  1777. * steps (offsets) on y axis. Power can go up to 31.5dB and max
  1778. * PCDAC/PDADC step for each curve is 64 but we can write more than
  1779. * one curves on hw so we can go up to 128 (which is the max step we
  1780. * can write on the final table).
  1781. *
  1782. * We write y values (PCDAC/PDADC steps) on hw.
  1783. */
  1784. static void
  1785. ath5k_create_power_curve(s16 pmin, s16 pmax,
  1786. const s16 *pwr, const u8 *vpd,
  1787. u8 num_points,
  1788. u8 *vpd_table, u8 type)
  1789. {
  1790. u8 idx[2] = { 0, 1 };
  1791. s16 pwr_i = 2*pmin;
  1792. int i;
  1793. if (num_points < 2)
  1794. return;
  1795. /* We want the whole line, so adjust boundaries
  1796. * to cover the entire power range. Note that
  1797. * power values are already 0.25dB so no need
  1798. * to multiply pwr_i by 2 */
  1799. if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
  1800. pwr_i = pmin;
  1801. pmin = 0;
  1802. pmax = 63;
  1803. }
  1804. /* Find surrounding turning points (TPs)
  1805. * and interpolate between them */
  1806. for (i = 0; (i <= (u16) (pmax - pmin)) &&
  1807. (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
  1808. /* We passed the right TP, move to the next set of TPs
  1809. * if we pass the last TP, extrapolate above using the last
  1810. * two TPs for ratio */
  1811. if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
  1812. idx[0]++;
  1813. idx[1]++;
  1814. }
  1815. vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
  1816. pwr[idx[0]], pwr[idx[1]],
  1817. vpd[idx[0]], vpd[idx[1]]);
  1818. /* Increase by 0.5dB
  1819. * (0.25 dB units) */
  1820. pwr_i += 2;
  1821. }
  1822. }
  1823. /*
  1824. * Get the surrounding per-channel power calibration piers
  1825. * for a given frequency so that we can interpolate between
  1826. * them and come up with an apropriate dataset for our current
  1827. * channel.
  1828. */
  1829. static void
  1830. ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
  1831. struct ieee80211_channel *channel,
  1832. struct ath5k_chan_pcal_info **pcinfo_l,
  1833. struct ath5k_chan_pcal_info **pcinfo_r)
  1834. {
  1835. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1836. struct ath5k_chan_pcal_info *pcinfo;
  1837. u8 idx_l, idx_r;
  1838. u8 mode, max, i;
  1839. u32 target = channel->center_freq;
  1840. idx_l = 0;
  1841. idx_r = 0;
  1842. if (!(channel->hw_value & CHANNEL_OFDM)) {
  1843. pcinfo = ee->ee_pwr_cal_b;
  1844. mode = AR5K_EEPROM_MODE_11B;
  1845. } else if (channel->hw_value & CHANNEL_2GHZ) {
  1846. pcinfo = ee->ee_pwr_cal_g;
  1847. mode = AR5K_EEPROM_MODE_11G;
  1848. } else {
  1849. pcinfo = ee->ee_pwr_cal_a;
  1850. mode = AR5K_EEPROM_MODE_11A;
  1851. }
  1852. max = ee->ee_n_piers[mode] - 1;
  1853. /* Frequency is below our calibrated
  1854. * range. Use the lowest power curve
  1855. * we have */
  1856. if (target < pcinfo[0].freq) {
  1857. idx_l = idx_r = 0;
  1858. goto done;
  1859. }
  1860. /* Frequency is above our calibrated
  1861. * range. Use the highest power curve
  1862. * we have */
  1863. if (target > pcinfo[max].freq) {
  1864. idx_l = idx_r = max;
  1865. goto done;
  1866. }
  1867. /* Frequency is inside our calibrated
  1868. * channel range. Pick the surrounding
  1869. * calibration piers so that we can
  1870. * interpolate */
  1871. for (i = 0; i <= max; i++) {
  1872. /* Frequency matches one of our calibration
  1873. * piers, no need to interpolate, just use
  1874. * that calibration pier */
  1875. if (pcinfo[i].freq == target) {
  1876. idx_l = idx_r = i;
  1877. goto done;
  1878. }
  1879. /* We found a calibration pier that's above
  1880. * frequency, use this pier and the previous
  1881. * one to interpolate */
  1882. if (target < pcinfo[i].freq) {
  1883. idx_r = i;
  1884. idx_l = idx_r - 1;
  1885. goto done;
  1886. }
  1887. }
  1888. done:
  1889. *pcinfo_l = &pcinfo[idx_l];
  1890. *pcinfo_r = &pcinfo[idx_r];
  1891. }
  1892. /*
  1893. * Get the surrounding per-rate power calibration data
  1894. * for a given frequency and interpolate between power
  1895. * values to set max target power supported by hw for
  1896. * each rate.
  1897. */
  1898. static void
  1899. ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
  1900. struct ieee80211_channel *channel,
  1901. struct ath5k_rate_pcal_info *rates)
  1902. {
  1903. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1904. struct ath5k_rate_pcal_info *rpinfo;
  1905. u8 idx_l, idx_r;
  1906. u8 mode, max, i;
  1907. u32 target = channel->center_freq;
  1908. idx_l = 0;
  1909. idx_r = 0;
  1910. if (!(channel->hw_value & CHANNEL_OFDM)) {
  1911. rpinfo = ee->ee_rate_tpwr_b;
  1912. mode = AR5K_EEPROM_MODE_11B;
  1913. } else if (channel->hw_value & CHANNEL_2GHZ) {
  1914. rpinfo = ee->ee_rate_tpwr_g;
  1915. mode = AR5K_EEPROM_MODE_11G;
  1916. } else {
  1917. rpinfo = ee->ee_rate_tpwr_a;
  1918. mode = AR5K_EEPROM_MODE_11A;
  1919. }
  1920. max = ee->ee_rate_target_pwr_num[mode] - 1;
  1921. /* Get the surrounding calibration
  1922. * piers - same as above */
  1923. if (target < rpinfo[0].freq) {
  1924. idx_l = idx_r = 0;
  1925. goto done;
  1926. }
  1927. if (target > rpinfo[max].freq) {
  1928. idx_l = idx_r = max;
  1929. goto done;
  1930. }
  1931. for (i = 0; i <= max; i++) {
  1932. if (rpinfo[i].freq == target) {
  1933. idx_l = idx_r = i;
  1934. goto done;
  1935. }
  1936. if (target < rpinfo[i].freq) {
  1937. idx_r = i;
  1938. idx_l = idx_r - 1;
  1939. goto done;
  1940. }
  1941. }
  1942. done:
  1943. /* Now interpolate power value, based on the frequency */
  1944. rates->freq = target;
  1945. rates->target_power_6to24 =
  1946. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  1947. rpinfo[idx_r].freq,
  1948. rpinfo[idx_l].target_power_6to24,
  1949. rpinfo[idx_r].target_power_6to24);
  1950. rates->target_power_36 =
  1951. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  1952. rpinfo[idx_r].freq,
  1953. rpinfo[idx_l].target_power_36,
  1954. rpinfo[idx_r].target_power_36);
  1955. rates->target_power_48 =
  1956. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  1957. rpinfo[idx_r].freq,
  1958. rpinfo[idx_l].target_power_48,
  1959. rpinfo[idx_r].target_power_48);
  1960. rates->target_power_54 =
  1961. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  1962. rpinfo[idx_r].freq,
  1963. rpinfo[idx_l].target_power_54,
  1964. rpinfo[idx_r].target_power_54);
  1965. }
  1966. /*
  1967. * Get the max edge power for this channel if
  1968. * we have such data from EEPROM's Conformance Test
  1969. * Limits (CTL), and limit max power if needed.
  1970. */
  1971. static void
  1972. ath5k_get_max_ctl_power(struct ath5k_hw *ah,
  1973. struct ieee80211_channel *channel)
  1974. {
  1975. struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
  1976. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1977. struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
  1978. u8 *ctl_val = ee->ee_ctl;
  1979. s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
  1980. s16 edge_pwr = 0;
  1981. u8 rep_idx;
  1982. u8 i, ctl_mode;
  1983. u8 ctl_idx = 0xFF;
  1984. u32 target = channel->center_freq;
  1985. ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
  1986. switch (channel->hw_value & CHANNEL_MODES) {
  1987. case CHANNEL_A:
  1988. if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
  1989. ctl_mode |= AR5K_CTL_TURBO;
  1990. else
  1991. ctl_mode |= AR5K_CTL_11A;
  1992. break;
  1993. case CHANNEL_G:
  1994. if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
  1995. ctl_mode |= AR5K_CTL_TURBOG;
  1996. else
  1997. ctl_mode |= AR5K_CTL_11G;
  1998. break;
  1999. case CHANNEL_B:
  2000. ctl_mode |= AR5K_CTL_11B;
  2001. break;
  2002. case CHANNEL_XR:
  2003. /* Fall through */
  2004. default:
  2005. return;
  2006. }
  2007. for (i = 0; i < ee->ee_ctls; i++) {
  2008. if (ctl_val[i] == ctl_mode) {
  2009. ctl_idx = i;
  2010. break;
  2011. }
  2012. }
  2013. /* If we have a CTL dataset available grab it and find the
  2014. * edge power for our frequency */
  2015. if (ctl_idx == 0xFF)
  2016. return;
  2017. /* Edge powers are sorted by frequency from lower
  2018. * to higher. Each CTL corresponds to 8 edge power
  2019. * measurements. */
  2020. rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
  2021. /* Don't do boundaries check because we
  2022. * might have more that one bands defined
  2023. * for this mode */
  2024. /* Get the edge power that's closer to our
  2025. * frequency */
  2026. for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
  2027. rep_idx += i;
  2028. if (target <= rep[rep_idx].freq)
  2029. edge_pwr = (s16) rep[rep_idx].edge;
  2030. }
  2031. if (edge_pwr)
  2032. ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
  2033. }
  2034. /*
  2035. * Power to PCDAC table functions
  2036. */
  2037. /*
  2038. * Fill Power to PCDAC table on RF5111
  2039. *
  2040. * No further processing is needed for RF5111, the only thing we have to
  2041. * do is fill the values below and above calibration range since eeprom data
  2042. * may not cover the entire PCDAC table.
  2043. */
  2044. static void
  2045. ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
  2046. s16 *table_max)
  2047. {
  2048. u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
  2049. u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
  2050. u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
  2051. s16 min_pwr, max_pwr;
  2052. /* Get table boundaries */
  2053. min_pwr = table_min[0];
  2054. pcdac_0 = pcdac_tmp[0];
  2055. max_pwr = table_max[0];
  2056. pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
  2057. /* Extrapolate below minimum using pcdac_0 */
  2058. pcdac_i = 0;
  2059. for (i = 0; i < min_pwr; i++)
  2060. pcdac_out[pcdac_i++] = pcdac_0;
  2061. /* Copy values from pcdac_tmp */
  2062. pwr_idx = min_pwr;
  2063. for (i = 0 ; pwr_idx <= max_pwr &&
  2064. pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
  2065. pcdac_out[pcdac_i++] = pcdac_tmp[i];
  2066. pwr_idx++;
  2067. }
  2068. /* Extrapolate above maximum */
  2069. while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
  2070. pcdac_out[pcdac_i++] = pcdac_n;
  2071. }
  2072. /*
  2073. * Combine available XPD Curves and fill Linear Power to PCDAC table
  2074. * on RF5112
  2075. *
  2076. * RFX112 can have up to 2 curves (one for low txpower range and one for
  2077. * higher txpower range). We need to put them both on pcdac_out and place
  2078. * them in the correct location. In case we only have one curve available
  2079. * just fit it on pcdac_out (it's supposed to cover the entire range of
  2080. * available pwr levels since it's always the higher power curve). Extrapolate
  2081. * below and above final table if needed.
  2082. */
  2083. static void
  2084. ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
  2085. s16 *table_max, u8 pdcurves)
  2086. {
  2087. u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
  2088. u8 *pcdac_low_pwr;
  2089. u8 *pcdac_high_pwr;
  2090. u8 *pcdac_tmp;
  2091. u8 pwr;
  2092. s16 max_pwr_idx;
  2093. s16 min_pwr_idx;
  2094. s16 mid_pwr_idx = 0;
  2095. /* Edge flag turs on the 7nth bit on the PCDAC
  2096. * to delcare the higher power curve (force values
  2097. * to be greater than 64). If we only have one curve
  2098. * we don't need to set this, if we have 2 curves and
  2099. * fill the table backwards this can also be used to
  2100. * switch from higher power curve to lower power curve */
  2101. u8 edge_flag;
  2102. int i;
  2103. /* When we have only one curve available
  2104. * that's the higher power curve. If we have
  2105. * two curves the first is the high power curve
  2106. * and the next is the low power curve. */
  2107. if (pdcurves > 1) {
  2108. pcdac_low_pwr = ah->ah_txpower.tmpL[1];
  2109. pcdac_high_pwr = ah->ah_txpower.tmpL[0];
  2110. mid_pwr_idx = table_max[1] - table_min[1] - 1;
  2111. max_pwr_idx = (table_max[0] - table_min[0]) / 2;
  2112. /* If table size goes beyond 31.5dB, keep the
  2113. * upper 31.5dB range when setting tx power.
  2114. * Note: 126 = 31.5 dB in quarter dB steps */
  2115. if (table_max[0] - table_min[1] > 126)
  2116. min_pwr_idx = table_max[0] - 126;
  2117. else
  2118. min_pwr_idx = table_min[1];
  2119. /* Since we fill table backwards
  2120. * start from high power curve */
  2121. pcdac_tmp = pcdac_high_pwr;
  2122. edge_flag = 0x40;
  2123. } else {
  2124. pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
  2125. pcdac_high_pwr = ah->ah_txpower.tmpL[0];
  2126. min_pwr_idx = table_min[0];
  2127. max_pwr_idx = (table_max[0] - table_min[0]) / 2;
  2128. pcdac_tmp = pcdac_high_pwr;
  2129. edge_flag = 0;
  2130. }
  2131. /* This is used when setting tx power*/
  2132. ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
  2133. /* Fill Power to PCDAC table backwards */
  2134. pwr = max_pwr_idx;
  2135. for (i = 63; i >= 0; i--) {
  2136. /* Entering lower power range, reset
  2137. * edge flag and set pcdac_tmp to lower
  2138. * power curve.*/
  2139. if (edge_flag == 0x40 &&
  2140. (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
  2141. edge_flag = 0x00;
  2142. pcdac_tmp = pcdac_low_pwr;
  2143. pwr = mid_pwr_idx/2;
  2144. }
  2145. /* Don't go below 1, extrapolate below if we have
  2146. * already swithced to the lower power curve -or
  2147. * we only have one curve and edge_flag is zero
  2148. * anyway */
  2149. if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
  2150. while (i >= 0) {
  2151. pcdac_out[i] = pcdac_out[i + 1];
  2152. i--;
  2153. }
  2154. break;
  2155. }
  2156. pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
  2157. /* Extrapolate above if pcdac is greater than
  2158. * 126 -this can happen because we OR pcdac_out
  2159. * value with edge_flag on high power curve */
  2160. if (pcdac_out[i] > 126)
  2161. pcdac_out[i] = 126;
  2162. /* Decrease by a 0.5dB step */
  2163. pwr--;
  2164. }
  2165. }
  2166. /* Write PCDAC values on hw */
  2167. static void
  2168. ath5k_write_pcdac_table(struct ath5k_hw *ah)
  2169. {
  2170. u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
  2171. int i;
  2172. /*
  2173. * Write TX power values
  2174. */
  2175. for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
  2176. ath5k_hw_reg_write(ah,
  2177. (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
  2178. (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
  2179. AR5K_PHY_PCDAC_TXPOWER(i));
  2180. }
  2181. }
  2182. /*
  2183. * Power to PDADC table functions
  2184. */
  2185. /*
  2186. * Set the gain boundaries and create final Power to PDADC table
  2187. *
  2188. * We can have up to 4 pd curves, we need to do a simmilar process
  2189. * as we do for RF5112. This time we don't have an edge_flag but we
  2190. * set the gain boundaries on a separate register.
  2191. */
  2192. static void
  2193. ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
  2194. s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
  2195. {
  2196. u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
  2197. u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
  2198. u8 *pdadc_tmp;
  2199. s16 pdadc_0;
  2200. u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
  2201. u8 pd_gain_overlap;
  2202. /* Note: Register value is initialized on initvals
  2203. * there is no feedback from hw.
  2204. * XXX: What about pd_gain_overlap from EEPROM ? */
  2205. pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
  2206. AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
  2207. /* Create final PDADC table */
  2208. for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
  2209. pdadc_tmp = ah->ah_txpower.tmpL[pdg];
  2210. if (pdg == pdcurves - 1)
  2211. /* 2 dB boundary stretch for last
  2212. * (higher power) curve */
  2213. gain_boundaries[pdg] = pwr_max[pdg] + 4;
  2214. else
  2215. /* Set gain boundary in the middle
  2216. * between this curve and the next one */
  2217. gain_boundaries[pdg] =
  2218. (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
  2219. /* Sanity check in case our 2 db stretch got out of
  2220. * range. */
  2221. if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
  2222. gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
  2223. /* For the first curve (lower power)
  2224. * start from 0 dB */
  2225. if (pdg == 0)
  2226. pdadc_0 = 0;
  2227. else
  2228. /* For the other curves use the gain overlap */
  2229. pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
  2230. pd_gain_overlap;
  2231. /* Force each power step to be at least 0.5 dB */
  2232. if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
  2233. pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
  2234. else
  2235. pwr_step = 1;
  2236. /* If pdadc_0 is negative, we need to extrapolate
  2237. * below this pdgain by a number of pwr_steps */
  2238. while ((pdadc_0 < 0) && (pdadc_i < 128)) {
  2239. s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
  2240. pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
  2241. pdadc_0++;
  2242. }
  2243. /* Set last pwr level, using gain boundaries */
  2244. pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
  2245. /* Limit it to be inside pwr range */
  2246. table_size = pwr_max[pdg] - pwr_min[pdg];
  2247. max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
  2248. /* Fill pdadc_out table */
  2249. while (pdadc_0 < max_idx && pdadc_i < 128)
  2250. pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
  2251. /* Need to extrapolate above this pdgain? */
  2252. if (pdadc_n <= max_idx)
  2253. continue;
  2254. /* Force each power step to be at least 0.5 dB */
  2255. if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
  2256. pwr_step = pdadc_tmp[table_size - 1] -
  2257. pdadc_tmp[table_size - 2];
  2258. else
  2259. pwr_step = 1;
  2260. /* Extrapolate above */
  2261. while ((pdadc_0 < (s16) pdadc_n) &&
  2262. (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
  2263. s16 tmp = pdadc_tmp[table_size - 1] +
  2264. (pdadc_0 - max_idx) * pwr_step;
  2265. pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
  2266. pdadc_0++;
  2267. }
  2268. }
  2269. while (pdg < AR5K_EEPROM_N_PD_GAINS) {
  2270. gain_boundaries[pdg] = gain_boundaries[pdg - 1];
  2271. pdg++;
  2272. }
  2273. while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
  2274. pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
  2275. pdadc_i++;
  2276. }
  2277. /* Set gain boundaries */
  2278. ath5k_hw_reg_write(ah,
  2279. AR5K_REG_SM(pd_gain_overlap,
  2280. AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
  2281. AR5K_REG_SM(gain_boundaries[0],
  2282. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
  2283. AR5K_REG_SM(gain_boundaries[1],
  2284. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
  2285. AR5K_REG_SM(gain_boundaries[2],
  2286. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
  2287. AR5K_REG_SM(gain_boundaries[3],
  2288. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
  2289. AR5K_PHY_TPC_RG5);
  2290. /* Used for setting rate power table */
  2291. ah->ah_txpower.txp_min_idx = pwr_min[0];
  2292. }
  2293. /* Write PDADC values on hw */
  2294. static void
  2295. ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
  2296. {
  2297. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  2298. u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
  2299. u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
  2300. u8 pdcurves = ee->ee_pd_gains[ee_mode];
  2301. u32 reg;
  2302. u8 i;
  2303. /* Select the right pdgain curves */
  2304. /* Clear current settings */
  2305. reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
  2306. reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
  2307. AR5K_PHY_TPC_RG1_PDGAIN_2 |
  2308. AR5K_PHY_TPC_RG1_PDGAIN_3 |
  2309. AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
  2310. /*
  2311. * Use pd_gains curve from eeprom
  2312. *
  2313. * This overrides the default setting from initvals
  2314. * in case some vendors (e.g. Zcomax) don't use the default
  2315. * curves. If we don't honor their settings we 'll get a
  2316. * 5dB (1 * gain overlap ?) drop.
  2317. */
  2318. reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
  2319. switch (pdcurves) {
  2320. case 3:
  2321. reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
  2322. /* Fall through */
  2323. case 2:
  2324. reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
  2325. /* Fall through */
  2326. case 1:
  2327. reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
  2328. break;
  2329. }
  2330. ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
  2331. /*
  2332. * Write TX power values
  2333. */
  2334. for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
  2335. ath5k_hw_reg_write(ah,
  2336. ((pdadc_out[4*i + 0] & 0xff) << 0) |
  2337. ((pdadc_out[4*i + 1] & 0xff) << 8) |
  2338. ((pdadc_out[4*i + 2] & 0xff) << 16) |
  2339. ((pdadc_out[4*i + 3] & 0xff) << 24),
  2340. AR5K_PHY_PDADC_TXPOWER(i));
  2341. }
  2342. }
  2343. /*
  2344. * Common code for PCDAC/PDADC tables
  2345. */
  2346. /*
  2347. * This is the main function that uses all of the above
  2348. * to set PCDAC/PDADC table on hw for the current channel.
  2349. * This table is used for tx power calibration on the basband,
  2350. * without it we get weird tx power levels and in some cases
  2351. * distorted spectral mask
  2352. */
  2353. static int
  2354. ath5k_setup_channel_powertable(struct ath5k_hw *ah,
  2355. struct ieee80211_channel *channel,
  2356. u8 ee_mode, u8 type)
  2357. {
  2358. struct ath5k_pdgain_info *pdg_L, *pdg_R;
  2359. struct ath5k_chan_pcal_info *pcinfo_L;
  2360. struct ath5k_chan_pcal_info *pcinfo_R;
  2361. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  2362. u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
  2363. s16 table_min[AR5K_EEPROM_N_PD_GAINS];
  2364. s16 table_max[AR5K_EEPROM_N_PD_GAINS];
  2365. u8 *tmpL;
  2366. u8 *tmpR;
  2367. u32 target = channel->center_freq;
  2368. int pdg, i;
  2369. /* Get surounding freq piers for this channel */
  2370. ath5k_get_chan_pcal_surrounding_piers(ah, channel,
  2371. &pcinfo_L,
  2372. &pcinfo_R);
  2373. /* Loop over pd gain curves on
  2374. * surounding freq piers by index */
  2375. for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
  2376. /* Fill curves in reverse order
  2377. * from lower power (max gain)
  2378. * to higher power. Use curve -> idx
  2379. * backmapping we did on eeprom init */
  2380. u8 idx = pdg_curve_to_idx[pdg];
  2381. /* Grab the needed curves by index */
  2382. pdg_L = &pcinfo_L->pd_curves[idx];
  2383. pdg_R = &pcinfo_R->pd_curves[idx];
  2384. /* Initialize the temp tables */
  2385. tmpL = ah->ah_txpower.tmpL[pdg];
  2386. tmpR = ah->ah_txpower.tmpR[pdg];
  2387. /* Set curve's x boundaries and create
  2388. * curves so that they cover the same
  2389. * range (if we don't do that one table
  2390. * will have values on some range and the
  2391. * other one won't have any so interpolation
  2392. * will fail) */
  2393. table_min[pdg] = min(pdg_L->pd_pwr[0],
  2394. pdg_R->pd_pwr[0]) / 2;
  2395. table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
  2396. pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
  2397. /* Now create the curves on surrounding channels
  2398. * and interpolate if needed to get the final
  2399. * curve for this gain on this channel */
  2400. switch (type) {
  2401. case AR5K_PWRTABLE_LINEAR_PCDAC:
  2402. /* Override min/max so that we don't loose
  2403. * accuracy (don't divide by 2) */
  2404. table_min[pdg] = min(pdg_L->pd_pwr[0],
  2405. pdg_R->pd_pwr[0]);
  2406. table_max[pdg] =
  2407. max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
  2408. pdg_R->pd_pwr[pdg_R->pd_points - 1]);
  2409. /* Override minimum so that we don't get
  2410. * out of bounds while extrapolating
  2411. * below. Don't do this when we have 2
  2412. * curves and we are on the high power curve
  2413. * because table_min is ok in this case */
  2414. if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
  2415. table_min[pdg] =
  2416. ath5k_get_linear_pcdac_min(pdg_L->pd_step,
  2417. pdg_R->pd_step,
  2418. pdg_L->pd_pwr,
  2419. pdg_R->pd_pwr);
  2420. /* Don't go too low because we will
  2421. * miss the upper part of the curve.
  2422. * Note: 126 = 31.5dB (max power supported)
  2423. * in 0.25dB units */
  2424. if (table_max[pdg] - table_min[pdg] > 126)
  2425. table_min[pdg] = table_max[pdg] - 126;
  2426. }
  2427. /* Fall through */
  2428. case AR5K_PWRTABLE_PWR_TO_PCDAC:
  2429. case AR5K_PWRTABLE_PWR_TO_PDADC:
  2430. ath5k_create_power_curve(table_min[pdg],
  2431. table_max[pdg],
  2432. pdg_L->pd_pwr,
  2433. pdg_L->pd_step,
  2434. pdg_L->pd_points, tmpL, type);
  2435. /* We are in a calibration
  2436. * pier, no need to interpolate
  2437. * between freq piers */
  2438. if (pcinfo_L == pcinfo_R)
  2439. continue;
  2440. ath5k_create_power_curve(table_min[pdg],
  2441. table_max[pdg],
  2442. pdg_R->pd_pwr,
  2443. pdg_R->pd_step,
  2444. pdg_R->pd_points, tmpR, type);
  2445. break;
  2446. default:
  2447. return -EINVAL;
  2448. }
  2449. /* Interpolate between curves
  2450. * of surounding freq piers to
  2451. * get the final curve for this
  2452. * pd gain. Re-use tmpL for interpolation
  2453. * output */
  2454. for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
  2455. (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
  2456. tmpL[i] = (u8) ath5k_get_interpolated_value(target,
  2457. (s16) pcinfo_L->freq,
  2458. (s16) pcinfo_R->freq,
  2459. (s16) tmpL[i],
  2460. (s16) tmpR[i]);
  2461. }
  2462. }
  2463. /* Now we have a set of curves for this
  2464. * channel on tmpL (x range is table_max - table_min
  2465. * and y values are tmpL[pdg][]) sorted in the same
  2466. * order as EEPROM (because we've used the backmapping).
  2467. * So for RF5112 it's from higher power to lower power
  2468. * and for RF2413 it's from lower power to higher power.
  2469. * For RF5111 we only have one curve. */
  2470. /* Fill min and max power levels for this
  2471. * channel by interpolating the values on
  2472. * surounding channels to complete the dataset */
  2473. ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
  2474. (s16) pcinfo_L->freq,
  2475. (s16) pcinfo_R->freq,
  2476. pcinfo_L->min_pwr, pcinfo_R->min_pwr);
  2477. ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
  2478. (s16) pcinfo_L->freq,
  2479. (s16) pcinfo_R->freq,
  2480. pcinfo_L->max_pwr, pcinfo_R->max_pwr);
  2481. /* Fill PCDAC/PDADC table */
  2482. switch (type) {
  2483. case AR5K_PWRTABLE_LINEAR_PCDAC:
  2484. /* For RF5112 we can have one or two curves
  2485. * and each curve covers a certain power lvl
  2486. * range so we need to do some more processing */
  2487. ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
  2488. ee->ee_pd_gains[ee_mode]);
  2489. /* Set txp.offset so that we can
  2490. * match max power value with max
  2491. * table index */
  2492. ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
  2493. break;
  2494. case AR5K_PWRTABLE_PWR_TO_PCDAC:
  2495. /* We are done for RF5111 since it has only
  2496. * one curve, just fit the curve on the table */
  2497. ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
  2498. /* No rate powertable adjustment for RF5111 */
  2499. ah->ah_txpower.txp_min_idx = 0;
  2500. ah->ah_txpower.txp_offset = 0;
  2501. break;
  2502. case AR5K_PWRTABLE_PWR_TO_PDADC:
  2503. /* Set PDADC boundaries and fill
  2504. * final PDADC table */
  2505. ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
  2506. ee->ee_pd_gains[ee_mode]);
  2507. /* Set txp.offset, note that table_min
  2508. * can be negative */
  2509. ah->ah_txpower.txp_offset = table_min[0];
  2510. break;
  2511. default:
  2512. return -EINVAL;
  2513. }
  2514. ah->ah_txpower.txp_setup = true;
  2515. return 0;
  2516. }
  2517. /* Write power table for current channel to hw */
  2518. static void
  2519. ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
  2520. {
  2521. if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
  2522. ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
  2523. else
  2524. ath5k_write_pcdac_table(ah);
  2525. }
  2526. /*
  2527. * Per-rate tx power setting
  2528. *
  2529. * This is the code that sets the desired tx power (below
  2530. * maximum) on hw for each rate (we also have TPC that sets
  2531. * power per packet). We do that by providing an index on the
  2532. * PCDAC/PDADC table we set up.
  2533. */
  2534. /*
  2535. * Set rate power table
  2536. *
  2537. * For now we only limit txpower based on maximum tx power
  2538. * supported by hw (what's inside rate_info). We need to limit
  2539. * this even more, based on regulatory domain etc.
  2540. *
  2541. * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
  2542. * and is indexed as follows:
  2543. * rates[0] - rates[7] -> OFDM rates
  2544. * rates[8] - rates[14] -> CCK rates
  2545. * rates[15] -> XR rates (they all have the same power)
  2546. */
  2547. static void
  2548. ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
  2549. struct ath5k_rate_pcal_info *rate_info,
  2550. u8 ee_mode)
  2551. {
  2552. unsigned int i;
  2553. u16 *rates;
  2554. /* max_pwr is power level we got from driver/user in 0.5dB
  2555. * units, switch to 0.25dB units so we can compare */
  2556. max_pwr *= 2;
  2557. max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
  2558. /* apply rate limits */
  2559. rates = ah->ah_txpower.txp_rates_power_table;
  2560. /* OFDM rates 6 to 24Mb/s */
  2561. for (i = 0; i < 5; i++)
  2562. rates[i] = min(max_pwr, rate_info->target_power_6to24);
  2563. /* Rest OFDM rates */
  2564. rates[5] = min(rates[0], rate_info->target_power_36);
  2565. rates[6] = min(rates[0], rate_info->target_power_48);
  2566. rates[7] = min(rates[0], rate_info->target_power_54);
  2567. /* CCK rates */
  2568. /* 1L */
  2569. rates[8] = min(rates[0], rate_info->target_power_6to24);
  2570. /* 2L */
  2571. rates[9] = min(rates[0], rate_info->target_power_36);
  2572. /* 2S */
  2573. rates[10] = min(rates[0], rate_info->target_power_36);
  2574. /* 5L */
  2575. rates[11] = min(rates[0], rate_info->target_power_48);
  2576. /* 5S */
  2577. rates[12] = min(rates[0], rate_info->target_power_48);
  2578. /* 11L */
  2579. rates[13] = min(rates[0], rate_info->target_power_54);
  2580. /* 11S */
  2581. rates[14] = min(rates[0], rate_info->target_power_54);
  2582. /* XR rates */
  2583. rates[15] = min(rates[0], rate_info->target_power_6to24);
  2584. /* CCK rates have different peak to average ratio
  2585. * so we have to tweak their power so that gainf
  2586. * correction works ok. For this we use OFDM to
  2587. * CCK delta from eeprom */
  2588. if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
  2589. (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
  2590. for (i = 8; i <= 15; i++)
  2591. rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
  2592. /* Now that we have all rates setup use table offset to
  2593. * match the power range set by user with the power indices
  2594. * on PCDAC/PDADC table */
  2595. for (i = 0; i < 16; i++) {
  2596. rates[i] += ah->ah_txpower.txp_offset;
  2597. /* Don't get out of bounds */
  2598. if (rates[i] > 63)
  2599. rates[i] = 63;
  2600. }
  2601. /* Min/max in 0.25dB units */
  2602. ah->ah_txpower.txp_min_pwr = 2 * rates[7];
  2603. ah->ah_txpower.txp_cur_pwr = 2 * rates[0];
  2604. ah->ah_txpower.txp_ofdm = rates[7];
  2605. }
  2606. /*
  2607. * Set transmission power
  2608. */
  2609. static int
  2610. ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
  2611. u8 txpower)
  2612. {
  2613. struct ath5k_rate_pcal_info rate_info;
  2614. struct ieee80211_channel *curr_channel = ah->ah_current_channel;
  2615. int ee_mode;
  2616. u8 type;
  2617. int ret;
  2618. if (txpower > AR5K_TUNE_MAX_TXPOWER) {
  2619. ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
  2620. return -EINVAL;
  2621. }
  2622. ee_mode = ath5k_eeprom_mode_from_channel(channel);
  2623. if (ee_mode < 0) {
  2624. ATH5K_ERR(ah->ah_sc,
  2625. "invalid channel: %d\n", channel->center_freq);
  2626. return -EINVAL;
  2627. }
  2628. /* Initialize TX power table */
  2629. switch (ah->ah_radio) {
  2630. case AR5K_RF5110:
  2631. /* TODO */
  2632. return 0;
  2633. case AR5K_RF5111:
  2634. type = AR5K_PWRTABLE_PWR_TO_PCDAC;
  2635. break;
  2636. case AR5K_RF5112:
  2637. type = AR5K_PWRTABLE_LINEAR_PCDAC;
  2638. break;
  2639. case AR5K_RF2413:
  2640. case AR5K_RF5413:
  2641. case AR5K_RF2316:
  2642. case AR5K_RF2317:
  2643. case AR5K_RF2425:
  2644. type = AR5K_PWRTABLE_PWR_TO_PDADC;
  2645. break;
  2646. default:
  2647. return -EINVAL;
  2648. }
  2649. /*
  2650. * If we don't change channel/mode skip tx powertable calculation
  2651. * and use the cached one.
  2652. */
  2653. if (!ah->ah_txpower.txp_setup ||
  2654. (channel->hw_value != curr_channel->hw_value) ||
  2655. (channel->center_freq != curr_channel->center_freq)) {
  2656. /* Reset TX power values */
  2657. memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
  2658. ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
  2659. /* Calculate the powertable */
  2660. ret = ath5k_setup_channel_powertable(ah, channel,
  2661. ee_mode, type);
  2662. if (ret)
  2663. return ret;
  2664. }
  2665. /* Write table on hw */
  2666. ath5k_write_channel_powertable(ah, ee_mode, type);
  2667. /* Limit max power if we have a CTL available */
  2668. ath5k_get_max_ctl_power(ah, channel);
  2669. /* FIXME: Antenna reduction stuff */
  2670. /* FIXME: Limit power on turbo modes */
  2671. /* FIXME: TPC scale reduction */
  2672. /* Get surounding channels for per-rate power table
  2673. * calibration */
  2674. ath5k_get_rate_pcal_data(ah, channel, &rate_info);
  2675. /* Setup rate power table */
  2676. ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
  2677. /* Write rate power table on hw */
  2678. ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
  2679. AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
  2680. AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
  2681. ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
  2682. AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
  2683. AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
  2684. ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
  2685. AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
  2686. AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
  2687. ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
  2688. AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
  2689. AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
  2690. /* FIXME: TPC support */
  2691. if (ah->ah_txpower.txp_tpc) {
  2692. ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
  2693. AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
  2694. ath5k_hw_reg_write(ah,
  2695. AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
  2696. AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
  2697. AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
  2698. AR5K_TPC);
  2699. } else {
  2700. ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
  2701. AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
  2702. }
  2703. return 0;
  2704. }
  2705. int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
  2706. {
  2707. ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
  2708. "changing txpower to %d\n", txpower);
  2709. return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
  2710. }
  2711. /*************\
  2712. Init function
  2713. \*************/
  2714. int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
  2715. u8 mode, bool fast)
  2716. {
  2717. struct ieee80211_channel *curr_channel;
  2718. int ret, i;
  2719. u32 phy_tst1;
  2720. ret = 0;
  2721. /*
  2722. * Sanity check for fast flag
  2723. * Don't try fast channel change when changing modulation
  2724. * mode/band. We check for chip compatibility on
  2725. * ath5k_hw_reset.
  2726. */
  2727. curr_channel = ah->ah_current_channel;
  2728. if (fast && (channel->hw_value != curr_channel->hw_value))
  2729. return -EINVAL;
  2730. /*
  2731. * On fast channel change we only set the synth parameters
  2732. * while PHY is running, enable calibration and skip the rest.
  2733. */
  2734. if (fast) {
  2735. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
  2736. AR5K_PHY_RFBUS_REQ_REQUEST);
  2737. for (i = 0; i < 100; i++) {
  2738. if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
  2739. break;
  2740. udelay(5);
  2741. }
  2742. /* Failed */
  2743. if (i >= 100)
  2744. return -EIO;
  2745. }
  2746. /*
  2747. * Set TX power
  2748. *
  2749. * Note: We need to do that before we set
  2750. * RF buffer settings on 5211/5212+ so that we
  2751. * properly set curve indices.
  2752. */
  2753. ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ?
  2754. ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER);
  2755. if (ret)
  2756. return ret;
  2757. /*
  2758. * For 5210 we do all initialization using
  2759. * initvals, so we don't have to modify
  2760. * any settings (5210 also only supports
  2761. * a/aturbo modes)
  2762. */
  2763. if ((ah->ah_version != AR5K_AR5210) && !fast) {
  2764. /*
  2765. * Write initial RF gain settings
  2766. * This should work for both 5111/5112
  2767. */
  2768. ret = ath5k_hw_rfgain_init(ah, channel->band);
  2769. if (ret)
  2770. return ret;
  2771. mdelay(1);
  2772. /*
  2773. * Write RF buffer
  2774. */
  2775. ret = ath5k_hw_rfregs_init(ah, channel, mode);
  2776. if (ret)
  2777. return ret;
  2778. /* Write OFDM timings on 5212*/
  2779. if (ah->ah_version == AR5K_AR5212 &&
  2780. channel->hw_value & CHANNEL_OFDM) {
  2781. ret = ath5k_hw_write_ofdm_timings(ah, channel);
  2782. if (ret)
  2783. return ret;
  2784. /* Spur info is available only from EEPROM versions
  2785. * greater than 5.3, but the EEPROM routines will use
  2786. * static values for older versions */
  2787. if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
  2788. ath5k_hw_set_spur_mitigation_filter(ah,
  2789. channel);
  2790. }
  2791. /*Enable/disable 802.11b mode on 5111
  2792. (enable 2111 frequency converter + CCK)*/
  2793. if (ah->ah_radio == AR5K_RF5111) {
  2794. if (mode == AR5K_MODE_11B)
  2795. AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
  2796. AR5K_TXCFG_B_MODE);
  2797. else
  2798. AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
  2799. AR5K_TXCFG_B_MODE);
  2800. }
  2801. } else if (ah->ah_version == AR5K_AR5210) {
  2802. mdelay(1);
  2803. /* Disable phy and wait */
  2804. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
  2805. mdelay(1);
  2806. }
  2807. /* Set channel on PHY */
  2808. ret = ath5k_hw_channel(ah, channel);
  2809. if (ret)
  2810. return ret;
  2811. /*
  2812. * Enable the PHY and wait until completion
  2813. * This includes BaseBand and Synthesizer
  2814. * activation.
  2815. */
  2816. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
  2817. /*
  2818. * On 5211+ read activation -> rx delay
  2819. * and use it.
  2820. */
  2821. if (ah->ah_version != AR5K_AR5210) {
  2822. u32 delay;
  2823. delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
  2824. AR5K_PHY_RX_DELAY_M;
  2825. delay = (channel->hw_value & CHANNEL_CCK) ?
  2826. ((delay << 2) / 22) : (delay / 10);
  2827. if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
  2828. delay = delay << 1;
  2829. if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
  2830. delay = delay << 2;
  2831. /* XXX: /2 on turbo ? Let's be safe
  2832. * for now */
  2833. udelay(100 + delay);
  2834. } else {
  2835. mdelay(1);
  2836. }
  2837. if (fast)
  2838. /*
  2839. * Release RF Bus grant
  2840. */
  2841. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
  2842. AR5K_PHY_RFBUS_REQ_REQUEST);
  2843. else {
  2844. /*
  2845. * Perform ADC test to see if baseband is ready
  2846. * Set tx hold and check adc test register
  2847. */
  2848. phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
  2849. ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
  2850. for (i = 0; i <= 20; i++) {
  2851. if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
  2852. break;
  2853. udelay(200);
  2854. }
  2855. ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
  2856. }
  2857. /*
  2858. * Start automatic gain control calibration
  2859. *
  2860. * During AGC calibration RX path is re-routed to
  2861. * a power detector so we don't receive anything.
  2862. *
  2863. * This method is used to calibrate some static offsets
  2864. * used together with on-the fly I/Q calibration (the
  2865. * one performed via ath5k_hw_phy_calibrate), which doesn't
  2866. * interrupt rx path.
  2867. *
  2868. * While rx path is re-routed to the power detector we also
  2869. * start a noise floor calibration to measure the
  2870. * card's noise floor (the noise we measure when we are not
  2871. * transmitting or receiving anything).
  2872. *
  2873. * If we are in a noisy environment, AGC calibration may time
  2874. * out and/or noise floor calibration might timeout.
  2875. */
  2876. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  2877. AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
  2878. /* At the same time start I/Q calibration for QAM constellation
  2879. * -no need for CCK- */
  2880. ah->ah_calibration = false;
  2881. if (!(mode == AR5K_MODE_11B)) {
  2882. ah->ah_calibration = true;
  2883. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
  2884. AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
  2885. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
  2886. AR5K_PHY_IQ_RUN);
  2887. }
  2888. /* Wait for gain calibration to finish (we check for I/Q calibration
  2889. * during ath5k_phy_calibrate) */
  2890. if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
  2891. AR5K_PHY_AGCCTL_CAL, 0, false)) {
  2892. ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
  2893. channel->center_freq);
  2894. }
  2895. /* Restore antenna mode */
  2896. ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
  2897. return ret;
  2898. }