bnx2x_cmn.h 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047
  1. /* bnx2x_cmn.h: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10. * Written by: Eliezer Tamir
  11. * Based on code from Michael Chan's bnx2 driver
  12. * UDP CSUM errata workaround by Arik Gendelman
  13. * Slowpath and fastpath rework by Vladislav Zolotarov
  14. * Statistics and Link management by Yitchak Gertner
  15. *
  16. */
  17. #ifndef BNX2X_CMN_H
  18. #define BNX2X_CMN_H
  19. #include <linux/types.h>
  20. #include <linux/netdevice.h>
  21. #include "bnx2x.h"
  22. extern int num_queues;
  23. /*********************** Interfaces ****************************
  24. * Functions that need to be implemented by each driver version
  25. */
  26. /**
  27. * Initialize link parameters structure variables.
  28. *
  29. * @param bp
  30. * @param load_mode
  31. *
  32. * @return u8
  33. */
  34. u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
  35. /**
  36. * Configure hw according to link parameters structure.
  37. *
  38. * @param bp
  39. */
  40. void bnx2x_link_set(struct bnx2x *bp);
  41. /**
  42. * Query link status
  43. *
  44. * @param bp
  45. * @param is_serdes
  46. *
  47. * @return 0 - link is UP
  48. */
  49. u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
  50. /**
  51. * Handles link status change
  52. *
  53. * @param bp
  54. */
  55. void bnx2x__link_status_update(struct bnx2x *bp);
  56. /**
  57. * Report link status to upper layer
  58. *
  59. * @param bp
  60. *
  61. * @return int
  62. */
  63. void bnx2x_link_report(struct bnx2x *bp);
  64. /**
  65. * calculates MF speed according to current linespeed and MF
  66. * configuration
  67. *
  68. * @param bp
  69. *
  70. * @return u16
  71. */
  72. u16 bnx2x_get_mf_speed(struct bnx2x *bp);
  73. /**
  74. * MSI-X slowpath interrupt handler
  75. *
  76. * @param irq
  77. * @param dev_instance
  78. *
  79. * @return irqreturn_t
  80. */
  81. irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
  82. /**
  83. * non MSI-X interrupt handler
  84. *
  85. * @param irq
  86. * @param dev_instance
  87. *
  88. * @return irqreturn_t
  89. */
  90. irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
  91. #ifdef BCM_CNIC
  92. /**
  93. * Send command to cnic driver
  94. *
  95. * @param bp
  96. * @param cmd
  97. */
  98. int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
  99. /**
  100. * Provides cnic information for proper interrupt handling
  101. *
  102. * @param bp
  103. */
  104. void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
  105. #endif
  106. /**
  107. * Enable HW interrupts.
  108. *
  109. * @param bp
  110. */
  111. void bnx2x_int_enable(struct bnx2x *bp);
  112. /**
  113. * Disable interrupts. This function ensures that there are no
  114. * ISRs or SP DPCs (sp_task) are running after it returns.
  115. *
  116. * @param bp
  117. * @param disable_hw if true, disable HW interrupts.
  118. */
  119. void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
  120. /**
  121. * Loads device firmware
  122. *
  123. * @param bp
  124. *
  125. * @return int
  126. */
  127. int bnx2x_init_firmware(struct bnx2x *bp);
  128. /**
  129. * Init HW blocks according to current initialization stage:
  130. * COMMON, PORT or FUNCTION.
  131. *
  132. * @param bp
  133. * @param load_code: COMMON, PORT or FUNCTION
  134. *
  135. * @return int
  136. */
  137. int bnx2x_init_hw(struct bnx2x *bp, u32 load_code);
  138. /**
  139. * Init driver internals:
  140. * - rings
  141. * - status blocks
  142. * - etc.
  143. *
  144. * @param bp
  145. * @param load_code COMMON, PORT or FUNCTION
  146. */
  147. void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
  148. /**
  149. * Allocate driver's memory.
  150. *
  151. * @param bp
  152. *
  153. * @return int
  154. */
  155. int bnx2x_alloc_mem(struct bnx2x *bp);
  156. /**
  157. * Release driver's memory.
  158. *
  159. * @param bp
  160. */
  161. void bnx2x_free_mem(struct bnx2x *bp);
  162. /**
  163. * Setup eth Client.
  164. *
  165. * @param bp
  166. * @param fp
  167. * @param is_leading
  168. *
  169. * @return int
  170. */
  171. int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
  172. int is_leading);
  173. /**
  174. * Set number of queues according to mode
  175. *
  176. * @param bp
  177. *
  178. */
  179. void bnx2x_set_num_queues(struct bnx2x *bp);
  180. /**
  181. * Cleanup chip internals:
  182. * - Cleanup MAC configuration.
  183. * - Close clients.
  184. * - etc.
  185. *
  186. * @param bp
  187. * @param unload_mode
  188. */
  189. void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
  190. /**
  191. * Acquire HW lock.
  192. *
  193. * @param bp
  194. * @param resource Resource bit which was locked
  195. *
  196. * @return int
  197. */
  198. int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
  199. /**
  200. * Release HW lock.
  201. *
  202. * @param bp driver handle
  203. * @param resource Resource bit which was locked
  204. *
  205. * @return int
  206. */
  207. int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
  208. /**
  209. * Configure eth MAC address in the HW according to the value in
  210. * netdev->dev_addr.
  211. *
  212. * @param bp driver handle
  213. * @param set
  214. */
  215. void bnx2x_set_eth_mac(struct bnx2x *bp, int set);
  216. #ifdef BCM_CNIC
  217. /**
  218. * Set/Clear FIP MAC(s) at the next enties in the CAM after the ETH
  219. * MAC(s). This function will wait until the ramdord completion
  220. * returns.
  221. *
  222. * @param bp driver handle
  223. * @param set set or clear the CAM entry
  224. *
  225. * @return 0 if cussess, -ENODEV if ramrod doesn't return.
  226. */
  227. int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set);
  228. /**
  229. * Set/Clear ALL_ENODE mcast MAC.
  230. *
  231. * @param bp
  232. * @param set
  233. *
  234. * @return int
  235. */
  236. int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set);
  237. #endif
  238. /**
  239. * Set MAC filtering configurations.
  240. *
  241. * @remarks called with netif_tx_lock from dev_mcast.c
  242. *
  243. * @param dev net_device
  244. */
  245. void bnx2x_set_rx_mode(struct net_device *dev);
  246. /**
  247. * Configure MAC filtering rules in a FW.
  248. *
  249. * @param bp driver handle
  250. */
  251. void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
  252. /* Parity errors related */
  253. void bnx2x_inc_load_cnt(struct bnx2x *bp);
  254. u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
  255. bool bnx2x_chk_parity_attn(struct bnx2x *bp);
  256. bool bnx2x_reset_is_done(struct bnx2x *bp);
  257. void bnx2x_disable_close_the_gate(struct bnx2x *bp);
  258. /**
  259. * Perform statistics handling according to event
  260. *
  261. * @param bp driver handle
  262. * @param event bnx2x_stats_event
  263. */
  264. void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
  265. /**
  266. * Handle ramrods completion
  267. *
  268. * @param fp fastpath handle for the event
  269. * @param rr_cqe eth_rx_cqe
  270. */
  271. void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
  272. /**
  273. * Init/halt function before/after sending
  274. * CLIENT_SETUP/CFC_DEL for the first/last client.
  275. *
  276. * @param bp
  277. *
  278. * @return int
  279. */
  280. int bnx2x_func_start(struct bnx2x *bp);
  281. /**
  282. * Prepare ILT configurations according to current driver
  283. * parameters.
  284. *
  285. * @param bp
  286. */
  287. void bnx2x_ilt_set_info(struct bnx2x *bp);
  288. /**
  289. * Inintialize dcbx protocol
  290. *
  291. * @param bp
  292. */
  293. void bnx2x_dcbx_init(struct bnx2x *bp);
  294. /**
  295. * Set power state to the requested value. Currently only D0 and
  296. * D3hot are supported.
  297. *
  298. * @param bp
  299. * @param state D0 or D3hot
  300. *
  301. * @return int
  302. */
  303. int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
  304. /* dev_close main block */
  305. int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
  306. /* dev_open main block */
  307. int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
  308. /* hard_xmit callback */
  309. netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
  310. /* select_queue callback */
  311. u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
  312. int bnx2x_change_mac_addr(struct net_device *dev, void *p);
  313. /* NAPI poll Rx part */
  314. int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
  315. /* NAPI poll Tx part */
  316. int bnx2x_tx_int(struct bnx2x_fastpath *fp);
  317. /* suspend/resume callbacks */
  318. int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
  319. int bnx2x_resume(struct pci_dev *pdev);
  320. /* Release IRQ vectors */
  321. void bnx2x_free_irq(struct bnx2x *bp);
  322. void bnx2x_init_rx_rings(struct bnx2x *bp);
  323. void bnx2x_free_skbs(struct bnx2x *bp);
  324. void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
  325. void bnx2x_netif_start(struct bnx2x *bp);
  326. /**
  327. * Fill msix_table, request vectors, update num_queues according
  328. * to number of available vectors
  329. *
  330. * @param bp
  331. *
  332. * @return int
  333. */
  334. int bnx2x_enable_msix(struct bnx2x *bp);
  335. /**
  336. * Request msi mode from OS, updated internals accordingly
  337. *
  338. * @param bp
  339. *
  340. * @return int
  341. */
  342. int bnx2x_enable_msi(struct bnx2x *bp);
  343. /**
  344. * NAPI callback
  345. *
  346. * @param napi
  347. * @param budget
  348. *
  349. * @return int
  350. */
  351. int bnx2x_poll(struct napi_struct *napi, int budget);
  352. /**
  353. * Allocate/release memories outsize main driver structure
  354. *
  355. * @param bp
  356. *
  357. * @return int
  358. */
  359. int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
  360. void bnx2x_free_mem_bp(struct bnx2x *bp);
  361. /**
  362. * Change mtu netdev callback
  363. *
  364. * @param dev
  365. * @param new_mtu
  366. *
  367. * @return int
  368. */
  369. int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
  370. /**
  371. * tx timeout netdev callback
  372. *
  373. * @param dev
  374. * @param new_mtu
  375. *
  376. * @return int
  377. */
  378. void bnx2x_tx_timeout(struct net_device *dev);
  379. #ifdef BCM_VLAN
  380. /**
  381. * vlan rx register netdev callback
  382. *
  383. * @param dev
  384. * @param new_mtu
  385. *
  386. * @return int
  387. */
  388. void bnx2x_vlan_rx_register(struct net_device *dev,
  389. struct vlan_group *vlgrp);
  390. #endif
  391. static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
  392. {
  393. barrier(); /* status block is written to by the chip */
  394. fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
  395. }
  396. static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
  397. struct bnx2x_fastpath *fp,
  398. u16 bd_prod, u16 rx_comp_prod,
  399. u16 rx_sge_prod)
  400. {
  401. struct ustorm_eth_rx_producers rx_prods = {0};
  402. int i;
  403. /* Update producers */
  404. rx_prods.bd_prod = bd_prod;
  405. rx_prods.cqe_prod = rx_comp_prod;
  406. rx_prods.sge_prod = rx_sge_prod;
  407. /*
  408. * Make sure that the BD and SGE data is updated before updating the
  409. * producers since FW might read the BD/SGE right after the producer
  410. * is updated.
  411. * This is only applicable for weak-ordered memory model archs such
  412. * as IA-64. The following barrier is also mandatory since FW will
  413. * assumes BDs must have buffers.
  414. */
  415. wmb();
  416. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
  417. REG_WR(bp,
  418. BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset + i*4,
  419. ((u32 *)&rx_prods)[i]);
  420. mmiowb(); /* keep prod updates ordered */
  421. DP(NETIF_MSG_RX_STATUS,
  422. "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
  423. fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
  424. }
  425. static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
  426. u8 segment, u16 index, u8 op,
  427. u8 update, u32 igu_addr)
  428. {
  429. struct igu_regular cmd_data = {0};
  430. cmd_data.sb_id_and_flags =
  431. ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
  432. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  433. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  434. (op << IGU_REGULAR_ENABLE_INT_SHIFT));
  435. DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n",
  436. cmd_data.sb_id_and_flags, igu_addr);
  437. REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
  438. /* Make sure that ACK is written */
  439. mmiowb();
  440. barrier();
  441. }
  442. static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp,
  443. u8 idu_sb_id, bool is_Pf)
  444. {
  445. u32 data, ctl, cnt = 100;
  446. u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
  447. u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
  448. u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
  449. u32 sb_bit = 1 << (idu_sb_id%32);
  450. u32 func_encode = BP_FUNC(bp) |
  451. ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT);
  452. u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
  453. /* Not supported in BC mode */
  454. if (CHIP_INT_MODE_IS_BC(bp))
  455. return;
  456. data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
  457. << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
  458. IGU_REGULAR_CLEANUP_SET |
  459. IGU_REGULAR_BCLEANUP;
  460. ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
  461. func_encode << IGU_CTRL_REG_FID_SHIFT |
  462. IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
  463. DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
  464. data, igu_addr_data);
  465. REG_WR(bp, igu_addr_data, data);
  466. mmiowb();
  467. barrier();
  468. DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
  469. ctl, igu_addr_ctl);
  470. REG_WR(bp, igu_addr_ctl, ctl);
  471. mmiowb();
  472. barrier();
  473. /* wait for clean up to finish */
  474. while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
  475. msleep(20);
  476. if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
  477. DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: "
  478. "idu_sb_id %d offset %d bit %d (cnt %d)\n",
  479. idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
  480. }
  481. }
  482. static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
  483. u8 storm, u16 index, u8 op, u8 update)
  484. {
  485. u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
  486. COMMAND_REG_INT_ACK);
  487. struct igu_ack_register igu_ack;
  488. igu_ack.status_block_index = index;
  489. igu_ack.sb_id_and_flags =
  490. ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  491. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  492. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  493. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  494. DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
  495. (*(u32 *)&igu_ack), hc_addr);
  496. REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
  497. /* Make sure that ACK is written */
  498. mmiowb();
  499. barrier();
  500. }
  501. static inline void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
  502. u16 index, u8 op, u8 update)
  503. {
  504. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
  505. bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
  506. igu_addr);
  507. }
  508. static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
  509. u16 index, u8 op, u8 update)
  510. {
  511. if (bp->common.int_block == INT_BLOCK_HC)
  512. bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
  513. else {
  514. u8 segment;
  515. if (CHIP_INT_MODE_IS_BC(bp))
  516. segment = storm;
  517. else if (igu_sb_id != bp->igu_dsb_id)
  518. segment = IGU_SEG_ACCESS_DEF;
  519. else if (storm == ATTENTION_ID)
  520. segment = IGU_SEG_ACCESS_ATTN;
  521. else
  522. segment = IGU_SEG_ACCESS_DEF;
  523. bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
  524. }
  525. }
  526. static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
  527. {
  528. u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
  529. COMMAND_REG_SIMD_MASK);
  530. u32 result = REG_RD(bp, hc_addr);
  531. DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
  532. result, hc_addr);
  533. barrier();
  534. return result;
  535. }
  536. static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
  537. {
  538. u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
  539. u32 result = REG_RD(bp, igu_addr);
  540. DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n",
  541. result, igu_addr);
  542. barrier();
  543. return result;
  544. }
  545. static inline u16 bnx2x_ack_int(struct bnx2x *bp)
  546. {
  547. barrier();
  548. if (bp->common.int_block == INT_BLOCK_HC)
  549. return bnx2x_hc_ack_int(bp);
  550. else
  551. return bnx2x_igu_ack_int(bp);
  552. }
  553. static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
  554. {
  555. /* Tell compiler that consumer and producer can change */
  556. barrier();
  557. return fp->tx_pkt_prod != fp->tx_pkt_cons;
  558. }
  559. static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
  560. {
  561. s16 used;
  562. u16 prod;
  563. u16 cons;
  564. prod = fp->tx_bd_prod;
  565. cons = fp->tx_bd_cons;
  566. /* NUM_TX_RINGS = number of "next-page" entries
  567. It will be used as a threshold */
  568. used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
  569. #ifdef BNX2X_STOP_ON_ERROR
  570. WARN_ON(used < 0);
  571. WARN_ON(used > fp->bp->tx_ring_size);
  572. WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
  573. #endif
  574. return (s16)(fp->bp->tx_ring_size) - used;
  575. }
  576. static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
  577. {
  578. u16 hw_cons;
  579. /* Tell compiler that status block fields can change */
  580. barrier();
  581. hw_cons = le16_to_cpu(*fp->tx_cons_sb);
  582. return hw_cons != fp->tx_pkt_cons;
  583. }
  584. static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
  585. {
  586. u16 rx_cons_sb;
  587. /* Tell compiler that status block fields can change */
  588. barrier();
  589. rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
  590. if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
  591. rx_cons_sb++;
  592. return (fp->rx_comp_cons != rx_cons_sb);
  593. }
  594. /**
  595. * disables tx from stack point of view
  596. *
  597. * @param bp
  598. */
  599. static inline void bnx2x_tx_disable(struct bnx2x *bp)
  600. {
  601. netif_tx_disable(bp->dev);
  602. netif_carrier_off(bp->dev);
  603. }
  604. static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
  605. struct bnx2x_fastpath *fp, u16 index)
  606. {
  607. struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
  608. struct page *page = sw_buf->page;
  609. struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
  610. /* Skip "next page" elements */
  611. if (!page)
  612. return;
  613. dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
  614. SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
  615. __free_pages(page, PAGES_PER_SGE_SHIFT);
  616. sw_buf->page = NULL;
  617. sge->addr_hi = 0;
  618. sge->addr_lo = 0;
  619. }
  620. static inline void bnx2x_add_all_napi(struct bnx2x *bp)
  621. {
  622. int i;
  623. /* Add NAPI objects */
  624. for_each_napi_queue(bp, i)
  625. netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
  626. bnx2x_poll, BNX2X_NAPI_WEIGHT);
  627. }
  628. static inline void bnx2x_del_all_napi(struct bnx2x *bp)
  629. {
  630. int i;
  631. for_each_napi_queue(bp, i)
  632. netif_napi_del(&bnx2x_fp(bp, i, napi));
  633. }
  634. static inline void bnx2x_disable_msi(struct bnx2x *bp)
  635. {
  636. if (bp->flags & USING_MSIX_FLAG) {
  637. pci_disable_msix(bp->pdev);
  638. bp->flags &= ~USING_MSIX_FLAG;
  639. } else if (bp->flags & USING_MSI_FLAG) {
  640. pci_disable_msi(bp->pdev);
  641. bp->flags &= ~USING_MSI_FLAG;
  642. }
  643. }
  644. static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
  645. {
  646. return num_queues ?
  647. min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
  648. min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
  649. }
  650. static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
  651. {
  652. int i, j;
  653. for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
  654. int idx = RX_SGE_CNT * i - 1;
  655. for (j = 0; j < 2; j++) {
  656. SGE_MASK_CLEAR_BIT(fp, idx);
  657. idx--;
  658. }
  659. }
  660. }
  661. static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
  662. {
  663. /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
  664. memset(fp->sge_mask, 0xff,
  665. (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
  666. /* Clear the two last indices in the page to 1:
  667. these are the indices that correspond to the "next" element,
  668. hence will never be indicated and should be removed from
  669. the calculations. */
  670. bnx2x_clear_sge_mask_next_elems(fp);
  671. }
  672. static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
  673. struct bnx2x_fastpath *fp, u16 index)
  674. {
  675. struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
  676. struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
  677. struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
  678. dma_addr_t mapping;
  679. if (unlikely(page == NULL))
  680. return -ENOMEM;
  681. mapping = dma_map_page(&bp->pdev->dev, page, 0,
  682. SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
  683. if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
  684. __free_pages(page, PAGES_PER_SGE_SHIFT);
  685. return -ENOMEM;
  686. }
  687. sw_buf->page = page;
  688. dma_unmap_addr_set(sw_buf, mapping, mapping);
  689. sge->addr_hi = cpu_to_le32(U64_HI(mapping));
  690. sge->addr_lo = cpu_to_le32(U64_LO(mapping));
  691. return 0;
  692. }
  693. static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
  694. struct bnx2x_fastpath *fp, u16 index)
  695. {
  696. struct sk_buff *skb;
  697. struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
  698. struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
  699. dma_addr_t mapping;
  700. skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
  701. if (unlikely(skb == NULL))
  702. return -ENOMEM;
  703. mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_size,
  704. DMA_FROM_DEVICE);
  705. if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
  706. dev_kfree_skb(skb);
  707. return -ENOMEM;
  708. }
  709. rx_buf->skb = skb;
  710. dma_unmap_addr_set(rx_buf, mapping, mapping);
  711. rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
  712. rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
  713. return 0;
  714. }
  715. /* note that we are not allocating a new skb,
  716. * we are just moving one from cons to prod
  717. * we are not creating a new mapping,
  718. * so there is no need to check for dma_mapping_error().
  719. */
  720. static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
  721. u16 cons, u16 prod)
  722. {
  723. struct bnx2x *bp = fp->bp;
  724. struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
  725. struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
  726. struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
  727. struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
  728. dma_sync_single_for_device(&bp->pdev->dev,
  729. dma_unmap_addr(cons_rx_buf, mapping),
  730. RX_COPY_THRESH, DMA_FROM_DEVICE);
  731. prod_rx_buf->skb = cons_rx_buf->skb;
  732. dma_unmap_addr_set(prod_rx_buf, mapping,
  733. dma_unmap_addr(cons_rx_buf, mapping));
  734. *prod_bd = *cons_bd;
  735. }
  736. static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
  737. struct bnx2x_fastpath *fp, int last)
  738. {
  739. int i;
  740. for (i = 0; i < last; i++)
  741. bnx2x_free_rx_sge(bp, fp, i);
  742. }
  743. static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
  744. struct bnx2x_fastpath *fp, int last)
  745. {
  746. int i;
  747. for (i = 0; i < last; i++) {
  748. struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
  749. struct sk_buff *skb = rx_buf->skb;
  750. if (skb == NULL) {
  751. DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
  752. continue;
  753. }
  754. if (fp->tpa_state[i] == BNX2X_TPA_START)
  755. dma_unmap_single(&bp->pdev->dev,
  756. dma_unmap_addr(rx_buf, mapping),
  757. bp->rx_buf_size, DMA_FROM_DEVICE);
  758. dev_kfree_skb(skb);
  759. rx_buf->skb = NULL;
  760. }
  761. }
  762. static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
  763. {
  764. int i, j;
  765. for_each_tx_queue(bp, j) {
  766. struct bnx2x_fastpath *fp = &bp->fp[j];
  767. for (i = 1; i <= NUM_TX_RINGS; i++) {
  768. struct eth_tx_next_bd *tx_next_bd =
  769. &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
  770. tx_next_bd->addr_hi =
  771. cpu_to_le32(U64_HI(fp->tx_desc_mapping +
  772. BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
  773. tx_next_bd->addr_lo =
  774. cpu_to_le32(U64_LO(fp->tx_desc_mapping +
  775. BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
  776. }
  777. SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
  778. fp->tx_db.data.zero_fill1 = 0;
  779. fp->tx_db.data.prod = 0;
  780. fp->tx_pkt_prod = 0;
  781. fp->tx_pkt_cons = 0;
  782. fp->tx_bd_prod = 0;
  783. fp->tx_bd_cons = 0;
  784. fp->tx_pkt = 0;
  785. }
  786. }
  787. static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
  788. {
  789. int i;
  790. for (i = 1; i <= NUM_RX_RINGS; i++) {
  791. struct eth_rx_bd *rx_bd;
  792. rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
  793. rx_bd->addr_hi =
  794. cpu_to_le32(U64_HI(fp->rx_desc_mapping +
  795. BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
  796. rx_bd->addr_lo =
  797. cpu_to_le32(U64_LO(fp->rx_desc_mapping +
  798. BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
  799. }
  800. }
  801. static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
  802. {
  803. int i;
  804. for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
  805. struct eth_rx_sge *sge;
  806. sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
  807. sge->addr_hi =
  808. cpu_to_le32(U64_HI(fp->rx_sge_mapping +
  809. BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
  810. sge->addr_lo =
  811. cpu_to_le32(U64_LO(fp->rx_sge_mapping +
  812. BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
  813. }
  814. }
  815. static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
  816. {
  817. int i;
  818. for (i = 1; i <= NUM_RCQ_RINGS; i++) {
  819. struct eth_rx_cqe_next_page *nextpg;
  820. nextpg = (struct eth_rx_cqe_next_page *)
  821. &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
  822. nextpg->addr_hi =
  823. cpu_to_le32(U64_HI(fp->rx_comp_mapping +
  824. BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
  825. nextpg->addr_lo =
  826. cpu_to_le32(U64_LO(fp->rx_comp_mapping +
  827. BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
  828. }
  829. }
  830. #ifdef BCM_CNIC
  831. static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
  832. {
  833. bnx2x_fcoe(bp, cl_id) = BNX2X_FCOE_ETH_CL_ID +
  834. BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
  835. bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID;
  836. bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
  837. bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
  838. bnx2x_fcoe(bp, bp) = bp;
  839. bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
  840. bnx2x_fcoe(bp, index) = FCOE_IDX;
  841. bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
  842. bnx2x_fcoe(bp, tx_cons_sb) = BNX2X_FCOE_L2_TX_INDEX;
  843. /* qZone id equals to FW (per path) client id */
  844. bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fcoe(bp, cl_id) +
  845. BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
  846. ETH_MAX_RX_CLIENTS_E1H);
  847. /* init shortcut */
  848. bnx2x_fcoe(bp, ustorm_rx_prods_offset) = CHIP_IS_E2(bp) ?
  849. USTORM_RX_PRODS_E2_OFFSET(bnx2x_fcoe(bp, cl_qzone_id)) :
  850. USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), bnx2x_fcoe_fp(bp)->cl_id);
  851. }
  852. #endif
  853. static inline void __storm_memset_struct(struct bnx2x *bp,
  854. u32 addr, size_t size, u32 *data)
  855. {
  856. int i;
  857. for (i = 0; i < size/4; i++)
  858. REG_WR(bp, addr + (i * 4), data[i]);
  859. }
  860. static inline void storm_memset_mac_filters(struct bnx2x *bp,
  861. struct tstorm_eth_mac_filter_config *mac_filters,
  862. u16 abs_fid)
  863. {
  864. size_t size = sizeof(struct tstorm_eth_mac_filter_config);
  865. u32 addr = BAR_TSTRORM_INTMEM +
  866. TSTORM_MAC_FILTER_CONFIG_OFFSET(abs_fid);
  867. __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
  868. }
  869. static inline void storm_memset_cmng(struct bnx2x *bp,
  870. struct cmng_struct_per_port *cmng,
  871. u8 port)
  872. {
  873. size_t size = sizeof(struct cmng_struct_per_port);
  874. u32 addr = BAR_XSTRORM_INTMEM +
  875. XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
  876. __storm_memset_struct(bp, addr, size, (u32 *)cmng);
  877. }
  878. /* HW Lock for shared dual port PHYs */
  879. void bnx2x_acquire_phy_lock(struct bnx2x *bp);
  880. void bnx2x_release_phy_lock(struct bnx2x *bp);
  881. #endif /* BNX2X_CMN_H */