cputable.c 63 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. #include <asm/mmu.h>
  21. struct cpu_spec* cur_cpu_spec = NULL;
  22. EXPORT_SYMBOL(cur_cpu_spec);
  23. /* The platform string corresponding to the real PVR */
  24. const char *powerpc_base_platform;
  25. /* NOTE:
  26. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  27. * the responsibility of the appropriate CPU save/restore functions to
  28. * eventually copy these settings over. Those save/restore aren't yet
  29. * part of the cputable though. That has to be fixed for both ppc32
  30. * and ppc64
  31. */
  32. #ifdef CONFIG_PPC32
  33. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  46. extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec);
  47. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  48. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  49. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  50. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  54. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  55. #endif /* CONFIG_PPC32 */
  56. #ifdef CONFIG_PPC64
  57. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  58. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  59. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  60. extern void __restore_cpu_pa6t(void);
  61. extern void __restore_cpu_ppc970(void);
  62. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  63. extern void __restore_cpu_power7(void);
  64. #endif /* CONFIG_PPC64 */
  65. #if defined(CONFIG_E500)
  66. extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
  67. extern void __restore_cpu_e5500(void);
  68. #endif /* CONFIG_E500 */
  69. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  70. * ones as well...
  71. */
  72. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  73. PPC_FEATURE_HAS_MMU)
  74. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  75. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  76. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  77. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  78. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  79. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  80. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  81. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  82. PPC_FEATURE_TRUE_LE | \
  83. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  84. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  85. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  86. PPC_FEATURE_TRUE_LE | \
  87. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  88. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  89. PPC_FEATURE_TRUE_LE | \
  90. PPC_FEATURE_HAS_ALTIVEC_COMP)
  91. #ifdef CONFIG_PPC_BOOK3E_64
  92. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  93. #else
  94. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  95. PPC_FEATURE_BOOKE)
  96. #endif
  97. static struct cpu_spec __initdata cpu_specs[] = {
  98. #ifdef CONFIG_PPC_BOOK3S_64
  99. { /* Power3 */
  100. .pvr_mask = 0xffff0000,
  101. .pvr_value = 0x00400000,
  102. .cpu_name = "POWER3 (630)",
  103. .cpu_features = CPU_FTRS_POWER3,
  104. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  105. .mmu_features = MMU_FTR_HPTE_TABLE,
  106. .icache_bsize = 128,
  107. .dcache_bsize = 128,
  108. .num_pmcs = 8,
  109. .pmc_type = PPC_PMC_IBM,
  110. .oprofile_cpu_type = "ppc64/power3",
  111. .oprofile_type = PPC_OPROFILE_RS64,
  112. .platform = "power3",
  113. },
  114. { /* Power3+ */
  115. .pvr_mask = 0xffff0000,
  116. .pvr_value = 0x00410000,
  117. .cpu_name = "POWER3 (630+)",
  118. .cpu_features = CPU_FTRS_POWER3,
  119. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  120. .mmu_features = MMU_FTR_HPTE_TABLE,
  121. .icache_bsize = 128,
  122. .dcache_bsize = 128,
  123. .num_pmcs = 8,
  124. .pmc_type = PPC_PMC_IBM,
  125. .oprofile_cpu_type = "ppc64/power3",
  126. .oprofile_type = PPC_OPROFILE_RS64,
  127. .platform = "power3",
  128. },
  129. { /* Northstar */
  130. .pvr_mask = 0xffff0000,
  131. .pvr_value = 0x00330000,
  132. .cpu_name = "RS64-II (northstar)",
  133. .cpu_features = CPU_FTRS_RS64,
  134. .cpu_user_features = COMMON_USER_PPC64,
  135. .mmu_features = MMU_FTR_HPTE_TABLE,
  136. .icache_bsize = 128,
  137. .dcache_bsize = 128,
  138. .num_pmcs = 8,
  139. .pmc_type = PPC_PMC_IBM,
  140. .oprofile_cpu_type = "ppc64/rs64",
  141. .oprofile_type = PPC_OPROFILE_RS64,
  142. .platform = "rs64",
  143. },
  144. { /* Pulsar */
  145. .pvr_mask = 0xffff0000,
  146. .pvr_value = 0x00340000,
  147. .cpu_name = "RS64-III (pulsar)",
  148. .cpu_features = CPU_FTRS_RS64,
  149. .cpu_user_features = COMMON_USER_PPC64,
  150. .mmu_features = MMU_FTR_HPTE_TABLE,
  151. .icache_bsize = 128,
  152. .dcache_bsize = 128,
  153. .num_pmcs = 8,
  154. .pmc_type = PPC_PMC_IBM,
  155. .oprofile_cpu_type = "ppc64/rs64",
  156. .oprofile_type = PPC_OPROFILE_RS64,
  157. .platform = "rs64",
  158. },
  159. { /* I-star */
  160. .pvr_mask = 0xffff0000,
  161. .pvr_value = 0x00360000,
  162. .cpu_name = "RS64-III (icestar)",
  163. .cpu_features = CPU_FTRS_RS64,
  164. .cpu_user_features = COMMON_USER_PPC64,
  165. .mmu_features = MMU_FTR_HPTE_TABLE,
  166. .icache_bsize = 128,
  167. .dcache_bsize = 128,
  168. .num_pmcs = 8,
  169. .pmc_type = PPC_PMC_IBM,
  170. .oprofile_cpu_type = "ppc64/rs64",
  171. .oprofile_type = PPC_OPROFILE_RS64,
  172. .platform = "rs64",
  173. },
  174. { /* S-star */
  175. .pvr_mask = 0xffff0000,
  176. .pvr_value = 0x00370000,
  177. .cpu_name = "RS64-IV (sstar)",
  178. .cpu_features = CPU_FTRS_RS64,
  179. .cpu_user_features = COMMON_USER_PPC64,
  180. .mmu_features = MMU_FTR_HPTE_TABLE,
  181. .icache_bsize = 128,
  182. .dcache_bsize = 128,
  183. .num_pmcs = 8,
  184. .pmc_type = PPC_PMC_IBM,
  185. .oprofile_cpu_type = "ppc64/rs64",
  186. .oprofile_type = PPC_OPROFILE_RS64,
  187. .platform = "rs64",
  188. },
  189. { /* Power4 */
  190. .pvr_mask = 0xffff0000,
  191. .pvr_value = 0x00350000,
  192. .cpu_name = "POWER4 (gp)",
  193. .cpu_features = CPU_FTRS_POWER4,
  194. .cpu_user_features = COMMON_USER_POWER4,
  195. .mmu_features = MMU_FTR_HPTE_TABLE,
  196. .icache_bsize = 128,
  197. .dcache_bsize = 128,
  198. .num_pmcs = 8,
  199. .pmc_type = PPC_PMC_IBM,
  200. .oprofile_cpu_type = "ppc64/power4",
  201. .oprofile_type = PPC_OPROFILE_POWER4,
  202. .platform = "power4",
  203. },
  204. { /* Power4+ */
  205. .pvr_mask = 0xffff0000,
  206. .pvr_value = 0x00380000,
  207. .cpu_name = "POWER4+ (gq)",
  208. .cpu_features = CPU_FTRS_POWER4,
  209. .cpu_user_features = COMMON_USER_POWER4,
  210. .mmu_features = MMU_FTR_HPTE_TABLE,
  211. .icache_bsize = 128,
  212. .dcache_bsize = 128,
  213. .num_pmcs = 8,
  214. .pmc_type = PPC_PMC_IBM,
  215. .oprofile_cpu_type = "ppc64/power4",
  216. .oprofile_type = PPC_OPROFILE_POWER4,
  217. .platform = "power4",
  218. },
  219. { /* PPC970 */
  220. .pvr_mask = 0xffff0000,
  221. .pvr_value = 0x00390000,
  222. .cpu_name = "PPC970",
  223. .cpu_features = CPU_FTRS_PPC970,
  224. .cpu_user_features = COMMON_USER_POWER4 |
  225. PPC_FEATURE_HAS_ALTIVEC_COMP,
  226. .mmu_features = MMU_FTR_HPTE_TABLE,
  227. .icache_bsize = 128,
  228. .dcache_bsize = 128,
  229. .num_pmcs = 8,
  230. .pmc_type = PPC_PMC_IBM,
  231. .cpu_setup = __setup_cpu_ppc970,
  232. .cpu_restore = __restore_cpu_ppc970,
  233. .oprofile_cpu_type = "ppc64/970",
  234. .oprofile_type = PPC_OPROFILE_POWER4,
  235. .platform = "ppc970",
  236. },
  237. { /* PPC970FX */
  238. .pvr_mask = 0xffff0000,
  239. .pvr_value = 0x003c0000,
  240. .cpu_name = "PPC970FX",
  241. .cpu_features = CPU_FTRS_PPC970,
  242. .cpu_user_features = COMMON_USER_POWER4 |
  243. PPC_FEATURE_HAS_ALTIVEC_COMP,
  244. .mmu_features = MMU_FTR_HPTE_TABLE,
  245. .icache_bsize = 128,
  246. .dcache_bsize = 128,
  247. .num_pmcs = 8,
  248. .pmc_type = PPC_PMC_IBM,
  249. .cpu_setup = __setup_cpu_ppc970,
  250. .cpu_restore = __restore_cpu_ppc970,
  251. .oprofile_cpu_type = "ppc64/970",
  252. .oprofile_type = PPC_OPROFILE_POWER4,
  253. .platform = "ppc970",
  254. },
  255. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  256. .pvr_mask = 0xffffffff,
  257. .pvr_value = 0x00440100,
  258. .cpu_name = "PPC970MP",
  259. .cpu_features = CPU_FTRS_PPC970,
  260. .cpu_user_features = COMMON_USER_POWER4 |
  261. PPC_FEATURE_HAS_ALTIVEC_COMP,
  262. .mmu_features = MMU_FTR_HPTE_TABLE,
  263. .icache_bsize = 128,
  264. .dcache_bsize = 128,
  265. .num_pmcs = 8,
  266. .pmc_type = PPC_PMC_IBM,
  267. .cpu_setup = __setup_cpu_ppc970,
  268. .cpu_restore = __restore_cpu_ppc970,
  269. .oprofile_cpu_type = "ppc64/970MP",
  270. .oprofile_type = PPC_OPROFILE_POWER4,
  271. .platform = "ppc970",
  272. },
  273. { /* PPC970MP */
  274. .pvr_mask = 0xffff0000,
  275. .pvr_value = 0x00440000,
  276. .cpu_name = "PPC970MP",
  277. .cpu_features = CPU_FTRS_PPC970,
  278. .cpu_user_features = COMMON_USER_POWER4 |
  279. PPC_FEATURE_HAS_ALTIVEC_COMP,
  280. .mmu_features = MMU_FTR_HPTE_TABLE,
  281. .icache_bsize = 128,
  282. .dcache_bsize = 128,
  283. .num_pmcs = 8,
  284. .pmc_type = PPC_PMC_IBM,
  285. .cpu_setup = __setup_cpu_ppc970MP,
  286. .cpu_restore = __restore_cpu_ppc970,
  287. .oprofile_cpu_type = "ppc64/970MP",
  288. .oprofile_type = PPC_OPROFILE_POWER4,
  289. .platform = "ppc970",
  290. },
  291. { /* PPC970GX */
  292. .pvr_mask = 0xffff0000,
  293. .pvr_value = 0x00450000,
  294. .cpu_name = "PPC970GX",
  295. .cpu_features = CPU_FTRS_PPC970,
  296. .cpu_user_features = COMMON_USER_POWER4 |
  297. PPC_FEATURE_HAS_ALTIVEC_COMP,
  298. .mmu_features = MMU_FTR_HPTE_TABLE,
  299. .icache_bsize = 128,
  300. .dcache_bsize = 128,
  301. .num_pmcs = 8,
  302. .pmc_type = PPC_PMC_IBM,
  303. .cpu_setup = __setup_cpu_ppc970,
  304. .oprofile_cpu_type = "ppc64/970",
  305. .oprofile_type = PPC_OPROFILE_POWER4,
  306. .platform = "ppc970",
  307. },
  308. { /* Power5 GR */
  309. .pvr_mask = 0xffff0000,
  310. .pvr_value = 0x003a0000,
  311. .cpu_name = "POWER5 (gr)",
  312. .cpu_features = CPU_FTRS_POWER5,
  313. .cpu_user_features = COMMON_USER_POWER5,
  314. .mmu_features = MMU_FTR_HPTE_TABLE,
  315. .icache_bsize = 128,
  316. .dcache_bsize = 128,
  317. .num_pmcs = 6,
  318. .pmc_type = PPC_PMC_IBM,
  319. .oprofile_cpu_type = "ppc64/power5",
  320. .oprofile_type = PPC_OPROFILE_POWER4,
  321. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  322. * and above but only works on POWER5 and above
  323. */
  324. .oprofile_mmcra_sihv = MMCRA_SIHV,
  325. .oprofile_mmcra_sipr = MMCRA_SIPR,
  326. .platform = "power5",
  327. },
  328. { /* Power5++ */
  329. .pvr_mask = 0xffffff00,
  330. .pvr_value = 0x003b0300,
  331. .cpu_name = "POWER5+ (gs)",
  332. .cpu_features = CPU_FTRS_POWER5,
  333. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  334. .mmu_features = MMU_FTR_HPTE_TABLE,
  335. .icache_bsize = 128,
  336. .dcache_bsize = 128,
  337. .num_pmcs = 6,
  338. .oprofile_cpu_type = "ppc64/power5++",
  339. .oprofile_type = PPC_OPROFILE_POWER4,
  340. .oprofile_mmcra_sihv = MMCRA_SIHV,
  341. .oprofile_mmcra_sipr = MMCRA_SIPR,
  342. .platform = "power5+",
  343. },
  344. { /* Power5 GS */
  345. .pvr_mask = 0xffff0000,
  346. .pvr_value = 0x003b0000,
  347. .cpu_name = "POWER5+ (gs)",
  348. .cpu_features = CPU_FTRS_POWER5,
  349. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  350. .mmu_features = MMU_FTR_HPTE_TABLE,
  351. .icache_bsize = 128,
  352. .dcache_bsize = 128,
  353. .num_pmcs = 6,
  354. .pmc_type = PPC_PMC_IBM,
  355. .oprofile_cpu_type = "ppc64/power5+",
  356. .oprofile_type = PPC_OPROFILE_POWER4,
  357. .oprofile_mmcra_sihv = MMCRA_SIHV,
  358. .oprofile_mmcra_sipr = MMCRA_SIPR,
  359. .platform = "power5+",
  360. },
  361. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  362. .pvr_mask = 0xffffffff,
  363. .pvr_value = 0x0f000001,
  364. .cpu_name = "POWER5+",
  365. .cpu_features = CPU_FTRS_POWER5,
  366. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  367. .mmu_features = MMU_FTR_HPTE_TABLE,
  368. .icache_bsize = 128,
  369. .dcache_bsize = 128,
  370. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  371. .oprofile_type = PPC_OPROFILE_POWER4,
  372. .platform = "power5+",
  373. },
  374. { /* Power6 */
  375. .pvr_mask = 0xffff0000,
  376. .pvr_value = 0x003e0000,
  377. .cpu_name = "POWER6 (raw)",
  378. .cpu_features = CPU_FTRS_POWER6,
  379. .cpu_user_features = COMMON_USER_POWER6 |
  380. PPC_FEATURE_POWER6_EXT,
  381. .mmu_features = MMU_FTR_HPTE_TABLE,
  382. .icache_bsize = 128,
  383. .dcache_bsize = 128,
  384. .num_pmcs = 6,
  385. .pmc_type = PPC_PMC_IBM,
  386. .oprofile_cpu_type = "ppc64/power6",
  387. .oprofile_type = PPC_OPROFILE_POWER4,
  388. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  389. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  390. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  391. POWER6_MMCRA_OTHER,
  392. .platform = "power6x",
  393. },
  394. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  395. .pvr_mask = 0xffffffff,
  396. .pvr_value = 0x0f000002,
  397. .cpu_name = "POWER6 (architected)",
  398. .cpu_features = CPU_FTRS_POWER6,
  399. .cpu_user_features = COMMON_USER_POWER6,
  400. .mmu_features = MMU_FTR_HPTE_TABLE,
  401. .icache_bsize = 128,
  402. .dcache_bsize = 128,
  403. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  404. .oprofile_type = PPC_OPROFILE_POWER4,
  405. .platform = "power6",
  406. },
  407. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  408. .pvr_mask = 0xffffffff,
  409. .pvr_value = 0x0f000003,
  410. .cpu_name = "POWER7 (architected)",
  411. .cpu_features = CPU_FTRS_POWER7,
  412. .cpu_user_features = COMMON_USER_POWER7,
  413. .mmu_features = MMU_FTR_HPTE_TABLE |
  414. MMU_FTR_TLBIE_206,
  415. .icache_bsize = 128,
  416. .dcache_bsize = 128,
  417. .oprofile_type = PPC_OPROFILE_POWER4,
  418. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  419. .platform = "power7",
  420. },
  421. { /* Power7 */
  422. .pvr_mask = 0xffff0000,
  423. .pvr_value = 0x003f0000,
  424. .cpu_name = "POWER7 (raw)",
  425. .cpu_features = CPU_FTRS_POWER7,
  426. .cpu_user_features = COMMON_USER_POWER7,
  427. .mmu_features = MMU_FTR_HPTE_TABLE |
  428. MMU_FTR_TLBIE_206,
  429. .icache_bsize = 128,
  430. .dcache_bsize = 128,
  431. .num_pmcs = 6,
  432. .pmc_type = PPC_PMC_IBM,
  433. .oprofile_cpu_type = "ppc64/power7",
  434. .oprofile_type = PPC_OPROFILE_POWER4,
  435. .platform = "power7",
  436. },
  437. { /* Power7+ */
  438. .pvr_mask = 0xffff0000,
  439. .pvr_value = 0x004A0000,
  440. .cpu_name = "POWER7+ (raw)",
  441. .cpu_features = CPU_FTRS_POWER7,
  442. .cpu_user_features = COMMON_USER_POWER7,
  443. .mmu_features = MMU_FTR_HPTE_TABLE |
  444. MMU_FTR_TLBIE_206,
  445. .icache_bsize = 128,
  446. .dcache_bsize = 128,
  447. .num_pmcs = 6,
  448. .pmc_type = PPC_PMC_IBM,
  449. .oprofile_cpu_type = "ppc64/power7",
  450. .oprofile_type = PPC_OPROFILE_POWER4,
  451. .platform = "power7+",
  452. },
  453. { /* Cell Broadband Engine */
  454. .pvr_mask = 0xffff0000,
  455. .pvr_value = 0x00700000,
  456. .cpu_name = "Cell Broadband Engine",
  457. .cpu_features = CPU_FTRS_CELL,
  458. .cpu_user_features = COMMON_USER_PPC64 |
  459. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  460. PPC_FEATURE_SMT,
  461. .mmu_features = MMU_FTR_HPTE_TABLE,
  462. .icache_bsize = 128,
  463. .dcache_bsize = 128,
  464. .num_pmcs = 4,
  465. .pmc_type = PPC_PMC_IBM,
  466. .oprofile_cpu_type = "ppc64/cell-be",
  467. .oprofile_type = PPC_OPROFILE_CELL,
  468. .platform = "ppc-cell-be",
  469. },
  470. { /* PA Semi PA6T */
  471. .pvr_mask = 0x7fff0000,
  472. .pvr_value = 0x00900000,
  473. .cpu_name = "PA6T",
  474. .cpu_features = CPU_FTRS_PA6T,
  475. .cpu_user_features = COMMON_USER_PA6T,
  476. .mmu_features = MMU_FTR_HPTE_TABLE,
  477. .icache_bsize = 64,
  478. .dcache_bsize = 64,
  479. .num_pmcs = 6,
  480. .pmc_type = PPC_PMC_PA6T,
  481. .cpu_setup = __setup_cpu_pa6t,
  482. .cpu_restore = __restore_cpu_pa6t,
  483. .oprofile_cpu_type = "ppc64/pa6t",
  484. .oprofile_type = PPC_OPROFILE_PA6T,
  485. .platform = "pa6t",
  486. },
  487. { /* default match */
  488. .pvr_mask = 0x00000000,
  489. .pvr_value = 0x00000000,
  490. .cpu_name = "POWER4 (compatible)",
  491. .cpu_features = CPU_FTRS_COMPATIBLE,
  492. .cpu_user_features = COMMON_USER_PPC64,
  493. .mmu_features = MMU_FTR_HPTE_TABLE,
  494. .icache_bsize = 128,
  495. .dcache_bsize = 128,
  496. .num_pmcs = 6,
  497. .pmc_type = PPC_PMC_IBM,
  498. .platform = "power4",
  499. }
  500. #endif /* CONFIG_PPC_BOOK3S_64 */
  501. #ifdef CONFIG_PPC32
  502. #if CLASSIC_PPC
  503. { /* 601 */
  504. .pvr_mask = 0xffff0000,
  505. .pvr_value = 0x00010000,
  506. .cpu_name = "601",
  507. .cpu_features = CPU_FTRS_PPC601,
  508. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  509. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  510. .mmu_features = MMU_FTR_HPTE_TABLE,
  511. .icache_bsize = 32,
  512. .dcache_bsize = 32,
  513. .machine_check = machine_check_generic,
  514. .platform = "ppc601",
  515. },
  516. { /* 603 */
  517. .pvr_mask = 0xffff0000,
  518. .pvr_value = 0x00030000,
  519. .cpu_name = "603",
  520. .cpu_features = CPU_FTRS_603,
  521. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  522. .mmu_features = 0,
  523. .icache_bsize = 32,
  524. .dcache_bsize = 32,
  525. .cpu_setup = __setup_cpu_603,
  526. .machine_check = machine_check_generic,
  527. .platform = "ppc603",
  528. },
  529. { /* 603e */
  530. .pvr_mask = 0xffff0000,
  531. .pvr_value = 0x00060000,
  532. .cpu_name = "603e",
  533. .cpu_features = CPU_FTRS_603,
  534. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  535. .mmu_features = 0,
  536. .icache_bsize = 32,
  537. .dcache_bsize = 32,
  538. .cpu_setup = __setup_cpu_603,
  539. .machine_check = machine_check_generic,
  540. .platform = "ppc603",
  541. },
  542. { /* 603ev */
  543. .pvr_mask = 0xffff0000,
  544. .pvr_value = 0x00070000,
  545. .cpu_name = "603ev",
  546. .cpu_features = CPU_FTRS_603,
  547. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  548. .mmu_features = 0,
  549. .icache_bsize = 32,
  550. .dcache_bsize = 32,
  551. .cpu_setup = __setup_cpu_603,
  552. .machine_check = machine_check_generic,
  553. .platform = "ppc603",
  554. },
  555. { /* 604 */
  556. .pvr_mask = 0xffff0000,
  557. .pvr_value = 0x00040000,
  558. .cpu_name = "604",
  559. .cpu_features = CPU_FTRS_604,
  560. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  561. .mmu_features = MMU_FTR_HPTE_TABLE,
  562. .icache_bsize = 32,
  563. .dcache_bsize = 32,
  564. .num_pmcs = 2,
  565. .cpu_setup = __setup_cpu_604,
  566. .machine_check = machine_check_generic,
  567. .platform = "ppc604",
  568. },
  569. { /* 604e */
  570. .pvr_mask = 0xfffff000,
  571. .pvr_value = 0x00090000,
  572. .cpu_name = "604e",
  573. .cpu_features = CPU_FTRS_604,
  574. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  575. .mmu_features = MMU_FTR_HPTE_TABLE,
  576. .icache_bsize = 32,
  577. .dcache_bsize = 32,
  578. .num_pmcs = 4,
  579. .cpu_setup = __setup_cpu_604,
  580. .machine_check = machine_check_generic,
  581. .platform = "ppc604",
  582. },
  583. { /* 604r */
  584. .pvr_mask = 0xffff0000,
  585. .pvr_value = 0x00090000,
  586. .cpu_name = "604r",
  587. .cpu_features = CPU_FTRS_604,
  588. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  589. .mmu_features = MMU_FTR_HPTE_TABLE,
  590. .icache_bsize = 32,
  591. .dcache_bsize = 32,
  592. .num_pmcs = 4,
  593. .cpu_setup = __setup_cpu_604,
  594. .machine_check = machine_check_generic,
  595. .platform = "ppc604",
  596. },
  597. { /* 604ev */
  598. .pvr_mask = 0xffff0000,
  599. .pvr_value = 0x000a0000,
  600. .cpu_name = "604ev",
  601. .cpu_features = CPU_FTRS_604,
  602. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  603. .mmu_features = MMU_FTR_HPTE_TABLE,
  604. .icache_bsize = 32,
  605. .dcache_bsize = 32,
  606. .num_pmcs = 4,
  607. .cpu_setup = __setup_cpu_604,
  608. .machine_check = machine_check_generic,
  609. .platform = "ppc604",
  610. },
  611. { /* 740/750 (0x4202, don't support TAU ?) */
  612. .pvr_mask = 0xffffffff,
  613. .pvr_value = 0x00084202,
  614. .cpu_name = "740/750",
  615. .cpu_features = CPU_FTRS_740_NOTAU,
  616. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  617. .mmu_features = MMU_FTR_HPTE_TABLE,
  618. .icache_bsize = 32,
  619. .dcache_bsize = 32,
  620. .num_pmcs = 4,
  621. .cpu_setup = __setup_cpu_750,
  622. .machine_check = machine_check_generic,
  623. .platform = "ppc750",
  624. },
  625. { /* 750CX (80100 and 8010x?) */
  626. .pvr_mask = 0xfffffff0,
  627. .pvr_value = 0x00080100,
  628. .cpu_name = "750CX",
  629. .cpu_features = CPU_FTRS_750,
  630. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  631. .mmu_features = MMU_FTR_HPTE_TABLE,
  632. .icache_bsize = 32,
  633. .dcache_bsize = 32,
  634. .num_pmcs = 4,
  635. .cpu_setup = __setup_cpu_750cx,
  636. .machine_check = machine_check_generic,
  637. .platform = "ppc750",
  638. },
  639. { /* 750CX (82201 and 82202) */
  640. .pvr_mask = 0xfffffff0,
  641. .pvr_value = 0x00082200,
  642. .cpu_name = "750CX",
  643. .cpu_features = CPU_FTRS_750,
  644. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  645. .mmu_features = MMU_FTR_HPTE_TABLE,
  646. .icache_bsize = 32,
  647. .dcache_bsize = 32,
  648. .num_pmcs = 4,
  649. .pmc_type = PPC_PMC_IBM,
  650. .cpu_setup = __setup_cpu_750cx,
  651. .machine_check = machine_check_generic,
  652. .platform = "ppc750",
  653. },
  654. { /* 750CXe (82214) */
  655. .pvr_mask = 0xfffffff0,
  656. .pvr_value = 0x00082210,
  657. .cpu_name = "750CXe",
  658. .cpu_features = CPU_FTRS_750,
  659. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  660. .mmu_features = MMU_FTR_HPTE_TABLE,
  661. .icache_bsize = 32,
  662. .dcache_bsize = 32,
  663. .num_pmcs = 4,
  664. .pmc_type = PPC_PMC_IBM,
  665. .cpu_setup = __setup_cpu_750cx,
  666. .machine_check = machine_check_generic,
  667. .platform = "ppc750",
  668. },
  669. { /* 750CXe "Gekko" (83214) */
  670. .pvr_mask = 0xffffffff,
  671. .pvr_value = 0x00083214,
  672. .cpu_name = "750CXe",
  673. .cpu_features = CPU_FTRS_750,
  674. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  675. .mmu_features = MMU_FTR_HPTE_TABLE,
  676. .icache_bsize = 32,
  677. .dcache_bsize = 32,
  678. .num_pmcs = 4,
  679. .pmc_type = PPC_PMC_IBM,
  680. .cpu_setup = __setup_cpu_750cx,
  681. .machine_check = machine_check_generic,
  682. .platform = "ppc750",
  683. },
  684. { /* 750CL (and "Broadway") */
  685. .pvr_mask = 0xfffff0e0,
  686. .pvr_value = 0x00087000,
  687. .cpu_name = "750CL",
  688. .cpu_features = CPU_FTRS_750CL,
  689. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  690. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  691. .icache_bsize = 32,
  692. .dcache_bsize = 32,
  693. .num_pmcs = 4,
  694. .pmc_type = PPC_PMC_IBM,
  695. .cpu_setup = __setup_cpu_750,
  696. .machine_check = machine_check_generic,
  697. .platform = "ppc750",
  698. .oprofile_cpu_type = "ppc/750",
  699. .oprofile_type = PPC_OPROFILE_G4,
  700. },
  701. { /* 745/755 */
  702. .pvr_mask = 0xfffff000,
  703. .pvr_value = 0x00083000,
  704. .cpu_name = "745/755",
  705. .cpu_features = CPU_FTRS_750,
  706. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  707. .mmu_features = MMU_FTR_HPTE_TABLE,
  708. .icache_bsize = 32,
  709. .dcache_bsize = 32,
  710. .num_pmcs = 4,
  711. .pmc_type = PPC_PMC_IBM,
  712. .cpu_setup = __setup_cpu_750,
  713. .machine_check = machine_check_generic,
  714. .platform = "ppc750",
  715. },
  716. { /* 750FX rev 1.x */
  717. .pvr_mask = 0xffffff00,
  718. .pvr_value = 0x70000100,
  719. .cpu_name = "750FX",
  720. .cpu_features = CPU_FTRS_750FX1,
  721. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  722. .mmu_features = MMU_FTR_HPTE_TABLE,
  723. .icache_bsize = 32,
  724. .dcache_bsize = 32,
  725. .num_pmcs = 4,
  726. .pmc_type = PPC_PMC_IBM,
  727. .cpu_setup = __setup_cpu_750,
  728. .machine_check = machine_check_generic,
  729. .platform = "ppc750",
  730. .oprofile_cpu_type = "ppc/750",
  731. .oprofile_type = PPC_OPROFILE_G4,
  732. },
  733. { /* 750FX rev 2.0 must disable HID0[DPM] */
  734. .pvr_mask = 0xffffffff,
  735. .pvr_value = 0x70000200,
  736. .cpu_name = "750FX",
  737. .cpu_features = CPU_FTRS_750FX2,
  738. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  739. .mmu_features = MMU_FTR_HPTE_TABLE,
  740. .icache_bsize = 32,
  741. .dcache_bsize = 32,
  742. .num_pmcs = 4,
  743. .pmc_type = PPC_PMC_IBM,
  744. .cpu_setup = __setup_cpu_750,
  745. .machine_check = machine_check_generic,
  746. .platform = "ppc750",
  747. .oprofile_cpu_type = "ppc/750",
  748. .oprofile_type = PPC_OPROFILE_G4,
  749. },
  750. { /* 750FX (All revs except 2.0) */
  751. .pvr_mask = 0xffff0000,
  752. .pvr_value = 0x70000000,
  753. .cpu_name = "750FX",
  754. .cpu_features = CPU_FTRS_750FX,
  755. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  756. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  757. .icache_bsize = 32,
  758. .dcache_bsize = 32,
  759. .num_pmcs = 4,
  760. .pmc_type = PPC_PMC_IBM,
  761. .cpu_setup = __setup_cpu_750fx,
  762. .machine_check = machine_check_generic,
  763. .platform = "ppc750",
  764. .oprofile_cpu_type = "ppc/750",
  765. .oprofile_type = PPC_OPROFILE_G4,
  766. },
  767. { /* 750GX */
  768. .pvr_mask = 0xffff0000,
  769. .pvr_value = 0x70020000,
  770. .cpu_name = "750GX",
  771. .cpu_features = CPU_FTRS_750GX,
  772. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  773. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  774. .icache_bsize = 32,
  775. .dcache_bsize = 32,
  776. .num_pmcs = 4,
  777. .pmc_type = PPC_PMC_IBM,
  778. .cpu_setup = __setup_cpu_750fx,
  779. .machine_check = machine_check_generic,
  780. .platform = "ppc750",
  781. .oprofile_cpu_type = "ppc/750",
  782. .oprofile_type = PPC_OPROFILE_G4,
  783. },
  784. { /* 740/750 (L2CR bit need fixup for 740) */
  785. .pvr_mask = 0xffff0000,
  786. .pvr_value = 0x00080000,
  787. .cpu_name = "740/750",
  788. .cpu_features = CPU_FTRS_740,
  789. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  790. .mmu_features = MMU_FTR_HPTE_TABLE,
  791. .icache_bsize = 32,
  792. .dcache_bsize = 32,
  793. .num_pmcs = 4,
  794. .pmc_type = PPC_PMC_IBM,
  795. .cpu_setup = __setup_cpu_750,
  796. .machine_check = machine_check_generic,
  797. .platform = "ppc750",
  798. },
  799. { /* 7400 rev 1.1 ? (no TAU) */
  800. .pvr_mask = 0xffffffff,
  801. .pvr_value = 0x000c1101,
  802. .cpu_name = "7400 (1.1)",
  803. .cpu_features = CPU_FTRS_7400_NOTAU,
  804. .cpu_user_features = COMMON_USER |
  805. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  806. .mmu_features = MMU_FTR_HPTE_TABLE,
  807. .icache_bsize = 32,
  808. .dcache_bsize = 32,
  809. .num_pmcs = 4,
  810. .pmc_type = PPC_PMC_G4,
  811. .cpu_setup = __setup_cpu_7400,
  812. .machine_check = machine_check_generic,
  813. .platform = "ppc7400",
  814. },
  815. { /* 7400 */
  816. .pvr_mask = 0xffff0000,
  817. .pvr_value = 0x000c0000,
  818. .cpu_name = "7400",
  819. .cpu_features = CPU_FTRS_7400,
  820. .cpu_user_features = COMMON_USER |
  821. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  822. .mmu_features = MMU_FTR_HPTE_TABLE,
  823. .icache_bsize = 32,
  824. .dcache_bsize = 32,
  825. .num_pmcs = 4,
  826. .pmc_type = PPC_PMC_G4,
  827. .cpu_setup = __setup_cpu_7400,
  828. .machine_check = machine_check_generic,
  829. .platform = "ppc7400",
  830. },
  831. { /* 7410 */
  832. .pvr_mask = 0xffff0000,
  833. .pvr_value = 0x800c0000,
  834. .cpu_name = "7410",
  835. .cpu_features = CPU_FTRS_7400,
  836. .cpu_user_features = COMMON_USER |
  837. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  838. .mmu_features = MMU_FTR_HPTE_TABLE,
  839. .icache_bsize = 32,
  840. .dcache_bsize = 32,
  841. .num_pmcs = 4,
  842. .pmc_type = PPC_PMC_G4,
  843. .cpu_setup = __setup_cpu_7410,
  844. .machine_check = machine_check_generic,
  845. .platform = "ppc7400",
  846. },
  847. { /* 7450 2.0 - no doze/nap */
  848. .pvr_mask = 0xffffffff,
  849. .pvr_value = 0x80000200,
  850. .cpu_name = "7450",
  851. .cpu_features = CPU_FTRS_7450_20,
  852. .cpu_user_features = COMMON_USER |
  853. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  854. .mmu_features = MMU_FTR_HPTE_TABLE,
  855. .icache_bsize = 32,
  856. .dcache_bsize = 32,
  857. .num_pmcs = 6,
  858. .pmc_type = PPC_PMC_G4,
  859. .cpu_setup = __setup_cpu_745x,
  860. .oprofile_cpu_type = "ppc/7450",
  861. .oprofile_type = PPC_OPROFILE_G4,
  862. .machine_check = machine_check_generic,
  863. .platform = "ppc7450",
  864. },
  865. { /* 7450 2.1 */
  866. .pvr_mask = 0xffffffff,
  867. .pvr_value = 0x80000201,
  868. .cpu_name = "7450",
  869. .cpu_features = CPU_FTRS_7450_21,
  870. .cpu_user_features = COMMON_USER |
  871. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  872. .mmu_features = MMU_FTR_HPTE_TABLE,
  873. .icache_bsize = 32,
  874. .dcache_bsize = 32,
  875. .num_pmcs = 6,
  876. .pmc_type = PPC_PMC_G4,
  877. .cpu_setup = __setup_cpu_745x,
  878. .oprofile_cpu_type = "ppc/7450",
  879. .oprofile_type = PPC_OPROFILE_G4,
  880. .machine_check = machine_check_generic,
  881. .platform = "ppc7450",
  882. },
  883. { /* 7450 2.3 and newer */
  884. .pvr_mask = 0xffff0000,
  885. .pvr_value = 0x80000000,
  886. .cpu_name = "7450",
  887. .cpu_features = CPU_FTRS_7450_23,
  888. .cpu_user_features = COMMON_USER |
  889. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  890. .mmu_features = MMU_FTR_HPTE_TABLE,
  891. .icache_bsize = 32,
  892. .dcache_bsize = 32,
  893. .num_pmcs = 6,
  894. .pmc_type = PPC_PMC_G4,
  895. .cpu_setup = __setup_cpu_745x,
  896. .oprofile_cpu_type = "ppc/7450",
  897. .oprofile_type = PPC_OPROFILE_G4,
  898. .machine_check = machine_check_generic,
  899. .platform = "ppc7450",
  900. },
  901. { /* 7455 rev 1.x */
  902. .pvr_mask = 0xffffff00,
  903. .pvr_value = 0x80010100,
  904. .cpu_name = "7455",
  905. .cpu_features = CPU_FTRS_7455_1,
  906. .cpu_user_features = COMMON_USER |
  907. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  908. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  909. .icache_bsize = 32,
  910. .dcache_bsize = 32,
  911. .num_pmcs = 6,
  912. .pmc_type = PPC_PMC_G4,
  913. .cpu_setup = __setup_cpu_745x,
  914. .oprofile_cpu_type = "ppc/7450",
  915. .oprofile_type = PPC_OPROFILE_G4,
  916. .machine_check = machine_check_generic,
  917. .platform = "ppc7450",
  918. },
  919. { /* 7455 rev 2.0 */
  920. .pvr_mask = 0xffffffff,
  921. .pvr_value = 0x80010200,
  922. .cpu_name = "7455",
  923. .cpu_features = CPU_FTRS_7455_20,
  924. .cpu_user_features = COMMON_USER |
  925. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  926. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  927. .icache_bsize = 32,
  928. .dcache_bsize = 32,
  929. .num_pmcs = 6,
  930. .pmc_type = PPC_PMC_G4,
  931. .cpu_setup = __setup_cpu_745x,
  932. .oprofile_cpu_type = "ppc/7450",
  933. .oprofile_type = PPC_OPROFILE_G4,
  934. .machine_check = machine_check_generic,
  935. .platform = "ppc7450",
  936. },
  937. { /* 7455 others */
  938. .pvr_mask = 0xffff0000,
  939. .pvr_value = 0x80010000,
  940. .cpu_name = "7455",
  941. .cpu_features = CPU_FTRS_7455,
  942. .cpu_user_features = COMMON_USER |
  943. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  944. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  945. .icache_bsize = 32,
  946. .dcache_bsize = 32,
  947. .num_pmcs = 6,
  948. .pmc_type = PPC_PMC_G4,
  949. .cpu_setup = __setup_cpu_745x,
  950. .oprofile_cpu_type = "ppc/7450",
  951. .oprofile_type = PPC_OPROFILE_G4,
  952. .machine_check = machine_check_generic,
  953. .platform = "ppc7450",
  954. },
  955. { /* 7447/7457 Rev 1.0 */
  956. .pvr_mask = 0xffffffff,
  957. .pvr_value = 0x80020100,
  958. .cpu_name = "7447/7457",
  959. .cpu_features = CPU_FTRS_7447_10,
  960. .cpu_user_features = COMMON_USER |
  961. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  962. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  963. .icache_bsize = 32,
  964. .dcache_bsize = 32,
  965. .num_pmcs = 6,
  966. .pmc_type = PPC_PMC_G4,
  967. .cpu_setup = __setup_cpu_745x,
  968. .oprofile_cpu_type = "ppc/7450",
  969. .oprofile_type = PPC_OPROFILE_G4,
  970. .machine_check = machine_check_generic,
  971. .platform = "ppc7450",
  972. },
  973. { /* 7447/7457 Rev 1.1 */
  974. .pvr_mask = 0xffffffff,
  975. .pvr_value = 0x80020101,
  976. .cpu_name = "7447/7457",
  977. .cpu_features = CPU_FTRS_7447_10,
  978. .cpu_user_features = COMMON_USER |
  979. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  980. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  981. .icache_bsize = 32,
  982. .dcache_bsize = 32,
  983. .num_pmcs = 6,
  984. .pmc_type = PPC_PMC_G4,
  985. .cpu_setup = __setup_cpu_745x,
  986. .oprofile_cpu_type = "ppc/7450",
  987. .oprofile_type = PPC_OPROFILE_G4,
  988. .machine_check = machine_check_generic,
  989. .platform = "ppc7450",
  990. },
  991. { /* 7447/7457 Rev 1.2 and later */
  992. .pvr_mask = 0xffff0000,
  993. .pvr_value = 0x80020000,
  994. .cpu_name = "7447/7457",
  995. .cpu_features = CPU_FTRS_7447,
  996. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  997. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  998. .icache_bsize = 32,
  999. .dcache_bsize = 32,
  1000. .num_pmcs = 6,
  1001. .pmc_type = PPC_PMC_G4,
  1002. .cpu_setup = __setup_cpu_745x,
  1003. .oprofile_cpu_type = "ppc/7450",
  1004. .oprofile_type = PPC_OPROFILE_G4,
  1005. .machine_check = machine_check_generic,
  1006. .platform = "ppc7450",
  1007. },
  1008. { /* 7447A */
  1009. .pvr_mask = 0xffff0000,
  1010. .pvr_value = 0x80030000,
  1011. .cpu_name = "7447A",
  1012. .cpu_features = CPU_FTRS_7447A,
  1013. .cpu_user_features = COMMON_USER |
  1014. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1015. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1016. .icache_bsize = 32,
  1017. .dcache_bsize = 32,
  1018. .num_pmcs = 6,
  1019. .pmc_type = PPC_PMC_G4,
  1020. .cpu_setup = __setup_cpu_745x,
  1021. .oprofile_cpu_type = "ppc/7450",
  1022. .oprofile_type = PPC_OPROFILE_G4,
  1023. .machine_check = machine_check_generic,
  1024. .platform = "ppc7450",
  1025. },
  1026. { /* 7448 */
  1027. .pvr_mask = 0xffff0000,
  1028. .pvr_value = 0x80040000,
  1029. .cpu_name = "7448",
  1030. .cpu_features = CPU_FTRS_7448,
  1031. .cpu_user_features = COMMON_USER |
  1032. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1033. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1034. .icache_bsize = 32,
  1035. .dcache_bsize = 32,
  1036. .num_pmcs = 6,
  1037. .pmc_type = PPC_PMC_G4,
  1038. .cpu_setup = __setup_cpu_745x,
  1039. .oprofile_cpu_type = "ppc/7450",
  1040. .oprofile_type = PPC_OPROFILE_G4,
  1041. .machine_check = machine_check_generic,
  1042. .platform = "ppc7450",
  1043. },
  1044. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1045. .pvr_mask = 0x7fff0000,
  1046. .pvr_value = 0x00810000,
  1047. .cpu_name = "82xx",
  1048. .cpu_features = CPU_FTRS_82XX,
  1049. .cpu_user_features = COMMON_USER,
  1050. .mmu_features = 0,
  1051. .icache_bsize = 32,
  1052. .dcache_bsize = 32,
  1053. .cpu_setup = __setup_cpu_603,
  1054. .machine_check = machine_check_generic,
  1055. .platform = "ppc603",
  1056. },
  1057. { /* All G2_LE (603e core, plus some) have the same pvr */
  1058. .pvr_mask = 0x7fff0000,
  1059. .pvr_value = 0x00820000,
  1060. .cpu_name = "G2_LE",
  1061. .cpu_features = CPU_FTRS_G2_LE,
  1062. .cpu_user_features = COMMON_USER,
  1063. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1064. .icache_bsize = 32,
  1065. .dcache_bsize = 32,
  1066. .cpu_setup = __setup_cpu_603,
  1067. .machine_check = machine_check_generic,
  1068. .platform = "ppc603",
  1069. },
  1070. { /* e300c1 (a 603e core, plus some) on 83xx */
  1071. .pvr_mask = 0x7fff0000,
  1072. .pvr_value = 0x00830000,
  1073. .cpu_name = "e300c1",
  1074. .cpu_features = CPU_FTRS_E300,
  1075. .cpu_user_features = COMMON_USER,
  1076. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1077. .icache_bsize = 32,
  1078. .dcache_bsize = 32,
  1079. .cpu_setup = __setup_cpu_603,
  1080. .machine_check = machine_check_generic,
  1081. .platform = "ppc603",
  1082. },
  1083. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1084. .pvr_mask = 0x7fff0000,
  1085. .pvr_value = 0x00840000,
  1086. .cpu_name = "e300c2",
  1087. .cpu_features = CPU_FTRS_E300C2,
  1088. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1089. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1090. MMU_FTR_NEED_DTLB_SW_LRU,
  1091. .icache_bsize = 32,
  1092. .dcache_bsize = 32,
  1093. .cpu_setup = __setup_cpu_603,
  1094. .machine_check = machine_check_generic,
  1095. .platform = "ppc603",
  1096. },
  1097. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1098. .pvr_mask = 0x7fff0000,
  1099. .pvr_value = 0x00850000,
  1100. .cpu_name = "e300c3",
  1101. .cpu_features = CPU_FTRS_E300,
  1102. .cpu_user_features = COMMON_USER,
  1103. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1104. MMU_FTR_NEED_DTLB_SW_LRU,
  1105. .icache_bsize = 32,
  1106. .dcache_bsize = 32,
  1107. .cpu_setup = __setup_cpu_603,
  1108. .num_pmcs = 4,
  1109. .oprofile_cpu_type = "ppc/e300",
  1110. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1111. .platform = "ppc603",
  1112. },
  1113. { /* e300c4 (e300c1, plus one IU) */
  1114. .pvr_mask = 0x7fff0000,
  1115. .pvr_value = 0x00860000,
  1116. .cpu_name = "e300c4",
  1117. .cpu_features = CPU_FTRS_E300,
  1118. .cpu_user_features = COMMON_USER,
  1119. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1120. MMU_FTR_NEED_DTLB_SW_LRU,
  1121. .icache_bsize = 32,
  1122. .dcache_bsize = 32,
  1123. .cpu_setup = __setup_cpu_603,
  1124. .machine_check = machine_check_generic,
  1125. .num_pmcs = 4,
  1126. .oprofile_cpu_type = "ppc/e300",
  1127. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1128. .platform = "ppc603",
  1129. },
  1130. { /* default match, we assume split I/D cache & TB (non-601)... */
  1131. .pvr_mask = 0x00000000,
  1132. .pvr_value = 0x00000000,
  1133. .cpu_name = "(generic PPC)",
  1134. .cpu_features = CPU_FTRS_CLASSIC32,
  1135. .cpu_user_features = COMMON_USER,
  1136. .mmu_features = MMU_FTR_HPTE_TABLE,
  1137. .icache_bsize = 32,
  1138. .dcache_bsize = 32,
  1139. .machine_check = machine_check_generic,
  1140. .platform = "ppc603",
  1141. },
  1142. #endif /* CLASSIC_PPC */
  1143. #ifdef CONFIG_8xx
  1144. { /* 8xx */
  1145. .pvr_mask = 0xffff0000,
  1146. .pvr_value = 0x00500000,
  1147. .cpu_name = "8xx",
  1148. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1149. * if the 8xx code is there.... */
  1150. .cpu_features = CPU_FTRS_8XX,
  1151. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1152. .mmu_features = MMU_FTR_TYPE_8xx,
  1153. .icache_bsize = 16,
  1154. .dcache_bsize = 16,
  1155. .platform = "ppc823",
  1156. },
  1157. #endif /* CONFIG_8xx */
  1158. #ifdef CONFIG_40x
  1159. { /* 403GC */
  1160. .pvr_mask = 0xffffff00,
  1161. .pvr_value = 0x00200200,
  1162. .cpu_name = "403GC",
  1163. .cpu_features = CPU_FTRS_40X,
  1164. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1165. .mmu_features = MMU_FTR_TYPE_40x,
  1166. .icache_bsize = 16,
  1167. .dcache_bsize = 16,
  1168. .machine_check = machine_check_4xx,
  1169. .platform = "ppc403",
  1170. },
  1171. { /* 403GCX */
  1172. .pvr_mask = 0xffffff00,
  1173. .pvr_value = 0x00201400,
  1174. .cpu_name = "403GCX",
  1175. .cpu_features = CPU_FTRS_40X,
  1176. .cpu_user_features = PPC_FEATURE_32 |
  1177. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1178. .mmu_features = MMU_FTR_TYPE_40x,
  1179. .icache_bsize = 16,
  1180. .dcache_bsize = 16,
  1181. .machine_check = machine_check_4xx,
  1182. .platform = "ppc403",
  1183. },
  1184. { /* 403G ?? */
  1185. .pvr_mask = 0xffff0000,
  1186. .pvr_value = 0x00200000,
  1187. .cpu_name = "403G ??",
  1188. .cpu_features = CPU_FTRS_40X,
  1189. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1190. .mmu_features = MMU_FTR_TYPE_40x,
  1191. .icache_bsize = 16,
  1192. .dcache_bsize = 16,
  1193. .machine_check = machine_check_4xx,
  1194. .platform = "ppc403",
  1195. },
  1196. { /* 405GP */
  1197. .pvr_mask = 0xffff0000,
  1198. .pvr_value = 0x40110000,
  1199. .cpu_name = "405GP",
  1200. .cpu_features = CPU_FTRS_40X,
  1201. .cpu_user_features = PPC_FEATURE_32 |
  1202. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1203. .mmu_features = MMU_FTR_TYPE_40x,
  1204. .icache_bsize = 32,
  1205. .dcache_bsize = 32,
  1206. .machine_check = machine_check_4xx,
  1207. .platform = "ppc405",
  1208. },
  1209. { /* STB 03xxx */
  1210. .pvr_mask = 0xffff0000,
  1211. .pvr_value = 0x40130000,
  1212. .cpu_name = "STB03xxx",
  1213. .cpu_features = CPU_FTRS_40X,
  1214. .cpu_user_features = PPC_FEATURE_32 |
  1215. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1216. .mmu_features = MMU_FTR_TYPE_40x,
  1217. .icache_bsize = 32,
  1218. .dcache_bsize = 32,
  1219. .machine_check = machine_check_4xx,
  1220. .platform = "ppc405",
  1221. },
  1222. { /* STB 04xxx */
  1223. .pvr_mask = 0xffff0000,
  1224. .pvr_value = 0x41810000,
  1225. .cpu_name = "STB04xxx",
  1226. .cpu_features = CPU_FTRS_40X,
  1227. .cpu_user_features = PPC_FEATURE_32 |
  1228. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1229. .mmu_features = MMU_FTR_TYPE_40x,
  1230. .icache_bsize = 32,
  1231. .dcache_bsize = 32,
  1232. .machine_check = machine_check_4xx,
  1233. .platform = "ppc405",
  1234. },
  1235. { /* NP405L */
  1236. .pvr_mask = 0xffff0000,
  1237. .pvr_value = 0x41610000,
  1238. .cpu_name = "NP405L",
  1239. .cpu_features = CPU_FTRS_40X,
  1240. .cpu_user_features = PPC_FEATURE_32 |
  1241. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1242. .mmu_features = MMU_FTR_TYPE_40x,
  1243. .icache_bsize = 32,
  1244. .dcache_bsize = 32,
  1245. .machine_check = machine_check_4xx,
  1246. .platform = "ppc405",
  1247. },
  1248. { /* NP4GS3 */
  1249. .pvr_mask = 0xffff0000,
  1250. .pvr_value = 0x40B10000,
  1251. .cpu_name = "NP4GS3",
  1252. .cpu_features = CPU_FTRS_40X,
  1253. .cpu_user_features = PPC_FEATURE_32 |
  1254. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1255. .mmu_features = MMU_FTR_TYPE_40x,
  1256. .icache_bsize = 32,
  1257. .dcache_bsize = 32,
  1258. .machine_check = machine_check_4xx,
  1259. .platform = "ppc405",
  1260. },
  1261. { /* NP405H */
  1262. .pvr_mask = 0xffff0000,
  1263. .pvr_value = 0x41410000,
  1264. .cpu_name = "NP405H",
  1265. .cpu_features = CPU_FTRS_40X,
  1266. .cpu_user_features = PPC_FEATURE_32 |
  1267. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1268. .mmu_features = MMU_FTR_TYPE_40x,
  1269. .icache_bsize = 32,
  1270. .dcache_bsize = 32,
  1271. .machine_check = machine_check_4xx,
  1272. .platform = "ppc405",
  1273. },
  1274. { /* 405GPr */
  1275. .pvr_mask = 0xffff0000,
  1276. .pvr_value = 0x50910000,
  1277. .cpu_name = "405GPr",
  1278. .cpu_features = CPU_FTRS_40X,
  1279. .cpu_user_features = PPC_FEATURE_32 |
  1280. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1281. .mmu_features = MMU_FTR_TYPE_40x,
  1282. .icache_bsize = 32,
  1283. .dcache_bsize = 32,
  1284. .machine_check = machine_check_4xx,
  1285. .platform = "ppc405",
  1286. },
  1287. { /* STBx25xx */
  1288. .pvr_mask = 0xffff0000,
  1289. .pvr_value = 0x51510000,
  1290. .cpu_name = "STBx25xx",
  1291. .cpu_features = CPU_FTRS_40X,
  1292. .cpu_user_features = PPC_FEATURE_32 |
  1293. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1294. .mmu_features = MMU_FTR_TYPE_40x,
  1295. .icache_bsize = 32,
  1296. .dcache_bsize = 32,
  1297. .machine_check = machine_check_4xx,
  1298. .platform = "ppc405",
  1299. },
  1300. { /* 405LP */
  1301. .pvr_mask = 0xffff0000,
  1302. .pvr_value = 0x41F10000,
  1303. .cpu_name = "405LP",
  1304. .cpu_features = CPU_FTRS_40X,
  1305. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1306. .mmu_features = MMU_FTR_TYPE_40x,
  1307. .icache_bsize = 32,
  1308. .dcache_bsize = 32,
  1309. .machine_check = machine_check_4xx,
  1310. .platform = "ppc405",
  1311. },
  1312. { /* Xilinx Virtex-II Pro */
  1313. .pvr_mask = 0xfffff000,
  1314. .pvr_value = 0x20010000,
  1315. .cpu_name = "Virtex-II Pro",
  1316. .cpu_features = CPU_FTRS_40X,
  1317. .cpu_user_features = PPC_FEATURE_32 |
  1318. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1319. .mmu_features = MMU_FTR_TYPE_40x,
  1320. .icache_bsize = 32,
  1321. .dcache_bsize = 32,
  1322. .machine_check = machine_check_4xx,
  1323. .platform = "ppc405",
  1324. },
  1325. { /* Xilinx Virtex-4 FX */
  1326. .pvr_mask = 0xfffff000,
  1327. .pvr_value = 0x20011000,
  1328. .cpu_name = "Virtex-4 FX",
  1329. .cpu_features = CPU_FTRS_40X,
  1330. .cpu_user_features = PPC_FEATURE_32 |
  1331. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1332. .mmu_features = MMU_FTR_TYPE_40x,
  1333. .icache_bsize = 32,
  1334. .dcache_bsize = 32,
  1335. .machine_check = machine_check_4xx,
  1336. .platform = "ppc405",
  1337. },
  1338. { /* 405EP */
  1339. .pvr_mask = 0xffff0000,
  1340. .pvr_value = 0x51210000,
  1341. .cpu_name = "405EP",
  1342. .cpu_features = CPU_FTRS_40X,
  1343. .cpu_user_features = PPC_FEATURE_32 |
  1344. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1345. .mmu_features = MMU_FTR_TYPE_40x,
  1346. .icache_bsize = 32,
  1347. .dcache_bsize = 32,
  1348. .machine_check = machine_check_4xx,
  1349. .platform = "ppc405",
  1350. },
  1351. { /* 405EX Rev. A/B with Security */
  1352. .pvr_mask = 0xffff000f,
  1353. .pvr_value = 0x12910007,
  1354. .cpu_name = "405EX Rev. A/B",
  1355. .cpu_features = CPU_FTRS_40X,
  1356. .cpu_user_features = PPC_FEATURE_32 |
  1357. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1358. .mmu_features = MMU_FTR_TYPE_40x,
  1359. .icache_bsize = 32,
  1360. .dcache_bsize = 32,
  1361. .machine_check = machine_check_4xx,
  1362. .platform = "ppc405",
  1363. },
  1364. { /* 405EX Rev. C without Security */
  1365. .pvr_mask = 0xffff000f,
  1366. .pvr_value = 0x1291000d,
  1367. .cpu_name = "405EX Rev. C",
  1368. .cpu_features = CPU_FTRS_40X,
  1369. .cpu_user_features = PPC_FEATURE_32 |
  1370. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1371. .mmu_features = MMU_FTR_TYPE_40x,
  1372. .icache_bsize = 32,
  1373. .dcache_bsize = 32,
  1374. .machine_check = machine_check_4xx,
  1375. .platform = "ppc405",
  1376. },
  1377. { /* 405EX Rev. C with Security */
  1378. .pvr_mask = 0xffff000f,
  1379. .pvr_value = 0x1291000f,
  1380. .cpu_name = "405EX Rev. C",
  1381. .cpu_features = CPU_FTRS_40X,
  1382. .cpu_user_features = PPC_FEATURE_32 |
  1383. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1384. .mmu_features = MMU_FTR_TYPE_40x,
  1385. .icache_bsize = 32,
  1386. .dcache_bsize = 32,
  1387. .machine_check = machine_check_4xx,
  1388. .platform = "ppc405",
  1389. },
  1390. { /* 405EX Rev. D without Security */
  1391. .pvr_mask = 0xffff000f,
  1392. .pvr_value = 0x12910003,
  1393. .cpu_name = "405EX Rev. D",
  1394. .cpu_features = CPU_FTRS_40X,
  1395. .cpu_user_features = PPC_FEATURE_32 |
  1396. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1397. .mmu_features = MMU_FTR_TYPE_40x,
  1398. .icache_bsize = 32,
  1399. .dcache_bsize = 32,
  1400. .machine_check = machine_check_4xx,
  1401. .platform = "ppc405",
  1402. },
  1403. { /* 405EX Rev. D with Security */
  1404. .pvr_mask = 0xffff000f,
  1405. .pvr_value = 0x12910005,
  1406. .cpu_name = "405EX Rev. D",
  1407. .cpu_features = CPU_FTRS_40X,
  1408. .cpu_user_features = PPC_FEATURE_32 |
  1409. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1410. .mmu_features = MMU_FTR_TYPE_40x,
  1411. .icache_bsize = 32,
  1412. .dcache_bsize = 32,
  1413. .machine_check = machine_check_4xx,
  1414. .platform = "ppc405",
  1415. },
  1416. { /* 405EXr Rev. A/B without Security */
  1417. .pvr_mask = 0xffff000f,
  1418. .pvr_value = 0x12910001,
  1419. .cpu_name = "405EXr Rev. A/B",
  1420. .cpu_features = CPU_FTRS_40X,
  1421. .cpu_user_features = PPC_FEATURE_32 |
  1422. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1423. .mmu_features = MMU_FTR_TYPE_40x,
  1424. .icache_bsize = 32,
  1425. .dcache_bsize = 32,
  1426. .machine_check = machine_check_4xx,
  1427. .platform = "ppc405",
  1428. },
  1429. { /* 405EXr Rev. C without Security */
  1430. .pvr_mask = 0xffff000f,
  1431. .pvr_value = 0x12910009,
  1432. .cpu_name = "405EXr Rev. C",
  1433. .cpu_features = CPU_FTRS_40X,
  1434. .cpu_user_features = PPC_FEATURE_32 |
  1435. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1436. .mmu_features = MMU_FTR_TYPE_40x,
  1437. .icache_bsize = 32,
  1438. .dcache_bsize = 32,
  1439. .machine_check = machine_check_4xx,
  1440. .platform = "ppc405",
  1441. },
  1442. { /* 405EXr Rev. C with Security */
  1443. .pvr_mask = 0xffff000f,
  1444. .pvr_value = 0x1291000b,
  1445. .cpu_name = "405EXr Rev. C",
  1446. .cpu_features = CPU_FTRS_40X,
  1447. .cpu_user_features = PPC_FEATURE_32 |
  1448. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1449. .mmu_features = MMU_FTR_TYPE_40x,
  1450. .icache_bsize = 32,
  1451. .dcache_bsize = 32,
  1452. .machine_check = machine_check_4xx,
  1453. .platform = "ppc405",
  1454. },
  1455. { /* 405EXr Rev. D without Security */
  1456. .pvr_mask = 0xffff000f,
  1457. .pvr_value = 0x12910000,
  1458. .cpu_name = "405EXr Rev. D",
  1459. .cpu_features = CPU_FTRS_40X,
  1460. .cpu_user_features = PPC_FEATURE_32 |
  1461. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1462. .mmu_features = MMU_FTR_TYPE_40x,
  1463. .icache_bsize = 32,
  1464. .dcache_bsize = 32,
  1465. .machine_check = machine_check_4xx,
  1466. .platform = "ppc405",
  1467. },
  1468. { /* 405EXr Rev. D with Security */
  1469. .pvr_mask = 0xffff000f,
  1470. .pvr_value = 0x12910002,
  1471. .cpu_name = "405EXr Rev. D",
  1472. .cpu_features = CPU_FTRS_40X,
  1473. .cpu_user_features = PPC_FEATURE_32 |
  1474. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1475. .mmu_features = MMU_FTR_TYPE_40x,
  1476. .icache_bsize = 32,
  1477. .dcache_bsize = 32,
  1478. .machine_check = machine_check_4xx,
  1479. .platform = "ppc405",
  1480. },
  1481. {
  1482. /* 405EZ */
  1483. .pvr_mask = 0xffff0000,
  1484. .pvr_value = 0x41510000,
  1485. .cpu_name = "405EZ",
  1486. .cpu_features = CPU_FTRS_40X,
  1487. .cpu_user_features = PPC_FEATURE_32 |
  1488. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1489. .mmu_features = MMU_FTR_TYPE_40x,
  1490. .icache_bsize = 32,
  1491. .dcache_bsize = 32,
  1492. .machine_check = machine_check_4xx,
  1493. .platform = "ppc405",
  1494. },
  1495. { /* default match */
  1496. .pvr_mask = 0x00000000,
  1497. .pvr_value = 0x00000000,
  1498. .cpu_name = "(generic 40x PPC)",
  1499. .cpu_features = CPU_FTRS_40X,
  1500. .cpu_user_features = PPC_FEATURE_32 |
  1501. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1502. .mmu_features = MMU_FTR_TYPE_40x,
  1503. .icache_bsize = 32,
  1504. .dcache_bsize = 32,
  1505. .machine_check = machine_check_4xx,
  1506. .platform = "ppc405",
  1507. }
  1508. #endif /* CONFIG_40x */
  1509. #ifdef CONFIG_44x
  1510. {
  1511. .pvr_mask = 0xf0000fff,
  1512. .pvr_value = 0x40000850,
  1513. .cpu_name = "440GR Rev. A",
  1514. .cpu_features = CPU_FTRS_44X,
  1515. .cpu_user_features = COMMON_USER_BOOKE,
  1516. .mmu_features = MMU_FTR_TYPE_44x,
  1517. .icache_bsize = 32,
  1518. .dcache_bsize = 32,
  1519. .machine_check = machine_check_4xx,
  1520. .platform = "ppc440",
  1521. },
  1522. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1523. .pvr_mask = 0xf0000fff,
  1524. .pvr_value = 0x40000858,
  1525. .cpu_name = "440EP Rev. A",
  1526. .cpu_features = CPU_FTRS_44X,
  1527. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1528. .mmu_features = MMU_FTR_TYPE_44x,
  1529. .icache_bsize = 32,
  1530. .dcache_bsize = 32,
  1531. .cpu_setup = __setup_cpu_440ep,
  1532. .machine_check = machine_check_4xx,
  1533. .platform = "ppc440",
  1534. },
  1535. {
  1536. .pvr_mask = 0xf0000fff,
  1537. .pvr_value = 0x400008d3,
  1538. .cpu_name = "440GR Rev. B",
  1539. .cpu_features = CPU_FTRS_44X,
  1540. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1541. .mmu_features = MMU_FTR_TYPE_44x,
  1542. .icache_bsize = 32,
  1543. .dcache_bsize = 32,
  1544. .machine_check = machine_check_4xx,
  1545. .platform = "ppc440",
  1546. },
  1547. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1548. .pvr_mask = 0xf0000ff7,
  1549. .pvr_value = 0x400008d4,
  1550. .cpu_name = "440EP Rev. C",
  1551. .cpu_features = CPU_FTRS_44X,
  1552. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1553. .mmu_features = MMU_FTR_TYPE_44x,
  1554. .icache_bsize = 32,
  1555. .dcache_bsize = 32,
  1556. .cpu_setup = __setup_cpu_440ep,
  1557. .machine_check = machine_check_4xx,
  1558. .platform = "ppc440",
  1559. },
  1560. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1561. .pvr_mask = 0xf0000fff,
  1562. .pvr_value = 0x400008db,
  1563. .cpu_name = "440EP Rev. B",
  1564. .cpu_features = CPU_FTRS_44X,
  1565. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1566. .mmu_features = MMU_FTR_TYPE_44x,
  1567. .icache_bsize = 32,
  1568. .dcache_bsize = 32,
  1569. .cpu_setup = __setup_cpu_440ep,
  1570. .machine_check = machine_check_4xx,
  1571. .platform = "ppc440",
  1572. },
  1573. { /* 440GRX */
  1574. .pvr_mask = 0xf0000ffb,
  1575. .pvr_value = 0x200008D0,
  1576. .cpu_name = "440GRX",
  1577. .cpu_features = CPU_FTRS_44X,
  1578. .cpu_user_features = COMMON_USER_BOOKE,
  1579. .mmu_features = MMU_FTR_TYPE_44x,
  1580. .icache_bsize = 32,
  1581. .dcache_bsize = 32,
  1582. .cpu_setup = __setup_cpu_440grx,
  1583. .machine_check = machine_check_440A,
  1584. .platform = "ppc440",
  1585. },
  1586. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1587. .pvr_mask = 0xf0000ffb,
  1588. .pvr_value = 0x200008D8,
  1589. .cpu_name = "440EPX",
  1590. .cpu_features = CPU_FTRS_44X,
  1591. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1592. .mmu_features = MMU_FTR_TYPE_44x,
  1593. .icache_bsize = 32,
  1594. .dcache_bsize = 32,
  1595. .cpu_setup = __setup_cpu_440epx,
  1596. .machine_check = machine_check_440A,
  1597. .platform = "ppc440",
  1598. },
  1599. { /* 440GP Rev. B */
  1600. .pvr_mask = 0xf0000fff,
  1601. .pvr_value = 0x40000440,
  1602. .cpu_name = "440GP Rev. B",
  1603. .cpu_features = CPU_FTRS_44X,
  1604. .cpu_user_features = COMMON_USER_BOOKE,
  1605. .mmu_features = MMU_FTR_TYPE_44x,
  1606. .icache_bsize = 32,
  1607. .dcache_bsize = 32,
  1608. .machine_check = machine_check_4xx,
  1609. .platform = "ppc440gp",
  1610. },
  1611. { /* 440GP Rev. C */
  1612. .pvr_mask = 0xf0000fff,
  1613. .pvr_value = 0x40000481,
  1614. .cpu_name = "440GP Rev. C",
  1615. .cpu_features = CPU_FTRS_44X,
  1616. .cpu_user_features = COMMON_USER_BOOKE,
  1617. .mmu_features = MMU_FTR_TYPE_44x,
  1618. .icache_bsize = 32,
  1619. .dcache_bsize = 32,
  1620. .machine_check = machine_check_4xx,
  1621. .platform = "ppc440gp",
  1622. },
  1623. { /* 440GX Rev. A */
  1624. .pvr_mask = 0xf0000fff,
  1625. .pvr_value = 0x50000850,
  1626. .cpu_name = "440GX Rev. A",
  1627. .cpu_features = CPU_FTRS_44X,
  1628. .cpu_user_features = COMMON_USER_BOOKE,
  1629. .mmu_features = MMU_FTR_TYPE_44x,
  1630. .icache_bsize = 32,
  1631. .dcache_bsize = 32,
  1632. .cpu_setup = __setup_cpu_440gx,
  1633. .machine_check = machine_check_440A,
  1634. .platform = "ppc440",
  1635. },
  1636. { /* 440GX Rev. B */
  1637. .pvr_mask = 0xf0000fff,
  1638. .pvr_value = 0x50000851,
  1639. .cpu_name = "440GX Rev. B",
  1640. .cpu_features = CPU_FTRS_44X,
  1641. .cpu_user_features = COMMON_USER_BOOKE,
  1642. .mmu_features = MMU_FTR_TYPE_44x,
  1643. .icache_bsize = 32,
  1644. .dcache_bsize = 32,
  1645. .cpu_setup = __setup_cpu_440gx,
  1646. .machine_check = machine_check_440A,
  1647. .platform = "ppc440",
  1648. },
  1649. { /* 440GX Rev. C */
  1650. .pvr_mask = 0xf0000fff,
  1651. .pvr_value = 0x50000892,
  1652. .cpu_name = "440GX Rev. C",
  1653. .cpu_features = CPU_FTRS_44X,
  1654. .cpu_user_features = COMMON_USER_BOOKE,
  1655. .mmu_features = MMU_FTR_TYPE_44x,
  1656. .icache_bsize = 32,
  1657. .dcache_bsize = 32,
  1658. .cpu_setup = __setup_cpu_440gx,
  1659. .machine_check = machine_check_440A,
  1660. .platform = "ppc440",
  1661. },
  1662. { /* 440GX Rev. F */
  1663. .pvr_mask = 0xf0000fff,
  1664. .pvr_value = 0x50000894,
  1665. .cpu_name = "440GX Rev. F",
  1666. .cpu_features = CPU_FTRS_44X,
  1667. .cpu_user_features = COMMON_USER_BOOKE,
  1668. .mmu_features = MMU_FTR_TYPE_44x,
  1669. .icache_bsize = 32,
  1670. .dcache_bsize = 32,
  1671. .cpu_setup = __setup_cpu_440gx,
  1672. .machine_check = machine_check_440A,
  1673. .platform = "ppc440",
  1674. },
  1675. { /* 440SP Rev. A */
  1676. .pvr_mask = 0xfff00fff,
  1677. .pvr_value = 0x53200891,
  1678. .cpu_name = "440SP Rev. A",
  1679. .cpu_features = CPU_FTRS_44X,
  1680. .cpu_user_features = COMMON_USER_BOOKE,
  1681. .mmu_features = MMU_FTR_TYPE_44x,
  1682. .icache_bsize = 32,
  1683. .dcache_bsize = 32,
  1684. .machine_check = machine_check_4xx,
  1685. .platform = "ppc440",
  1686. },
  1687. { /* 440SPe Rev. A */
  1688. .pvr_mask = 0xfff00fff,
  1689. .pvr_value = 0x53400890,
  1690. .cpu_name = "440SPe Rev. A",
  1691. .cpu_features = CPU_FTRS_44X,
  1692. .cpu_user_features = COMMON_USER_BOOKE,
  1693. .mmu_features = MMU_FTR_TYPE_44x,
  1694. .icache_bsize = 32,
  1695. .dcache_bsize = 32,
  1696. .cpu_setup = __setup_cpu_440spe,
  1697. .machine_check = machine_check_440A,
  1698. .platform = "ppc440",
  1699. },
  1700. { /* 440SPe Rev. B */
  1701. .pvr_mask = 0xfff00fff,
  1702. .pvr_value = 0x53400891,
  1703. .cpu_name = "440SPe Rev. B",
  1704. .cpu_features = CPU_FTRS_44X,
  1705. .cpu_user_features = COMMON_USER_BOOKE,
  1706. .mmu_features = MMU_FTR_TYPE_44x,
  1707. .icache_bsize = 32,
  1708. .dcache_bsize = 32,
  1709. .cpu_setup = __setup_cpu_440spe,
  1710. .machine_check = machine_check_440A,
  1711. .platform = "ppc440",
  1712. },
  1713. { /* 440 in Xilinx Virtex-5 FXT */
  1714. .pvr_mask = 0xfffffff0,
  1715. .pvr_value = 0x7ff21910,
  1716. .cpu_name = "440 in Virtex-5 FXT",
  1717. .cpu_features = CPU_FTRS_44X,
  1718. .cpu_user_features = COMMON_USER_BOOKE,
  1719. .mmu_features = MMU_FTR_TYPE_44x,
  1720. .icache_bsize = 32,
  1721. .dcache_bsize = 32,
  1722. .cpu_setup = __setup_cpu_440x5,
  1723. .machine_check = machine_check_440A,
  1724. .platform = "ppc440",
  1725. },
  1726. { /* 460EX */
  1727. .pvr_mask = 0xffff0006,
  1728. .pvr_value = 0x13020002,
  1729. .cpu_name = "460EX",
  1730. .cpu_features = CPU_FTRS_440x6,
  1731. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1732. .mmu_features = MMU_FTR_TYPE_44x,
  1733. .icache_bsize = 32,
  1734. .dcache_bsize = 32,
  1735. .cpu_setup = __setup_cpu_460ex,
  1736. .machine_check = machine_check_440A,
  1737. .platform = "ppc440",
  1738. },
  1739. { /* 460EX Rev B */
  1740. .pvr_mask = 0xffff0007,
  1741. .pvr_value = 0x13020004,
  1742. .cpu_name = "460EX Rev. B",
  1743. .cpu_features = CPU_FTRS_440x6,
  1744. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1745. .mmu_features = MMU_FTR_TYPE_44x,
  1746. .icache_bsize = 32,
  1747. .dcache_bsize = 32,
  1748. .cpu_setup = __setup_cpu_460ex,
  1749. .machine_check = machine_check_440A,
  1750. .platform = "ppc440",
  1751. },
  1752. { /* 460GT */
  1753. .pvr_mask = 0xffff0006,
  1754. .pvr_value = 0x13020000,
  1755. .cpu_name = "460GT",
  1756. .cpu_features = CPU_FTRS_440x6,
  1757. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1758. .mmu_features = MMU_FTR_TYPE_44x,
  1759. .icache_bsize = 32,
  1760. .dcache_bsize = 32,
  1761. .cpu_setup = __setup_cpu_460gt,
  1762. .machine_check = machine_check_440A,
  1763. .platform = "ppc440",
  1764. },
  1765. { /* 460GT Rev B */
  1766. .pvr_mask = 0xffff0007,
  1767. .pvr_value = 0x13020005,
  1768. .cpu_name = "460GT Rev. B",
  1769. .cpu_features = CPU_FTRS_440x6,
  1770. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1771. .mmu_features = MMU_FTR_TYPE_44x,
  1772. .icache_bsize = 32,
  1773. .dcache_bsize = 32,
  1774. .cpu_setup = __setup_cpu_460gt,
  1775. .machine_check = machine_check_440A,
  1776. .platform = "ppc440",
  1777. },
  1778. { /* 460SX */
  1779. .pvr_mask = 0xffffff00,
  1780. .pvr_value = 0x13541800,
  1781. .cpu_name = "460SX",
  1782. .cpu_features = CPU_FTRS_44X,
  1783. .cpu_user_features = COMMON_USER_BOOKE,
  1784. .mmu_features = MMU_FTR_TYPE_44x,
  1785. .icache_bsize = 32,
  1786. .dcache_bsize = 32,
  1787. .cpu_setup = __setup_cpu_460sx,
  1788. .machine_check = machine_check_440A,
  1789. .platform = "ppc440",
  1790. },
  1791. { /* 464 in APM821xx */
  1792. .pvr_mask = 0xffffff00,
  1793. .pvr_value = 0x12C41C80,
  1794. .cpu_name = "APM821XX",
  1795. .cpu_features = CPU_FTRS_44X,
  1796. .cpu_user_features = COMMON_USER_BOOKE |
  1797. PPC_FEATURE_HAS_FPU,
  1798. .mmu_features = MMU_FTR_TYPE_44x,
  1799. .icache_bsize = 32,
  1800. .dcache_bsize = 32,
  1801. .cpu_setup = __setup_cpu_apm821xx,
  1802. .machine_check = machine_check_440A,
  1803. .platform = "ppc440",
  1804. },
  1805. { /* 476 core */
  1806. .pvr_mask = 0xffff0000,
  1807. .pvr_value = 0x11a50000,
  1808. .cpu_name = "476",
  1809. .cpu_features = CPU_FTRS_47X,
  1810. .cpu_user_features = COMMON_USER_BOOKE |
  1811. PPC_FEATURE_HAS_FPU,
  1812. .mmu_features = MMU_FTR_TYPE_47x |
  1813. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1814. .icache_bsize = 32,
  1815. .dcache_bsize = 128,
  1816. .machine_check = machine_check_47x,
  1817. .platform = "ppc470",
  1818. },
  1819. { /* 476 iss */
  1820. .pvr_mask = 0xffff0000,
  1821. .pvr_value = 0x00050000,
  1822. .cpu_name = "476",
  1823. .cpu_features = CPU_FTRS_47X,
  1824. .cpu_user_features = COMMON_USER_BOOKE |
  1825. PPC_FEATURE_HAS_FPU,
  1826. .mmu_features = MMU_FTR_TYPE_47x |
  1827. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1828. .icache_bsize = 32,
  1829. .dcache_bsize = 128,
  1830. .machine_check = machine_check_47x,
  1831. .platform = "ppc470",
  1832. },
  1833. { /* default match */
  1834. .pvr_mask = 0x00000000,
  1835. .pvr_value = 0x00000000,
  1836. .cpu_name = "(generic 44x PPC)",
  1837. .cpu_features = CPU_FTRS_44X,
  1838. .cpu_user_features = COMMON_USER_BOOKE,
  1839. .mmu_features = MMU_FTR_TYPE_44x,
  1840. .icache_bsize = 32,
  1841. .dcache_bsize = 32,
  1842. .machine_check = machine_check_4xx,
  1843. .platform = "ppc440",
  1844. }
  1845. #endif /* CONFIG_44x */
  1846. #ifdef CONFIG_E200
  1847. { /* e200z5 */
  1848. .pvr_mask = 0xfff00000,
  1849. .pvr_value = 0x81000000,
  1850. .cpu_name = "e200z5",
  1851. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1852. .cpu_features = CPU_FTRS_E200,
  1853. .cpu_user_features = COMMON_USER_BOOKE |
  1854. PPC_FEATURE_HAS_EFP_SINGLE |
  1855. PPC_FEATURE_UNIFIED_CACHE,
  1856. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1857. .dcache_bsize = 32,
  1858. .machine_check = machine_check_e200,
  1859. .platform = "ppc5554",
  1860. },
  1861. { /* e200z6 */
  1862. .pvr_mask = 0xfff00000,
  1863. .pvr_value = 0x81100000,
  1864. .cpu_name = "e200z6",
  1865. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1866. .cpu_features = CPU_FTRS_E200,
  1867. .cpu_user_features = COMMON_USER_BOOKE |
  1868. PPC_FEATURE_HAS_SPE_COMP |
  1869. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1870. PPC_FEATURE_UNIFIED_CACHE,
  1871. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1872. .dcache_bsize = 32,
  1873. .machine_check = machine_check_e200,
  1874. .platform = "ppc5554",
  1875. },
  1876. { /* default match */
  1877. .pvr_mask = 0x00000000,
  1878. .pvr_value = 0x00000000,
  1879. .cpu_name = "(generic E200 PPC)",
  1880. .cpu_features = CPU_FTRS_E200,
  1881. .cpu_user_features = COMMON_USER_BOOKE |
  1882. PPC_FEATURE_HAS_EFP_SINGLE |
  1883. PPC_FEATURE_UNIFIED_CACHE,
  1884. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1885. .dcache_bsize = 32,
  1886. .cpu_setup = __setup_cpu_e200,
  1887. .machine_check = machine_check_e200,
  1888. .platform = "ppc5554",
  1889. }
  1890. #endif /* CONFIG_E200 */
  1891. #endif /* CONFIG_PPC32 */
  1892. #ifdef CONFIG_E500
  1893. #ifdef CONFIG_PPC32
  1894. { /* e500 */
  1895. .pvr_mask = 0xffff0000,
  1896. .pvr_value = 0x80200000,
  1897. .cpu_name = "e500",
  1898. .cpu_features = CPU_FTRS_E500,
  1899. .cpu_user_features = COMMON_USER_BOOKE |
  1900. PPC_FEATURE_HAS_SPE_COMP |
  1901. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1902. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1903. .icache_bsize = 32,
  1904. .dcache_bsize = 32,
  1905. .num_pmcs = 4,
  1906. .oprofile_cpu_type = "ppc/e500",
  1907. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1908. .cpu_setup = __setup_cpu_e500v1,
  1909. .machine_check = machine_check_e500,
  1910. .platform = "ppc8540",
  1911. },
  1912. { /* e500v2 */
  1913. .pvr_mask = 0xffff0000,
  1914. .pvr_value = 0x80210000,
  1915. .cpu_name = "e500v2",
  1916. .cpu_features = CPU_FTRS_E500_2,
  1917. .cpu_user_features = COMMON_USER_BOOKE |
  1918. PPC_FEATURE_HAS_SPE_COMP |
  1919. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1920. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  1921. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  1922. .icache_bsize = 32,
  1923. .dcache_bsize = 32,
  1924. .num_pmcs = 4,
  1925. .oprofile_cpu_type = "ppc/e500",
  1926. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1927. .cpu_setup = __setup_cpu_e500v2,
  1928. .machine_check = machine_check_e500,
  1929. .platform = "ppc8548",
  1930. },
  1931. { /* e500mc */
  1932. .pvr_mask = 0xffff0000,
  1933. .pvr_value = 0x80230000,
  1934. .cpu_name = "e500mc",
  1935. .cpu_features = CPU_FTRS_E500MC,
  1936. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1937. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1938. MMU_FTR_USE_TLBILX,
  1939. .icache_bsize = 64,
  1940. .dcache_bsize = 64,
  1941. .num_pmcs = 4,
  1942. .oprofile_cpu_type = "ppc/e500mc",
  1943. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1944. .cpu_setup = __setup_cpu_e500mc,
  1945. .machine_check = machine_check_e500mc,
  1946. .platform = "ppce500mc",
  1947. },
  1948. #endif /* CONFIG_PPC32 */
  1949. { /* e5500 */
  1950. .pvr_mask = 0xffff0000,
  1951. .pvr_value = 0x80240000,
  1952. .cpu_name = "e5500",
  1953. .cpu_features = CPU_FTRS_E500MC,
  1954. .cpu_user_features = COMMON_USER_BOOKE,
  1955. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  1956. MMU_FTR_USE_TLBILX,
  1957. .icache_bsize = 64,
  1958. .dcache_bsize = 64,
  1959. .num_pmcs = 4,
  1960. .oprofile_cpu_type = "ppc/e500mc",
  1961. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1962. .cpu_setup = __setup_cpu_e5500,
  1963. .cpu_restore = __restore_cpu_e5500,
  1964. .machine_check = machine_check_e500mc,
  1965. .platform = "ppce5500",
  1966. },
  1967. #ifdef CONFIG_PPC32
  1968. { /* default match */
  1969. .pvr_mask = 0x00000000,
  1970. .pvr_value = 0x00000000,
  1971. .cpu_name = "(generic E500 PPC)",
  1972. .cpu_features = CPU_FTRS_E500,
  1973. .cpu_user_features = COMMON_USER_BOOKE |
  1974. PPC_FEATURE_HAS_SPE_COMP |
  1975. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1976. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1977. .icache_bsize = 32,
  1978. .dcache_bsize = 32,
  1979. .machine_check = machine_check_e500,
  1980. .platform = "powerpc",
  1981. }
  1982. #endif /* CONFIG_PPC32 */
  1983. #endif /* CONFIG_E500 */
  1984. #ifdef CONFIG_PPC_BOOK3E_64
  1985. { /* This is a default entry to get going, to be replaced by
  1986. * a real one at some stage
  1987. */
  1988. #define CPU_FTRS_BASE_BOOK3E (CPU_FTR_USE_TB | \
  1989. CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
  1990. CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
  1991. .pvr_mask = 0x00000000,
  1992. .pvr_value = 0x00000000,
  1993. .cpu_name = "Book3E",
  1994. .cpu_features = CPU_FTRS_BASE_BOOK3E,
  1995. .cpu_user_features = COMMON_USER_PPC64,
  1996. .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
  1997. MMU_FTR_USE_TLBIVAX_BCAST |
  1998. MMU_FTR_LOCK_BCAST_INVAL,
  1999. .icache_bsize = 64,
  2000. .dcache_bsize = 64,
  2001. .num_pmcs = 0,
  2002. .machine_check = machine_check_generic,
  2003. .platform = "power6",
  2004. },
  2005. #endif
  2006. };
  2007. static struct cpu_spec the_cpu_spec;
  2008. static void __init setup_cpu_spec(unsigned long offset, struct cpu_spec *s)
  2009. {
  2010. struct cpu_spec *t = &the_cpu_spec;
  2011. struct cpu_spec old;
  2012. t = PTRRELOC(t);
  2013. old = *t;
  2014. /* Copy everything, then do fixups */
  2015. *t = *s;
  2016. /*
  2017. * If we are overriding a previous value derived from the real
  2018. * PVR with a new value obtained using a logical PVR value,
  2019. * don't modify the performance monitor fields.
  2020. */
  2021. if (old.num_pmcs && !s->num_pmcs) {
  2022. t->num_pmcs = old.num_pmcs;
  2023. t->pmc_type = old.pmc_type;
  2024. t->oprofile_type = old.oprofile_type;
  2025. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  2026. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  2027. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  2028. /*
  2029. * If we have passed through this logic once before and
  2030. * have pulled the default case because the real PVR was
  2031. * not found inside cpu_specs[], then we are possibly
  2032. * running in compatibility mode. In that case, let the
  2033. * oprofiler know which set of compatibility counters to
  2034. * pull from by making sure the oprofile_cpu_type string
  2035. * is set to that of compatibility mode. If the
  2036. * oprofile_cpu_type already has a value, then we are
  2037. * possibly overriding a real PVR with a logical one,
  2038. * and, in that case, keep the current value for
  2039. * oprofile_cpu_type.
  2040. */
  2041. if (old.oprofile_cpu_type != NULL) {
  2042. t->oprofile_cpu_type = old.oprofile_cpu_type;
  2043. t->oprofile_type = old.oprofile_type;
  2044. }
  2045. }
  2046. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2047. /*
  2048. * Set the base platform string once; assumes
  2049. * we're called with real pvr first.
  2050. */
  2051. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  2052. *PTRRELOC(&powerpc_base_platform) = t->platform;
  2053. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  2054. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  2055. * that processor. I will consolidate that at a later time, for now,
  2056. * just use #ifdef. We also don't need to PTRRELOC the function
  2057. * pointer on ppc64 and booke as we are running at 0 in real mode
  2058. * on ppc64 and reloc_offset is always 0 on booke.
  2059. */
  2060. if (s->cpu_setup) {
  2061. s->cpu_setup(offset, s);
  2062. }
  2063. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  2064. }
  2065. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  2066. {
  2067. struct cpu_spec *s = cpu_specs;
  2068. int i;
  2069. s = PTRRELOC(s);
  2070. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2071. if ((pvr & s->pvr_mask) == s->pvr_value) {
  2072. setup_cpu_spec(offset, s);
  2073. return s;
  2074. }
  2075. }
  2076. BUG();
  2077. return NULL;
  2078. }