timer-tmu.c 4.2 KB

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  1. /*
  2. * arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
  3. *
  4. * Copyright (C) 2005 Paul Mundt
  5. *
  6. * TMU handling code hacked out of arch/sh/kernel/time.c
  7. *
  8. * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
  9. * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  10. * Copyright (C) 2002, 2003, 2004 Paul Mundt
  11. * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
  12. *
  13. * This file is subject to the terms and conditions of the GNU General Public
  14. * License. See the file "COPYING" in the main directory of this archive
  15. * for more details.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/seqlock.h>
  22. #include <asm/timer.h>
  23. #include <asm/rtc.h>
  24. #include <asm/io.h>
  25. #include <asm/irq.h>
  26. #include <asm/clock.h>
  27. #define TMU_TOCR_INIT 0x00
  28. #define TMU0_TCR_INIT 0x0020
  29. #define TMU_TSTR_INIT 1
  30. #define TMU0_TCR_CALIB 0x0000
  31. static DEFINE_SPINLOCK(tmu0_lock);
  32. static unsigned long tmu_timer_get_offset(void)
  33. {
  34. int count;
  35. unsigned long flags;
  36. static int count_p = 0x7fffffff; /* for the first call after boot */
  37. static unsigned long jiffies_p = 0;
  38. /*
  39. * cache volatile jiffies temporarily; we have IRQs turned off.
  40. */
  41. unsigned long jiffies_t;
  42. spin_lock_irqsave(&tmu0_lock, flags);
  43. /* timer count may underflow right here */
  44. count = ctrl_inl(TMU0_TCNT); /* read the latched count */
  45. jiffies_t = jiffies;
  46. /*
  47. * avoiding timer inconsistencies (they are rare, but they happen)...
  48. * there is one kind of problem that must be avoided here:
  49. * 1. the timer counter underflows
  50. */
  51. if (jiffies_t == jiffies_p) {
  52. if (count > count_p) {
  53. /* the nutcase */
  54. if (ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */
  55. count -= LATCH;
  56. } else {
  57. printk("%s (): hardware timer problem?\n",
  58. __FUNCTION__);
  59. }
  60. }
  61. } else
  62. jiffies_p = jiffies_t;
  63. count_p = count;
  64. spin_unlock_irqrestore(&tmu0_lock, flags);
  65. count = ((LATCH-1) - count) * TICK_SIZE;
  66. count = (count + LATCH/2) / LATCH;
  67. return count;
  68. }
  69. static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
  70. {
  71. unsigned long timer_status;
  72. /* Clear UNF bit */
  73. timer_status = ctrl_inw(TMU0_TCR);
  74. timer_status &= ~0x100;
  75. ctrl_outw(timer_status, TMU0_TCR);
  76. /*
  77. * Here we are in the timer irq handler. We just have irqs locally
  78. * disabled but we don't know if the timer_bh is running on the other
  79. * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
  80. * the irq version of write_lock because as just said we have irq
  81. * locally disabled. -arca
  82. */
  83. write_seqlock(&xtime_lock);
  84. handle_timer_tick();
  85. write_sequnlock(&xtime_lock);
  86. return IRQ_HANDLED;
  87. }
  88. static struct irqaction tmu_irq = {
  89. .name = "timer",
  90. .handler = tmu_timer_interrupt,
  91. .flags = IRQF_DISABLED,
  92. .mask = CPU_MASK_NONE,
  93. };
  94. static void tmu_clk_init(struct clk *clk)
  95. {
  96. u8 divisor = TMU0_TCR_INIT & 0x7;
  97. ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
  98. clk->rate = clk->parent->rate / (4 << (divisor << 1));
  99. }
  100. static void tmu_clk_recalc(struct clk *clk)
  101. {
  102. u8 divisor = ctrl_inw(TMU0_TCR) & 0x7;
  103. clk->rate = clk->parent->rate / (4 << (divisor << 1));
  104. }
  105. static struct clk_ops tmu_clk_ops = {
  106. .init = tmu_clk_init,
  107. .recalc = tmu_clk_recalc,
  108. };
  109. static struct clk tmu0_clk = {
  110. .name = "tmu0_clk",
  111. .ops = &tmu_clk_ops,
  112. };
  113. static int tmu_timer_start(void)
  114. {
  115. ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
  116. return 0;
  117. }
  118. static int tmu_timer_stop(void)
  119. {
  120. ctrl_outb(0, TMU_TSTR);
  121. return 0;
  122. }
  123. static int tmu_timer_init(void)
  124. {
  125. unsigned long interval;
  126. setup_irq(TIMER_IRQ, &tmu_irq);
  127. tmu0_clk.parent = clk_get("module_clk");
  128. /* Start TMU0 */
  129. tmu_timer_stop();
  130. #if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
  131. ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
  132. #endif
  133. clk_register(&tmu0_clk);
  134. clk_enable(&tmu0_clk);
  135. interval = (clk_get_rate(&tmu0_clk) + HZ / 2) / HZ;
  136. printk(KERN_INFO "Interval = %ld\n", interval);
  137. ctrl_outl(interval, TMU0_TCOR);
  138. ctrl_outl(interval, TMU0_TCNT);
  139. tmu_timer_start();
  140. return 0;
  141. }
  142. struct sys_timer_ops tmu_timer_ops = {
  143. .init = tmu_timer_init,
  144. .start = tmu_timer_start,
  145. .stop = tmu_timer_stop,
  146. #ifndef CONFIG_GENERIC_TIME
  147. .get_offset = tmu_timer_get_offset,
  148. #endif
  149. };
  150. struct sys_timer tmu_timer = {
  151. .name = "tmu",
  152. .ops = &tmu_timer_ops,
  153. };