mpc832x_mds.c 4.4 KB

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  1. /*
  2. * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
  3. *
  4. * Description:
  5. * MPC832xE MDS board specific routines.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. #include <linux/stddef.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/errno.h>
  16. #include <linux/reboot.h>
  17. #include <linux/pci.h>
  18. #include <linux/kdev_t.h>
  19. #include <linux/major.h>
  20. #include <linux/console.h>
  21. #include <linux/delay.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/root_dev.h>
  24. #include <linux/initrd.h>
  25. #include <asm/system.h>
  26. #include <asm/atomic.h>
  27. #include <asm/time.h>
  28. #include <asm/io.h>
  29. #include <asm/machdep.h>
  30. #include <asm/ipic.h>
  31. #include <asm/bootinfo.h>
  32. #include <asm/irq.h>
  33. #include <asm/prom.h>
  34. #include <asm/udbg.h>
  35. #include <sysdev/fsl_soc.h>
  36. #include <asm/qe.h>
  37. #include <asm/qe_ic.h>
  38. #include "mpc83xx.h"
  39. #include "mpc832x_mds.h"
  40. #undef DEBUG
  41. #ifdef DEBUG
  42. #define DBG(fmt...) udbg_printf(fmt)
  43. #else
  44. #define DBG(fmt...)
  45. #endif
  46. #ifndef CONFIG_PCI
  47. unsigned long isa_io_base = 0;
  48. unsigned long isa_mem_base = 0;
  49. #endif
  50. static u8 *bcsr_regs = NULL;
  51. u8 *get_bcsr(void)
  52. {
  53. return bcsr_regs;
  54. }
  55. /* ************************************************************************
  56. *
  57. * Setup the architecture
  58. *
  59. */
  60. static void __init mpc832x_sys_setup_arch(void)
  61. {
  62. struct device_node *np;
  63. if (ppc_md.progress)
  64. ppc_md.progress("mpc832x_sys_setup_arch()", 0);
  65. np = of_find_node_by_type(NULL, "cpu");
  66. if (np != 0) {
  67. unsigned int *fp =
  68. (int *)get_property(np, "clock-frequency", NULL);
  69. if (fp != 0)
  70. loops_per_jiffy = *fp / HZ;
  71. else
  72. loops_per_jiffy = 50000000 / HZ;
  73. of_node_put(np);
  74. }
  75. /* Map BCSR area */
  76. np = of_find_node_by_name(NULL, "bcsr");
  77. if (np != 0) {
  78. struct resource res;
  79. of_address_to_resource(np, 0, &res);
  80. bcsr_regs = ioremap(res.start, res.end - res.start +1);
  81. of_node_put(np);
  82. }
  83. #ifdef CONFIG_PCI
  84. for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
  85. add_bridge(np);
  86. ppc_md.pci_swizzle = common_swizzle;
  87. ppc_md.pci_exclude_device = mpc83xx_exclude_device;
  88. #endif
  89. #ifdef CONFIG_QUICC_ENGINE
  90. qe_reset();
  91. if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
  92. par_io_init(np);
  93. of_node_put(np);
  94. for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  95. par_io_of_config(np);
  96. }
  97. if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
  98. != NULL){
  99. /* Reset the Ethernet PHY */
  100. bcsr_regs[9] &= ~0x20;
  101. udelay(1000);
  102. bcsr_regs[9] |= 0x20;
  103. iounmap(bcsr_regs);
  104. of_node_put(np);
  105. }
  106. #endif /* CONFIG_QUICC_ENGINE */
  107. #ifdef CONFIG_BLK_DEV_INITRD
  108. if (initrd_start)
  109. ROOT_DEV = Root_RAM0;
  110. else
  111. #endif
  112. #ifdef CONFIG_ROOT_NFS
  113. ROOT_DEV = Root_NFS;
  114. #else
  115. ROOT_DEV = Root_HDA1;
  116. #endif
  117. }
  118. void __init mpc832x_sys_init_IRQ(void)
  119. {
  120. struct device_node *np;
  121. np = of_find_node_by_type(NULL, "ipic");
  122. if (!np)
  123. return;
  124. ipic_init(np, 0);
  125. /* Initialize the default interrupt mapping priorities,
  126. * in case the boot rom changed something on us.
  127. */
  128. ipic_set_default_priority();
  129. of_node_put(np);
  130. #ifdef CONFIG_QUICC_ENGINE
  131. np = of_find_node_by_type(NULL, "qeic");
  132. if (!np)
  133. return;
  134. qe_ic_init(np, 0);
  135. of_node_put(np);
  136. #endif /* CONFIG_QUICC_ENGINE */
  137. }
  138. #if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
  139. extern ulong ds1374_get_rtc_time(void);
  140. extern int ds1374_set_rtc_time(ulong);
  141. static int __init mpc832x_rtc_hookup(void)
  142. {
  143. struct timespec tv;
  144. ppc_md.get_rtc_time = ds1374_get_rtc_time;
  145. ppc_md.set_rtc_time = ds1374_set_rtc_time;
  146. tv.tv_nsec = 0;
  147. tv.tv_sec = (ppc_md.get_rtc_time) ();
  148. do_settimeofday(&tv);
  149. return 0;
  150. }
  151. late_initcall(mpc832x_rtc_hookup);
  152. #endif
  153. /*
  154. * Called very early, MMU is off, device-tree isn't unflattened
  155. */
  156. static int __init mpc832x_sys_probe(void)
  157. {
  158. char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
  159. "model", NULL);
  160. if (model == NULL)
  161. return 0;
  162. if (strcmp(model, "MPC8323EMDS"))
  163. return 0;
  164. DBG("%s found\n", model);
  165. return 1;
  166. }
  167. define_machine(mpc832x_mds) {
  168. .name = "MPC832x MDS",
  169. .probe = mpc832x_sys_probe,
  170. .setup_arch = mpc832x_sys_setup_arch,
  171. .init_IRQ = mpc832x_sys_init_IRQ,
  172. .get_irq = ipic_get_irq,
  173. .restart = mpc83xx_restart,
  174. .time_init = mpc83xx_time_init,
  175. .calibrate_decr = generic_calibrate_decr,
  176. .progress = udbg_progress,
  177. };