mpc8272ads.dts 8.8 KB

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  1. /*
  2. * MPC8272 ADS Device Tree Source
  3. *
  4. * Copyright 2005 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8272ADS";
  13. compatible = "MPC8260ADS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. linux,phandle = <100>;
  17. cpus {
  18. #cpus = <1>;
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. linux,phandle = <200>;
  22. PowerPC,8272@0 {
  23. device_type = "cpu";
  24. reg = <0>;
  25. d-cache-line-size = <20>; // 32 bytes
  26. i-cache-line-size = <20>; // 32 bytes
  27. d-cache-size = <4000>; // L1, 16K
  28. i-cache-size = <4000>; // L1, 16K
  29. timebase-frequency = <0>;
  30. bus-frequency = <0>;
  31. clock-frequency = <0>;
  32. 32-bit;
  33. linux,phandle = <201>;
  34. linux,boot-cpu;
  35. };
  36. };
  37. interrupt-controller@f8200000 {
  38. linux,phandle = <f8200000>;
  39. #address-cells = <0>;
  40. #interrupt-cells = <2>;
  41. interrupt-controller;
  42. reg = <f8200000 f8200004>;
  43. built-in;
  44. device_type = "pci-pic";
  45. };
  46. memory {
  47. device_type = "memory";
  48. linux,phandle = <300>;
  49. reg = <00000000 4000000 f4500000 00000020>;
  50. };
  51. soc8272@f0000000 {
  52. #address-cells = <1>;
  53. #size-cells = <1>;
  54. #interrupt-cells = <2>;
  55. device_type = "soc";
  56. ranges = < 0 0 2 00000000 f0000000 00053000>;
  57. reg = <f0000000 0>;
  58. mdio@0 {
  59. device_type = "mdio";
  60. compatible = "fs_enet";
  61. reg = <0 0>;
  62. linux,phandle = <24520>;
  63. #address-cells = <1>;
  64. #size-cells = <0>;
  65. ethernet-phy@0 {
  66. linux,phandle = <2452000>;
  67. interrupt-parent = <10c00>;
  68. interrupts = <19 1>;
  69. reg = <0>;
  70. bitbang = [ 12 12 13 02 02 01 ];
  71. device_type = "ethernet-phy";
  72. };
  73. ethernet-phy@1 {
  74. linux,phandle = <2452001>;
  75. interrupt-parent = <10c00>;
  76. interrupts = <19 1>;
  77. bitbang = [ 12 12 13 02 02 01 ];
  78. reg = <3>;
  79. device_type = "ethernet-phy";
  80. };
  81. };
  82. ethernet@24000 {
  83. #address-cells = <1>;
  84. #size-cells = <0>;
  85. device_type = "network";
  86. device-id = <2>;
  87. compatible = "fs_enet";
  88. model = "FCC";
  89. reg = <11300 20 8400 100 11380 30>;
  90. mac-address = [ 00 11 2F 99 43 54 ];
  91. interrupts = <20 2>;
  92. interrupt-parent = <10c00>;
  93. phy-handle = <2452000>;
  94. rx-clock = <13>;
  95. tx-clock = <12>;
  96. };
  97. ethernet@25000 {
  98. device_type = "network";
  99. device-id = <3>;
  100. compatible = "fs_enet";
  101. model = "FCC";
  102. reg = <11320 20 8500 100 113b0 30>;
  103. mac-address = [ 00 11 2F 99 44 54 ];
  104. interrupts = <21 2>;
  105. interrupt-parent = <10c00>;
  106. phy-handle = <2452001>;
  107. rx-clock = <17>;
  108. tx-clock = <18>;
  109. };
  110. cpm@f0000000 {
  111. linux,phandle = <f0000000>;
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. #interrupt-cells = <2>;
  115. device_type = "cpm";
  116. model = "CPM2";
  117. ranges = <00000000 00000000 3ffff>;
  118. reg = <10d80 3280>;
  119. command-proc = <119c0>;
  120. brg-frequency = <17D7840>;
  121. cpm_clk = <BEBC200>;
  122. scc@11a00 {
  123. device_type = "serial";
  124. compatible = "cpm_uart";
  125. model = "SCC";
  126. device-id = <2>;
  127. reg = <11a00 20 8000 100>;
  128. current-speed = <1c200>;
  129. interrupts = <28 2>;
  130. interrupt-parent = <10c00>;
  131. clock-setup = <0 00ffffff>;
  132. rx-clock = <1>;
  133. tx-clock = <1>;
  134. };
  135. scc@11a60 {
  136. device_type = "serial";
  137. compatible = "cpm_uart";
  138. model = "SCC";
  139. device-id = <5>;
  140. reg = <11a60 20 8300 100>;
  141. current-speed = <1c200>;
  142. interrupts = <2b 2>;
  143. interrupt-parent = <10c00>;
  144. clock-setup = <1b ffffff00>;
  145. rx-clock = <4>;
  146. tx-clock = <4>;
  147. };
  148. };
  149. interrupt-controller@10c00 {
  150. linux,phandle = <10c00>;
  151. #address-cells = <0>;
  152. #interrupt-cells = <2>;
  153. interrupt-controller;
  154. reg = <10c00 80>;
  155. built-in;
  156. device_type = "cpm-pic";
  157. compatible = "CPM2";
  158. };
  159. pci@0500 {
  160. linux,phandle = <0500>;
  161. #interrupt-cells = <1>;
  162. #size-cells = <2>;
  163. #address-cells = <3>;
  164. compatible = "8272";
  165. device_type = "pci";
  166. reg = <10430 4dc>;
  167. clock-frequency = <3f940aa>;
  168. interrupt-map-mask = <f800 0 0 7>;
  169. interrupt-map = <
  170. /* IDSEL 0x16 */
  171. b000 0 0 1 f8200000 40 0
  172. b000 0 0 2 f8200000 41 0
  173. b000 0 0 3 f8200000 42 0
  174. b000 0 0 4 f8200000 43 0
  175. /* IDSEL 0x17 */
  176. b800 0 0 1 f8200000 43 0
  177. b800 0 0 2 f8200000 40 0
  178. b800 0 0 3 f8200000 41 0
  179. b800 0 0 4 f8200000 42 0
  180. /* IDSEL 0x18 */
  181. c000 0 0 1 f8200000 42 0
  182. c000 0 0 2 f8200000 43 0
  183. c000 0 0 3 f8200000 40 0
  184. c000 0 0 4 f8200000 41 0>;
  185. interrupt-parent = <10c00>;
  186. interrupts = <14 3>;
  187. bus-range = <0 0>;
  188. ranges = <02000000 0 80000000 80000000 0 40000000
  189. 01000000 0 00000000 f6000000 0 02000000>;
  190. };
  191. /* May need to remove if on a part without crypto engine */
  192. crypto@30000 {
  193. device_type = "crypto";
  194. model = "SEC2";
  195. compatible = "talitos";
  196. reg = <30000 10000>;
  197. interrupts = <b 0>;
  198. interrupt-parent = <10c00>;
  199. num-channels = <4>;
  200. channel-fifo-len = <18>;
  201. exec-units-mask = <0000007e>;
  202. /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
  203. descriptor-types-mask = <01010ebf>;
  204. };
  205. };
  206. };