i915_dma.c 43 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651
  1. /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #include "drmP.h"
  29. #include "drm.h"
  30. #include "drm_crtc_helper.h"
  31. #include "drm_fb_helper.h"
  32. #include "intel_drv.h"
  33. #include "i915_drm.h"
  34. #include "i915_drv.h"
  35. /* Really want an OS-independent resettable timer. Would like to have
  36. * this loop run for (eg) 3 sec, but have the timer reset every time
  37. * the head pointer changes, so that EBUSY only happens if the ring
  38. * actually stalls for (eg) 3 seconds.
  39. */
  40. int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  41. {
  42. drm_i915_private_t *dev_priv = dev->dev_private;
  43. drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  44. u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
  45. u32 last_acthd = I915_READ(acthd_reg);
  46. u32 acthd;
  47. u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  48. int i;
  49. for (i = 0; i < 100000; i++) {
  50. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  51. acthd = I915_READ(acthd_reg);
  52. ring->space = ring->head - (ring->tail + 8);
  53. if (ring->space < 0)
  54. ring->space += ring->Size;
  55. if (ring->space >= n)
  56. return 0;
  57. if (dev->primary->master) {
  58. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  59. if (master_priv->sarea_priv)
  60. master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  61. }
  62. if (ring->head != last_head)
  63. i = 0;
  64. if (acthd != last_acthd)
  65. i = 0;
  66. last_head = ring->head;
  67. last_acthd = acthd;
  68. msleep_interruptible(10);
  69. }
  70. return -EBUSY;
  71. }
  72. /* As a ringbuffer is only allowed to wrap between instructions, fill
  73. * the tail with NOOPs.
  74. */
  75. int i915_wrap_ring(struct drm_device *dev)
  76. {
  77. drm_i915_private_t *dev_priv = dev->dev_private;
  78. volatile unsigned int *virt;
  79. int rem;
  80. rem = dev_priv->ring.Size - dev_priv->ring.tail;
  81. if (dev_priv->ring.space < rem) {
  82. int ret = i915_wait_ring(dev, rem, __func__);
  83. if (ret)
  84. return ret;
  85. }
  86. dev_priv->ring.space -= rem;
  87. virt = (unsigned int *)
  88. (dev_priv->ring.virtual_start + dev_priv->ring.tail);
  89. rem /= 4;
  90. while (rem--)
  91. *virt++ = MI_NOOP;
  92. dev_priv->ring.tail = 0;
  93. return 0;
  94. }
  95. /**
  96. * Sets up the hardware status page for devices that need a physical address
  97. * in the register.
  98. */
  99. static int i915_init_phys_hws(struct drm_device *dev)
  100. {
  101. drm_i915_private_t *dev_priv = dev->dev_private;
  102. /* Program Hardware Status Page */
  103. dev_priv->status_page_dmah =
  104. drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  105. if (!dev_priv->status_page_dmah) {
  106. DRM_ERROR("Can not allocate hardware status page\n");
  107. return -ENOMEM;
  108. }
  109. dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
  110. dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  111. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  112. I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  113. DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  114. return 0;
  115. }
  116. /**
  117. * Frees the hardware status page, whether it's a physical address or a virtual
  118. * address set up by the X Server.
  119. */
  120. static void i915_free_hws(struct drm_device *dev)
  121. {
  122. drm_i915_private_t *dev_priv = dev->dev_private;
  123. if (dev_priv->status_page_dmah) {
  124. drm_pci_free(dev, dev_priv->status_page_dmah);
  125. dev_priv->status_page_dmah = NULL;
  126. }
  127. if (dev_priv->status_gfx_addr) {
  128. dev_priv->status_gfx_addr = 0;
  129. drm_core_ioremapfree(&dev_priv->hws_map, dev);
  130. }
  131. /* Need to rewrite hardware status page */
  132. I915_WRITE(HWS_PGA, 0x1ffff000);
  133. }
  134. void i915_kernel_lost_context(struct drm_device * dev)
  135. {
  136. drm_i915_private_t *dev_priv = dev->dev_private;
  137. struct drm_i915_master_private *master_priv;
  138. drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  139. /*
  140. * We should never lose context on the ring with modesetting
  141. * as we don't expose it to userspace
  142. */
  143. if (drm_core_check_feature(dev, DRIVER_MODESET))
  144. return;
  145. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  146. ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  147. ring->space = ring->head - (ring->tail + 8);
  148. if (ring->space < 0)
  149. ring->space += ring->Size;
  150. if (!dev->primary->master)
  151. return;
  152. master_priv = dev->primary->master->driver_priv;
  153. if (ring->head == ring->tail && master_priv->sarea_priv)
  154. master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  155. }
  156. static int i915_dma_cleanup(struct drm_device * dev)
  157. {
  158. drm_i915_private_t *dev_priv = dev->dev_private;
  159. /* Make sure interrupts are disabled here because the uninstall ioctl
  160. * may not have been called from userspace and after dev_private
  161. * is freed, it's too late.
  162. */
  163. if (dev->irq_enabled)
  164. drm_irq_uninstall(dev);
  165. if (dev_priv->ring.virtual_start) {
  166. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  167. dev_priv->ring.virtual_start = NULL;
  168. dev_priv->ring.map.handle = NULL;
  169. dev_priv->ring.map.size = 0;
  170. }
  171. /* Clear the HWS virtual address at teardown */
  172. if (I915_NEED_GFX_HWS(dev))
  173. i915_free_hws(dev);
  174. return 0;
  175. }
  176. static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
  177. {
  178. drm_i915_private_t *dev_priv = dev->dev_private;
  179. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  180. master_priv->sarea = drm_getsarea(dev);
  181. if (master_priv->sarea) {
  182. master_priv->sarea_priv = (drm_i915_sarea_t *)
  183. ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
  184. } else {
  185. DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
  186. }
  187. if (init->ring_size != 0) {
  188. if (dev_priv->ring.ring_obj != NULL) {
  189. i915_dma_cleanup(dev);
  190. DRM_ERROR("Client tried to initialize ringbuffer in "
  191. "GEM mode\n");
  192. return -EINVAL;
  193. }
  194. dev_priv->ring.Size = init->ring_size;
  195. dev_priv->ring.map.offset = init->ring_start;
  196. dev_priv->ring.map.size = init->ring_size;
  197. dev_priv->ring.map.type = 0;
  198. dev_priv->ring.map.flags = 0;
  199. dev_priv->ring.map.mtrr = 0;
  200. drm_core_ioremap_wc(&dev_priv->ring.map, dev);
  201. if (dev_priv->ring.map.handle == NULL) {
  202. i915_dma_cleanup(dev);
  203. DRM_ERROR("can not ioremap virtual address for"
  204. " ring buffer\n");
  205. return -ENOMEM;
  206. }
  207. }
  208. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  209. dev_priv->cpp = init->cpp;
  210. dev_priv->back_offset = init->back_offset;
  211. dev_priv->front_offset = init->front_offset;
  212. dev_priv->current_page = 0;
  213. if (master_priv->sarea_priv)
  214. master_priv->sarea_priv->pf_current_page = 0;
  215. /* Allow hardware batchbuffers unless told otherwise.
  216. */
  217. dev_priv->allow_batchbuffer = 1;
  218. return 0;
  219. }
  220. static int i915_dma_resume(struct drm_device * dev)
  221. {
  222. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  223. DRM_DEBUG_DRIVER("%s\n", __func__);
  224. if (dev_priv->ring.map.handle == NULL) {
  225. DRM_ERROR("can not ioremap virtual address for"
  226. " ring buffer\n");
  227. return -ENOMEM;
  228. }
  229. /* Program Hardware Status Page */
  230. if (!dev_priv->hw_status_page) {
  231. DRM_ERROR("Can not find hardware status page\n");
  232. return -EINVAL;
  233. }
  234. DRM_DEBUG_DRIVER("hw status page @ %p\n",
  235. dev_priv->hw_status_page);
  236. if (dev_priv->status_gfx_addr != 0)
  237. I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
  238. else
  239. I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  240. DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  241. return 0;
  242. }
  243. static int i915_dma_init(struct drm_device *dev, void *data,
  244. struct drm_file *file_priv)
  245. {
  246. drm_i915_init_t *init = data;
  247. int retcode = 0;
  248. switch (init->func) {
  249. case I915_INIT_DMA:
  250. retcode = i915_initialize(dev, init);
  251. break;
  252. case I915_CLEANUP_DMA:
  253. retcode = i915_dma_cleanup(dev);
  254. break;
  255. case I915_RESUME_DMA:
  256. retcode = i915_dma_resume(dev);
  257. break;
  258. default:
  259. retcode = -EINVAL;
  260. break;
  261. }
  262. return retcode;
  263. }
  264. /* Implement basically the same security restrictions as hardware does
  265. * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
  266. *
  267. * Most of the calculations below involve calculating the size of a
  268. * particular instruction. It's important to get the size right as
  269. * that tells us where the next instruction to check is. Any illegal
  270. * instruction detected will be given a size of zero, which is a
  271. * signal to abort the rest of the buffer.
  272. */
  273. static int do_validate_cmd(int cmd)
  274. {
  275. switch (((cmd >> 29) & 0x7)) {
  276. case 0x0:
  277. switch ((cmd >> 23) & 0x3f) {
  278. case 0x0:
  279. return 1; /* MI_NOOP */
  280. case 0x4:
  281. return 1; /* MI_FLUSH */
  282. default:
  283. return 0; /* disallow everything else */
  284. }
  285. break;
  286. case 0x1:
  287. return 0; /* reserved */
  288. case 0x2:
  289. return (cmd & 0xff) + 2; /* 2d commands */
  290. case 0x3:
  291. if (((cmd >> 24) & 0x1f) <= 0x18)
  292. return 1;
  293. switch ((cmd >> 24) & 0x1f) {
  294. case 0x1c:
  295. return 1;
  296. case 0x1d:
  297. switch ((cmd >> 16) & 0xff) {
  298. case 0x3:
  299. return (cmd & 0x1f) + 2;
  300. case 0x4:
  301. return (cmd & 0xf) + 2;
  302. default:
  303. return (cmd & 0xffff) + 2;
  304. }
  305. case 0x1e:
  306. if (cmd & (1 << 23))
  307. return (cmd & 0xffff) + 1;
  308. else
  309. return 1;
  310. case 0x1f:
  311. if ((cmd & (1 << 23)) == 0) /* inline vertices */
  312. return (cmd & 0x1ffff) + 2;
  313. else if (cmd & (1 << 17)) /* indirect random */
  314. if ((cmd & 0xffff) == 0)
  315. return 0; /* unknown length, too hard */
  316. else
  317. return (((cmd & 0xffff) + 1) / 2) + 1;
  318. else
  319. return 2; /* indirect sequential */
  320. default:
  321. return 0;
  322. }
  323. default:
  324. return 0;
  325. }
  326. return 0;
  327. }
  328. static int validate_cmd(int cmd)
  329. {
  330. int ret = do_validate_cmd(cmd);
  331. /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
  332. return ret;
  333. }
  334. static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
  335. {
  336. drm_i915_private_t *dev_priv = dev->dev_private;
  337. int i;
  338. RING_LOCALS;
  339. if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
  340. return -EINVAL;
  341. BEGIN_LP_RING((dwords+1)&~1);
  342. for (i = 0; i < dwords;) {
  343. int cmd, sz;
  344. cmd = buffer[i];
  345. if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
  346. return -EINVAL;
  347. OUT_RING(cmd);
  348. while (++i, --sz) {
  349. OUT_RING(buffer[i]);
  350. }
  351. }
  352. if (dwords & 1)
  353. OUT_RING(0);
  354. ADVANCE_LP_RING();
  355. return 0;
  356. }
  357. int
  358. i915_emit_box(struct drm_device *dev,
  359. struct drm_clip_rect *boxes,
  360. int i, int DR1, int DR4)
  361. {
  362. drm_i915_private_t *dev_priv = dev->dev_private;
  363. struct drm_clip_rect box = boxes[i];
  364. RING_LOCALS;
  365. if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
  366. DRM_ERROR("Bad box %d,%d..%d,%d\n",
  367. box.x1, box.y1, box.x2, box.y2);
  368. return -EINVAL;
  369. }
  370. if (IS_I965G(dev)) {
  371. BEGIN_LP_RING(4);
  372. OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
  373. OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
  374. OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
  375. OUT_RING(DR4);
  376. ADVANCE_LP_RING();
  377. } else {
  378. BEGIN_LP_RING(6);
  379. OUT_RING(GFX_OP_DRAWRECT_INFO);
  380. OUT_RING(DR1);
  381. OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
  382. OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
  383. OUT_RING(DR4);
  384. OUT_RING(0);
  385. ADVANCE_LP_RING();
  386. }
  387. return 0;
  388. }
  389. /* XXX: Emitting the counter should really be moved to part of the IRQ
  390. * emit. For now, do it in both places:
  391. */
  392. static void i915_emit_breadcrumb(struct drm_device *dev)
  393. {
  394. drm_i915_private_t *dev_priv = dev->dev_private;
  395. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  396. RING_LOCALS;
  397. dev_priv->counter++;
  398. if (dev_priv->counter > 0x7FFFFFFFUL)
  399. dev_priv->counter = 0;
  400. if (master_priv->sarea_priv)
  401. master_priv->sarea_priv->last_enqueue = dev_priv->counter;
  402. BEGIN_LP_RING(4);
  403. OUT_RING(MI_STORE_DWORD_INDEX);
  404. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  405. OUT_RING(dev_priv->counter);
  406. OUT_RING(0);
  407. ADVANCE_LP_RING();
  408. }
  409. static int i915_dispatch_cmdbuffer(struct drm_device * dev,
  410. drm_i915_cmdbuffer_t *cmd,
  411. struct drm_clip_rect *cliprects,
  412. void *cmdbuf)
  413. {
  414. int nbox = cmd->num_cliprects;
  415. int i = 0, count, ret;
  416. if (cmd->sz & 0x3) {
  417. DRM_ERROR("alignment");
  418. return -EINVAL;
  419. }
  420. i915_kernel_lost_context(dev);
  421. count = nbox ? nbox : 1;
  422. for (i = 0; i < count; i++) {
  423. if (i < nbox) {
  424. ret = i915_emit_box(dev, cliprects, i,
  425. cmd->DR1, cmd->DR4);
  426. if (ret)
  427. return ret;
  428. }
  429. ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
  430. if (ret)
  431. return ret;
  432. }
  433. i915_emit_breadcrumb(dev);
  434. return 0;
  435. }
  436. static int i915_dispatch_batchbuffer(struct drm_device * dev,
  437. drm_i915_batchbuffer_t * batch,
  438. struct drm_clip_rect *cliprects)
  439. {
  440. drm_i915_private_t *dev_priv = dev->dev_private;
  441. int nbox = batch->num_cliprects;
  442. int i = 0, count;
  443. RING_LOCALS;
  444. if ((batch->start | batch->used) & 0x7) {
  445. DRM_ERROR("alignment");
  446. return -EINVAL;
  447. }
  448. i915_kernel_lost_context(dev);
  449. count = nbox ? nbox : 1;
  450. for (i = 0; i < count; i++) {
  451. if (i < nbox) {
  452. int ret = i915_emit_box(dev, cliprects, i,
  453. batch->DR1, batch->DR4);
  454. if (ret)
  455. return ret;
  456. }
  457. if (!IS_I830(dev) && !IS_845G(dev)) {
  458. BEGIN_LP_RING(2);
  459. if (IS_I965G(dev)) {
  460. OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
  461. OUT_RING(batch->start);
  462. } else {
  463. OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
  464. OUT_RING(batch->start | MI_BATCH_NON_SECURE);
  465. }
  466. ADVANCE_LP_RING();
  467. } else {
  468. BEGIN_LP_RING(4);
  469. OUT_RING(MI_BATCH_BUFFER);
  470. OUT_RING(batch->start | MI_BATCH_NON_SECURE);
  471. OUT_RING(batch->start + batch->used - 4);
  472. OUT_RING(0);
  473. ADVANCE_LP_RING();
  474. }
  475. }
  476. i915_emit_breadcrumb(dev);
  477. return 0;
  478. }
  479. static int i915_dispatch_flip(struct drm_device * dev)
  480. {
  481. drm_i915_private_t *dev_priv = dev->dev_private;
  482. struct drm_i915_master_private *master_priv =
  483. dev->primary->master->driver_priv;
  484. RING_LOCALS;
  485. if (!master_priv->sarea_priv)
  486. return -EINVAL;
  487. DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
  488. __func__,
  489. dev_priv->current_page,
  490. master_priv->sarea_priv->pf_current_page);
  491. i915_kernel_lost_context(dev);
  492. BEGIN_LP_RING(2);
  493. OUT_RING(MI_FLUSH | MI_READ_FLUSH);
  494. OUT_RING(0);
  495. ADVANCE_LP_RING();
  496. BEGIN_LP_RING(6);
  497. OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
  498. OUT_RING(0);
  499. if (dev_priv->current_page == 0) {
  500. OUT_RING(dev_priv->back_offset);
  501. dev_priv->current_page = 1;
  502. } else {
  503. OUT_RING(dev_priv->front_offset);
  504. dev_priv->current_page = 0;
  505. }
  506. OUT_RING(0);
  507. ADVANCE_LP_RING();
  508. BEGIN_LP_RING(2);
  509. OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
  510. OUT_RING(0);
  511. ADVANCE_LP_RING();
  512. master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
  513. BEGIN_LP_RING(4);
  514. OUT_RING(MI_STORE_DWORD_INDEX);
  515. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  516. OUT_RING(dev_priv->counter);
  517. OUT_RING(0);
  518. ADVANCE_LP_RING();
  519. master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  520. return 0;
  521. }
  522. static int i915_quiescent(struct drm_device * dev)
  523. {
  524. drm_i915_private_t *dev_priv = dev->dev_private;
  525. i915_kernel_lost_context(dev);
  526. return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
  527. }
  528. static int i915_flush_ioctl(struct drm_device *dev, void *data,
  529. struct drm_file *file_priv)
  530. {
  531. int ret;
  532. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  533. mutex_lock(&dev->struct_mutex);
  534. ret = i915_quiescent(dev);
  535. mutex_unlock(&dev->struct_mutex);
  536. return ret;
  537. }
  538. static int i915_batchbuffer(struct drm_device *dev, void *data,
  539. struct drm_file *file_priv)
  540. {
  541. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  542. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  543. drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
  544. master_priv->sarea_priv;
  545. drm_i915_batchbuffer_t *batch = data;
  546. int ret;
  547. struct drm_clip_rect *cliprects = NULL;
  548. if (!dev_priv->allow_batchbuffer) {
  549. DRM_ERROR("Batchbuffer ioctl disabled\n");
  550. return -EINVAL;
  551. }
  552. DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
  553. batch->start, batch->used, batch->num_cliprects);
  554. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  555. if (batch->num_cliprects < 0)
  556. return -EINVAL;
  557. if (batch->num_cliprects) {
  558. cliprects = kcalloc(batch->num_cliprects,
  559. sizeof(struct drm_clip_rect),
  560. GFP_KERNEL);
  561. if (cliprects == NULL)
  562. return -ENOMEM;
  563. ret = copy_from_user(cliprects, batch->cliprects,
  564. batch->num_cliprects *
  565. sizeof(struct drm_clip_rect));
  566. if (ret != 0)
  567. goto fail_free;
  568. }
  569. mutex_lock(&dev->struct_mutex);
  570. ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
  571. mutex_unlock(&dev->struct_mutex);
  572. if (sarea_priv)
  573. sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  574. fail_free:
  575. kfree(cliprects);
  576. return ret;
  577. }
  578. static int i915_cmdbuffer(struct drm_device *dev, void *data,
  579. struct drm_file *file_priv)
  580. {
  581. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  582. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  583. drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
  584. master_priv->sarea_priv;
  585. drm_i915_cmdbuffer_t *cmdbuf = data;
  586. struct drm_clip_rect *cliprects = NULL;
  587. void *batch_data;
  588. int ret;
  589. DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
  590. cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
  591. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  592. if (cmdbuf->num_cliprects < 0)
  593. return -EINVAL;
  594. batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
  595. if (batch_data == NULL)
  596. return -ENOMEM;
  597. ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
  598. if (ret != 0)
  599. goto fail_batch_free;
  600. if (cmdbuf->num_cliprects) {
  601. cliprects = kcalloc(cmdbuf->num_cliprects,
  602. sizeof(struct drm_clip_rect), GFP_KERNEL);
  603. if (cliprects == NULL)
  604. goto fail_batch_free;
  605. ret = copy_from_user(cliprects, cmdbuf->cliprects,
  606. cmdbuf->num_cliprects *
  607. sizeof(struct drm_clip_rect));
  608. if (ret != 0)
  609. goto fail_clip_free;
  610. }
  611. mutex_lock(&dev->struct_mutex);
  612. ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
  613. mutex_unlock(&dev->struct_mutex);
  614. if (ret) {
  615. DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
  616. goto fail_clip_free;
  617. }
  618. if (sarea_priv)
  619. sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  620. fail_clip_free:
  621. kfree(cliprects);
  622. fail_batch_free:
  623. kfree(batch_data);
  624. return ret;
  625. }
  626. static int i915_flip_bufs(struct drm_device *dev, void *data,
  627. struct drm_file *file_priv)
  628. {
  629. int ret;
  630. DRM_DEBUG_DRIVER("%s\n", __func__);
  631. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  632. mutex_lock(&dev->struct_mutex);
  633. ret = i915_dispatch_flip(dev);
  634. mutex_unlock(&dev->struct_mutex);
  635. return ret;
  636. }
  637. static int i915_getparam(struct drm_device *dev, void *data,
  638. struct drm_file *file_priv)
  639. {
  640. drm_i915_private_t *dev_priv = dev->dev_private;
  641. drm_i915_getparam_t *param = data;
  642. int value;
  643. if (!dev_priv) {
  644. DRM_ERROR("called with no initialization\n");
  645. return -EINVAL;
  646. }
  647. switch (param->param) {
  648. case I915_PARAM_IRQ_ACTIVE:
  649. value = dev->pdev->irq ? 1 : 0;
  650. break;
  651. case I915_PARAM_ALLOW_BATCHBUFFER:
  652. value = dev_priv->allow_batchbuffer ? 1 : 0;
  653. break;
  654. case I915_PARAM_LAST_DISPATCH:
  655. value = READ_BREADCRUMB(dev_priv);
  656. break;
  657. case I915_PARAM_CHIPSET_ID:
  658. value = dev->pci_device;
  659. break;
  660. case I915_PARAM_HAS_GEM:
  661. value = dev_priv->has_gem;
  662. break;
  663. case I915_PARAM_NUM_FENCES_AVAIL:
  664. value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  665. break;
  666. default:
  667. DRM_DEBUG_DRIVER("Unknown parameter %d\n",
  668. param->param);
  669. return -EINVAL;
  670. }
  671. if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
  672. DRM_ERROR("DRM_COPY_TO_USER failed\n");
  673. return -EFAULT;
  674. }
  675. return 0;
  676. }
  677. static int i915_setparam(struct drm_device *dev, void *data,
  678. struct drm_file *file_priv)
  679. {
  680. drm_i915_private_t *dev_priv = dev->dev_private;
  681. drm_i915_setparam_t *param = data;
  682. if (!dev_priv) {
  683. DRM_ERROR("called with no initialization\n");
  684. return -EINVAL;
  685. }
  686. switch (param->param) {
  687. case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
  688. break;
  689. case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
  690. dev_priv->tex_lru_log_granularity = param->value;
  691. break;
  692. case I915_SETPARAM_ALLOW_BATCHBUFFER:
  693. dev_priv->allow_batchbuffer = param->value;
  694. break;
  695. case I915_SETPARAM_NUM_USED_FENCES:
  696. if (param->value > dev_priv->num_fence_regs ||
  697. param->value < 0)
  698. return -EINVAL;
  699. /* Userspace can use first N regs */
  700. dev_priv->fence_reg_start = param->value;
  701. break;
  702. default:
  703. DRM_DEBUG_DRIVER("unknown parameter %d\n",
  704. param->param);
  705. return -EINVAL;
  706. }
  707. return 0;
  708. }
  709. static int i915_set_status_page(struct drm_device *dev, void *data,
  710. struct drm_file *file_priv)
  711. {
  712. drm_i915_private_t *dev_priv = dev->dev_private;
  713. drm_i915_hws_addr_t *hws = data;
  714. if (!I915_NEED_GFX_HWS(dev))
  715. return -EINVAL;
  716. if (!dev_priv) {
  717. DRM_ERROR("called with no initialization\n");
  718. return -EINVAL;
  719. }
  720. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  721. WARN(1, "tried to set status page when mode setting active\n");
  722. return 0;
  723. }
  724. DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
  725. dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
  726. dev_priv->hws_map.offset = dev->agp->base + hws->addr;
  727. dev_priv->hws_map.size = 4*1024;
  728. dev_priv->hws_map.type = 0;
  729. dev_priv->hws_map.flags = 0;
  730. dev_priv->hws_map.mtrr = 0;
  731. drm_core_ioremap_wc(&dev_priv->hws_map, dev);
  732. if (dev_priv->hws_map.handle == NULL) {
  733. i915_dma_cleanup(dev);
  734. dev_priv->status_gfx_addr = 0;
  735. DRM_ERROR("can not ioremap virtual address for"
  736. " G33 hw status page\n");
  737. return -ENOMEM;
  738. }
  739. dev_priv->hw_status_page = dev_priv->hws_map.handle;
  740. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  741. I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
  742. DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
  743. dev_priv->status_gfx_addr);
  744. DRM_DEBUG_DRIVER("load hws at %p\n",
  745. dev_priv->hw_status_page);
  746. return 0;
  747. }
  748. static int i915_get_bridge_dev(struct drm_device *dev)
  749. {
  750. struct drm_i915_private *dev_priv = dev->dev_private;
  751. dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
  752. if (!dev_priv->bridge_dev) {
  753. DRM_ERROR("bridge device not found\n");
  754. return -1;
  755. }
  756. return 0;
  757. }
  758. /**
  759. * i915_probe_agp - get AGP bootup configuration
  760. * @pdev: PCI device
  761. * @aperture_size: returns AGP aperture configured size
  762. * @preallocated_size: returns size of BIOS preallocated AGP space
  763. *
  764. * Since Intel integrated graphics are UMA, the BIOS has to set aside
  765. * some RAM for the framebuffer at early boot. This code figures out
  766. * how much was set aside so we can use it for our own purposes.
  767. */
  768. static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
  769. uint32_t *preallocated_size,
  770. uint32_t *start)
  771. {
  772. struct drm_i915_private *dev_priv = dev->dev_private;
  773. u16 tmp = 0;
  774. unsigned long overhead;
  775. unsigned long stolen;
  776. /* Get the fb aperture size and "stolen" memory amount. */
  777. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
  778. *aperture_size = 1024 * 1024;
  779. *preallocated_size = 1024 * 1024;
  780. switch (dev->pdev->device) {
  781. case PCI_DEVICE_ID_INTEL_82830_CGC:
  782. case PCI_DEVICE_ID_INTEL_82845G_IG:
  783. case PCI_DEVICE_ID_INTEL_82855GM_IG:
  784. case PCI_DEVICE_ID_INTEL_82865_IG:
  785. if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
  786. *aperture_size *= 64;
  787. else
  788. *aperture_size *= 128;
  789. break;
  790. default:
  791. /* 9xx supports large sizes, just look at the length */
  792. *aperture_size = pci_resource_len(dev->pdev, 2);
  793. break;
  794. }
  795. /*
  796. * Some of the preallocated space is taken by the GTT
  797. * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
  798. */
  799. if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev))
  800. overhead = 4096;
  801. else
  802. overhead = (*aperture_size / 1024) + 4096;
  803. switch (tmp & INTEL_GMCH_GMS_MASK) {
  804. case INTEL_855_GMCH_GMS_DISABLED:
  805. DRM_ERROR("video memory is disabled\n");
  806. return -1;
  807. case INTEL_855_GMCH_GMS_STOLEN_1M:
  808. stolen = 1 * 1024 * 1024;
  809. break;
  810. case INTEL_855_GMCH_GMS_STOLEN_4M:
  811. stolen = 4 * 1024 * 1024;
  812. break;
  813. case INTEL_855_GMCH_GMS_STOLEN_8M:
  814. stolen = 8 * 1024 * 1024;
  815. break;
  816. case INTEL_855_GMCH_GMS_STOLEN_16M:
  817. stolen = 16 * 1024 * 1024;
  818. break;
  819. case INTEL_855_GMCH_GMS_STOLEN_32M:
  820. stolen = 32 * 1024 * 1024;
  821. break;
  822. case INTEL_915G_GMCH_GMS_STOLEN_48M:
  823. stolen = 48 * 1024 * 1024;
  824. break;
  825. case INTEL_915G_GMCH_GMS_STOLEN_64M:
  826. stolen = 64 * 1024 * 1024;
  827. break;
  828. case INTEL_GMCH_GMS_STOLEN_128M:
  829. stolen = 128 * 1024 * 1024;
  830. break;
  831. case INTEL_GMCH_GMS_STOLEN_256M:
  832. stolen = 256 * 1024 * 1024;
  833. break;
  834. case INTEL_GMCH_GMS_STOLEN_96M:
  835. stolen = 96 * 1024 * 1024;
  836. break;
  837. case INTEL_GMCH_GMS_STOLEN_160M:
  838. stolen = 160 * 1024 * 1024;
  839. break;
  840. case INTEL_GMCH_GMS_STOLEN_224M:
  841. stolen = 224 * 1024 * 1024;
  842. break;
  843. case INTEL_GMCH_GMS_STOLEN_352M:
  844. stolen = 352 * 1024 * 1024;
  845. break;
  846. default:
  847. DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
  848. tmp & INTEL_GMCH_GMS_MASK);
  849. return -1;
  850. }
  851. *preallocated_size = stolen - overhead;
  852. *start = overhead;
  853. return 0;
  854. }
  855. #define PTE_ADDRESS_MASK 0xfffff000
  856. #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
  857. #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
  858. #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
  859. #define PTE_MAPPING_TYPE_CACHED (3 << 1)
  860. #define PTE_MAPPING_TYPE_MASK (3 << 1)
  861. #define PTE_VALID (1 << 0)
  862. /**
  863. * i915_gtt_to_phys - take a GTT address and turn it into a physical one
  864. * @dev: drm device
  865. * @gtt_addr: address to translate
  866. *
  867. * Some chip functions require allocations from stolen space but need the
  868. * physical address of the memory in question. We use this routine
  869. * to get a physical address suitable for register programming from a given
  870. * GTT address.
  871. */
  872. static unsigned long i915_gtt_to_phys(struct drm_device *dev,
  873. unsigned long gtt_addr)
  874. {
  875. unsigned long *gtt;
  876. unsigned long entry, phys;
  877. int gtt_bar = IS_I9XX(dev) ? 0 : 1;
  878. int gtt_offset, gtt_size;
  879. if (IS_I965G(dev)) {
  880. if (IS_G4X(dev) || IS_IGDNG(dev)) {
  881. gtt_offset = 2*1024*1024;
  882. gtt_size = 2*1024*1024;
  883. } else {
  884. gtt_offset = 512*1024;
  885. gtt_size = 512*1024;
  886. }
  887. } else {
  888. gtt_bar = 3;
  889. gtt_offset = 0;
  890. gtt_size = pci_resource_len(dev->pdev, gtt_bar);
  891. }
  892. gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
  893. gtt_size);
  894. if (!gtt) {
  895. DRM_ERROR("ioremap of GTT failed\n");
  896. return 0;
  897. }
  898. entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
  899. DRM_DEBUG("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
  900. /* Mask out these reserved bits on this hardware. */
  901. if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
  902. IS_I945G(dev) || IS_I945GM(dev)) {
  903. entry &= ~PTE_ADDRESS_MASK_HIGH;
  904. }
  905. /* If it's not a mapping type we know, then bail. */
  906. if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
  907. (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
  908. iounmap(gtt);
  909. return 0;
  910. }
  911. if (!(entry & PTE_VALID)) {
  912. DRM_ERROR("bad GTT entry in stolen space\n");
  913. iounmap(gtt);
  914. return 0;
  915. }
  916. iounmap(gtt);
  917. phys =(entry & PTE_ADDRESS_MASK) |
  918. ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
  919. DRM_DEBUG("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
  920. return phys;
  921. }
  922. static void i915_warn_stolen(struct drm_device *dev)
  923. {
  924. DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
  925. DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
  926. }
  927. static void i915_setup_compression(struct drm_device *dev, int size)
  928. {
  929. struct drm_i915_private *dev_priv = dev->dev_private;
  930. struct drm_mm_node *compressed_fb, *compressed_llb;
  931. unsigned long cfb_base, ll_base;
  932. /* Leave 1M for line length buffer & misc. */
  933. compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
  934. if (!compressed_fb) {
  935. i915_warn_stolen(dev);
  936. return;
  937. }
  938. compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
  939. if (!compressed_fb) {
  940. i915_warn_stolen(dev);
  941. return;
  942. }
  943. cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
  944. if (!cfb_base) {
  945. DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
  946. drm_mm_put_block(compressed_fb);
  947. }
  948. if (!IS_GM45(dev)) {
  949. compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
  950. 4096, 0);
  951. if (!compressed_llb) {
  952. i915_warn_stolen(dev);
  953. return;
  954. }
  955. compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
  956. if (!compressed_llb) {
  957. i915_warn_stolen(dev);
  958. return;
  959. }
  960. ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
  961. if (!ll_base) {
  962. DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
  963. drm_mm_put_block(compressed_fb);
  964. drm_mm_put_block(compressed_llb);
  965. }
  966. }
  967. dev_priv->cfb_size = size;
  968. if (IS_GM45(dev)) {
  969. g4x_disable_fbc(dev);
  970. I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
  971. } else {
  972. i8xx_disable_fbc(dev);
  973. I915_WRITE(FBC_CFB_BASE, cfb_base);
  974. I915_WRITE(FBC_LL_BASE, ll_base);
  975. }
  976. DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
  977. ll_base, size >> 20);
  978. }
  979. static int i915_load_modeset_init(struct drm_device *dev,
  980. unsigned long prealloc_start,
  981. unsigned long prealloc_size,
  982. unsigned long agp_size)
  983. {
  984. struct drm_i915_private *dev_priv = dev->dev_private;
  985. int fb_bar = IS_I9XX(dev) ? 2 : 0;
  986. int ret = 0;
  987. dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
  988. 0xff000000;
  989. if (IS_MOBILE(dev) || IS_I9XX(dev))
  990. dev_priv->cursor_needs_physical = true;
  991. else
  992. dev_priv->cursor_needs_physical = false;
  993. if (IS_I965G(dev) || IS_G33(dev))
  994. dev_priv->cursor_needs_physical = false;
  995. /* Basic memrange allocator for stolen space (aka vram) */
  996. drm_mm_init(&dev_priv->vram, 0, prealloc_size);
  997. DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
  998. /* We're off and running w/KMS */
  999. dev_priv->mm.suspended = 0;
  1000. /* Let GEM Manage from end of prealloc space to end of aperture.
  1001. *
  1002. * However, leave one page at the end still bound to the scratch page.
  1003. * There are a number of places where the hardware apparently
  1004. * prefetches past the end of the object, and we've seen multiple
  1005. * hangs with the GPU head pointer stuck in a batchbuffer bound
  1006. * at the last page of the aperture. One page should be enough to
  1007. * keep any prefetching inside of the aperture.
  1008. */
  1009. i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
  1010. mutex_lock(&dev->struct_mutex);
  1011. ret = i915_gem_init_ringbuffer(dev);
  1012. mutex_unlock(&dev->struct_mutex);
  1013. if (ret)
  1014. goto out;
  1015. /* Try to set up FBC with a reasonable compressed buffer size */
  1016. if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev) || IS_GM45(dev)) &&
  1017. i915_powersave) {
  1018. int cfb_size;
  1019. /* Try to get an 8M buffer... */
  1020. if (prealloc_size > (9*1024*1024))
  1021. cfb_size = 8*1024*1024;
  1022. else /* fall back to 7/8 of the stolen space */
  1023. cfb_size = prealloc_size * 7 / 8;
  1024. i915_setup_compression(dev, cfb_size);
  1025. }
  1026. /* Allow hardware batchbuffers unless told otherwise.
  1027. */
  1028. dev_priv->allow_batchbuffer = 1;
  1029. ret = intel_init_bios(dev);
  1030. if (ret)
  1031. DRM_INFO("failed to find VBIOS tables\n");
  1032. ret = drm_irq_install(dev);
  1033. if (ret)
  1034. goto destroy_ringbuffer;
  1035. /* Always safe in the mode setting case. */
  1036. /* FIXME: do pre/post-mode set stuff in core KMS code */
  1037. dev->vblank_disable_allowed = 1;
  1038. /*
  1039. * Initialize the hardware status page IRQ location.
  1040. */
  1041. I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
  1042. intel_modeset_init(dev);
  1043. drm_helper_initial_config(dev);
  1044. return 0;
  1045. destroy_ringbuffer:
  1046. i915_gem_cleanup_ringbuffer(dev);
  1047. out:
  1048. return ret;
  1049. }
  1050. int i915_master_create(struct drm_device *dev, struct drm_master *master)
  1051. {
  1052. struct drm_i915_master_private *master_priv;
  1053. master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
  1054. if (!master_priv)
  1055. return -ENOMEM;
  1056. master->driver_priv = master_priv;
  1057. return 0;
  1058. }
  1059. void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
  1060. {
  1061. struct drm_i915_master_private *master_priv = master->driver_priv;
  1062. if (!master_priv)
  1063. return;
  1064. kfree(master_priv);
  1065. master->driver_priv = NULL;
  1066. }
  1067. static void i915_get_mem_freq(struct drm_device *dev)
  1068. {
  1069. drm_i915_private_t *dev_priv = dev->dev_private;
  1070. u32 tmp;
  1071. if (!IS_IGD(dev))
  1072. return;
  1073. tmp = I915_READ(CLKCFG);
  1074. switch (tmp & CLKCFG_FSB_MASK) {
  1075. case CLKCFG_FSB_533:
  1076. dev_priv->fsb_freq = 533; /* 133*4 */
  1077. break;
  1078. case CLKCFG_FSB_800:
  1079. dev_priv->fsb_freq = 800; /* 200*4 */
  1080. break;
  1081. case CLKCFG_FSB_667:
  1082. dev_priv->fsb_freq = 667; /* 167*4 */
  1083. break;
  1084. case CLKCFG_FSB_400:
  1085. dev_priv->fsb_freq = 400; /* 100*4 */
  1086. break;
  1087. }
  1088. switch (tmp & CLKCFG_MEM_MASK) {
  1089. case CLKCFG_MEM_533:
  1090. dev_priv->mem_freq = 533;
  1091. break;
  1092. case CLKCFG_MEM_667:
  1093. dev_priv->mem_freq = 667;
  1094. break;
  1095. case CLKCFG_MEM_800:
  1096. dev_priv->mem_freq = 800;
  1097. break;
  1098. }
  1099. }
  1100. /**
  1101. * i915_driver_load - setup chip and create an initial config
  1102. * @dev: DRM device
  1103. * @flags: startup flags
  1104. *
  1105. * The driver load routine has to do several things:
  1106. * - drive output discovery via intel_modeset_init()
  1107. * - initialize the memory manager
  1108. * - allocate initial config memory
  1109. * - setup the DRM framebuffer with the allocated memory
  1110. */
  1111. int i915_driver_load(struct drm_device *dev, unsigned long flags)
  1112. {
  1113. struct drm_i915_private *dev_priv = dev->dev_private;
  1114. resource_size_t base, size;
  1115. int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
  1116. uint32_t agp_size, prealloc_size, prealloc_start;
  1117. /* i915 has 4 more counters */
  1118. dev->counters += 4;
  1119. dev->types[6] = _DRM_STAT_IRQ;
  1120. dev->types[7] = _DRM_STAT_PRIMARY;
  1121. dev->types[8] = _DRM_STAT_SECONDARY;
  1122. dev->types[9] = _DRM_STAT_DMA;
  1123. dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
  1124. if (dev_priv == NULL)
  1125. return -ENOMEM;
  1126. dev->dev_private = (void *)dev_priv;
  1127. dev_priv->dev = dev;
  1128. /* Add register map (needed for suspend/resume) */
  1129. base = drm_get_resource_start(dev, mmio_bar);
  1130. size = drm_get_resource_len(dev, mmio_bar);
  1131. if (i915_get_bridge_dev(dev)) {
  1132. ret = -EIO;
  1133. goto free_priv;
  1134. }
  1135. dev_priv->regs = ioremap(base, size);
  1136. if (!dev_priv->regs) {
  1137. DRM_ERROR("failed to map registers\n");
  1138. ret = -EIO;
  1139. goto put_bridge;
  1140. }
  1141. dev_priv->mm.gtt_mapping =
  1142. io_mapping_create_wc(dev->agp->base,
  1143. dev->agp->agp_info.aper_size * 1024*1024);
  1144. if (dev_priv->mm.gtt_mapping == NULL) {
  1145. ret = -EIO;
  1146. goto out_rmmap;
  1147. }
  1148. /* Set up a WC MTRR for non-PAT systems. This is more common than
  1149. * one would think, because the kernel disables PAT on first
  1150. * generation Core chips because WC PAT gets overridden by a UC
  1151. * MTRR if present. Even if a UC MTRR isn't present.
  1152. */
  1153. dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
  1154. dev->agp->agp_info.aper_size *
  1155. 1024 * 1024,
  1156. MTRR_TYPE_WRCOMB, 1);
  1157. if (dev_priv->mm.gtt_mtrr < 0) {
  1158. DRM_INFO("MTRR allocation failed. Graphics "
  1159. "performance may suffer.\n");
  1160. }
  1161. ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
  1162. if (ret)
  1163. goto out_iomapfree;
  1164. dev_priv->wq = create_workqueue("i915");
  1165. if (dev_priv->wq == NULL) {
  1166. DRM_ERROR("Failed to create our workqueue.\n");
  1167. ret = -ENOMEM;
  1168. goto out_iomapfree;
  1169. }
  1170. /* enable GEM by default */
  1171. dev_priv->has_gem = 1;
  1172. if (prealloc_size > agp_size * 3 / 4) {
  1173. DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
  1174. "memory stolen.\n",
  1175. prealloc_size / 1024, agp_size / 1024);
  1176. DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
  1177. "updating the BIOS to fix).\n");
  1178. dev_priv->has_gem = 0;
  1179. }
  1180. dev->driver->get_vblank_counter = i915_get_vblank_counter;
  1181. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  1182. if (IS_G4X(dev) || IS_IGDNG(dev)) {
  1183. dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  1184. dev->driver->get_vblank_counter = gm45_get_vblank_counter;
  1185. }
  1186. i915_gem_load(dev);
  1187. /* Init HWS */
  1188. if (!I915_NEED_GFX_HWS(dev)) {
  1189. ret = i915_init_phys_hws(dev);
  1190. if (ret != 0)
  1191. goto out_workqueue_free;
  1192. }
  1193. i915_get_mem_freq(dev);
  1194. /* On the 945G/GM, the chipset reports the MSI capability on the
  1195. * integrated graphics even though the support isn't actually there
  1196. * according to the published specs. It doesn't appear to function
  1197. * correctly in testing on 945G.
  1198. * This may be a side effect of MSI having been made available for PEG
  1199. * and the registers being closely associated.
  1200. *
  1201. * According to chipset errata, on the 965GM, MSI interrupts may
  1202. * be lost or delayed, but we use them anyways to avoid
  1203. * stuck interrupts on some machines.
  1204. */
  1205. if (!IS_I945G(dev) && !IS_I945GM(dev))
  1206. pci_enable_msi(dev->pdev);
  1207. spin_lock_init(&dev_priv->user_irq_lock);
  1208. spin_lock_init(&dev_priv->error_lock);
  1209. dev_priv->user_irq_refcount = 0;
  1210. ret = drm_vblank_init(dev, I915_NUM_PIPE);
  1211. if (ret) {
  1212. (void) i915_driver_unload(dev);
  1213. return ret;
  1214. }
  1215. /* Start out suspended */
  1216. dev_priv->mm.suspended = 1;
  1217. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1218. ret = i915_load_modeset_init(dev, prealloc_start,
  1219. prealloc_size, agp_size);
  1220. if (ret < 0) {
  1221. DRM_ERROR("failed to init modeset\n");
  1222. goto out_workqueue_free;
  1223. }
  1224. }
  1225. /* Must be done after probing outputs */
  1226. /* FIXME: verify on IGDNG */
  1227. if (!IS_IGDNG(dev))
  1228. intel_opregion_init(dev, 0);
  1229. setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
  1230. (unsigned long) dev);
  1231. return 0;
  1232. out_workqueue_free:
  1233. destroy_workqueue(dev_priv->wq);
  1234. out_iomapfree:
  1235. io_mapping_free(dev_priv->mm.gtt_mapping);
  1236. out_rmmap:
  1237. iounmap(dev_priv->regs);
  1238. put_bridge:
  1239. pci_dev_put(dev_priv->bridge_dev);
  1240. free_priv:
  1241. kfree(dev_priv);
  1242. return ret;
  1243. }
  1244. int i915_driver_unload(struct drm_device *dev)
  1245. {
  1246. struct drm_i915_private *dev_priv = dev->dev_private;
  1247. destroy_workqueue(dev_priv->wq);
  1248. del_timer_sync(&dev_priv->hangcheck_timer);
  1249. io_mapping_free(dev_priv->mm.gtt_mapping);
  1250. if (dev_priv->mm.gtt_mtrr >= 0) {
  1251. mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
  1252. dev->agp->agp_info.aper_size * 1024 * 1024);
  1253. dev_priv->mm.gtt_mtrr = -1;
  1254. }
  1255. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1256. drm_irq_uninstall(dev);
  1257. }
  1258. if (dev->pdev->msi_enabled)
  1259. pci_disable_msi(dev->pdev);
  1260. if (dev_priv->regs != NULL)
  1261. iounmap(dev_priv->regs);
  1262. if (!IS_IGDNG(dev))
  1263. intel_opregion_free(dev, 0);
  1264. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1265. intel_modeset_cleanup(dev);
  1266. i915_gem_free_all_phys_object(dev);
  1267. mutex_lock(&dev->struct_mutex);
  1268. i915_gem_cleanup_ringbuffer(dev);
  1269. mutex_unlock(&dev->struct_mutex);
  1270. drm_mm_takedown(&dev_priv->vram);
  1271. i915_gem_lastclose(dev);
  1272. }
  1273. pci_dev_put(dev_priv->bridge_dev);
  1274. kfree(dev->dev_private);
  1275. return 0;
  1276. }
  1277. int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
  1278. {
  1279. struct drm_i915_file_private *i915_file_priv;
  1280. DRM_DEBUG_DRIVER("\n");
  1281. i915_file_priv = (struct drm_i915_file_private *)
  1282. kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
  1283. if (!i915_file_priv)
  1284. return -ENOMEM;
  1285. file_priv->driver_priv = i915_file_priv;
  1286. INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
  1287. return 0;
  1288. }
  1289. /**
  1290. * i915_driver_lastclose - clean up after all DRM clients have exited
  1291. * @dev: DRM device
  1292. *
  1293. * Take care of cleaning up after all DRM clients have exited. In the
  1294. * mode setting case, we want to restore the kernel's initial mode (just
  1295. * in case the last client left us in a bad state).
  1296. *
  1297. * Additionally, in the non-mode setting case, we'll tear down the AGP
  1298. * and DMA structures, since the kernel won't be using them, and clea
  1299. * up any GEM state.
  1300. */
  1301. void i915_driver_lastclose(struct drm_device * dev)
  1302. {
  1303. drm_i915_private_t *dev_priv = dev->dev_private;
  1304. if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
  1305. drm_fb_helper_restore();
  1306. return;
  1307. }
  1308. i915_gem_lastclose(dev);
  1309. if (dev_priv->agp_heap)
  1310. i915_mem_takedown(&(dev_priv->agp_heap));
  1311. i915_dma_cleanup(dev);
  1312. }
  1313. void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
  1314. {
  1315. drm_i915_private_t *dev_priv = dev->dev_private;
  1316. i915_gem_release(dev, file_priv);
  1317. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  1318. i915_mem_release(dev, file_priv, dev_priv->agp_heap);
  1319. }
  1320. void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
  1321. {
  1322. struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
  1323. kfree(i915_file_priv);
  1324. }
  1325. struct drm_ioctl_desc i915_ioctls[] = {
  1326. DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1327. DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
  1328. DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
  1329. DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
  1330. DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
  1331. DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
  1332. DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
  1333. DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1334. DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
  1335. DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
  1336. DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1337. DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
  1338. DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
  1339. DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
  1340. DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
  1341. DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
  1342. DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1343. DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1344. DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
  1345. DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
  1346. DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
  1347. DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
  1348. DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
  1349. DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1350. DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1351. DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
  1352. DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
  1353. DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
  1354. DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
  1355. DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
  1356. DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
  1357. DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
  1358. DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
  1359. DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
  1360. DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
  1361. DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
  1362. DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),
  1363. };
  1364. int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
  1365. /**
  1366. * Determine if the device really is AGP or not.
  1367. *
  1368. * All Intel graphics chipsets are treated as AGP, even if they are really
  1369. * PCI-e.
  1370. *
  1371. * \param dev The device to be tested.
  1372. *
  1373. * \returns
  1374. * A value of 1 is always retured to indictate every i9x5 is AGP.
  1375. */
  1376. int i915_driver_device_is_agp(struct drm_device * dev)
  1377. {
  1378. return 1;
  1379. }