iwl-agn.c 111 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. #include "iwl-agn.h"
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /*
  59. * module name, copyright, version, etc.
  60. */
  61. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  62. #ifdef CONFIG_IWLWIFI_DEBUG
  63. #define VD "d"
  64. #else
  65. #define VD
  66. #endif
  67. #define DRV_VERSION IWLWIFI_VERSION VD
  68. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  69. MODULE_VERSION(DRV_VERSION);
  70. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  71. MODULE_LICENSE("GPL");
  72. MODULE_ALIAS("iwl4965");
  73. /*************** STATION TABLE MANAGEMENT ****
  74. * mac80211 should be examined to determine if sta_info is duplicating
  75. * the functionality provided here
  76. */
  77. /**************************************************************/
  78. /**
  79. * iwl_commit_rxon - commit staging_rxon to hardware
  80. *
  81. * The RXON command in staging_rxon is committed to the hardware and
  82. * the active_rxon structure is updated with the new data. This
  83. * function correctly transitions out of the RXON_ASSOC_MSK state if
  84. * a HW tune is required based on the RXON structure changes.
  85. */
  86. int iwl_commit_rxon(struct iwl_priv *priv)
  87. {
  88. /* cast away the const for active_rxon in this function */
  89. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  90. int ret;
  91. bool new_assoc =
  92. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  93. if (!iwl_is_alive(priv))
  94. return -EBUSY;
  95. /* always get timestamp with Rx frame */
  96. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  97. ret = iwl_check_rxon_cmd(priv);
  98. if (ret) {
  99. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  100. return -EINVAL;
  101. }
  102. /*
  103. * receive commit_rxon request
  104. * abort any previous channel switch if still in process
  105. */
  106. if (priv->switch_rxon.switch_in_progress &&
  107. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  108. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  109. le16_to_cpu(priv->switch_rxon.channel));
  110. priv->switch_rxon.switch_in_progress = false;
  111. }
  112. /* If we don't need to send a full RXON, we can use
  113. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  114. * and other flags for the current radio configuration. */
  115. if (!iwl_full_rxon_required(priv)) {
  116. ret = iwl_send_rxon_assoc(priv);
  117. if (ret) {
  118. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  119. return ret;
  120. }
  121. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  122. iwl_print_rx_config_cmd(priv);
  123. return 0;
  124. }
  125. /* If we are currently associated and the new config requires
  126. * an RXON_ASSOC and the new config wants the associated mask enabled,
  127. * we must clear the associated from the active configuration
  128. * before we apply the new config */
  129. if (iwl_is_associated(priv) && new_assoc) {
  130. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  131. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  132. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  133. sizeof(struct iwl_rxon_cmd),
  134. &priv->active_rxon);
  135. /* If the mask clearing failed then we set
  136. * active_rxon back to what it was previously */
  137. if (ret) {
  138. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  139. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  140. return ret;
  141. }
  142. iwl_clear_ucode_stations(priv, false);
  143. iwl_restore_stations(priv);
  144. }
  145. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  146. "* with%s RXON_FILTER_ASSOC_MSK\n"
  147. "* channel = %d\n"
  148. "* bssid = %pM\n",
  149. (new_assoc ? "" : "out"),
  150. le16_to_cpu(priv->staging_rxon.channel),
  151. priv->staging_rxon.bssid_addr);
  152. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  153. /* Apply the new configuration
  154. * RXON unassoc clears the station table in uCode so restoration of
  155. * stations is needed after it (the RXON command) completes
  156. */
  157. if (!new_assoc) {
  158. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  159. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  160. if (ret) {
  161. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  162. return ret;
  163. }
  164. IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON. \n");
  165. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  166. iwl_clear_ucode_stations(priv, false);
  167. iwl_restore_stations(priv);
  168. }
  169. priv->start_calib = 0;
  170. if (new_assoc) {
  171. /*
  172. * allow CTS-to-self if possible for new association.
  173. * this is relevant only for 5000 series and up,
  174. * but will not damage 4965
  175. */
  176. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  177. /* Apply the new configuration
  178. * RXON assoc doesn't clear the station table in uCode,
  179. */
  180. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  181. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  182. if (ret) {
  183. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  184. return ret;
  185. }
  186. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  187. }
  188. iwl_print_rx_config_cmd(priv);
  189. iwl_init_sensitivity(priv);
  190. /* If we issue a new RXON command which required a tune then we must
  191. * send a new TXPOWER command or we won't be able to Tx any frames */
  192. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  193. if (ret) {
  194. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  195. return ret;
  196. }
  197. return 0;
  198. }
  199. void iwl_update_chain_flags(struct iwl_priv *priv)
  200. {
  201. if (priv->cfg->ops->hcmd->set_rxon_chain)
  202. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  203. iwlcore_commit_rxon(priv);
  204. }
  205. static void iwl_clear_free_frames(struct iwl_priv *priv)
  206. {
  207. struct list_head *element;
  208. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  209. priv->frames_count);
  210. while (!list_empty(&priv->free_frames)) {
  211. element = priv->free_frames.next;
  212. list_del(element);
  213. kfree(list_entry(element, struct iwl_frame, list));
  214. priv->frames_count--;
  215. }
  216. if (priv->frames_count) {
  217. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  218. priv->frames_count);
  219. priv->frames_count = 0;
  220. }
  221. }
  222. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  223. {
  224. struct iwl_frame *frame;
  225. struct list_head *element;
  226. if (list_empty(&priv->free_frames)) {
  227. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  228. if (!frame) {
  229. IWL_ERR(priv, "Could not allocate frame!\n");
  230. return NULL;
  231. }
  232. priv->frames_count++;
  233. return frame;
  234. }
  235. element = priv->free_frames.next;
  236. list_del(element);
  237. return list_entry(element, struct iwl_frame, list);
  238. }
  239. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  240. {
  241. memset(frame, 0, sizeof(*frame));
  242. list_add(&frame->list, &priv->free_frames);
  243. }
  244. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  245. struct ieee80211_hdr *hdr,
  246. int left)
  247. {
  248. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  249. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  250. (priv->iw_mode != NL80211_IFTYPE_AP)))
  251. return 0;
  252. if (priv->ibss_beacon->len > left)
  253. return 0;
  254. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  255. return priv->ibss_beacon->len;
  256. }
  257. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  258. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  259. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  260. u8 *beacon, u32 frame_size)
  261. {
  262. u16 tim_idx;
  263. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  264. /*
  265. * The index is relative to frame start but we start looking at the
  266. * variable-length part of the beacon.
  267. */
  268. tim_idx = mgmt->u.beacon.variable - beacon;
  269. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  270. while ((tim_idx < (frame_size - 2)) &&
  271. (beacon[tim_idx] != WLAN_EID_TIM))
  272. tim_idx += beacon[tim_idx+1] + 2;
  273. /* If TIM field was found, set variables */
  274. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  275. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  276. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  277. } else
  278. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  279. }
  280. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  281. struct iwl_frame *frame)
  282. {
  283. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  284. u32 frame_size;
  285. u32 rate_flags;
  286. u32 rate;
  287. /*
  288. * We have to set up the TX command, the TX Beacon command, and the
  289. * beacon contents.
  290. */
  291. /* Initialize memory */
  292. tx_beacon_cmd = &frame->u.beacon;
  293. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  294. /* Set up TX beacon contents */
  295. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  296. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  297. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  298. return 0;
  299. /* Set up TX command fields */
  300. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  301. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  302. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  303. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  304. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  305. /* Set up TX beacon command fields */
  306. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  307. frame_size);
  308. /* Set up packet rate and flags */
  309. rate = iwl_rate_get_lowest_plcp(priv);
  310. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  311. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  312. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  313. rate_flags |= RATE_MCS_CCK_MSK;
  314. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  315. rate_flags);
  316. return sizeof(*tx_beacon_cmd) + frame_size;
  317. }
  318. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  319. {
  320. struct iwl_frame *frame;
  321. unsigned int frame_size;
  322. int rc;
  323. frame = iwl_get_free_frame(priv);
  324. if (!frame) {
  325. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  326. "command.\n");
  327. return -ENOMEM;
  328. }
  329. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  330. if (!frame_size) {
  331. IWL_ERR(priv, "Error configuring the beacon command\n");
  332. iwl_free_frame(priv, frame);
  333. return -EINVAL;
  334. }
  335. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  336. &frame->u.cmd[0]);
  337. iwl_free_frame(priv, frame);
  338. return rc;
  339. }
  340. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  341. {
  342. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  343. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  344. if (sizeof(dma_addr_t) > sizeof(u32))
  345. addr |=
  346. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  347. return addr;
  348. }
  349. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  350. {
  351. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  352. return le16_to_cpu(tb->hi_n_len) >> 4;
  353. }
  354. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  355. dma_addr_t addr, u16 len)
  356. {
  357. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  358. u16 hi_n_len = len << 4;
  359. put_unaligned_le32(addr, &tb->lo);
  360. if (sizeof(dma_addr_t) > sizeof(u32))
  361. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  362. tb->hi_n_len = cpu_to_le16(hi_n_len);
  363. tfd->num_tbs = idx + 1;
  364. }
  365. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  366. {
  367. return tfd->num_tbs & 0x1f;
  368. }
  369. /**
  370. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  371. * @priv - driver private data
  372. * @txq - tx queue
  373. *
  374. * Does NOT advance any TFD circular buffer read/write indexes
  375. * Does NOT free the TFD itself (which is within circular buffer)
  376. */
  377. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  378. {
  379. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  380. struct iwl_tfd *tfd;
  381. struct pci_dev *dev = priv->pci_dev;
  382. int index = txq->q.read_ptr;
  383. int i;
  384. int num_tbs;
  385. tfd = &tfd_tmp[index];
  386. /* Sanity check on number of chunks */
  387. num_tbs = iwl_tfd_get_num_tbs(tfd);
  388. if (num_tbs >= IWL_NUM_OF_TBS) {
  389. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  390. /* @todo issue fatal error, it is quite serious situation */
  391. return;
  392. }
  393. /* Unmap tx_cmd */
  394. if (num_tbs)
  395. pci_unmap_single(dev,
  396. pci_unmap_addr(&txq->meta[index], mapping),
  397. pci_unmap_len(&txq->meta[index], len),
  398. PCI_DMA_BIDIRECTIONAL);
  399. /* Unmap chunks, if any. */
  400. for (i = 1; i < num_tbs; i++) {
  401. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  402. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  403. if (txq->txb) {
  404. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  405. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  406. }
  407. }
  408. }
  409. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  410. struct iwl_tx_queue *txq,
  411. dma_addr_t addr, u16 len,
  412. u8 reset, u8 pad)
  413. {
  414. struct iwl_queue *q;
  415. struct iwl_tfd *tfd, *tfd_tmp;
  416. u32 num_tbs;
  417. q = &txq->q;
  418. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  419. tfd = &tfd_tmp[q->write_ptr];
  420. if (reset)
  421. memset(tfd, 0, sizeof(*tfd));
  422. num_tbs = iwl_tfd_get_num_tbs(tfd);
  423. /* Each TFD can point to a maximum 20 Tx buffers */
  424. if (num_tbs >= IWL_NUM_OF_TBS) {
  425. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  426. IWL_NUM_OF_TBS);
  427. return -EINVAL;
  428. }
  429. BUG_ON(addr & ~DMA_BIT_MASK(36));
  430. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  431. IWL_ERR(priv, "Unaligned address = %llx\n",
  432. (unsigned long long)addr);
  433. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  434. return 0;
  435. }
  436. /*
  437. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  438. * given Tx queue, and enable the DMA channel used for that queue.
  439. *
  440. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  441. * channels supported in hardware.
  442. */
  443. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  444. struct iwl_tx_queue *txq)
  445. {
  446. int txq_id = txq->q.id;
  447. /* Circular buffer (TFD queue in DRAM) physical base address */
  448. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  449. txq->q.dma_addr >> 8);
  450. return 0;
  451. }
  452. /******************************************************************************
  453. *
  454. * Generic RX handler implementations
  455. *
  456. ******************************************************************************/
  457. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  458. struct iwl_rx_mem_buffer *rxb)
  459. {
  460. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  461. struct iwl_alive_resp *palive;
  462. struct delayed_work *pwork;
  463. palive = &pkt->u.alive_frame;
  464. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  465. "0x%01X 0x%01X\n",
  466. palive->is_valid, palive->ver_type,
  467. palive->ver_subtype);
  468. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  469. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  470. memcpy(&priv->card_alive_init,
  471. &pkt->u.alive_frame,
  472. sizeof(struct iwl_init_alive_resp));
  473. pwork = &priv->init_alive_start;
  474. } else {
  475. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  476. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  477. sizeof(struct iwl_alive_resp));
  478. pwork = &priv->alive_start;
  479. }
  480. /* We delay the ALIVE response by 5ms to
  481. * give the HW RF Kill time to activate... */
  482. if (palive->is_valid == UCODE_VALID_OK)
  483. queue_delayed_work(priv->workqueue, pwork,
  484. msecs_to_jiffies(5));
  485. else
  486. IWL_WARN(priv, "uCode did not respond OK.\n");
  487. }
  488. static void iwl_bg_beacon_update(struct work_struct *work)
  489. {
  490. struct iwl_priv *priv =
  491. container_of(work, struct iwl_priv, beacon_update);
  492. struct sk_buff *beacon;
  493. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  494. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  495. if (!beacon) {
  496. IWL_ERR(priv, "update beacon failed\n");
  497. return;
  498. }
  499. mutex_lock(&priv->mutex);
  500. /* new beacon skb is allocated every time; dispose previous.*/
  501. if (priv->ibss_beacon)
  502. dev_kfree_skb(priv->ibss_beacon);
  503. priv->ibss_beacon = beacon;
  504. mutex_unlock(&priv->mutex);
  505. iwl_send_beacon_cmd(priv);
  506. }
  507. /**
  508. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  509. *
  510. * This callback is provided in order to send a statistics request.
  511. *
  512. * This timer function is continually reset to execute within
  513. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  514. * was received. We need to ensure we receive the statistics in order
  515. * to update the temperature used for calibrating the TXPOWER.
  516. */
  517. static void iwl_bg_statistics_periodic(unsigned long data)
  518. {
  519. struct iwl_priv *priv = (struct iwl_priv *)data;
  520. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  521. return;
  522. /* dont send host command if rf-kill is on */
  523. if (!iwl_is_ready_rf(priv))
  524. return;
  525. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  526. }
  527. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  528. u32 start_idx, u32 num_events,
  529. u32 mode)
  530. {
  531. u32 i;
  532. u32 ptr; /* SRAM byte address of log data */
  533. u32 ev, time, data; /* event log data */
  534. unsigned long reg_flags;
  535. if (mode == 0)
  536. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  537. else
  538. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  539. /* Make sure device is powered up for SRAM reads */
  540. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  541. if (iwl_grab_nic_access(priv)) {
  542. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  543. return;
  544. }
  545. /* Set starting address; reads will auto-increment */
  546. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  547. rmb();
  548. /*
  549. * "time" is actually "data" for mode 0 (no timestamp).
  550. * place event id # at far right for easier visual parsing.
  551. */
  552. for (i = 0; i < num_events; i++) {
  553. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  554. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  555. if (mode == 0) {
  556. trace_iwlwifi_dev_ucode_cont_event(priv,
  557. 0, time, ev);
  558. } else {
  559. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  560. trace_iwlwifi_dev_ucode_cont_event(priv,
  561. time, data, ev);
  562. }
  563. }
  564. /* Allow device to power down */
  565. iwl_release_nic_access(priv);
  566. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  567. }
  568. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  569. {
  570. u32 capacity; /* event log capacity in # entries */
  571. u32 base; /* SRAM byte address of event log header */
  572. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  573. u32 num_wraps; /* # times uCode wrapped to top of log */
  574. u32 next_entry; /* index of next entry to be written by uCode */
  575. if (priv->ucode_type == UCODE_INIT)
  576. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  577. else
  578. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  579. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  580. capacity = iwl_read_targ_mem(priv, base);
  581. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  582. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  583. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  584. } else
  585. return;
  586. if (num_wraps == priv->event_log.num_wraps) {
  587. iwl_print_cont_event_trace(priv,
  588. base, priv->event_log.next_entry,
  589. next_entry - priv->event_log.next_entry,
  590. mode);
  591. priv->event_log.non_wraps_count++;
  592. } else {
  593. if ((num_wraps - priv->event_log.num_wraps) > 1)
  594. priv->event_log.wraps_more_count++;
  595. else
  596. priv->event_log.wraps_once_count++;
  597. trace_iwlwifi_dev_ucode_wrap_event(priv,
  598. num_wraps - priv->event_log.num_wraps,
  599. next_entry, priv->event_log.next_entry);
  600. if (next_entry < priv->event_log.next_entry) {
  601. iwl_print_cont_event_trace(priv, base,
  602. priv->event_log.next_entry,
  603. capacity - priv->event_log.next_entry,
  604. mode);
  605. iwl_print_cont_event_trace(priv, base, 0,
  606. next_entry, mode);
  607. } else {
  608. iwl_print_cont_event_trace(priv, base,
  609. next_entry, capacity - next_entry,
  610. mode);
  611. iwl_print_cont_event_trace(priv, base, 0,
  612. next_entry, mode);
  613. }
  614. }
  615. priv->event_log.num_wraps = num_wraps;
  616. priv->event_log.next_entry = next_entry;
  617. }
  618. /**
  619. * iwl_bg_ucode_trace - Timer callback to log ucode event
  620. *
  621. * The timer is continually set to execute every
  622. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  623. * this function is to perform continuous uCode event logging operation
  624. * if enabled
  625. */
  626. static void iwl_bg_ucode_trace(unsigned long data)
  627. {
  628. struct iwl_priv *priv = (struct iwl_priv *)data;
  629. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  630. return;
  631. if (priv->event_log.ucode_trace) {
  632. iwl_continuous_event_trace(priv);
  633. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  634. mod_timer(&priv->ucode_trace,
  635. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  636. }
  637. }
  638. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  639. struct iwl_rx_mem_buffer *rxb)
  640. {
  641. #ifdef CONFIG_IWLWIFI_DEBUG
  642. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  643. struct iwl4965_beacon_notif *beacon =
  644. (struct iwl4965_beacon_notif *)pkt->u.raw;
  645. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  646. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  647. "tsf %d %d rate %d\n",
  648. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  649. beacon->beacon_notify_hdr.failure_frame,
  650. le32_to_cpu(beacon->ibss_mgr_status),
  651. le32_to_cpu(beacon->high_tsf),
  652. le32_to_cpu(beacon->low_tsf), rate);
  653. #endif
  654. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  655. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  656. queue_work(priv->workqueue, &priv->beacon_update);
  657. }
  658. /* Handle notification from uCode that card's power state is changing
  659. * due to software, hardware, or critical temperature RFKILL */
  660. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  661. struct iwl_rx_mem_buffer *rxb)
  662. {
  663. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  664. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  665. unsigned long status = priv->status;
  666. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  667. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  668. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  669. (flags & CT_CARD_DISABLED) ?
  670. "Reached" : "Not reached");
  671. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  672. CT_CARD_DISABLED)) {
  673. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  674. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  675. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  676. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  677. if (!(flags & RXON_CARD_DISABLED)) {
  678. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  679. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  680. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  681. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  682. }
  683. if (flags & CT_CARD_DISABLED)
  684. iwl_tt_enter_ct_kill(priv);
  685. }
  686. if (!(flags & CT_CARD_DISABLED))
  687. iwl_tt_exit_ct_kill(priv);
  688. if (flags & HW_CARD_DISABLED)
  689. set_bit(STATUS_RF_KILL_HW, &priv->status);
  690. else
  691. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  692. if (!(flags & RXON_CARD_DISABLED))
  693. iwl_scan_cancel(priv);
  694. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  695. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  696. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  697. test_bit(STATUS_RF_KILL_HW, &priv->status));
  698. else
  699. wake_up_interruptible(&priv->wait_command_queue);
  700. }
  701. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  702. {
  703. if (src == IWL_PWR_SRC_VAUX) {
  704. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  705. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  706. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  707. ~APMG_PS_CTRL_MSK_PWR_SRC);
  708. } else {
  709. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  710. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  711. ~APMG_PS_CTRL_MSK_PWR_SRC);
  712. }
  713. return 0;
  714. }
  715. /**
  716. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  717. *
  718. * Setup the RX handlers for each of the reply types sent from the uCode
  719. * to the host.
  720. *
  721. * This function chains into the hardware specific files for them to setup
  722. * any hardware specific handlers as well.
  723. */
  724. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  725. {
  726. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  727. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  728. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  729. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  730. iwl_rx_spectrum_measure_notif;
  731. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  732. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  733. iwl_rx_pm_debug_statistics_notif;
  734. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  735. /*
  736. * The same handler is used for both the REPLY to a discrete
  737. * statistics request from the host as well as for the periodic
  738. * statistics notifications (after received beacons) from the uCode.
  739. */
  740. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  741. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  742. iwl_setup_rx_scan_handlers(priv);
  743. /* status change handler */
  744. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  745. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  746. iwl_rx_missed_beacon_notif;
  747. /* Rx handlers */
  748. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  749. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  750. /* block ack */
  751. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
  752. /* Set up hardware specific Rx handlers */
  753. priv->cfg->ops->lib->rx_handler_setup(priv);
  754. }
  755. /**
  756. * iwl_rx_handle - Main entry function for receiving responses from uCode
  757. *
  758. * Uses the priv->rx_handlers callback function array to invoke
  759. * the appropriate handlers, including command responses,
  760. * frame-received notifications, and other notifications.
  761. */
  762. void iwl_rx_handle(struct iwl_priv *priv)
  763. {
  764. struct iwl_rx_mem_buffer *rxb;
  765. struct iwl_rx_packet *pkt;
  766. struct iwl_rx_queue *rxq = &priv->rxq;
  767. u32 r, i;
  768. int reclaim;
  769. unsigned long flags;
  770. u8 fill_rx = 0;
  771. u32 count = 8;
  772. int total_empty;
  773. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  774. * buffer that the driver may process (last buffer filled by ucode). */
  775. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  776. i = rxq->read;
  777. /* Rx interrupt, but nothing sent from uCode */
  778. if (i == r)
  779. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  780. /* calculate total frames need to be restock after handling RX */
  781. total_empty = r - rxq->write_actual;
  782. if (total_empty < 0)
  783. total_empty += RX_QUEUE_SIZE;
  784. if (total_empty > (RX_QUEUE_SIZE / 2))
  785. fill_rx = 1;
  786. while (i != r) {
  787. rxb = rxq->queue[i];
  788. /* If an RXB doesn't have a Rx queue slot associated with it,
  789. * then a bug has been introduced in the queue refilling
  790. * routines -- catch it here */
  791. BUG_ON(rxb == NULL);
  792. rxq->queue[i] = NULL;
  793. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  794. PAGE_SIZE << priv->hw_params.rx_page_order,
  795. PCI_DMA_FROMDEVICE);
  796. pkt = rxb_addr(rxb);
  797. trace_iwlwifi_dev_rx(priv, pkt,
  798. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  799. /* Reclaim a command buffer only if this packet is a response
  800. * to a (driver-originated) command.
  801. * If the packet (e.g. Rx frame) originated from uCode,
  802. * there is no command buffer to reclaim.
  803. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  804. * but apparently a few don't get set; catch them here. */
  805. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  806. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  807. (pkt->hdr.cmd != REPLY_RX) &&
  808. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  809. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  810. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  811. (pkt->hdr.cmd != REPLY_TX);
  812. /* Based on type of command response or notification,
  813. * handle those that need handling via function in
  814. * rx_handlers table. See iwl_setup_rx_handlers() */
  815. if (priv->rx_handlers[pkt->hdr.cmd]) {
  816. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  817. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  818. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  819. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  820. } else {
  821. /* No handling needed */
  822. IWL_DEBUG_RX(priv,
  823. "r %d i %d No handler needed for %s, 0x%02x\n",
  824. r, i, get_cmd_string(pkt->hdr.cmd),
  825. pkt->hdr.cmd);
  826. }
  827. /*
  828. * XXX: After here, we should always check rxb->page
  829. * against NULL before touching it or its virtual
  830. * memory (pkt). Because some rx_handler might have
  831. * already taken or freed the pages.
  832. */
  833. if (reclaim) {
  834. /* Invoke any callbacks, transfer the buffer to caller,
  835. * and fire off the (possibly) blocking iwl_send_cmd()
  836. * as we reclaim the driver command queue */
  837. if (rxb->page)
  838. iwl_tx_cmd_complete(priv, rxb);
  839. else
  840. IWL_WARN(priv, "Claim null rxb?\n");
  841. }
  842. /* Reuse the page if possible. For notification packets and
  843. * SKBs that fail to Rx correctly, add them back into the
  844. * rx_free list for reuse later. */
  845. spin_lock_irqsave(&rxq->lock, flags);
  846. if (rxb->page != NULL) {
  847. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  848. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  849. PCI_DMA_FROMDEVICE);
  850. list_add_tail(&rxb->list, &rxq->rx_free);
  851. rxq->free_count++;
  852. } else
  853. list_add_tail(&rxb->list, &rxq->rx_used);
  854. spin_unlock_irqrestore(&rxq->lock, flags);
  855. i = (i + 1) & RX_QUEUE_MASK;
  856. /* If there are a lot of unused frames,
  857. * restock the Rx queue so ucode wont assert. */
  858. if (fill_rx) {
  859. count++;
  860. if (count >= 8) {
  861. rxq->read = i;
  862. iwl_rx_replenish_now(priv);
  863. count = 0;
  864. }
  865. }
  866. }
  867. /* Backtrack one entry */
  868. rxq->read = i;
  869. if (fill_rx)
  870. iwl_rx_replenish_now(priv);
  871. else
  872. iwl_rx_queue_restock(priv);
  873. }
  874. /* call this function to flush any scheduled tasklet */
  875. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  876. {
  877. /* wait to make sure we flush pending tasklet*/
  878. synchronize_irq(priv->pci_dev->irq);
  879. tasklet_kill(&priv->irq_tasklet);
  880. }
  881. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  882. {
  883. u32 inta, handled = 0;
  884. u32 inta_fh;
  885. unsigned long flags;
  886. u32 i;
  887. #ifdef CONFIG_IWLWIFI_DEBUG
  888. u32 inta_mask;
  889. #endif
  890. spin_lock_irqsave(&priv->lock, flags);
  891. /* Ack/clear/reset pending uCode interrupts.
  892. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  893. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  894. inta = iwl_read32(priv, CSR_INT);
  895. iwl_write32(priv, CSR_INT, inta);
  896. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  897. * Any new interrupts that happen after this, either while we're
  898. * in this tasklet, or later, will show up in next ISR/tasklet. */
  899. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  900. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  901. #ifdef CONFIG_IWLWIFI_DEBUG
  902. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  903. /* just for debug */
  904. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  905. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  906. inta, inta_mask, inta_fh);
  907. }
  908. #endif
  909. spin_unlock_irqrestore(&priv->lock, flags);
  910. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  911. * atomic, make sure that inta covers all the interrupts that
  912. * we've discovered, even if FH interrupt came in just after
  913. * reading CSR_INT. */
  914. if (inta_fh & CSR49_FH_INT_RX_MASK)
  915. inta |= CSR_INT_BIT_FH_RX;
  916. if (inta_fh & CSR49_FH_INT_TX_MASK)
  917. inta |= CSR_INT_BIT_FH_TX;
  918. /* Now service all interrupt bits discovered above. */
  919. if (inta & CSR_INT_BIT_HW_ERR) {
  920. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  921. /* Tell the device to stop sending interrupts */
  922. iwl_disable_interrupts(priv);
  923. priv->isr_stats.hw++;
  924. iwl_irq_handle_error(priv);
  925. handled |= CSR_INT_BIT_HW_ERR;
  926. return;
  927. }
  928. #ifdef CONFIG_IWLWIFI_DEBUG
  929. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  930. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  931. if (inta & CSR_INT_BIT_SCD) {
  932. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  933. "the frame/frames.\n");
  934. priv->isr_stats.sch++;
  935. }
  936. /* Alive notification via Rx interrupt will do the real work */
  937. if (inta & CSR_INT_BIT_ALIVE) {
  938. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  939. priv->isr_stats.alive++;
  940. }
  941. }
  942. #endif
  943. /* Safely ignore these bits for debug checks below */
  944. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  945. /* HW RF KILL switch toggled */
  946. if (inta & CSR_INT_BIT_RF_KILL) {
  947. int hw_rf_kill = 0;
  948. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  949. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  950. hw_rf_kill = 1;
  951. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  952. hw_rf_kill ? "disable radio" : "enable radio");
  953. priv->isr_stats.rfkill++;
  954. /* driver only loads ucode once setting the interface up.
  955. * the driver allows loading the ucode even if the radio
  956. * is killed. Hence update the killswitch state here. The
  957. * rfkill handler will care about restarting if needed.
  958. */
  959. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  960. if (hw_rf_kill)
  961. set_bit(STATUS_RF_KILL_HW, &priv->status);
  962. else
  963. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  964. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  965. }
  966. handled |= CSR_INT_BIT_RF_KILL;
  967. }
  968. /* Chip got too hot and stopped itself */
  969. if (inta & CSR_INT_BIT_CT_KILL) {
  970. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  971. priv->isr_stats.ctkill++;
  972. handled |= CSR_INT_BIT_CT_KILL;
  973. }
  974. /* Error detected by uCode */
  975. if (inta & CSR_INT_BIT_SW_ERR) {
  976. IWL_ERR(priv, "Microcode SW error detected. "
  977. " Restarting 0x%X.\n", inta);
  978. priv->isr_stats.sw++;
  979. priv->isr_stats.sw_err = inta;
  980. iwl_irq_handle_error(priv);
  981. handled |= CSR_INT_BIT_SW_ERR;
  982. }
  983. /*
  984. * uCode wakes up after power-down sleep.
  985. * Tell device about any new tx or host commands enqueued,
  986. * and about any Rx buffers made available while asleep.
  987. */
  988. if (inta & CSR_INT_BIT_WAKEUP) {
  989. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  990. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  991. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  992. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  993. priv->isr_stats.wakeup++;
  994. handled |= CSR_INT_BIT_WAKEUP;
  995. }
  996. /* All uCode command responses, including Tx command responses,
  997. * Rx "responses" (frame-received notification), and other
  998. * notifications from uCode come through here*/
  999. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1000. iwl_rx_handle(priv);
  1001. priv->isr_stats.rx++;
  1002. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1003. }
  1004. /* This "Tx" DMA channel is used only for loading uCode */
  1005. if (inta & CSR_INT_BIT_FH_TX) {
  1006. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1007. priv->isr_stats.tx++;
  1008. handled |= CSR_INT_BIT_FH_TX;
  1009. /* Wake up uCode load routine, now that load is complete */
  1010. priv->ucode_write_complete = 1;
  1011. wake_up_interruptible(&priv->wait_command_queue);
  1012. }
  1013. if (inta & ~handled) {
  1014. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1015. priv->isr_stats.unhandled++;
  1016. }
  1017. if (inta & ~(priv->inta_mask)) {
  1018. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1019. inta & ~priv->inta_mask);
  1020. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1021. }
  1022. /* Re-enable all interrupts */
  1023. /* only Re-enable if diabled by irq */
  1024. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1025. iwl_enable_interrupts(priv);
  1026. #ifdef CONFIG_IWLWIFI_DEBUG
  1027. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1028. inta = iwl_read32(priv, CSR_INT);
  1029. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1030. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1031. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1032. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1033. }
  1034. #endif
  1035. }
  1036. /* tasklet for iwlagn interrupt */
  1037. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1038. {
  1039. u32 inta = 0;
  1040. u32 handled = 0;
  1041. unsigned long flags;
  1042. u32 i;
  1043. #ifdef CONFIG_IWLWIFI_DEBUG
  1044. u32 inta_mask;
  1045. #endif
  1046. spin_lock_irqsave(&priv->lock, flags);
  1047. /* Ack/clear/reset pending uCode interrupts.
  1048. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1049. */
  1050. iwl_write32(priv, CSR_INT, priv->_agn.inta);
  1051. inta = priv->_agn.inta;
  1052. #ifdef CONFIG_IWLWIFI_DEBUG
  1053. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1054. /* just for debug */
  1055. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1056. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1057. inta, inta_mask);
  1058. }
  1059. #endif
  1060. spin_unlock_irqrestore(&priv->lock, flags);
  1061. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  1062. priv->_agn.inta = 0;
  1063. /* Now service all interrupt bits discovered above. */
  1064. if (inta & CSR_INT_BIT_HW_ERR) {
  1065. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1066. /* Tell the device to stop sending interrupts */
  1067. iwl_disable_interrupts(priv);
  1068. priv->isr_stats.hw++;
  1069. iwl_irq_handle_error(priv);
  1070. handled |= CSR_INT_BIT_HW_ERR;
  1071. return;
  1072. }
  1073. #ifdef CONFIG_IWLWIFI_DEBUG
  1074. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1075. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1076. if (inta & CSR_INT_BIT_SCD) {
  1077. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1078. "the frame/frames.\n");
  1079. priv->isr_stats.sch++;
  1080. }
  1081. /* Alive notification via Rx interrupt will do the real work */
  1082. if (inta & CSR_INT_BIT_ALIVE) {
  1083. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1084. priv->isr_stats.alive++;
  1085. }
  1086. }
  1087. #endif
  1088. /* Safely ignore these bits for debug checks below */
  1089. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1090. /* HW RF KILL switch toggled */
  1091. if (inta & CSR_INT_BIT_RF_KILL) {
  1092. int hw_rf_kill = 0;
  1093. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1094. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1095. hw_rf_kill = 1;
  1096. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1097. hw_rf_kill ? "disable radio" : "enable radio");
  1098. priv->isr_stats.rfkill++;
  1099. /* driver only loads ucode once setting the interface up.
  1100. * the driver allows loading the ucode even if the radio
  1101. * is killed. Hence update the killswitch state here. The
  1102. * rfkill handler will care about restarting if needed.
  1103. */
  1104. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1105. if (hw_rf_kill)
  1106. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1107. else
  1108. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1109. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1110. }
  1111. handled |= CSR_INT_BIT_RF_KILL;
  1112. }
  1113. /* Chip got too hot and stopped itself */
  1114. if (inta & CSR_INT_BIT_CT_KILL) {
  1115. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1116. priv->isr_stats.ctkill++;
  1117. handled |= CSR_INT_BIT_CT_KILL;
  1118. }
  1119. /* Error detected by uCode */
  1120. if (inta & CSR_INT_BIT_SW_ERR) {
  1121. IWL_ERR(priv, "Microcode SW error detected. "
  1122. " Restarting 0x%X.\n", inta);
  1123. priv->isr_stats.sw++;
  1124. priv->isr_stats.sw_err = inta;
  1125. iwl_irq_handle_error(priv);
  1126. handled |= CSR_INT_BIT_SW_ERR;
  1127. }
  1128. /* uCode wakes up after power-down sleep */
  1129. if (inta & CSR_INT_BIT_WAKEUP) {
  1130. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1131. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1132. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1133. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1134. priv->isr_stats.wakeup++;
  1135. handled |= CSR_INT_BIT_WAKEUP;
  1136. }
  1137. /* All uCode command responses, including Tx command responses,
  1138. * Rx "responses" (frame-received notification), and other
  1139. * notifications from uCode come through here*/
  1140. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1141. CSR_INT_BIT_RX_PERIODIC)) {
  1142. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1143. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1144. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1145. iwl_write32(priv, CSR_FH_INT_STATUS,
  1146. CSR49_FH_INT_RX_MASK);
  1147. }
  1148. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1149. handled |= CSR_INT_BIT_RX_PERIODIC;
  1150. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1151. }
  1152. /* Sending RX interrupt require many steps to be done in the
  1153. * the device:
  1154. * 1- write interrupt to current index in ICT table.
  1155. * 2- dma RX frame.
  1156. * 3- update RX shared data to indicate last write index.
  1157. * 4- send interrupt.
  1158. * This could lead to RX race, driver could receive RX interrupt
  1159. * but the shared data changes does not reflect this;
  1160. * periodic interrupt will detect any dangling Rx activity.
  1161. */
  1162. /* Disable periodic interrupt; we use it as just a one-shot. */
  1163. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1164. CSR_INT_PERIODIC_DIS);
  1165. iwl_rx_handle(priv);
  1166. /*
  1167. * Enable periodic interrupt in 8 msec only if we received
  1168. * real RX interrupt (instead of just periodic int), to catch
  1169. * any dangling Rx interrupt. If it was just the periodic
  1170. * interrupt, there was no dangling Rx activity, and no need
  1171. * to extend the periodic interrupt; one-shot is enough.
  1172. */
  1173. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1174. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1175. CSR_INT_PERIODIC_ENA);
  1176. priv->isr_stats.rx++;
  1177. }
  1178. /* This "Tx" DMA channel is used only for loading uCode */
  1179. if (inta & CSR_INT_BIT_FH_TX) {
  1180. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1181. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1182. priv->isr_stats.tx++;
  1183. handled |= CSR_INT_BIT_FH_TX;
  1184. /* Wake up uCode load routine, now that load is complete */
  1185. priv->ucode_write_complete = 1;
  1186. wake_up_interruptible(&priv->wait_command_queue);
  1187. }
  1188. if (inta & ~handled) {
  1189. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1190. priv->isr_stats.unhandled++;
  1191. }
  1192. if (inta & ~(priv->inta_mask)) {
  1193. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1194. inta & ~priv->inta_mask);
  1195. }
  1196. /* Re-enable all interrupts */
  1197. /* only Re-enable if diabled by irq */
  1198. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1199. iwl_enable_interrupts(priv);
  1200. }
  1201. /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
  1202. #define ACK_CNT_RATIO (50)
  1203. #define BA_TIMEOUT_CNT (5)
  1204. #define BA_TIMEOUT_MAX (16)
  1205. /**
  1206. * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
  1207. *
  1208. * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
  1209. * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
  1210. * operation state.
  1211. */
  1212. bool iwl_good_ack_health(struct iwl_priv *priv,
  1213. struct iwl_rx_packet *pkt)
  1214. {
  1215. bool rc = true;
  1216. int actual_ack_cnt_delta, expected_ack_cnt_delta;
  1217. int ba_timeout_delta;
  1218. actual_ack_cnt_delta =
  1219. le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
  1220. le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
  1221. expected_ack_cnt_delta =
  1222. le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
  1223. le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
  1224. ba_timeout_delta =
  1225. le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
  1226. le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
  1227. if ((priv->_agn.agg_tids_count > 0) &&
  1228. (expected_ack_cnt_delta > 0) &&
  1229. (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
  1230. < ACK_CNT_RATIO) &&
  1231. (ba_timeout_delta > BA_TIMEOUT_CNT)) {
  1232. IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
  1233. " expected_ack_cnt = %d\n",
  1234. actual_ack_cnt_delta, expected_ack_cnt_delta);
  1235. #ifdef CONFIG_IWLWIFI_DEBUG
  1236. IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
  1237. priv->delta_statistics.tx.rx_detected_cnt);
  1238. IWL_DEBUG_RADIO(priv,
  1239. "ack_or_ba_timeout_collision delta = %d\n",
  1240. priv->delta_statistics.tx.
  1241. ack_or_ba_timeout_collision);
  1242. #endif
  1243. IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
  1244. ba_timeout_delta);
  1245. if (!actual_ack_cnt_delta &&
  1246. (ba_timeout_delta >= BA_TIMEOUT_MAX))
  1247. rc = false;
  1248. }
  1249. return rc;
  1250. }
  1251. /******************************************************************************
  1252. *
  1253. * uCode download functions
  1254. *
  1255. ******************************************************************************/
  1256. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1257. {
  1258. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1259. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1260. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1261. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1262. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1263. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1264. }
  1265. static void iwl_nic_start(struct iwl_priv *priv)
  1266. {
  1267. /* Remove all resets to allow NIC to operate */
  1268. iwl_write32(priv, CSR_RESET, 0);
  1269. }
  1270. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1271. static int iwl_mac_setup_register(struct iwl_priv *priv);
  1272. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1273. {
  1274. const char *name_pre = priv->cfg->fw_name_pre;
  1275. if (first)
  1276. priv->fw_index = priv->cfg->ucode_api_max;
  1277. else
  1278. priv->fw_index--;
  1279. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1280. IWL_ERR(priv, "no suitable firmware found!\n");
  1281. return -ENOENT;
  1282. }
  1283. sprintf(priv->firmware_name, "%s%d%s",
  1284. name_pre, priv->fw_index, ".ucode");
  1285. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  1286. priv->firmware_name);
  1287. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1288. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1289. iwl_ucode_callback);
  1290. }
  1291. /**
  1292. * iwl_ucode_callback - callback when firmware was loaded
  1293. *
  1294. * If loaded successfully, copies the firmware into buffers
  1295. * for the card to fetch (via DMA).
  1296. */
  1297. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1298. {
  1299. struct iwl_priv *priv = context;
  1300. struct iwl_ucode_header *ucode;
  1301. const unsigned int api_max = priv->cfg->ucode_api_max;
  1302. const unsigned int api_min = priv->cfg->ucode_api_min;
  1303. u8 *src;
  1304. size_t len;
  1305. u32 api_ver, build;
  1306. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1307. int err;
  1308. u16 eeprom_ver;
  1309. if (!ucode_raw) {
  1310. IWL_ERR(priv, "request for firmware file '%s' failed.\n",
  1311. priv->firmware_name);
  1312. goto try_again;
  1313. }
  1314. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1315. priv->firmware_name, ucode_raw->size);
  1316. /* Make sure that we got at least the v1 header! */
  1317. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1318. IWL_ERR(priv, "File size way too small!\n");
  1319. goto try_again;
  1320. }
  1321. /* Data from ucode file: header followed by uCode images */
  1322. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1323. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1324. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1325. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1326. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1327. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1328. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1329. init_data_size =
  1330. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1331. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1332. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1333. /* api_ver should match the api version forming part of the
  1334. * firmware filename ... but we don't check for that and only rely
  1335. * on the API version read from firmware header from here on forward */
  1336. if (api_ver < api_min || api_ver > api_max) {
  1337. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1338. "Driver supports v%u, firmware is v%u.\n",
  1339. api_max, api_ver);
  1340. goto try_again;
  1341. }
  1342. if (api_ver != api_max)
  1343. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1344. "got v%u. New firmware can be obtained "
  1345. "from http://www.intellinuxwireless.org.\n",
  1346. api_max, api_ver);
  1347. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1348. IWL_UCODE_MAJOR(priv->ucode_ver),
  1349. IWL_UCODE_MINOR(priv->ucode_ver),
  1350. IWL_UCODE_API(priv->ucode_ver),
  1351. IWL_UCODE_SERIAL(priv->ucode_ver));
  1352. snprintf(priv->hw->wiphy->fw_version,
  1353. sizeof(priv->hw->wiphy->fw_version),
  1354. "%u.%u.%u.%u",
  1355. IWL_UCODE_MAJOR(priv->ucode_ver),
  1356. IWL_UCODE_MINOR(priv->ucode_ver),
  1357. IWL_UCODE_API(priv->ucode_ver),
  1358. IWL_UCODE_SERIAL(priv->ucode_ver));
  1359. if (build)
  1360. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1361. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1362. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1363. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1364. ? "OTP" : "EEPROM", eeprom_ver);
  1365. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1366. priv->ucode_ver);
  1367. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1368. inst_size);
  1369. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1370. data_size);
  1371. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1372. init_size);
  1373. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1374. init_data_size);
  1375. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1376. boot_size);
  1377. /*
  1378. * For any of the failures below (before allocating pci memory)
  1379. * we will try to load a version with a smaller API -- maybe the
  1380. * user just got a corrupted version of the latest API.
  1381. */
  1382. /* Verify size of file vs. image size info in file's header */
  1383. if (ucode_raw->size !=
  1384. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1385. inst_size + data_size + init_size +
  1386. init_data_size + boot_size) {
  1387. IWL_DEBUG_INFO(priv,
  1388. "uCode file size %d does not match expected size\n",
  1389. (int)ucode_raw->size);
  1390. goto try_again;
  1391. }
  1392. /* Verify that uCode images will fit in card's SRAM */
  1393. if (inst_size > priv->hw_params.max_inst_size) {
  1394. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1395. inst_size);
  1396. goto try_again;
  1397. }
  1398. if (data_size > priv->hw_params.max_data_size) {
  1399. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1400. data_size);
  1401. goto try_again;
  1402. }
  1403. if (init_size > priv->hw_params.max_inst_size) {
  1404. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1405. init_size);
  1406. goto try_again;
  1407. }
  1408. if (init_data_size > priv->hw_params.max_data_size) {
  1409. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1410. init_data_size);
  1411. goto try_again;
  1412. }
  1413. if (boot_size > priv->hw_params.max_bsm_size) {
  1414. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1415. boot_size);
  1416. goto try_again;
  1417. }
  1418. /* Allocate ucode buffers for card's bus-master loading ... */
  1419. /* Runtime instructions and 2 copies of data:
  1420. * 1) unmodified from disk
  1421. * 2) backup cache for save/restore during power-downs */
  1422. priv->ucode_code.len = inst_size;
  1423. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1424. priv->ucode_data.len = data_size;
  1425. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1426. priv->ucode_data_backup.len = data_size;
  1427. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1428. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1429. !priv->ucode_data_backup.v_addr)
  1430. goto err_pci_alloc;
  1431. /* Initialization instructions and data */
  1432. if (init_size && init_data_size) {
  1433. priv->ucode_init.len = init_size;
  1434. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1435. priv->ucode_init_data.len = init_data_size;
  1436. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1437. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1438. goto err_pci_alloc;
  1439. }
  1440. /* Bootstrap (instructions only, no data) */
  1441. if (boot_size) {
  1442. priv->ucode_boot.len = boot_size;
  1443. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1444. if (!priv->ucode_boot.v_addr)
  1445. goto err_pci_alloc;
  1446. }
  1447. /* Copy images into buffers for card's bus-master reads ... */
  1448. /* Runtime instructions (first block of data in file) */
  1449. len = inst_size;
  1450. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1451. memcpy(priv->ucode_code.v_addr, src, len);
  1452. src += len;
  1453. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1454. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1455. /* Runtime data (2nd block)
  1456. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1457. len = data_size;
  1458. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1459. memcpy(priv->ucode_data.v_addr, src, len);
  1460. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1461. src += len;
  1462. /* Initialization instructions (3rd block) */
  1463. if (init_size) {
  1464. len = init_size;
  1465. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1466. len);
  1467. memcpy(priv->ucode_init.v_addr, src, len);
  1468. src += len;
  1469. }
  1470. /* Initialization data (4th block) */
  1471. if (init_data_size) {
  1472. len = init_data_size;
  1473. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1474. len);
  1475. memcpy(priv->ucode_init_data.v_addr, src, len);
  1476. src += len;
  1477. }
  1478. /* Bootstrap instructions (5th block) */
  1479. len = boot_size;
  1480. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1481. memcpy(priv->ucode_boot.v_addr, src, len);
  1482. /**************************************************
  1483. * This is still part of probe() in a sense...
  1484. *
  1485. * 9. Setup and register with mac80211 and debugfs
  1486. **************************************************/
  1487. err = iwl_mac_setup_register(priv);
  1488. if (err)
  1489. goto out_unbind;
  1490. err = iwl_dbgfs_register(priv, DRV_NAME);
  1491. if (err)
  1492. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1493. /* We have our copies now, allow OS release its copies */
  1494. release_firmware(ucode_raw);
  1495. return;
  1496. try_again:
  1497. /* try next, if any */
  1498. if (iwl_request_firmware(priv, false))
  1499. goto out_unbind;
  1500. release_firmware(ucode_raw);
  1501. return;
  1502. err_pci_alloc:
  1503. IWL_ERR(priv, "failed to allocate pci memory\n");
  1504. iwl_dealloc_ucode_pci(priv);
  1505. out_unbind:
  1506. device_release_driver(&priv->pci_dev->dev);
  1507. release_firmware(ucode_raw);
  1508. }
  1509. static const char *desc_lookup_text[] = {
  1510. "OK",
  1511. "FAIL",
  1512. "BAD_PARAM",
  1513. "BAD_CHECKSUM",
  1514. "NMI_INTERRUPT_WDG",
  1515. "SYSASSERT",
  1516. "FATAL_ERROR",
  1517. "BAD_COMMAND",
  1518. "HW_ERROR_TUNE_LOCK",
  1519. "HW_ERROR_TEMPERATURE",
  1520. "ILLEGAL_CHAN_FREQ",
  1521. "VCC_NOT_STABLE",
  1522. "FH_ERROR",
  1523. "NMI_INTERRUPT_HOST",
  1524. "NMI_INTERRUPT_ACTION_PT",
  1525. "NMI_INTERRUPT_UNKNOWN",
  1526. "UCODE_VERSION_MISMATCH",
  1527. "HW_ERROR_ABS_LOCK",
  1528. "HW_ERROR_CAL_LOCK_FAIL",
  1529. "NMI_INTERRUPT_INST_ACTION_PT",
  1530. "NMI_INTERRUPT_DATA_ACTION_PT",
  1531. "NMI_TRM_HW_ER",
  1532. "NMI_INTERRUPT_TRM",
  1533. "NMI_INTERRUPT_BREAK_POINT"
  1534. "DEBUG_0",
  1535. "DEBUG_1",
  1536. "DEBUG_2",
  1537. "DEBUG_3",
  1538. "ADVANCED SYSASSERT"
  1539. };
  1540. static const char *desc_lookup(int i)
  1541. {
  1542. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1543. if (i < 0 || i > max)
  1544. i = max;
  1545. return desc_lookup_text[i];
  1546. }
  1547. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1548. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1549. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1550. {
  1551. u32 data2, line;
  1552. u32 desc, time, count, base, data1;
  1553. u32 blink1, blink2, ilink1, ilink2;
  1554. if (priv->ucode_type == UCODE_INIT)
  1555. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1556. else
  1557. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1558. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1559. IWL_ERR(priv,
  1560. "Not valid error log pointer 0x%08X for %s uCode\n",
  1561. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1562. return;
  1563. }
  1564. count = iwl_read_targ_mem(priv, base);
  1565. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1566. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1567. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1568. priv->status, count);
  1569. }
  1570. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1571. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1572. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1573. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1574. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1575. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1576. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1577. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1578. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1579. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1580. blink1, blink2, ilink1, ilink2);
  1581. IWL_ERR(priv, "Desc Time "
  1582. "data1 data2 line\n");
  1583. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1584. desc_lookup(desc), desc, time, data1, data2, line);
  1585. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1586. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1587. ilink1, ilink2);
  1588. }
  1589. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1590. /**
  1591. * iwl_print_event_log - Dump error event log to syslog
  1592. *
  1593. */
  1594. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1595. u32 num_events, u32 mode,
  1596. int pos, char **buf, size_t bufsz)
  1597. {
  1598. u32 i;
  1599. u32 base; /* SRAM byte address of event log header */
  1600. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1601. u32 ptr; /* SRAM byte address of log data */
  1602. u32 ev, time, data; /* event log data */
  1603. unsigned long reg_flags;
  1604. if (num_events == 0)
  1605. return pos;
  1606. if (priv->ucode_type == UCODE_INIT)
  1607. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1608. else
  1609. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1610. if (mode == 0)
  1611. event_size = 2 * sizeof(u32);
  1612. else
  1613. event_size = 3 * sizeof(u32);
  1614. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1615. /* Make sure device is powered up for SRAM reads */
  1616. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1617. iwl_grab_nic_access(priv);
  1618. /* Set starting address; reads will auto-increment */
  1619. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1620. rmb();
  1621. /* "time" is actually "data" for mode 0 (no timestamp).
  1622. * place event id # at far right for easier visual parsing. */
  1623. for (i = 0; i < num_events; i++) {
  1624. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1625. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1626. if (mode == 0) {
  1627. /* data, ev */
  1628. if (bufsz) {
  1629. pos += scnprintf(*buf + pos, bufsz - pos,
  1630. "EVT_LOG:0x%08x:%04u\n",
  1631. time, ev);
  1632. } else {
  1633. trace_iwlwifi_dev_ucode_event(priv, 0,
  1634. time, ev);
  1635. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1636. time, ev);
  1637. }
  1638. } else {
  1639. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1640. if (bufsz) {
  1641. pos += scnprintf(*buf + pos, bufsz - pos,
  1642. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1643. time, data, ev);
  1644. } else {
  1645. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1646. time, data, ev);
  1647. trace_iwlwifi_dev_ucode_event(priv, time,
  1648. data, ev);
  1649. }
  1650. }
  1651. }
  1652. /* Allow device to power down */
  1653. iwl_release_nic_access(priv);
  1654. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1655. return pos;
  1656. }
  1657. /**
  1658. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1659. */
  1660. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1661. u32 num_wraps, u32 next_entry,
  1662. u32 size, u32 mode,
  1663. int pos, char **buf, size_t bufsz)
  1664. {
  1665. /*
  1666. * display the newest DEFAULT_LOG_ENTRIES entries
  1667. * i.e the entries just before the next ont that uCode would fill.
  1668. */
  1669. if (num_wraps) {
  1670. if (next_entry < size) {
  1671. pos = iwl_print_event_log(priv,
  1672. capacity - (size - next_entry),
  1673. size - next_entry, mode,
  1674. pos, buf, bufsz);
  1675. pos = iwl_print_event_log(priv, 0,
  1676. next_entry, mode,
  1677. pos, buf, bufsz);
  1678. } else
  1679. pos = iwl_print_event_log(priv, next_entry - size,
  1680. size, mode, pos, buf, bufsz);
  1681. } else {
  1682. if (next_entry < size) {
  1683. pos = iwl_print_event_log(priv, 0, next_entry,
  1684. mode, pos, buf, bufsz);
  1685. } else {
  1686. pos = iwl_print_event_log(priv, next_entry - size,
  1687. size, mode, pos, buf, bufsz);
  1688. }
  1689. }
  1690. return pos;
  1691. }
  1692. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1693. #define MAX_EVENT_LOG_SIZE (512)
  1694. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1695. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1696. char **buf, bool display)
  1697. {
  1698. u32 base; /* SRAM byte address of event log header */
  1699. u32 capacity; /* event log capacity in # entries */
  1700. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1701. u32 num_wraps; /* # times uCode wrapped to top of log */
  1702. u32 next_entry; /* index of next entry to be written by uCode */
  1703. u32 size; /* # entries that we'll print */
  1704. int pos = 0;
  1705. size_t bufsz = 0;
  1706. if (priv->ucode_type == UCODE_INIT)
  1707. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1708. else
  1709. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1710. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1711. IWL_ERR(priv,
  1712. "Invalid event log pointer 0x%08X for %s uCode\n",
  1713. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1714. return -EINVAL;
  1715. }
  1716. /* event log header */
  1717. capacity = iwl_read_targ_mem(priv, base);
  1718. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1719. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1720. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1721. if (capacity > MAX_EVENT_LOG_SIZE) {
  1722. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1723. capacity, MAX_EVENT_LOG_SIZE);
  1724. capacity = MAX_EVENT_LOG_SIZE;
  1725. }
  1726. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1727. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1728. next_entry, MAX_EVENT_LOG_SIZE);
  1729. next_entry = MAX_EVENT_LOG_SIZE;
  1730. }
  1731. size = num_wraps ? capacity : next_entry;
  1732. /* bail out if nothing in log */
  1733. if (size == 0) {
  1734. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1735. return pos;
  1736. }
  1737. #ifdef CONFIG_IWLWIFI_DEBUG
  1738. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1739. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1740. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1741. #else
  1742. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1743. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1744. #endif
  1745. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1746. size);
  1747. #ifdef CONFIG_IWLWIFI_DEBUG
  1748. if (display) {
  1749. if (full_log)
  1750. bufsz = capacity * 48;
  1751. else
  1752. bufsz = size * 48;
  1753. *buf = kmalloc(bufsz, GFP_KERNEL);
  1754. if (!*buf)
  1755. return -ENOMEM;
  1756. }
  1757. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1758. /*
  1759. * if uCode has wrapped back to top of log,
  1760. * start at the oldest entry,
  1761. * i.e the next one that uCode would fill.
  1762. */
  1763. if (num_wraps)
  1764. pos = iwl_print_event_log(priv, next_entry,
  1765. capacity - next_entry, mode,
  1766. pos, buf, bufsz);
  1767. /* (then/else) start at top of log */
  1768. pos = iwl_print_event_log(priv, 0,
  1769. next_entry, mode, pos, buf, bufsz);
  1770. } else
  1771. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1772. next_entry, size, mode,
  1773. pos, buf, bufsz);
  1774. #else
  1775. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1776. next_entry, size, mode,
  1777. pos, buf, bufsz);
  1778. #endif
  1779. return pos;
  1780. }
  1781. /**
  1782. * iwl_alive_start - called after REPLY_ALIVE notification received
  1783. * from protocol/runtime uCode (initialization uCode's
  1784. * Alive gets handled by iwl_init_alive_start()).
  1785. */
  1786. static void iwl_alive_start(struct iwl_priv *priv)
  1787. {
  1788. int ret = 0;
  1789. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1790. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1791. /* We had an error bringing up the hardware, so take it
  1792. * all the way back down so we can try again */
  1793. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1794. goto restart;
  1795. }
  1796. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1797. * This is a paranoid check, because we would not have gotten the
  1798. * "runtime" alive if code weren't properly loaded. */
  1799. if (iwl_verify_ucode(priv)) {
  1800. /* Runtime instruction load was bad;
  1801. * take it all the way back down so we can try again */
  1802. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1803. goto restart;
  1804. }
  1805. ret = priv->cfg->ops->lib->alive_notify(priv);
  1806. if (ret) {
  1807. IWL_WARN(priv,
  1808. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1809. goto restart;
  1810. }
  1811. /* After the ALIVE response, we can send host commands to the uCode */
  1812. set_bit(STATUS_ALIVE, &priv->status);
  1813. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  1814. /* Enable timer to monitor the driver queues */
  1815. mod_timer(&priv->monitor_recover,
  1816. jiffies +
  1817. msecs_to_jiffies(priv->cfg->monitor_recover_period));
  1818. }
  1819. if (iwl_is_rfkill(priv))
  1820. return;
  1821. ieee80211_wake_queues(priv->hw);
  1822. priv->active_rate = IWL_RATES_MASK;
  1823. /* Configure Tx antenna selection based on H/W config */
  1824. if (priv->cfg->ops->hcmd->set_tx_ant)
  1825. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1826. if (iwl_is_associated(priv)) {
  1827. struct iwl_rxon_cmd *active_rxon =
  1828. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1829. /* apply any changes in staging */
  1830. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1831. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1832. } else {
  1833. /* Initialize our rx_config data */
  1834. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1835. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1836. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1837. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1838. }
  1839. /* Configure Bluetooth device coexistence support */
  1840. iwl_send_bt_config(priv);
  1841. iwl_reset_run_time_calib(priv);
  1842. /* Configure the adapter for unassociated operation */
  1843. iwlcore_commit_rxon(priv);
  1844. /* At this point, the NIC is initialized and operational */
  1845. iwl_rf_kill_ct_config(priv);
  1846. iwl_leds_init(priv);
  1847. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1848. set_bit(STATUS_READY, &priv->status);
  1849. wake_up_interruptible(&priv->wait_command_queue);
  1850. iwl_power_update_mode(priv, true);
  1851. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  1852. return;
  1853. restart:
  1854. queue_work(priv->workqueue, &priv->restart);
  1855. }
  1856. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1857. static void __iwl_down(struct iwl_priv *priv)
  1858. {
  1859. unsigned long flags;
  1860. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1861. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1862. if (!exit_pending)
  1863. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1864. iwl_clear_ucode_stations(priv, true);
  1865. /* Unblock any waiting calls */
  1866. wake_up_interruptible_all(&priv->wait_command_queue);
  1867. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1868. * exiting the module */
  1869. if (!exit_pending)
  1870. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1871. /* stop and reset the on-board processor */
  1872. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1873. /* tell the device to stop sending interrupts */
  1874. spin_lock_irqsave(&priv->lock, flags);
  1875. iwl_disable_interrupts(priv);
  1876. spin_unlock_irqrestore(&priv->lock, flags);
  1877. iwl_synchronize_irq(priv);
  1878. if (priv->mac80211_registered)
  1879. ieee80211_stop_queues(priv->hw);
  1880. /* If we have not previously called iwl_init() then
  1881. * clear all bits but the RF Kill bit and return */
  1882. if (!iwl_is_init(priv)) {
  1883. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1884. STATUS_RF_KILL_HW |
  1885. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1886. STATUS_GEO_CONFIGURED |
  1887. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1888. STATUS_EXIT_PENDING;
  1889. goto exit;
  1890. }
  1891. /* ...otherwise clear out all the status bits but the RF Kill
  1892. * bit and continue taking the NIC down. */
  1893. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1894. STATUS_RF_KILL_HW |
  1895. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1896. STATUS_GEO_CONFIGURED |
  1897. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1898. STATUS_FW_ERROR |
  1899. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1900. STATUS_EXIT_PENDING;
  1901. /* device going down, Stop using ICT table */
  1902. iwl_disable_ict(priv);
  1903. iwlagn_txq_ctx_stop(priv);
  1904. iwl_rxq_stop(priv);
  1905. /* Power-down device's busmaster DMA clocks */
  1906. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1907. udelay(5);
  1908. /* Make sure (redundant) we've released our request to stay awake */
  1909. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1910. /* Stop the device, and put it in low power state */
  1911. priv->cfg->ops->lib->apm_ops.stop(priv);
  1912. exit:
  1913. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1914. if (priv->ibss_beacon)
  1915. dev_kfree_skb(priv->ibss_beacon);
  1916. priv->ibss_beacon = NULL;
  1917. /* clear out any free frames */
  1918. iwl_clear_free_frames(priv);
  1919. }
  1920. static void iwl_down(struct iwl_priv *priv)
  1921. {
  1922. mutex_lock(&priv->mutex);
  1923. __iwl_down(priv);
  1924. mutex_unlock(&priv->mutex);
  1925. iwl_cancel_deferred_work(priv);
  1926. }
  1927. #define HW_READY_TIMEOUT (50)
  1928. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1929. {
  1930. int ret = 0;
  1931. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1932. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1933. /* See if we got it */
  1934. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1935. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1936. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1937. HW_READY_TIMEOUT);
  1938. if (ret != -ETIMEDOUT)
  1939. priv->hw_ready = true;
  1940. else
  1941. priv->hw_ready = false;
  1942. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1943. (priv->hw_ready == 1) ? "ready" : "not ready");
  1944. return ret;
  1945. }
  1946. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1947. {
  1948. int ret = 0;
  1949. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1950. ret = iwl_set_hw_ready(priv);
  1951. if (priv->hw_ready)
  1952. return ret;
  1953. /* If HW is not ready, prepare the conditions to check again */
  1954. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1955. CSR_HW_IF_CONFIG_REG_PREPARE);
  1956. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1957. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1958. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1959. /* HW should be ready by now, check again. */
  1960. if (ret != -ETIMEDOUT)
  1961. iwl_set_hw_ready(priv);
  1962. return ret;
  1963. }
  1964. #define MAX_HW_RESTARTS 5
  1965. static int __iwl_up(struct iwl_priv *priv)
  1966. {
  1967. int i;
  1968. int ret;
  1969. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1970. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1971. return -EIO;
  1972. }
  1973. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1974. IWL_ERR(priv, "ucode not available for device bringup\n");
  1975. return -EIO;
  1976. }
  1977. iwl_prepare_card_hw(priv);
  1978. if (!priv->hw_ready) {
  1979. IWL_WARN(priv, "Exit HW not ready\n");
  1980. return -EIO;
  1981. }
  1982. /* If platform's RF_KILL switch is NOT set to KILL */
  1983. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1984. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1985. else
  1986. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1987. if (iwl_is_rfkill(priv)) {
  1988. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1989. iwl_enable_interrupts(priv);
  1990. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1991. return 0;
  1992. }
  1993. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1994. ret = iwlagn_hw_nic_init(priv);
  1995. if (ret) {
  1996. IWL_ERR(priv, "Unable to init nic\n");
  1997. return ret;
  1998. }
  1999. /* make sure rfkill handshake bits are cleared */
  2000. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2001. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2002. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2003. /* clear (again), then enable host interrupts */
  2004. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2005. iwl_enable_interrupts(priv);
  2006. /* really make sure rfkill handshake bits are cleared */
  2007. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2008. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2009. /* Copy original ucode data image from disk into backup cache.
  2010. * This will be used to initialize the on-board processor's
  2011. * data SRAM for a clean start when the runtime program first loads. */
  2012. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2013. priv->ucode_data.len);
  2014. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2015. /* load bootstrap state machine,
  2016. * load bootstrap program into processor's memory,
  2017. * prepare to load the "initialize" uCode */
  2018. ret = priv->cfg->ops->lib->load_ucode(priv);
  2019. if (ret) {
  2020. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  2021. ret);
  2022. continue;
  2023. }
  2024. /* start card; "initialize" will load runtime ucode */
  2025. iwl_nic_start(priv);
  2026. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2027. return 0;
  2028. }
  2029. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2030. __iwl_down(priv);
  2031. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2032. /* tried to restart and config the device for as long as our
  2033. * patience could withstand */
  2034. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2035. return -EIO;
  2036. }
  2037. /*****************************************************************************
  2038. *
  2039. * Workqueue callbacks
  2040. *
  2041. *****************************************************************************/
  2042. static void iwl_bg_init_alive_start(struct work_struct *data)
  2043. {
  2044. struct iwl_priv *priv =
  2045. container_of(data, struct iwl_priv, init_alive_start.work);
  2046. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2047. return;
  2048. mutex_lock(&priv->mutex);
  2049. priv->cfg->ops->lib->init_alive_start(priv);
  2050. mutex_unlock(&priv->mutex);
  2051. }
  2052. static void iwl_bg_alive_start(struct work_struct *data)
  2053. {
  2054. struct iwl_priv *priv =
  2055. container_of(data, struct iwl_priv, alive_start.work);
  2056. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2057. return;
  2058. /* enable dram interrupt */
  2059. iwl_reset_ict(priv);
  2060. mutex_lock(&priv->mutex);
  2061. iwl_alive_start(priv);
  2062. mutex_unlock(&priv->mutex);
  2063. }
  2064. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2065. {
  2066. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2067. run_time_calib_work);
  2068. mutex_lock(&priv->mutex);
  2069. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2070. test_bit(STATUS_SCANNING, &priv->status)) {
  2071. mutex_unlock(&priv->mutex);
  2072. return;
  2073. }
  2074. if (priv->start_calib) {
  2075. iwl_chain_noise_calibration(priv, &priv->statistics);
  2076. iwl_sensitivity_calibration(priv, &priv->statistics);
  2077. }
  2078. mutex_unlock(&priv->mutex);
  2079. return;
  2080. }
  2081. static void iwl_bg_restart(struct work_struct *data)
  2082. {
  2083. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2084. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2085. return;
  2086. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2087. mutex_lock(&priv->mutex);
  2088. priv->vif = NULL;
  2089. priv->is_open = 0;
  2090. mutex_unlock(&priv->mutex);
  2091. iwl_down(priv);
  2092. ieee80211_restart_hw(priv->hw);
  2093. } else {
  2094. iwl_down(priv);
  2095. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2096. return;
  2097. mutex_lock(&priv->mutex);
  2098. __iwl_up(priv);
  2099. mutex_unlock(&priv->mutex);
  2100. }
  2101. }
  2102. static void iwl_bg_rx_replenish(struct work_struct *data)
  2103. {
  2104. struct iwl_priv *priv =
  2105. container_of(data, struct iwl_priv, rx_replenish);
  2106. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2107. return;
  2108. mutex_lock(&priv->mutex);
  2109. iwl_rx_replenish(priv);
  2110. mutex_unlock(&priv->mutex);
  2111. }
  2112. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2113. void iwl_post_associate(struct iwl_priv *priv)
  2114. {
  2115. struct ieee80211_conf *conf = NULL;
  2116. int ret = 0;
  2117. unsigned long flags;
  2118. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  2119. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2120. return;
  2121. }
  2122. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2123. return;
  2124. if (!priv->vif || !priv->is_open)
  2125. return;
  2126. iwl_scan_cancel_timeout(priv, 200);
  2127. conf = ieee80211_get_hw_conf(priv->hw);
  2128. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2129. iwlcore_commit_rxon(priv);
  2130. iwl_setup_rxon_timing(priv);
  2131. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2132. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2133. if (ret)
  2134. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2135. "Attempting to continue.\n");
  2136. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2137. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2138. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2139. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2140. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2141. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2142. priv->assoc_id, priv->beacon_int);
  2143. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2144. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2145. else
  2146. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2147. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2148. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2149. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2150. else
  2151. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2152. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2153. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2154. }
  2155. iwlcore_commit_rxon(priv);
  2156. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2157. priv->assoc_id, priv->active_rxon.bssid_addr);
  2158. switch (priv->iw_mode) {
  2159. case NL80211_IFTYPE_STATION:
  2160. break;
  2161. case NL80211_IFTYPE_ADHOC:
  2162. /* assume default assoc id */
  2163. priv->assoc_id = 1;
  2164. iwl_add_local_station(priv, priv->bssid, true);
  2165. iwl_send_beacon_cmd(priv);
  2166. break;
  2167. default:
  2168. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2169. __func__, priv->iw_mode);
  2170. break;
  2171. }
  2172. spin_lock_irqsave(&priv->lock, flags);
  2173. iwl_activate_qos(priv, 0);
  2174. spin_unlock_irqrestore(&priv->lock, flags);
  2175. /* the chain noise calibration will enabled PM upon completion
  2176. * If chain noise has already been run, then we need to enable
  2177. * power management here */
  2178. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2179. iwl_power_update_mode(priv, false);
  2180. /* Enable Rx differential gain and sensitivity calibrations */
  2181. iwl_chain_noise_reset(priv);
  2182. priv->start_calib = 1;
  2183. }
  2184. /*****************************************************************************
  2185. *
  2186. * mac80211 entry point functions
  2187. *
  2188. *****************************************************************************/
  2189. #define UCODE_READY_TIMEOUT (4 * HZ)
  2190. /*
  2191. * Not a mac80211 entry point function, but it fits in with all the
  2192. * other mac80211 functions grouped here.
  2193. */
  2194. static int iwl_mac_setup_register(struct iwl_priv *priv)
  2195. {
  2196. int ret;
  2197. struct ieee80211_hw *hw = priv->hw;
  2198. hw->rate_control_algorithm = "iwl-agn-rs";
  2199. /* Tell mac80211 our characteristics */
  2200. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2201. IEEE80211_HW_NOISE_DBM |
  2202. IEEE80211_HW_AMPDU_AGGREGATION |
  2203. IEEE80211_HW_SPECTRUM_MGMT;
  2204. if (!priv->cfg->broken_powersave)
  2205. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2206. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2207. if (priv->cfg->sku & IWL_SKU_N)
  2208. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2209. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2210. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2211. hw->wiphy->interface_modes =
  2212. BIT(NL80211_IFTYPE_STATION) |
  2213. BIT(NL80211_IFTYPE_ADHOC);
  2214. hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
  2215. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2216. /*
  2217. * For now, disable PS by default because it affects
  2218. * RX performance significantly.
  2219. */
  2220. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2221. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX + 1;
  2222. /* we create the 802.11 header and a zero-length SSID element */
  2223. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  2224. /* Default value; 4 EDCA QOS priorities */
  2225. hw->queues = 4;
  2226. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2227. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2228. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2229. &priv->bands[IEEE80211_BAND_2GHZ];
  2230. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2231. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2232. &priv->bands[IEEE80211_BAND_5GHZ];
  2233. ret = ieee80211_register_hw(priv->hw);
  2234. if (ret) {
  2235. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2236. return ret;
  2237. }
  2238. priv->mac80211_registered = 1;
  2239. return 0;
  2240. }
  2241. static int iwl_mac_start(struct ieee80211_hw *hw)
  2242. {
  2243. struct iwl_priv *priv = hw->priv;
  2244. int ret;
  2245. IWL_DEBUG_MAC80211(priv, "enter\n");
  2246. /* we should be verifying the device is ready to be opened */
  2247. mutex_lock(&priv->mutex);
  2248. ret = __iwl_up(priv);
  2249. mutex_unlock(&priv->mutex);
  2250. if (ret)
  2251. return ret;
  2252. if (iwl_is_rfkill(priv))
  2253. goto out;
  2254. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2255. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2256. * mac80211 will not be run successfully. */
  2257. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2258. test_bit(STATUS_READY, &priv->status),
  2259. UCODE_READY_TIMEOUT);
  2260. if (!ret) {
  2261. if (!test_bit(STATUS_READY, &priv->status)) {
  2262. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2263. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2264. return -ETIMEDOUT;
  2265. }
  2266. }
  2267. iwl_led_start(priv);
  2268. out:
  2269. priv->is_open = 1;
  2270. IWL_DEBUG_MAC80211(priv, "leave\n");
  2271. return 0;
  2272. }
  2273. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2274. {
  2275. struct iwl_priv *priv = hw->priv;
  2276. IWL_DEBUG_MAC80211(priv, "enter\n");
  2277. if (!priv->is_open)
  2278. return;
  2279. priv->is_open = 0;
  2280. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2281. /* stop mac, cancel any scan request and clear
  2282. * RXON_FILTER_ASSOC_MSK BIT
  2283. */
  2284. mutex_lock(&priv->mutex);
  2285. iwl_scan_cancel_timeout(priv, 100);
  2286. mutex_unlock(&priv->mutex);
  2287. }
  2288. iwl_down(priv);
  2289. flush_workqueue(priv->workqueue);
  2290. /* enable interrupts again in order to receive rfkill changes */
  2291. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2292. iwl_enable_interrupts(priv);
  2293. IWL_DEBUG_MAC80211(priv, "leave\n");
  2294. }
  2295. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2296. {
  2297. struct iwl_priv *priv = hw->priv;
  2298. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2299. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2300. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2301. if (iwlagn_tx_skb(priv, skb))
  2302. dev_kfree_skb_any(skb);
  2303. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2304. return NETDEV_TX_OK;
  2305. }
  2306. void iwl_config_ap(struct iwl_priv *priv)
  2307. {
  2308. int ret = 0;
  2309. unsigned long flags;
  2310. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2311. return;
  2312. /* The following should be done only at AP bring up */
  2313. if (!iwl_is_associated(priv)) {
  2314. /* RXON - unassoc (to set timing command) */
  2315. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2316. iwlcore_commit_rxon(priv);
  2317. /* RXON Timing */
  2318. iwl_setup_rxon_timing(priv);
  2319. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2320. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2321. if (ret)
  2322. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2323. "Attempting to continue.\n");
  2324. /* AP has all antennas */
  2325. priv->chain_noise_data.active_chains =
  2326. priv->hw_params.valid_rx_ant;
  2327. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2328. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2329. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2330. /* FIXME: what should be the assoc_id for AP? */
  2331. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2332. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2333. priv->staging_rxon.flags |=
  2334. RXON_FLG_SHORT_PREAMBLE_MSK;
  2335. else
  2336. priv->staging_rxon.flags &=
  2337. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2338. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2339. if (priv->assoc_capability &
  2340. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2341. priv->staging_rxon.flags |=
  2342. RXON_FLG_SHORT_SLOT_MSK;
  2343. else
  2344. priv->staging_rxon.flags &=
  2345. ~RXON_FLG_SHORT_SLOT_MSK;
  2346. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2347. priv->staging_rxon.flags &=
  2348. ~RXON_FLG_SHORT_SLOT_MSK;
  2349. }
  2350. /* restore RXON assoc */
  2351. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2352. iwlcore_commit_rxon(priv);
  2353. iwl_reset_qos(priv);
  2354. spin_lock_irqsave(&priv->lock, flags);
  2355. iwl_activate_qos(priv, 1);
  2356. spin_unlock_irqrestore(&priv->lock, flags);
  2357. iwl_add_bcast_station(priv);
  2358. }
  2359. iwl_send_beacon_cmd(priv);
  2360. /* FIXME - we need to add code here to detect a totally new
  2361. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2362. * clear sta table, add BCAST sta... */
  2363. }
  2364. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2365. struct ieee80211_vif *vif,
  2366. struct ieee80211_key_conf *keyconf,
  2367. struct ieee80211_sta *sta,
  2368. u32 iv32, u16 *phase1key)
  2369. {
  2370. struct iwl_priv *priv = hw->priv;
  2371. IWL_DEBUG_MAC80211(priv, "enter\n");
  2372. iwl_update_tkip_key(priv, keyconf,
  2373. sta ? sta->addr : iwl_bcast_addr,
  2374. iv32, phase1key);
  2375. IWL_DEBUG_MAC80211(priv, "leave\n");
  2376. }
  2377. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2378. struct ieee80211_vif *vif,
  2379. struct ieee80211_sta *sta,
  2380. struct ieee80211_key_conf *key)
  2381. {
  2382. struct iwl_priv *priv = hw->priv;
  2383. const u8 *addr;
  2384. int ret;
  2385. u8 sta_id;
  2386. bool is_default_wep_key = false;
  2387. IWL_DEBUG_MAC80211(priv, "enter\n");
  2388. if (priv->cfg->mod_params->sw_crypto) {
  2389. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2390. return -EOPNOTSUPP;
  2391. }
  2392. addr = sta ? sta->addr : iwl_bcast_addr;
  2393. sta_id = iwl_find_station(priv, addr);
  2394. if (sta_id == IWL_INVALID_STATION) {
  2395. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2396. addr);
  2397. return -EINVAL;
  2398. }
  2399. mutex_lock(&priv->mutex);
  2400. iwl_scan_cancel_timeout(priv, 100);
  2401. /* If we are getting WEP group key and we didn't receive any key mapping
  2402. * so far, we are in legacy wep mode (group key only), otherwise we are
  2403. * in 1X mode.
  2404. * In legacy wep mode, we use another host command to the uCode */
  2405. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2406. priv->iw_mode != NL80211_IFTYPE_AP) {
  2407. if (cmd == SET_KEY)
  2408. is_default_wep_key = !priv->key_mapping_key;
  2409. else
  2410. is_default_wep_key =
  2411. (key->hw_key_idx == HW_KEY_DEFAULT);
  2412. }
  2413. switch (cmd) {
  2414. case SET_KEY:
  2415. if (is_default_wep_key)
  2416. ret = iwl_set_default_wep_key(priv, key);
  2417. else
  2418. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2419. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2420. break;
  2421. case DISABLE_KEY:
  2422. if (is_default_wep_key)
  2423. ret = iwl_remove_default_wep_key(priv, key);
  2424. else
  2425. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2426. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2427. break;
  2428. default:
  2429. ret = -EINVAL;
  2430. }
  2431. mutex_unlock(&priv->mutex);
  2432. IWL_DEBUG_MAC80211(priv, "leave\n");
  2433. return ret;
  2434. }
  2435. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2436. struct ieee80211_vif *vif,
  2437. enum ieee80211_ampdu_mlme_action action,
  2438. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2439. {
  2440. struct iwl_priv *priv = hw->priv;
  2441. int ret;
  2442. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2443. sta->addr, tid);
  2444. if (!(priv->cfg->sku & IWL_SKU_N))
  2445. return -EACCES;
  2446. switch (action) {
  2447. case IEEE80211_AMPDU_RX_START:
  2448. IWL_DEBUG_HT(priv, "start Rx\n");
  2449. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2450. case IEEE80211_AMPDU_RX_STOP:
  2451. IWL_DEBUG_HT(priv, "stop Rx\n");
  2452. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2453. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2454. return 0;
  2455. else
  2456. return ret;
  2457. case IEEE80211_AMPDU_TX_START:
  2458. IWL_DEBUG_HT(priv, "start Tx\n");
  2459. ret = iwlagn_tx_agg_start(priv, sta->addr, tid, ssn);
  2460. if (ret == 0) {
  2461. priv->_agn.agg_tids_count++;
  2462. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2463. priv->_agn.agg_tids_count);
  2464. }
  2465. return ret;
  2466. case IEEE80211_AMPDU_TX_STOP:
  2467. IWL_DEBUG_HT(priv, "stop Tx\n");
  2468. ret = iwlagn_tx_agg_stop(priv, sta->addr, tid);
  2469. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  2470. priv->_agn.agg_tids_count--;
  2471. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2472. priv->_agn.agg_tids_count);
  2473. }
  2474. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2475. return 0;
  2476. else
  2477. return ret;
  2478. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2479. /* do nothing */
  2480. return -EOPNOTSUPP;
  2481. default:
  2482. IWL_DEBUG_HT(priv, "unknown\n");
  2483. return -EINVAL;
  2484. break;
  2485. }
  2486. return 0;
  2487. }
  2488. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2489. struct ieee80211_low_level_stats *stats)
  2490. {
  2491. struct iwl_priv *priv = hw->priv;
  2492. priv = hw->priv;
  2493. IWL_DEBUG_MAC80211(priv, "enter\n");
  2494. IWL_DEBUG_MAC80211(priv, "leave\n");
  2495. return 0;
  2496. }
  2497. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2498. struct ieee80211_vif *vif,
  2499. enum sta_notify_cmd cmd,
  2500. struct ieee80211_sta *sta)
  2501. {
  2502. struct iwl_priv *priv = hw->priv;
  2503. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2504. int sta_id;
  2505. switch (cmd) {
  2506. case STA_NOTIFY_SLEEP:
  2507. WARN_ON(!sta_priv->client);
  2508. sta_priv->asleep = true;
  2509. if (atomic_read(&sta_priv->pending_frames) > 0)
  2510. ieee80211_sta_block_awake(hw, sta, true);
  2511. break;
  2512. case STA_NOTIFY_AWAKE:
  2513. WARN_ON(!sta_priv->client);
  2514. if (!sta_priv->asleep)
  2515. break;
  2516. sta_priv->asleep = false;
  2517. sta_id = iwl_find_station(priv, sta->addr);
  2518. if (sta_id != IWL_INVALID_STATION)
  2519. iwl_sta_modify_ps_wake(priv, sta_id);
  2520. break;
  2521. default:
  2522. break;
  2523. }
  2524. }
  2525. /**
  2526. * iwl_restore_wepkeys - Restore WEP keys to device
  2527. */
  2528. static void iwl_restore_wepkeys(struct iwl_priv *priv)
  2529. {
  2530. mutex_lock(&priv->mutex);
  2531. if (priv->iw_mode == NL80211_IFTYPE_STATION &&
  2532. priv->default_wep_key &&
  2533. iwl_send_static_wepkey_cmd(priv, 0))
  2534. IWL_ERR(priv, "Could not send WEP static key\n");
  2535. mutex_unlock(&priv->mutex);
  2536. }
  2537. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  2538. struct ieee80211_vif *vif,
  2539. struct ieee80211_sta *sta)
  2540. {
  2541. struct iwl_priv *priv = hw->priv;
  2542. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2543. bool is_ap = priv->iw_mode == NL80211_IFTYPE_STATION;
  2544. int ret;
  2545. u8 sta_id;
  2546. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2547. sta->addr);
  2548. atomic_set(&sta_priv->pending_frames, 0);
  2549. if (vif->type == NL80211_IFTYPE_AP)
  2550. sta_priv->client = true;
  2551. ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
  2552. &sta_id);
  2553. if (ret) {
  2554. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2555. sta->addr, ret);
  2556. /* Should we return success if return code is EEXIST ? */
  2557. return ret;
  2558. }
  2559. iwl_restore_wepkeys(priv);
  2560. /* Initialize rate scaling */
  2561. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM \n",
  2562. sta->addr);
  2563. iwl_rs_rate_init(priv, sta, sta_id);
  2564. return ret;
  2565. }
  2566. /*****************************************************************************
  2567. *
  2568. * sysfs attributes
  2569. *
  2570. *****************************************************************************/
  2571. #ifdef CONFIG_IWLWIFI_DEBUG
  2572. /*
  2573. * The following adds a new attribute to the sysfs representation
  2574. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2575. * used for controlling the debug level.
  2576. *
  2577. * See the level definitions in iwl for details.
  2578. *
  2579. * The debug_level being managed using sysfs below is a per device debug
  2580. * level that is used instead of the global debug level if it (the per
  2581. * device debug level) is set.
  2582. */
  2583. static ssize_t show_debug_level(struct device *d,
  2584. struct device_attribute *attr, char *buf)
  2585. {
  2586. struct iwl_priv *priv = dev_get_drvdata(d);
  2587. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2588. }
  2589. static ssize_t store_debug_level(struct device *d,
  2590. struct device_attribute *attr,
  2591. const char *buf, size_t count)
  2592. {
  2593. struct iwl_priv *priv = dev_get_drvdata(d);
  2594. unsigned long val;
  2595. int ret;
  2596. ret = strict_strtoul(buf, 0, &val);
  2597. if (ret)
  2598. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2599. else {
  2600. priv->debug_level = val;
  2601. if (iwl_alloc_traffic_mem(priv))
  2602. IWL_ERR(priv,
  2603. "Not enough memory to generate traffic log\n");
  2604. }
  2605. return strnlen(buf, count);
  2606. }
  2607. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2608. show_debug_level, store_debug_level);
  2609. #endif /* CONFIG_IWLWIFI_DEBUG */
  2610. static ssize_t show_temperature(struct device *d,
  2611. struct device_attribute *attr, char *buf)
  2612. {
  2613. struct iwl_priv *priv = dev_get_drvdata(d);
  2614. if (!iwl_is_alive(priv))
  2615. return -EAGAIN;
  2616. return sprintf(buf, "%d\n", priv->temperature);
  2617. }
  2618. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2619. static ssize_t show_tx_power(struct device *d,
  2620. struct device_attribute *attr, char *buf)
  2621. {
  2622. struct iwl_priv *priv = dev_get_drvdata(d);
  2623. if (!iwl_is_ready_rf(priv))
  2624. return sprintf(buf, "off\n");
  2625. else
  2626. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2627. }
  2628. static ssize_t store_tx_power(struct device *d,
  2629. struct device_attribute *attr,
  2630. const char *buf, size_t count)
  2631. {
  2632. struct iwl_priv *priv = dev_get_drvdata(d);
  2633. unsigned long val;
  2634. int ret;
  2635. ret = strict_strtoul(buf, 10, &val);
  2636. if (ret)
  2637. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2638. else {
  2639. ret = iwl_set_tx_power(priv, val, false);
  2640. if (ret)
  2641. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2642. ret);
  2643. else
  2644. ret = count;
  2645. }
  2646. return ret;
  2647. }
  2648. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2649. static ssize_t show_statistics(struct device *d,
  2650. struct device_attribute *attr, char *buf)
  2651. {
  2652. struct iwl_priv *priv = dev_get_drvdata(d);
  2653. u32 size = sizeof(struct iwl_notif_statistics);
  2654. u32 len = 0, ofs = 0;
  2655. u8 *data = (u8 *)&priv->statistics;
  2656. int rc = 0;
  2657. if (!iwl_is_alive(priv))
  2658. return -EAGAIN;
  2659. mutex_lock(&priv->mutex);
  2660. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2661. mutex_unlock(&priv->mutex);
  2662. if (rc) {
  2663. len = sprintf(buf,
  2664. "Error sending statistics request: 0x%08X\n", rc);
  2665. return len;
  2666. }
  2667. while (size && (PAGE_SIZE - len)) {
  2668. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2669. PAGE_SIZE - len, 1);
  2670. len = strlen(buf);
  2671. if (PAGE_SIZE - len)
  2672. buf[len++] = '\n';
  2673. ofs += 16;
  2674. size -= min(size, 16U);
  2675. }
  2676. return len;
  2677. }
  2678. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2679. static ssize_t show_rts_ht_protection(struct device *d,
  2680. struct device_attribute *attr, char *buf)
  2681. {
  2682. struct iwl_priv *priv = dev_get_drvdata(d);
  2683. return sprintf(buf, "%s\n",
  2684. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2685. }
  2686. static ssize_t store_rts_ht_protection(struct device *d,
  2687. struct device_attribute *attr,
  2688. const char *buf, size_t count)
  2689. {
  2690. struct iwl_priv *priv = dev_get_drvdata(d);
  2691. unsigned long val;
  2692. int ret;
  2693. ret = strict_strtoul(buf, 10, &val);
  2694. if (ret)
  2695. IWL_INFO(priv, "Input is not in decimal form.\n");
  2696. else {
  2697. if (!iwl_is_associated(priv))
  2698. priv->cfg->use_rts_for_ht = val ? true : false;
  2699. else
  2700. IWL_ERR(priv, "Sta associated with AP - "
  2701. "Change protection mechanism is not allowed\n");
  2702. ret = count;
  2703. }
  2704. return ret;
  2705. }
  2706. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2707. show_rts_ht_protection, store_rts_ht_protection);
  2708. /*****************************************************************************
  2709. *
  2710. * driver setup and teardown
  2711. *
  2712. *****************************************************************************/
  2713. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2714. {
  2715. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2716. init_waitqueue_head(&priv->wait_command_queue);
  2717. INIT_WORK(&priv->restart, iwl_bg_restart);
  2718. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2719. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2720. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2721. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2722. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2723. iwl_setup_scan_deferred_work(priv);
  2724. if (priv->cfg->ops->lib->setup_deferred_work)
  2725. priv->cfg->ops->lib->setup_deferred_work(priv);
  2726. init_timer(&priv->statistics_periodic);
  2727. priv->statistics_periodic.data = (unsigned long)priv;
  2728. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2729. init_timer(&priv->ucode_trace);
  2730. priv->ucode_trace.data = (unsigned long)priv;
  2731. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2732. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2733. init_timer(&priv->monitor_recover);
  2734. priv->monitor_recover.data = (unsigned long)priv;
  2735. priv->monitor_recover.function =
  2736. priv->cfg->ops->lib->recover_from_tx_stall;
  2737. }
  2738. if (!priv->cfg->use_isr_legacy)
  2739. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2740. iwl_irq_tasklet, (unsigned long)priv);
  2741. else
  2742. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2743. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2744. }
  2745. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2746. {
  2747. if (priv->cfg->ops->lib->cancel_deferred_work)
  2748. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2749. cancel_delayed_work_sync(&priv->init_alive_start);
  2750. cancel_delayed_work(&priv->scan_check);
  2751. cancel_delayed_work(&priv->alive_start);
  2752. cancel_work_sync(&priv->beacon_update);
  2753. del_timer_sync(&priv->statistics_periodic);
  2754. del_timer_sync(&priv->ucode_trace);
  2755. if (priv->cfg->ops->lib->recover_from_tx_stall)
  2756. del_timer_sync(&priv->monitor_recover);
  2757. }
  2758. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2759. struct ieee80211_rate *rates)
  2760. {
  2761. int i;
  2762. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2763. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2764. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2765. rates[i].hw_value_short = i;
  2766. rates[i].flags = 0;
  2767. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2768. /*
  2769. * If CCK != 1M then set short preamble rate flag.
  2770. */
  2771. rates[i].flags |=
  2772. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2773. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2774. }
  2775. }
  2776. }
  2777. static int iwl_init_drv(struct iwl_priv *priv)
  2778. {
  2779. int ret;
  2780. priv->ibss_beacon = NULL;
  2781. spin_lock_init(&priv->sta_lock);
  2782. spin_lock_init(&priv->hcmd_lock);
  2783. INIT_LIST_HEAD(&priv->free_frames);
  2784. mutex_init(&priv->mutex);
  2785. mutex_init(&priv->sync_cmd_mutex);
  2786. priv->ieee_channels = NULL;
  2787. priv->ieee_rates = NULL;
  2788. priv->band = IEEE80211_BAND_2GHZ;
  2789. priv->iw_mode = NL80211_IFTYPE_STATION;
  2790. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2791. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2792. priv->_agn.agg_tids_count = 0;
  2793. /* initialize force reset */
  2794. priv->force_reset[IWL_RF_RESET].reset_duration =
  2795. IWL_DELAY_NEXT_FORCE_RF_RESET;
  2796. priv->force_reset[IWL_FW_RESET].reset_duration =
  2797. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  2798. /* Choose which receivers/antennas to use */
  2799. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2800. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2801. iwl_init_scan_params(priv);
  2802. iwl_reset_qos(priv);
  2803. priv->qos_data.qos_active = 0;
  2804. priv->qos_data.qos_cap.val = 0;
  2805. /* Set the tx_power_user_lmt to the lowest power level
  2806. * this value will get overwritten by channel max power avg
  2807. * from eeprom */
  2808. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2809. ret = iwl_init_channel_map(priv);
  2810. if (ret) {
  2811. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2812. goto err;
  2813. }
  2814. ret = iwlcore_init_geos(priv);
  2815. if (ret) {
  2816. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2817. goto err_free_channel_map;
  2818. }
  2819. iwl_init_hw_rates(priv, priv->ieee_rates);
  2820. return 0;
  2821. err_free_channel_map:
  2822. iwl_free_channel_map(priv);
  2823. err:
  2824. return ret;
  2825. }
  2826. static void iwl_uninit_drv(struct iwl_priv *priv)
  2827. {
  2828. iwl_calib_free_results(priv);
  2829. iwlcore_free_geos(priv);
  2830. iwl_free_channel_map(priv);
  2831. kfree(priv->scan);
  2832. }
  2833. static struct attribute *iwl_sysfs_entries[] = {
  2834. &dev_attr_statistics.attr,
  2835. &dev_attr_temperature.attr,
  2836. &dev_attr_tx_power.attr,
  2837. &dev_attr_rts_ht_protection.attr,
  2838. #ifdef CONFIG_IWLWIFI_DEBUG
  2839. &dev_attr_debug_level.attr,
  2840. #endif
  2841. NULL
  2842. };
  2843. static struct attribute_group iwl_attribute_group = {
  2844. .name = NULL, /* put in device directory */
  2845. .attrs = iwl_sysfs_entries,
  2846. };
  2847. static struct ieee80211_ops iwl_hw_ops = {
  2848. .tx = iwl_mac_tx,
  2849. .start = iwl_mac_start,
  2850. .stop = iwl_mac_stop,
  2851. .add_interface = iwl_mac_add_interface,
  2852. .remove_interface = iwl_mac_remove_interface,
  2853. .config = iwl_mac_config,
  2854. .configure_filter = iwl_configure_filter,
  2855. .set_key = iwl_mac_set_key,
  2856. .update_tkip_key = iwl_mac_update_tkip_key,
  2857. .get_stats = iwl_mac_get_stats,
  2858. .conf_tx = iwl_mac_conf_tx,
  2859. .reset_tsf = iwl_mac_reset_tsf,
  2860. .bss_info_changed = iwl_bss_info_changed,
  2861. .ampdu_action = iwl_mac_ampdu_action,
  2862. .hw_scan = iwl_mac_hw_scan,
  2863. .sta_notify = iwl_mac_sta_notify,
  2864. .sta_add = iwlagn_mac_sta_add,
  2865. .sta_remove = iwl_mac_sta_remove,
  2866. };
  2867. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2868. {
  2869. int err = 0;
  2870. struct iwl_priv *priv;
  2871. struct ieee80211_hw *hw;
  2872. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2873. unsigned long flags;
  2874. u16 pci_cmd;
  2875. /************************
  2876. * 1. Allocating HW data
  2877. ************************/
  2878. /* Disabling hardware scan means that mac80211 will perform scans
  2879. * "the hard way", rather than using device's scan. */
  2880. if (cfg->mod_params->disable_hw_scan) {
  2881. if (iwl_debug_level & IWL_DL_INFO)
  2882. dev_printk(KERN_DEBUG, &(pdev->dev),
  2883. "Disabling hw_scan\n");
  2884. iwl_hw_ops.hw_scan = NULL;
  2885. }
  2886. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2887. if (!hw) {
  2888. err = -ENOMEM;
  2889. goto out;
  2890. }
  2891. priv = hw->priv;
  2892. /* At this point both hw and priv are allocated. */
  2893. SET_IEEE80211_DEV(hw, &pdev->dev);
  2894. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2895. priv->cfg = cfg;
  2896. priv->pci_dev = pdev;
  2897. priv->inta_mask = CSR_INI_SET_MASK;
  2898. #ifdef CONFIG_IWLWIFI_DEBUG
  2899. atomic_set(&priv->restrict_refcnt, 0);
  2900. #endif
  2901. if (iwl_alloc_traffic_mem(priv))
  2902. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2903. /**************************
  2904. * 2. Initializing PCI bus
  2905. **************************/
  2906. if (pci_enable_device(pdev)) {
  2907. err = -ENODEV;
  2908. goto out_ieee80211_free_hw;
  2909. }
  2910. pci_set_master(pdev);
  2911. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2912. if (!err)
  2913. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2914. if (err) {
  2915. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2916. if (!err)
  2917. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2918. /* both attempts failed: */
  2919. if (err) {
  2920. IWL_WARN(priv, "No suitable DMA available.\n");
  2921. goto out_pci_disable_device;
  2922. }
  2923. }
  2924. err = pci_request_regions(pdev, DRV_NAME);
  2925. if (err)
  2926. goto out_pci_disable_device;
  2927. pci_set_drvdata(pdev, priv);
  2928. /***********************
  2929. * 3. Read REV register
  2930. ***********************/
  2931. priv->hw_base = pci_iomap(pdev, 0, 0);
  2932. if (!priv->hw_base) {
  2933. err = -ENODEV;
  2934. goto out_pci_release_regions;
  2935. }
  2936. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2937. (unsigned long long) pci_resource_len(pdev, 0));
  2938. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2939. /* these spin locks will be used in apm_ops.init and EEPROM access
  2940. * we should init now
  2941. */
  2942. spin_lock_init(&priv->reg_lock);
  2943. spin_lock_init(&priv->lock);
  2944. /*
  2945. * stop and reset the on-board processor just in case it is in a
  2946. * strange state ... like being left stranded by a primary kernel
  2947. * and this is now the kdump kernel trying to start up
  2948. */
  2949. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2950. iwl_hw_detect(priv);
  2951. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  2952. priv->cfg->name, priv->hw_rev);
  2953. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2954. * PCI Tx retries from interfering with C3 CPU state */
  2955. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2956. iwl_prepare_card_hw(priv);
  2957. if (!priv->hw_ready) {
  2958. IWL_WARN(priv, "Failed, HW not ready\n");
  2959. goto out_iounmap;
  2960. }
  2961. /*****************
  2962. * 4. Read EEPROM
  2963. *****************/
  2964. /* Read the EEPROM */
  2965. err = iwl_eeprom_init(priv);
  2966. if (err) {
  2967. IWL_ERR(priv, "Unable to init EEPROM\n");
  2968. goto out_iounmap;
  2969. }
  2970. err = iwl_eeprom_check_version(priv);
  2971. if (err)
  2972. goto out_free_eeprom;
  2973. /* extract MAC Address */
  2974. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2975. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2976. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2977. /************************
  2978. * 5. Setup HW constants
  2979. ************************/
  2980. if (iwl_set_hw_params(priv)) {
  2981. IWL_ERR(priv, "failed to set hw parameters\n");
  2982. goto out_free_eeprom;
  2983. }
  2984. /*******************
  2985. * 6. Setup priv
  2986. *******************/
  2987. err = iwl_init_drv(priv);
  2988. if (err)
  2989. goto out_free_eeprom;
  2990. /* At this point both hw and priv are initialized. */
  2991. /********************
  2992. * 7. Setup services
  2993. ********************/
  2994. spin_lock_irqsave(&priv->lock, flags);
  2995. iwl_disable_interrupts(priv);
  2996. spin_unlock_irqrestore(&priv->lock, flags);
  2997. pci_enable_msi(priv->pci_dev);
  2998. iwl_alloc_isr_ict(priv);
  2999. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  3000. IRQF_SHARED, DRV_NAME, priv);
  3001. if (err) {
  3002. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3003. goto out_disable_msi;
  3004. }
  3005. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  3006. if (err) {
  3007. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  3008. goto out_free_irq;
  3009. }
  3010. iwl_setup_deferred_work(priv);
  3011. iwl_setup_rx_handlers(priv);
  3012. /*********************************************
  3013. * 8. Enable interrupts and read RFKILL state
  3014. *********************************************/
  3015. /* enable interrupts if needed: hw bug w/a */
  3016. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3017. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3018. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3019. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3020. }
  3021. iwl_enable_interrupts(priv);
  3022. /* If platform's RF_KILL switch is NOT set to KILL */
  3023. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3024. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3025. else
  3026. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3027. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3028. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3029. iwl_power_initialize(priv);
  3030. iwl_tt_initialize(priv);
  3031. err = iwl_request_firmware(priv, true);
  3032. if (err)
  3033. goto out_remove_sysfs;
  3034. return 0;
  3035. out_remove_sysfs:
  3036. destroy_workqueue(priv->workqueue);
  3037. priv->workqueue = NULL;
  3038. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3039. out_free_irq:
  3040. free_irq(priv->pci_dev->irq, priv);
  3041. iwl_free_isr_ict(priv);
  3042. out_disable_msi:
  3043. pci_disable_msi(priv->pci_dev);
  3044. iwl_uninit_drv(priv);
  3045. out_free_eeprom:
  3046. iwl_eeprom_free(priv);
  3047. out_iounmap:
  3048. pci_iounmap(pdev, priv->hw_base);
  3049. out_pci_release_regions:
  3050. pci_set_drvdata(pdev, NULL);
  3051. pci_release_regions(pdev);
  3052. out_pci_disable_device:
  3053. pci_disable_device(pdev);
  3054. out_ieee80211_free_hw:
  3055. iwl_free_traffic_mem(priv);
  3056. ieee80211_free_hw(priv->hw);
  3057. out:
  3058. return err;
  3059. }
  3060. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3061. {
  3062. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3063. unsigned long flags;
  3064. if (!priv)
  3065. return;
  3066. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3067. iwl_dbgfs_unregister(priv);
  3068. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3069. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3070. * to be called and iwl_down since we are removing the device
  3071. * we need to set STATUS_EXIT_PENDING bit.
  3072. */
  3073. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3074. if (priv->mac80211_registered) {
  3075. ieee80211_unregister_hw(priv->hw);
  3076. priv->mac80211_registered = 0;
  3077. } else {
  3078. iwl_down(priv);
  3079. }
  3080. /*
  3081. * Make sure device is reset to low power before unloading driver.
  3082. * This may be redundant with iwl_down(), but there are paths to
  3083. * run iwl_down() without calling apm_ops.stop(), and there are
  3084. * paths to avoid running iwl_down() at all before leaving driver.
  3085. * This (inexpensive) call *makes sure* device is reset.
  3086. */
  3087. priv->cfg->ops->lib->apm_ops.stop(priv);
  3088. iwl_tt_exit(priv);
  3089. /* make sure we flush any pending irq or
  3090. * tasklet for the driver
  3091. */
  3092. spin_lock_irqsave(&priv->lock, flags);
  3093. iwl_disable_interrupts(priv);
  3094. spin_unlock_irqrestore(&priv->lock, flags);
  3095. iwl_synchronize_irq(priv);
  3096. iwl_dealloc_ucode_pci(priv);
  3097. if (priv->rxq.bd)
  3098. iwl_rx_queue_free(priv, &priv->rxq);
  3099. iwlagn_hw_txq_ctx_free(priv);
  3100. iwl_eeprom_free(priv);
  3101. /*netif_stop_queue(dev); */
  3102. flush_workqueue(priv->workqueue);
  3103. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3104. * priv->workqueue... so we can't take down the workqueue
  3105. * until now... */
  3106. destroy_workqueue(priv->workqueue);
  3107. priv->workqueue = NULL;
  3108. iwl_free_traffic_mem(priv);
  3109. free_irq(priv->pci_dev->irq, priv);
  3110. pci_disable_msi(priv->pci_dev);
  3111. pci_iounmap(pdev, priv->hw_base);
  3112. pci_release_regions(pdev);
  3113. pci_disable_device(pdev);
  3114. pci_set_drvdata(pdev, NULL);
  3115. iwl_uninit_drv(priv);
  3116. iwl_free_isr_ict(priv);
  3117. if (priv->ibss_beacon)
  3118. dev_kfree_skb(priv->ibss_beacon);
  3119. ieee80211_free_hw(priv->hw);
  3120. }
  3121. /*****************************************************************************
  3122. *
  3123. * driver and module entry point
  3124. *
  3125. *****************************************************************************/
  3126. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3127. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3128. #ifdef CONFIG_IWL4965
  3129. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3130. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3131. #endif /* CONFIG_IWL4965 */
  3132. #ifdef CONFIG_IWL5000
  3133. /* 5100 Series WiFi */
  3134. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3135. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3136. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3137. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3138. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3139. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3140. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3141. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3142. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3143. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3144. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3145. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3146. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3147. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3148. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3149. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3150. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3151. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3152. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3153. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3154. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3155. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3156. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3157. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3158. /* 5300 Series WiFi */
  3159. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3160. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3161. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3162. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3163. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3164. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3165. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3166. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3167. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3168. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3169. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3170. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3171. /* 5350 Series WiFi/WiMax */
  3172. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3173. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3174. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3175. /* 5150 Series Wifi/WiMax */
  3176. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3177. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3178. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3179. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3180. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3181. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3182. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3183. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3184. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3185. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3186. /* 6x00 Series */
  3187. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3188. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3189. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3190. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3191. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3192. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3193. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3194. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3195. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3196. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3197. /* 6x50 WiFi/WiMax Series */
  3198. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3199. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3200. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3201. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3202. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3203. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3204. /* 1000 Series WiFi */
  3205. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3206. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3207. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3208. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3209. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3210. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3211. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3212. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3213. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3214. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3215. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3216. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3217. #endif /* CONFIG_IWL5000 */
  3218. {0}
  3219. };
  3220. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3221. static struct pci_driver iwl_driver = {
  3222. .name = DRV_NAME,
  3223. .id_table = iwl_hw_card_ids,
  3224. .probe = iwl_pci_probe,
  3225. .remove = __devexit_p(iwl_pci_remove),
  3226. #ifdef CONFIG_PM
  3227. .suspend = iwl_pci_suspend,
  3228. .resume = iwl_pci_resume,
  3229. #endif
  3230. };
  3231. static int __init iwl_init(void)
  3232. {
  3233. int ret;
  3234. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3235. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3236. ret = iwlagn_rate_control_register();
  3237. if (ret) {
  3238. printk(KERN_ERR DRV_NAME
  3239. "Unable to register rate control algorithm: %d\n", ret);
  3240. return ret;
  3241. }
  3242. ret = pci_register_driver(&iwl_driver);
  3243. if (ret) {
  3244. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3245. goto error_register;
  3246. }
  3247. return ret;
  3248. error_register:
  3249. iwlagn_rate_control_unregister();
  3250. return ret;
  3251. }
  3252. static void __exit iwl_exit(void)
  3253. {
  3254. pci_unregister_driver(&iwl_driver);
  3255. iwlagn_rate_control_unregister();
  3256. }
  3257. module_exit(iwl_exit);
  3258. module_init(iwl_init);
  3259. #ifdef CONFIG_IWLWIFI_DEBUG
  3260. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3261. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3262. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3263. MODULE_PARM_DESC(debug, "debug output mask");
  3264. #endif