iwl-core.c 91 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233
  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <net/mac80211.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h" /* FIXME: remove */
  34. #include "iwl-debug.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-power.h"
  38. #include "iwl-sta.h"
  39. #include "iwl-helpers.h"
  40. MODULE_DESCRIPTION("iwl core");
  41. MODULE_VERSION(IWLWIFI_VERSION);
  42. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  43. MODULE_LICENSE("GPL");
  44. static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  45. {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  46. 0, COEX_UNASSOC_IDLE_FLAGS},
  47. {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  48. 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  49. {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  50. 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  51. {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  52. 0, COEX_CALIBRATION_FLAGS},
  53. {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  54. 0, COEX_PERIODIC_CALIBRATION_FLAGS},
  55. {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  56. 0, COEX_CONNECTION_ESTAB_FLAGS},
  57. {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  58. 0, COEX_ASSOCIATED_IDLE_FLAGS},
  59. {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  60. 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  61. {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  62. 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  63. {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  64. 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  65. {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  66. {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  67. {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  68. 0, COEX_STAND_ALONE_DEBUG_FLAGS},
  69. {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
  70. 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
  71. {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
  72. {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
  73. };
  74. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  75. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  76. IWL_RATE_SISO_##s##M_PLCP, \
  77. IWL_RATE_MIMO2_##s##M_PLCP,\
  78. IWL_RATE_MIMO3_##s##M_PLCP,\
  79. IWL_RATE_##r##M_IEEE, \
  80. IWL_RATE_##ip##M_INDEX, \
  81. IWL_RATE_##in##M_INDEX, \
  82. IWL_RATE_##rp##M_INDEX, \
  83. IWL_RATE_##rn##M_INDEX, \
  84. IWL_RATE_##pp##M_INDEX, \
  85. IWL_RATE_##np##M_INDEX }
  86. u32 iwl_debug_level;
  87. EXPORT_SYMBOL(iwl_debug_level);
  88. static irqreturn_t iwl_isr(int irq, void *data);
  89. /*
  90. * Parameter order:
  91. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  92. *
  93. * If there isn't a valid next or previous rate then INV is used which
  94. * maps to IWL_RATE_INVALID
  95. *
  96. */
  97. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  98. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  99. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  100. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  101. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  102. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  103. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  104. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  105. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  106. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  107. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  108. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  109. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  110. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  111. /* FIXME:RS: ^^ should be INV (legacy) */
  112. };
  113. EXPORT_SYMBOL(iwl_rates);
  114. /**
  115. * translate ucode response to mac80211 tx status control values
  116. */
  117. void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  118. struct ieee80211_tx_info *info)
  119. {
  120. struct ieee80211_tx_rate *r = &info->control.rates[0];
  121. info->antenna_sel_tx =
  122. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  123. if (rate_n_flags & RATE_MCS_HT_MSK)
  124. r->flags |= IEEE80211_TX_RC_MCS;
  125. if (rate_n_flags & RATE_MCS_GF_MSK)
  126. r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
  127. if (rate_n_flags & RATE_MCS_HT40_MSK)
  128. r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
  129. if (rate_n_flags & RATE_MCS_DUP_MSK)
  130. r->flags |= IEEE80211_TX_RC_DUP_DATA;
  131. if (rate_n_flags & RATE_MCS_SGI_MSK)
  132. r->flags |= IEEE80211_TX_RC_SHORT_GI;
  133. r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
  134. }
  135. EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
  136. int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
  137. {
  138. int idx = 0;
  139. /* HT rate format */
  140. if (rate_n_flags & RATE_MCS_HT_MSK) {
  141. idx = (rate_n_flags & 0xff);
  142. if (idx >= IWL_RATE_MIMO3_6M_PLCP)
  143. idx = idx - IWL_RATE_MIMO3_6M_PLCP;
  144. else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  145. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  146. idx += IWL_FIRST_OFDM_RATE;
  147. /* skip 9M not supported in ht*/
  148. if (idx >= IWL_RATE_9M_INDEX)
  149. idx += 1;
  150. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  151. return idx;
  152. /* legacy rate format, search for match in table */
  153. } else {
  154. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  155. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  156. return idx;
  157. }
  158. return -1;
  159. }
  160. EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
  161. int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
  162. {
  163. int idx = 0;
  164. int band_offset = 0;
  165. /* HT rate format: mac80211 wants an MCS number, which is just LSB */
  166. if (rate_n_flags & RATE_MCS_HT_MSK) {
  167. idx = (rate_n_flags & 0xff);
  168. return idx;
  169. /* Legacy rate format, search for match in table */
  170. } else {
  171. if (band == IEEE80211_BAND_5GHZ)
  172. band_offset = IWL_FIRST_OFDM_RATE;
  173. for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
  174. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  175. return idx - band_offset;
  176. }
  177. return -1;
  178. }
  179. u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
  180. {
  181. int i;
  182. u8 ind = ant;
  183. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  184. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  185. if (priv->hw_params.valid_tx_ant & BIT(ind))
  186. return ind;
  187. }
  188. return ant;
  189. }
  190. EXPORT_SYMBOL(iwl_toggle_tx_ant);
  191. const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  192. EXPORT_SYMBOL(iwl_bcast_addr);
  193. /* This function both allocates and initializes hw and priv. */
  194. struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  195. struct ieee80211_ops *hw_ops)
  196. {
  197. struct iwl_priv *priv;
  198. /* mac80211 allocates memory for this device instance, including
  199. * space for this driver's private structure */
  200. struct ieee80211_hw *hw =
  201. ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
  202. if (hw == NULL) {
  203. printk(KERN_ERR "%s: Can not allocate network device\n",
  204. cfg->name);
  205. goto out;
  206. }
  207. priv = hw->priv;
  208. priv->hw = hw;
  209. out:
  210. return hw;
  211. }
  212. EXPORT_SYMBOL(iwl_alloc_all);
  213. void iwl_hw_detect(struct iwl_priv *priv)
  214. {
  215. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  216. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  217. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  218. }
  219. EXPORT_SYMBOL(iwl_hw_detect);
  220. int iwl_hw_nic_init(struct iwl_priv *priv)
  221. {
  222. unsigned long flags;
  223. struct iwl_rx_queue *rxq = &priv->rxq;
  224. int ret;
  225. /* nic_init */
  226. spin_lock_irqsave(&priv->lock, flags);
  227. priv->cfg->ops->lib->apm_ops.init(priv);
  228. /* Set interrupt coalescing timer to 512 usecs */
  229. iwl_write8(priv, CSR_INT_COALESCING, 512 / 32);
  230. spin_unlock_irqrestore(&priv->lock, flags);
  231. ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
  232. priv->cfg->ops->lib->apm_ops.config(priv);
  233. /* Allocate the RX queue, or reset if it is already allocated */
  234. if (!rxq->bd) {
  235. ret = iwl_rx_queue_alloc(priv);
  236. if (ret) {
  237. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  238. return -ENOMEM;
  239. }
  240. } else
  241. iwl_rx_queue_reset(priv, rxq);
  242. iwl_rx_replenish(priv);
  243. iwl_rx_init(priv, rxq);
  244. spin_lock_irqsave(&priv->lock, flags);
  245. rxq->need_update = 1;
  246. iwl_rx_queue_update_write_ptr(priv, rxq);
  247. spin_unlock_irqrestore(&priv->lock, flags);
  248. /* Allocate and init all Tx and Command queues */
  249. ret = iwl_txq_ctx_reset(priv);
  250. if (ret)
  251. return ret;
  252. set_bit(STATUS_INIT, &priv->status);
  253. return 0;
  254. }
  255. EXPORT_SYMBOL(iwl_hw_nic_init);
  256. /*
  257. * QoS support
  258. */
  259. void iwl_activate_qos(struct iwl_priv *priv, u8 force)
  260. {
  261. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  262. return;
  263. priv->qos_data.def_qos_parm.qos_flags = 0;
  264. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  265. !priv->qos_data.qos_cap.q_AP.txop_request)
  266. priv->qos_data.def_qos_parm.qos_flags |=
  267. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  268. if (priv->qos_data.qos_active)
  269. priv->qos_data.def_qos_parm.qos_flags |=
  270. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  271. if (priv->current_ht_config.is_ht)
  272. priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  273. if (force || iwl_is_associated(priv)) {
  274. IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  275. priv->qos_data.qos_active,
  276. priv->qos_data.def_qos_parm.qos_flags);
  277. iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
  278. sizeof(struct iwl_qosparam_cmd),
  279. &priv->qos_data.def_qos_parm, NULL);
  280. }
  281. }
  282. EXPORT_SYMBOL(iwl_activate_qos);
  283. /*
  284. * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
  285. * (802.11b) (802.11a/g)
  286. * AC_BK 15 1023 7 0 0
  287. * AC_BE 15 1023 3 0 0
  288. * AC_VI 7 15 2 6.016ms 3.008ms
  289. * AC_VO 3 7 2 3.264ms 1.504ms
  290. */
  291. void iwl_reset_qos(struct iwl_priv *priv)
  292. {
  293. u16 cw_min = 15;
  294. u16 cw_max = 1023;
  295. u8 aifs = 2;
  296. bool is_legacy = false;
  297. unsigned long flags;
  298. int i;
  299. spin_lock_irqsave(&priv->lock, flags);
  300. /* QoS always active in AP and ADHOC mode
  301. * In STA mode wait for association
  302. */
  303. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  304. priv->iw_mode == NL80211_IFTYPE_AP)
  305. priv->qos_data.qos_active = 1;
  306. else
  307. priv->qos_data.qos_active = 0;
  308. /* check for legacy mode */
  309. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  310. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  311. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  312. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  313. cw_min = 31;
  314. is_legacy = 1;
  315. }
  316. if (priv->qos_data.qos_active)
  317. aifs = 3;
  318. /* AC_BE */
  319. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  320. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  321. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  322. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  323. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  324. if (priv->qos_data.qos_active) {
  325. /* AC_BK */
  326. i = 1;
  327. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  328. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  329. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  330. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  331. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  332. /* AC_VI */
  333. i = 2;
  334. priv->qos_data.def_qos_parm.ac[i].cw_min =
  335. cpu_to_le16((cw_min + 1) / 2 - 1);
  336. priv->qos_data.def_qos_parm.ac[i].cw_max =
  337. cpu_to_le16(cw_min);
  338. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  339. if (is_legacy)
  340. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  341. cpu_to_le16(6016);
  342. else
  343. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  344. cpu_to_le16(3008);
  345. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  346. /* AC_VO */
  347. i = 3;
  348. priv->qos_data.def_qos_parm.ac[i].cw_min =
  349. cpu_to_le16((cw_min + 1) / 4 - 1);
  350. priv->qos_data.def_qos_parm.ac[i].cw_max =
  351. cpu_to_le16((cw_min + 1) / 2 - 1);
  352. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  353. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  354. if (is_legacy)
  355. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  356. cpu_to_le16(3264);
  357. else
  358. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  359. cpu_to_le16(1504);
  360. } else {
  361. for (i = 1; i < 4; i++) {
  362. priv->qos_data.def_qos_parm.ac[i].cw_min =
  363. cpu_to_le16(cw_min);
  364. priv->qos_data.def_qos_parm.ac[i].cw_max =
  365. cpu_to_le16(cw_max);
  366. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  367. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  368. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  369. }
  370. }
  371. IWL_DEBUG_QOS(priv, "set QoS to default \n");
  372. spin_unlock_irqrestore(&priv->lock, flags);
  373. }
  374. EXPORT_SYMBOL(iwl_reset_qos);
  375. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  376. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  377. static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
  378. struct ieee80211_sta_ht_cap *ht_info,
  379. enum ieee80211_band band)
  380. {
  381. u16 max_bit_rate = 0;
  382. u8 rx_chains_num = priv->hw_params.rx_chains_num;
  383. u8 tx_chains_num = priv->hw_params.tx_chains_num;
  384. ht_info->cap = 0;
  385. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  386. ht_info->ht_supported = true;
  387. if (priv->cfg->ht_greenfield_support)
  388. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  389. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  390. if (priv->cfg->support_sm_ps)
  391. ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
  392. (WLAN_HT_CAP_SM_PS_DYNAMIC << 2));
  393. else
  394. ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
  395. (WLAN_HT_CAP_SM_PS_DISABLED << 2));
  396. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  397. if (priv->hw_params.ht40_channel & BIT(band)) {
  398. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  399. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  400. ht_info->mcs.rx_mask[4] = 0x01;
  401. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  402. }
  403. if (priv->cfg->mod_params->amsdu_size_8K)
  404. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  405. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  406. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  407. ht_info->mcs.rx_mask[0] = 0xFF;
  408. if (rx_chains_num >= 2)
  409. ht_info->mcs.rx_mask[1] = 0xFF;
  410. if (rx_chains_num >= 3)
  411. ht_info->mcs.rx_mask[2] = 0xFF;
  412. /* Highest supported Rx data rate */
  413. max_bit_rate *= rx_chains_num;
  414. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  415. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  416. /* Tx MCS capabilities */
  417. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  418. if (tx_chains_num != rx_chains_num) {
  419. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  420. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  421. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  422. }
  423. }
  424. /**
  425. * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
  426. */
  427. int iwlcore_init_geos(struct iwl_priv *priv)
  428. {
  429. struct iwl_channel_info *ch;
  430. struct ieee80211_supported_band *sband;
  431. struct ieee80211_channel *channels;
  432. struct ieee80211_channel *geo_ch;
  433. struct ieee80211_rate *rates;
  434. int i = 0;
  435. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  436. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  437. IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
  438. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  439. return 0;
  440. }
  441. channels = kzalloc(sizeof(struct ieee80211_channel) *
  442. priv->channel_count, GFP_KERNEL);
  443. if (!channels)
  444. return -ENOMEM;
  445. rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
  446. GFP_KERNEL);
  447. if (!rates) {
  448. kfree(channels);
  449. return -ENOMEM;
  450. }
  451. /* 5.2GHz channels start after the 2.4GHz channels */
  452. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  453. sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
  454. /* just OFDM */
  455. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  456. sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
  457. if (priv->cfg->sku & IWL_SKU_N)
  458. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  459. IEEE80211_BAND_5GHZ);
  460. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  461. sband->channels = channels;
  462. /* OFDM & CCK */
  463. sband->bitrates = rates;
  464. sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
  465. if (priv->cfg->sku & IWL_SKU_N)
  466. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  467. IEEE80211_BAND_2GHZ);
  468. priv->ieee_channels = channels;
  469. priv->ieee_rates = rates;
  470. for (i = 0; i < priv->channel_count; i++) {
  471. ch = &priv->channel_info[i];
  472. /* FIXME: might be removed if scan is OK */
  473. if (!is_channel_valid(ch))
  474. continue;
  475. if (is_channel_a_band(ch))
  476. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  477. else
  478. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  479. geo_ch = &sband->channels[sband->n_channels++];
  480. geo_ch->center_freq =
  481. ieee80211_channel_to_frequency(ch->channel);
  482. geo_ch->max_power = ch->max_power_avg;
  483. geo_ch->max_antenna_gain = 0xff;
  484. geo_ch->hw_value = ch->channel;
  485. if (is_channel_valid(ch)) {
  486. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  487. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  488. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  489. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  490. if (ch->flags & EEPROM_CHANNEL_RADAR)
  491. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  492. geo_ch->flags |= ch->ht40_extension_channel;
  493. if (ch->max_power_avg > priv->tx_power_device_lmt)
  494. priv->tx_power_device_lmt = ch->max_power_avg;
  495. } else {
  496. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  497. }
  498. IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  499. ch->channel, geo_ch->center_freq,
  500. is_channel_a_band(ch) ? "5.2" : "2.4",
  501. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  502. "restricted" : "valid",
  503. geo_ch->flags);
  504. }
  505. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  506. priv->cfg->sku & IWL_SKU_A) {
  507. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  508. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  509. priv->pci_dev->device,
  510. priv->pci_dev->subsystem_device);
  511. priv->cfg->sku &= ~IWL_SKU_A;
  512. }
  513. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  514. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  515. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  516. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  517. return 0;
  518. }
  519. EXPORT_SYMBOL(iwlcore_init_geos);
  520. /*
  521. * iwlcore_free_geos - undo allocations in iwlcore_init_geos
  522. */
  523. void iwlcore_free_geos(struct iwl_priv *priv)
  524. {
  525. kfree(priv->ieee_channels);
  526. kfree(priv->ieee_rates);
  527. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  528. }
  529. EXPORT_SYMBOL(iwlcore_free_geos);
  530. /*
  531. * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
  532. * function.
  533. */
  534. void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
  535. __le32 *tx_flags)
  536. {
  537. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  538. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  539. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  540. } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  541. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  542. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  543. }
  544. }
  545. EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
  546. static bool is_single_rx_stream(struct iwl_priv *priv)
  547. {
  548. return !priv->current_ht_config.is_ht ||
  549. priv->current_ht_config.single_chain_sufficient;
  550. }
  551. static u8 iwl_is_channel_extension(struct iwl_priv *priv,
  552. enum ieee80211_band band,
  553. u16 channel, u8 extension_chan_offset)
  554. {
  555. const struct iwl_channel_info *ch_info;
  556. ch_info = iwl_get_channel_info(priv, band, channel);
  557. if (!is_channel_valid(ch_info))
  558. return 0;
  559. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  560. return !(ch_info->ht40_extension_channel &
  561. IEEE80211_CHAN_NO_HT40PLUS);
  562. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  563. return !(ch_info->ht40_extension_channel &
  564. IEEE80211_CHAN_NO_HT40MINUS);
  565. return 0;
  566. }
  567. u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
  568. struct ieee80211_sta_ht_cap *sta_ht_inf)
  569. {
  570. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  571. if (!ht_conf->is_ht || !ht_conf->is_40mhz)
  572. return 0;
  573. /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  574. * the bit will not set if it is pure 40MHz case
  575. */
  576. if (sta_ht_inf) {
  577. if (!sta_ht_inf->ht_supported)
  578. return 0;
  579. }
  580. #ifdef CONFIG_IWLWIFI_DEBUG
  581. if (priv->disable_ht40)
  582. return 0;
  583. #endif
  584. return iwl_is_channel_extension(priv, priv->band,
  585. le16_to_cpu(priv->staging_rxon.channel),
  586. ht_conf->extension_chan_offset);
  587. }
  588. EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
  589. static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  590. {
  591. u16 new_val = 0;
  592. u16 beacon_factor = 0;
  593. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  594. new_val = beacon_val / beacon_factor;
  595. if (!new_val)
  596. new_val = max_beacon_val;
  597. return new_val;
  598. }
  599. void iwl_setup_rxon_timing(struct iwl_priv *priv)
  600. {
  601. u64 tsf;
  602. s32 interval_tm, rem;
  603. unsigned long flags;
  604. struct ieee80211_conf *conf = NULL;
  605. u16 beacon_int;
  606. conf = ieee80211_get_hw_conf(priv->hw);
  607. spin_lock_irqsave(&priv->lock, flags);
  608. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  609. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  610. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  611. beacon_int = priv->beacon_int;
  612. priv->rxon_timing.atim_window = 0;
  613. } else {
  614. beacon_int = priv->vif->bss_conf.beacon_int;
  615. /* TODO: we need to get atim_window from upper stack
  616. * for now we set to 0 */
  617. priv->rxon_timing.atim_window = 0;
  618. }
  619. beacon_int = iwl_adjust_beacon_interval(beacon_int,
  620. priv->hw_params.max_beacon_itrvl * 1024);
  621. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  622. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  623. interval_tm = beacon_int * 1024;
  624. rem = do_div(tsf, interval_tm);
  625. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  626. spin_unlock_irqrestore(&priv->lock, flags);
  627. IWL_DEBUG_ASSOC(priv,
  628. "beacon interval %d beacon timer %d beacon tim %d\n",
  629. le16_to_cpu(priv->rxon_timing.beacon_interval),
  630. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  631. le16_to_cpu(priv->rxon_timing.atim_window));
  632. }
  633. EXPORT_SYMBOL(iwl_setup_rxon_timing);
  634. void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  635. {
  636. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  637. if (hw_decrypt)
  638. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  639. else
  640. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  641. }
  642. EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
  643. /**
  644. * iwl_check_rxon_cmd - validate RXON structure is valid
  645. *
  646. * NOTE: This is really only useful during development and can eventually
  647. * be #ifdef'd out once the driver is stable and folks aren't actively
  648. * making changes
  649. */
  650. int iwl_check_rxon_cmd(struct iwl_priv *priv)
  651. {
  652. int error = 0;
  653. int counter = 1;
  654. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  655. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  656. error |= le32_to_cpu(rxon->flags &
  657. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  658. RXON_FLG_RADAR_DETECT_MSK));
  659. if (error)
  660. IWL_WARN(priv, "check 24G fields %d | %d\n",
  661. counter++, error);
  662. } else {
  663. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  664. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  665. if (error)
  666. IWL_WARN(priv, "check 52 fields %d | %d\n",
  667. counter++, error);
  668. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  669. if (error)
  670. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  671. counter++, error);
  672. }
  673. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  674. if (error)
  675. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  676. /* make sure basic rates 6Mbps and 1Mbps are supported */
  677. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  678. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  679. if (error)
  680. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  681. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  682. if (error)
  683. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  684. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  685. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  686. if (error)
  687. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  688. counter++, error);
  689. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  690. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  691. if (error)
  692. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  693. counter++, error);
  694. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  695. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  696. if (error)
  697. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  698. counter++, error);
  699. if (error)
  700. IWL_WARN(priv, "Tuning to channel %d\n",
  701. le16_to_cpu(rxon->channel));
  702. if (error) {
  703. IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
  704. return -1;
  705. }
  706. return 0;
  707. }
  708. EXPORT_SYMBOL(iwl_check_rxon_cmd);
  709. /**
  710. * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  711. * @priv: staging_rxon is compared to active_rxon
  712. *
  713. * If the RXON structure is changing enough to require a new tune,
  714. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  715. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  716. */
  717. int iwl_full_rxon_required(struct iwl_priv *priv)
  718. {
  719. /* These items are only settable from the full RXON command */
  720. if (!(iwl_is_associated(priv)) ||
  721. compare_ether_addr(priv->staging_rxon.bssid_addr,
  722. priv->active_rxon.bssid_addr) ||
  723. compare_ether_addr(priv->staging_rxon.node_addr,
  724. priv->active_rxon.node_addr) ||
  725. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  726. priv->active_rxon.wlap_bssid_addr) ||
  727. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  728. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  729. (priv->staging_rxon.air_propagation !=
  730. priv->active_rxon.air_propagation) ||
  731. (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
  732. priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
  733. (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
  734. priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
  735. (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
  736. priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
  737. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  738. return 1;
  739. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  740. * be updated with the RXON_ASSOC command -- however only some
  741. * flag transitions are allowed using RXON_ASSOC */
  742. /* Check if we are not switching bands */
  743. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  744. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  745. return 1;
  746. /* Check if we are switching association toggle */
  747. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  748. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  749. return 1;
  750. return 0;
  751. }
  752. EXPORT_SYMBOL(iwl_full_rxon_required);
  753. u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
  754. {
  755. int i;
  756. int rate_mask;
  757. /* Set rate mask*/
  758. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  759. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  760. else
  761. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  762. /* Find lowest valid rate */
  763. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  764. i = iwl_rates[i].next_ieee) {
  765. if (rate_mask & (1 << i))
  766. return iwl_rates[i].plcp;
  767. }
  768. /* No valid rate was found. Assign the lowest one */
  769. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  770. return IWL_RATE_1M_PLCP;
  771. else
  772. return IWL_RATE_6M_PLCP;
  773. }
  774. EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
  775. void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
  776. {
  777. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  778. if (!ht_conf->is_ht) {
  779. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  780. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  781. RXON_FLG_HT40_PROT_MSK |
  782. RXON_FLG_HT_PROT_MSK);
  783. return;
  784. }
  785. /* FIXME: if the definition of ht_protection changed, the "translation"
  786. * will be needed for rxon->flags
  787. */
  788. rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
  789. /* Set up channel bandwidth:
  790. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  791. /* clear the HT channel mode before set the mode */
  792. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  793. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  794. if (iwl_is_ht40_tx_allowed(priv, NULL)) {
  795. /* pure ht40 */
  796. if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  797. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  798. /* Note: control channel is opposite of extension channel */
  799. switch (ht_conf->extension_chan_offset) {
  800. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  801. rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  802. break;
  803. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  804. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  805. break;
  806. }
  807. } else {
  808. /* Note: control channel is opposite of extension channel */
  809. switch (ht_conf->extension_chan_offset) {
  810. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  811. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  812. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  813. break;
  814. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  815. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  816. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  817. break;
  818. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  819. default:
  820. /* channel location only valid if in Mixed mode */
  821. IWL_ERR(priv, "invalid extension channel offset\n");
  822. break;
  823. }
  824. }
  825. } else {
  826. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  827. }
  828. if (priv->cfg->ops->hcmd->set_rxon_chain)
  829. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  830. IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
  831. "extension channel offset 0x%x\n",
  832. le32_to_cpu(rxon->flags), ht_conf->ht_protection,
  833. ht_conf->extension_chan_offset);
  834. return;
  835. }
  836. EXPORT_SYMBOL(iwl_set_rxon_ht);
  837. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  838. #define IWL_NUM_RX_CHAINS_SINGLE 2
  839. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  840. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  841. /*
  842. * Determine how many receiver/antenna chains to use.
  843. *
  844. * More provides better reception via diversity. Fewer saves power
  845. * at the expense of throughput, but only when not in powersave to
  846. * start with.
  847. *
  848. * MIMO (dual stream) requires at least 2, but works better with 3.
  849. * This does not determine *which* chains to use, just how many.
  850. */
  851. static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
  852. {
  853. /* # of Rx chains to use when expecting MIMO. */
  854. if (is_single_rx_stream(priv))
  855. return IWL_NUM_RX_CHAINS_SINGLE;
  856. else
  857. return IWL_NUM_RX_CHAINS_MULTIPLE;
  858. }
  859. /*
  860. * When we are in power saving mode, unless device support spatial
  861. * multiplexing power save, use the active count for rx chain count.
  862. */
  863. static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  864. {
  865. int idle_cnt = active_cnt;
  866. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  867. if (priv->cfg->support_sm_ps) {
  868. /* # Rx chains when idling and maybe trying to save power */
  869. switch (priv->current_ht_config.sm_ps) {
  870. case WLAN_HT_CAP_SM_PS_STATIC:
  871. case WLAN_HT_CAP_SM_PS_DYNAMIC:
  872. idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
  873. IWL_NUM_IDLE_CHAINS_SINGLE;
  874. break;
  875. case WLAN_HT_CAP_SM_PS_DISABLED:
  876. idle_cnt = (is_cam) ? active_cnt :
  877. IWL_NUM_IDLE_CHAINS_SINGLE;
  878. break;
  879. case WLAN_HT_CAP_SM_PS_INVALID:
  880. default:
  881. IWL_ERR(priv, "invalid sm_ps mode %d\n",
  882. priv->current_ht_config.sm_ps);
  883. WARN_ON(1);
  884. break;
  885. }
  886. }
  887. return idle_cnt;
  888. }
  889. /* up to 4 chains */
  890. static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
  891. {
  892. u8 res;
  893. res = (chain_bitmap & BIT(0)) >> 0;
  894. res += (chain_bitmap & BIT(1)) >> 1;
  895. res += (chain_bitmap & BIT(2)) >> 2;
  896. res += (chain_bitmap & BIT(3)) >> 3;
  897. return res;
  898. }
  899. /**
  900. * iwl_is_monitor_mode - Determine if interface in monitor mode
  901. *
  902. * priv->iw_mode is set in add_interface, but add_interface is
  903. * never called for monitor mode. The only way mac80211 informs us about
  904. * monitor mode is through configuring filters (call to configure_filter).
  905. */
  906. bool iwl_is_monitor_mode(struct iwl_priv *priv)
  907. {
  908. return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
  909. }
  910. EXPORT_SYMBOL(iwl_is_monitor_mode);
  911. /**
  912. * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  913. *
  914. * Selects how many and which Rx receivers/antennas/chains to use.
  915. * This should not be used for scan command ... it puts data in wrong place.
  916. */
  917. void iwl_set_rxon_chain(struct iwl_priv *priv)
  918. {
  919. bool is_single = is_single_rx_stream(priv);
  920. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  921. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  922. u32 active_chains;
  923. u16 rx_chain;
  924. /* Tell uCode which antennas are actually connected.
  925. * Before first association, we assume all antennas are connected.
  926. * Just after first association, iwl_chain_noise_calibration()
  927. * checks which antennas actually *are* connected. */
  928. if (priv->chain_noise_data.active_chains)
  929. active_chains = priv->chain_noise_data.active_chains;
  930. else
  931. active_chains = priv->hw_params.valid_rx_ant;
  932. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  933. /* How many receivers should we use? */
  934. active_rx_cnt = iwl_get_active_rx_chain_count(priv);
  935. idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
  936. /* correct rx chain count according hw settings
  937. * and chain noise calibration
  938. */
  939. valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
  940. if (valid_rx_cnt < active_rx_cnt)
  941. active_rx_cnt = valid_rx_cnt;
  942. if (valid_rx_cnt < idle_rx_cnt)
  943. idle_rx_cnt = valid_rx_cnt;
  944. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  945. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  946. /* copied from 'iwl_bg_request_scan()' */
  947. /* Force use of chains B and C (0x6) for Rx for 4965
  948. * Avoid A (0x1) because of its off-channel reception on A-band.
  949. * MIMO is not used here, but value is required */
  950. if (iwl_is_monitor_mode(priv) &&
  951. !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
  952. ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
  953. rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
  954. rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
  955. rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  956. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  957. }
  958. priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
  959. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  960. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  961. else
  962. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  963. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  964. priv->staging_rxon.rx_chain,
  965. active_rx_cnt, idle_rx_cnt);
  966. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  967. active_rx_cnt < idle_rx_cnt);
  968. }
  969. EXPORT_SYMBOL(iwl_set_rxon_chain);
  970. /**
  971. * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
  972. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  973. * @channel: Any channel valid for the requested phymode
  974. * In addition to setting the staging RXON, priv->phymode is also set.
  975. *
  976. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  977. * in the staging RXON flag structure based on the phymode
  978. */
  979. int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
  980. {
  981. enum ieee80211_band band = ch->band;
  982. u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
  983. if (!iwl_get_channel_info(priv, band, channel)) {
  984. IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
  985. channel, band);
  986. return -EINVAL;
  987. }
  988. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  989. (priv->band == band))
  990. return 0;
  991. priv->staging_rxon.channel = cpu_to_le16(channel);
  992. if (band == IEEE80211_BAND_5GHZ)
  993. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  994. else
  995. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  996. priv->band = band;
  997. IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
  998. return 0;
  999. }
  1000. EXPORT_SYMBOL(iwl_set_rxon_channel);
  1001. void iwl_set_flags_for_band(struct iwl_priv *priv,
  1002. enum ieee80211_band band)
  1003. {
  1004. if (band == IEEE80211_BAND_5GHZ) {
  1005. priv->staging_rxon.flags &=
  1006. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1007. | RXON_FLG_CCK_MSK);
  1008. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1009. } else {
  1010. /* Copied from iwl_post_associate() */
  1011. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1012. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1013. else
  1014. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1015. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1016. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1017. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1018. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1019. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1020. }
  1021. }
  1022. /*
  1023. * initialize rxon structure with default values from eeprom
  1024. */
  1025. void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
  1026. {
  1027. const struct iwl_channel_info *ch_info;
  1028. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1029. switch (mode) {
  1030. case NL80211_IFTYPE_AP:
  1031. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1032. break;
  1033. case NL80211_IFTYPE_STATION:
  1034. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1035. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1036. break;
  1037. case NL80211_IFTYPE_ADHOC:
  1038. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1039. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1040. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1041. RXON_FILTER_ACCEPT_GRP_MSK;
  1042. break;
  1043. default:
  1044. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1045. break;
  1046. }
  1047. #if 0
  1048. /* TODO: Figure out when short_preamble would be set and cache from
  1049. * that */
  1050. if (!hw_to_local(priv->hw)->short_preamble)
  1051. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1052. else
  1053. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1054. #endif
  1055. ch_info = iwl_get_channel_info(priv, priv->band,
  1056. le16_to_cpu(priv->active_rxon.channel));
  1057. if (!ch_info)
  1058. ch_info = &priv->channel_info[0];
  1059. /*
  1060. * in some case A channels are all non IBSS
  1061. * in this case force B/G channel
  1062. */
  1063. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  1064. !(is_channel_ibss(ch_info)))
  1065. ch_info = &priv->channel_info[0];
  1066. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1067. priv->band = ch_info->band;
  1068. iwl_set_flags_for_band(priv, priv->band);
  1069. priv->staging_rxon.ofdm_basic_rates =
  1070. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1071. priv->staging_rxon.cck_basic_rates =
  1072. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1073. /* clear both MIX and PURE40 mode flag */
  1074. priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
  1075. RXON_FLG_CHANNEL_MODE_PURE_40);
  1076. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1077. memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
  1078. priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
  1079. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
  1080. priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
  1081. }
  1082. EXPORT_SYMBOL(iwl_connection_init_rx_config);
  1083. static void iwl_set_rate(struct iwl_priv *priv)
  1084. {
  1085. const struct ieee80211_supported_band *hw = NULL;
  1086. struct ieee80211_rate *rate;
  1087. int i;
  1088. hw = iwl_get_hw_mode(priv, priv->band);
  1089. if (!hw) {
  1090. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  1091. return;
  1092. }
  1093. priv->active_rate = 0;
  1094. priv->active_rate_basic = 0;
  1095. for (i = 0; i < hw->n_bitrates; i++) {
  1096. rate = &(hw->bitrates[i]);
  1097. if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
  1098. priv->active_rate |= (1 << rate->hw_value);
  1099. }
  1100. IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
  1101. priv->active_rate, priv->active_rate_basic);
  1102. /*
  1103. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  1104. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  1105. * OFDM
  1106. */
  1107. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  1108. priv->staging_rxon.cck_basic_rates =
  1109. ((priv->active_rate_basic &
  1110. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  1111. else
  1112. priv->staging_rxon.cck_basic_rates =
  1113. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1114. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  1115. priv->staging_rxon.ofdm_basic_rates =
  1116. ((priv->active_rate_basic &
  1117. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  1118. IWL_FIRST_OFDM_RATE) & 0xFF;
  1119. else
  1120. priv->staging_rxon.ofdm_basic_rates =
  1121. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1122. }
  1123. void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  1124. {
  1125. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1126. struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
  1127. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  1128. if (priv->switch_rxon.switch_in_progress) {
  1129. if (!le32_to_cpu(csa->status) &&
  1130. (csa->channel == priv->switch_rxon.channel)) {
  1131. rxon->channel = csa->channel;
  1132. priv->staging_rxon.channel = csa->channel;
  1133. IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
  1134. le16_to_cpu(csa->channel));
  1135. } else
  1136. IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
  1137. le16_to_cpu(csa->channel));
  1138. priv->switch_rxon.switch_in_progress = false;
  1139. }
  1140. }
  1141. EXPORT_SYMBOL(iwl_rx_csa);
  1142. #ifdef CONFIG_IWLWIFI_DEBUG
  1143. void iwl_print_rx_config_cmd(struct iwl_priv *priv)
  1144. {
  1145. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  1146. IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
  1147. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  1148. IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  1149. IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  1150. IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
  1151. le32_to_cpu(rxon->filter_flags));
  1152. IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
  1153. IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
  1154. rxon->ofdm_basic_rates);
  1155. IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  1156. IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
  1157. IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  1158. IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  1159. }
  1160. EXPORT_SYMBOL(iwl_print_rx_config_cmd);
  1161. #endif
  1162. /**
  1163. * iwl_irq_handle_error - called for HW or SW error interrupt from card
  1164. */
  1165. void iwl_irq_handle_error(struct iwl_priv *priv)
  1166. {
  1167. /* Set the FW error flag -- cleared on iwl_down */
  1168. set_bit(STATUS_FW_ERROR, &priv->status);
  1169. /* Cancel currently queued command. */
  1170. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  1171. #ifdef CONFIG_IWLWIFI_DEBUG
  1172. if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
  1173. priv->cfg->ops->lib->dump_nic_error_log(priv);
  1174. priv->cfg->ops->lib->dump_nic_event_log(priv);
  1175. iwl_print_rx_config_cmd(priv);
  1176. }
  1177. #endif
  1178. wake_up_interruptible(&priv->wait_command_queue);
  1179. /* Keep the restart process from trying to send host
  1180. * commands by clearing the INIT status bit */
  1181. clear_bit(STATUS_READY, &priv->status);
  1182. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1183. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  1184. "Restarting adapter due to uCode error.\n");
  1185. if (priv->cfg->mod_params->restart_fw)
  1186. queue_work(priv->workqueue, &priv->restart);
  1187. }
  1188. }
  1189. EXPORT_SYMBOL(iwl_irq_handle_error);
  1190. int iwl_apm_stop_master(struct iwl_priv *priv)
  1191. {
  1192. int ret = 0;
  1193. /* stop device's busmaster DMA activity */
  1194. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  1195. ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  1196. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  1197. if (ret)
  1198. IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
  1199. IWL_DEBUG_INFO(priv, "stop master\n");
  1200. return ret;
  1201. }
  1202. EXPORT_SYMBOL(iwl_apm_stop_master);
  1203. void iwl_apm_stop(struct iwl_priv *priv)
  1204. {
  1205. IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
  1206. /* Stop device's DMA activity */
  1207. iwl_apm_stop_master(priv);
  1208. /* Reset the entire device */
  1209. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  1210. udelay(10);
  1211. /*
  1212. * Clear "initialization complete" bit to move adapter from
  1213. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  1214. */
  1215. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1216. }
  1217. EXPORT_SYMBOL(iwl_apm_stop);
  1218. /*
  1219. * Start up NIC's basic functionality after it has been reset
  1220. * (e.g. after platform boot, or shutdown via iwl_apm_stop())
  1221. * NOTE: This does not load uCode nor start the embedded processor
  1222. */
  1223. int iwl_apm_init(struct iwl_priv *priv)
  1224. {
  1225. int ret = 0;
  1226. u16 lctl;
  1227. IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
  1228. /*
  1229. * Use "set_bit" below rather than "write", to preserve any hardware
  1230. * bits already set by default after reset.
  1231. */
  1232. /* Disable L0S exit timer (platform NMI Work/Around) */
  1233. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  1234. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  1235. /*
  1236. * Disable L0s without affecting L1;
  1237. * don't wait for ICH L0s (ICH bug W/A)
  1238. */
  1239. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  1240. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  1241. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  1242. iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  1243. /*
  1244. * Enable HAP INTA (interrupt from management bus) to
  1245. * wake device's PCI Express link L1a -> L0s
  1246. * NOTE: This is no-op for 3945 (non-existant bit)
  1247. */
  1248. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1249. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  1250. /*
  1251. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  1252. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  1253. * If so (likely), disable L0S, so device moves directly L0->L1;
  1254. * costs negligible amount of power savings.
  1255. * If not (unlikely), enable L0S, so there is at least some
  1256. * power savings, even without L1.
  1257. */
  1258. if (priv->cfg->set_l0s) {
  1259. lctl = iwl_pcie_link_ctl(priv);
  1260. if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
  1261. PCI_CFG_LINK_CTRL_VAL_L1_EN) {
  1262. /* L1-ASPM enabled; disable(!) L0S */
  1263. iwl_set_bit(priv, CSR_GIO_REG,
  1264. CSR_GIO_REG_VAL_L0S_ENABLED);
  1265. IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
  1266. } else {
  1267. /* L1-ASPM disabled; enable(!) L0S */
  1268. iwl_clear_bit(priv, CSR_GIO_REG,
  1269. CSR_GIO_REG_VAL_L0S_ENABLED);
  1270. IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
  1271. }
  1272. }
  1273. /* Configure analog phase-lock-loop before activating to D0A */
  1274. if (priv->cfg->pll_cfg_val)
  1275. iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
  1276. /*
  1277. * Set "initialization complete" bit to move adapter from
  1278. * D0U* --> D0A* (powered-up active) state.
  1279. */
  1280. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1281. /*
  1282. * Wait for clock stabilization; once stabilized, access to
  1283. * device-internal resources is supported, e.g. iwl_write_prph()
  1284. * and accesses to uCode SRAM.
  1285. */
  1286. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  1287. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  1288. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  1289. if (ret < 0) {
  1290. IWL_DEBUG_INFO(priv, "Failed to init the card\n");
  1291. goto out;
  1292. }
  1293. /*
  1294. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  1295. * BSM (Boostrap State Machine) is only in 3945 and 4965;
  1296. * later devices (i.e. 5000 and later) have non-volatile SRAM,
  1297. * and don't need BSM to restore data after power-saving sleep.
  1298. *
  1299. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  1300. * do not disable clocks. This preserves any hardware bits already
  1301. * set by default in "CLK_CTRL_REG" after reset.
  1302. */
  1303. if (priv->cfg->use_bsm)
  1304. iwl_write_prph(priv, APMG_CLK_EN_REG,
  1305. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  1306. else
  1307. iwl_write_prph(priv, APMG_CLK_EN_REG,
  1308. APMG_CLK_VAL_DMA_CLK_RQT);
  1309. udelay(20);
  1310. /* Disable L1-Active */
  1311. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  1312. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  1313. out:
  1314. return ret;
  1315. }
  1316. EXPORT_SYMBOL(iwl_apm_init);
  1317. void iwl_configure_filter(struct ieee80211_hw *hw,
  1318. unsigned int changed_flags,
  1319. unsigned int *total_flags,
  1320. u64 multicast)
  1321. {
  1322. struct iwl_priv *priv = hw->priv;
  1323. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  1324. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  1325. changed_flags, *total_flags);
  1326. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  1327. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  1328. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  1329. else
  1330. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  1331. }
  1332. if (changed_flags & FIF_ALLMULTI) {
  1333. if (*total_flags & FIF_ALLMULTI)
  1334. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  1335. else
  1336. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  1337. }
  1338. if (changed_flags & FIF_CONTROL) {
  1339. if (*total_flags & FIF_CONTROL)
  1340. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  1341. else
  1342. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  1343. }
  1344. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1345. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1346. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  1347. else
  1348. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  1349. }
  1350. /* We avoid iwl_commit_rxon here to commit the new filter flags
  1351. * since mac80211 will call ieee80211_hw_config immediately.
  1352. * (mc_list is not supported at this time). Otherwise, we need to
  1353. * queue a background iwl_commit_rxon work.
  1354. */
  1355. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  1356. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  1357. }
  1358. EXPORT_SYMBOL(iwl_configure_filter);
  1359. int iwl_set_hw_params(struct iwl_priv *priv)
  1360. {
  1361. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  1362. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1363. if (priv->cfg->mod_params->amsdu_size_8K)
  1364. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
  1365. else
  1366. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
  1367. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  1368. if (priv->cfg->mod_params->disable_11n)
  1369. priv->cfg->sku &= ~IWL_SKU_N;
  1370. /* Device-specific setup */
  1371. return priv->cfg->ops->lib->set_hw_params(priv);
  1372. }
  1373. EXPORT_SYMBOL(iwl_set_hw_params);
  1374. int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
  1375. {
  1376. int ret = 0;
  1377. s8 prev_tx_power = priv->tx_power_user_lmt;
  1378. if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
  1379. IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
  1380. tx_power,
  1381. IWL_TX_POWER_TARGET_POWER_MIN);
  1382. return -EINVAL;
  1383. }
  1384. if (tx_power > priv->tx_power_device_lmt) {
  1385. IWL_WARN(priv,
  1386. "Requested user TXPOWER %d above upper limit %d.\n",
  1387. tx_power, priv->tx_power_device_lmt);
  1388. return -EINVAL;
  1389. }
  1390. if (priv->tx_power_user_lmt != tx_power)
  1391. force = true;
  1392. /* if nic is not up don't send command */
  1393. if (iwl_is_ready_rf(priv)) {
  1394. priv->tx_power_user_lmt = tx_power;
  1395. if (force && priv->cfg->ops->lib->send_tx_power)
  1396. ret = priv->cfg->ops->lib->send_tx_power(priv);
  1397. else if (!priv->cfg->ops->lib->send_tx_power)
  1398. ret = -EOPNOTSUPP;
  1399. /*
  1400. * if fail to set tx_power, restore the orig. tx power
  1401. */
  1402. if (ret)
  1403. priv->tx_power_user_lmt = prev_tx_power;
  1404. }
  1405. /*
  1406. * Even this is an async host command, the command
  1407. * will always report success from uCode
  1408. * So once driver can placing the command into the queue
  1409. * successfully, driver can use priv->tx_power_user_lmt
  1410. * to reflect the current tx power
  1411. */
  1412. return ret;
  1413. }
  1414. EXPORT_SYMBOL(iwl_set_tx_power);
  1415. #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
  1416. /* Free dram table */
  1417. void iwl_free_isr_ict(struct iwl_priv *priv)
  1418. {
  1419. if (priv->ict_tbl_vir) {
  1420. pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
  1421. PAGE_SIZE, priv->ict_tbl_vir,
  1422. priv->ict_tbl_dma);
  1423. priv->ict_tbl_vir = NULL;
  1424. }
  1425. }
  1426. EXPORT_SYMBOL(iwl_free_isr_ict);
  1427. /* allocate dram shared table it is a PAGE_SIZE aligned
  1428. * also reset all data related to ICT table interrupt.
  1429. */
  1430. int iwl_alloc_isr_ict(struct iwl_priv *priv)
  1431. {
  1432. if (priv->cfg->use_isr_legacy)
  1433. return 0;
  1434. /* allocate shrared data table */
  1435. priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
  1436. ICT_COUNT) + PAGE_SIZE,
  1437. &priv->ict_tbl_dma);
  1438. if (!priv->ict_tbl_vir)
  1439. return -ENOMEM;
  1440. /* align table to PAGE_SIZE boundry */
  1441. priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
  1442. IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
  1443. (unsigned long long)priv->ict_tbl_dma,
  1444. (unsigned long long)priv->aligned_ict_tbl_dma,
  1445. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1446. priv->ict_tbl = priv->ict_tbl_vir +
  1447. (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
  1448. IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
  1449. priv->ict_tbl, priv->ict_tbl_vir,
  1450. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1451. /* reset table and index to all 0 */
  1452. memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
  1453. priv->ict_index = 0;
  1454. /* add periodic RX interrupt */
  1455. priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
  1456. return 0;
  1457. }
  1458. EXPORT_SYMBOL(iwl_alloc_isr_ict);
  1459. /* Device is going up inform it about using ICT interrupt table,
  1460. * also we need to tell the driver to start using ICT interrupt.
  1461. */
  1462. int iwl_reset_ict(struct iwl_priv *priv)
  1463. {
  1464. u32 val;
  1465. unsigned long flags;
  1466. if (!priv->ict_tbl_vir)
  1467. return 0;
  1468. spin_lock_irqsave(&priv->lock, flags);
  1469. iwl_disable_interrupts(priv);
  1470. memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
  1471. val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
  1472. val |= CSR_DRAM_INT_TBL_ENABLE;
  1473. val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
  1474. IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
  1475. "aligned dma address %Lx\n",
  1476. val, (unsigned long long)priv->aligned_ict_tbl_dma);
  1477. iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
  1478. priv->use_ict = true;
  1479. priv->ict_index = 0;
  1480. iwl_write32(priv, CSR_INT, priv->inta_mask);
  1481. iwl_enable_interrupts(priv);
  1482. spin_unlock_irqrestore(&priv->lock, flags);
  1483. return 0;
  1484. }
  1485. EXPORT_SYMBOL(iwl_reset_ict);
  1486. /* Device is going down disable ict interrupt usage */
  1487. void iwl_disable_ict(struct iwl_priv *priv)
  1488. {
  1489. unsigned long flags;
  1490. spin_lock_irqsave(&priv->lock, flags);
  1491. priv->use_ict = false;
  1492. spin_unlock_irqrestore(&priv->lock, flags);
  1493. }
  1494. EXPORT_SYMBOL(iwl_disable_ict);
  1495. /* interrupt handler using ict table, with this interrupt driver will
  1496. * stop using INTA register to get device's interrupt, reading this register
  1497. * is expensive, device will write interrupts in ICT dram table, increment
  1498. * index then will fire interrupt to driver, driver will OR all ICT table
  1499. * entries from current index up to table entry with 0 value. the result is
  1500. * the interrupt we need to service, driver will set the entries back to 0 and
  1501. * set index.
  1502. */
  1503. irqreturn_t iwl_isr_ict(int irq, void *data)
  1504. {
  1505. struct iwl_priv *priv = data;
  1506. u32 inta, inta_mask;
  1507. u32 val = 0;
  1508. if (!priv)
  1509. return IRQ_NONE;
  1510. /* dram interrupt table not set yet,
  1511. * use legacy interrupt.
  1512. */
  1513. if (!priv->use_ict)
  1514. return iwl_isr(irq, data);
  1515. spin_lock(&priv->lock);
  1516. /* Disable (but don't clear!) interrupts here to avoid
  1517. * back-to-back ISRs and sporadic interrupts from our NIC.
  1518. * If we have something to service, the tasklet will re-enable ints.
  1519. * If we *don't* have something, we'll re-enable before leaving here.
  1520. */
  1521. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1522. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1523. /* Ignore interrupt if there's nothing in NIC to service.
  1524. * This may be due to IRQ shared with another device,
  1525. * or due to sporadic interrupts thrown from our NIC. */
  1526. if (!priv->ict_tbl[priv->ict_index]) {
  1527. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1528. goto none;
  1529. }
  1530. /* read all entries that not 0 start with ict_index */
  1531. while (priv->ict_tbl[priv->ict_index]) {
  1532. val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
  1533. IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
  1534. priv->ict_index,
  1535. le32_to_cpu(priv->ict_tbl[priv->ict_index]));
  1536. priv->ict_tbl[priv->ict_index] = 0;
  1537. priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
  1538. ICT_COUNT);
  1539. }
  1540. /* We should not get this value, just ignore it. */
  1541. if (val == 0xffffffff)
  1542. val = 0;
  1543. inta = (0xff & val) | ((0xff00 & val) << 16);
  1544. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
  1545. inta, inta_mask, val);
  1546. inta &= priv->inta_mask;
  1547. priv->inta |= inta;
  1548. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1549. if (likely(inta))
  1550. tasklet_schedule(&priv->irq_tasklet);
  1551. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
  1552. /* Allow interrupt if was disabled by this handler and
  1553. * no tasklet was schedules, We should not enable interrupt,
  1554. * tasklet will enable it.
  1555. */
  1556. iwl_enable_interrupts(priv);
  1557. }
  1558. spin_unlock(&priv->lock);
  1559. return IRQ_HANDLED;
  1560. none:
  1561. /* re-enable interrupts here since we don't have anything to service.
  1562. * only Re-enable if disabled by irq.
  1563. */
  1564. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1565. iwl_enable_interrupts(priv);
  1566. spin_unlock(&priv->lock);
  1567. return IRQ_NONE;
  1568. }
  1569. EXPORT_SYMBOL(iwl_isr_ict);
  1570. static irqreturn_t iwl_isr(int irq, void *data)
  1571. {
  1572. struct iwl_priv *priv = data;
  1573. u32 inta, inta_mask;
  1574. #ifdef CONFIG_IWLWIFI_DEBUG
  1575. u32 inta_fh;
  1576. #endif
  1577. if (!priv)
  1578. return IRQ_NONE;
  1579. spin_lock(&priv->lock);
  1580. /* Disable (but don't clear!) interrupts here to avoid
  1581. * back-to-back ISRs and sporadic interrupts from our NIC.
  1582. * If we have something to service, the tasklet will re-enable ints.
  1583. * If we *don't* have something, we'll re-enable before leaving here. */
  1584. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1585. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1586. /* Discover which interrupts are active/pending */
  1587. inta = iwl_read32(priv, CSR_INT);
  1588. /* Ignore interrupt if there's nothing in NIC to service.
  1589. * This may be due to IRQ shared with another device,
  1590. * or due to sporadic interrupts thrown from our NIC. */
  1591. if (!inta) {
  1592. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1593. goto none;
  1594. }
  1595. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1596. /* Hardware disappeared. It might have already raised
  1597. * an interrupt */
  1598. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1599. goto unplugged;
  1600. }
  1601. #ifdef CONFIG_IWLWIFI_DEBUG
  1602. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1603. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1604. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
  1605. "fh 0x%08x\n", inta, inta_mask, inta_fh);
  1606. }
  1607. #endif
  1608. priv->inta |= inta;
  1609. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1610. if (likely(inta))
  1611. tasklet_schedule(&priv->irq_tasklet);
  1612. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1613. iwl_enable_interrupts(priv);
  1614. unplugged:
  1615. spin_unlock(&priv->lock);
  1616. return IRQ_HANDLED;
  1617. none:
  1618. /* re-enable interrupts here since we don't have anything to service. */
  1619. /* only Re-enable if diabled by irq and no schedules tasklet. */
  1620. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1621. iwl_enable_interrupts(priv);
  1622. spin_unlock(&priv->lock);
  1623. return IRQ_NONE;
  1624. }
  1625. irqreturn_t iwl_isr_legacy(int irq, void *data)
  1626. {
  1627. struct iwl_priv *priv = data;
  1628. u32 inta, inta_mask;
  1629. u32 inta_fh;
  1630. if (!priv)
  1631. return IRQ_NONE;
  1632. spin_lock(&priv->lock);
  1633. /* Disable (but don't clear!) interrupts here to avoid
  1634. * back-to-back ISRs and sporadic interrupts from our NIC.
  1635. * If we have something to service, the tasklet will re-enable ints.
  1636. * If we *don't* have something, we'll re-enable before leaving here. */
  1637. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1638. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1639. /* Discover which interrupts are active/pending */
  1640. inta = iwl_read32(priv, CSR_INT);
  1641. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1642. /* Ignore interrupt if there's nothing in NIC to service.
  1643. * This may be due to IRQ shared with another device,
  1644. * or due to sporadic interrupts thrown from our NIC. */
  1645. if (!inta && !inta_fh) {
  1646. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
  1647. goto none;
  1648. }
  1649. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1650. /* Hardware disappeared. It might have already raised
  1651. * an interrupt */
  1652. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1653. goto unplugged;
  1654. }
  1655. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1656. inta, inta_mask, inta_fh);
  1657. inta &= ~CSR_INT_BIT_SCD;
  1658. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1659. if (likely(inta || inta_fh))
  1660. tasklet_schedule(&priv->irq_tasklet);
  1661. unplugged:
  1662. spin_unlock(&priv->lock);
  1663. return IRQ_HANDLED;
  1664. none:
  1665. /* re-enable interrupts here since we don't have anything to service. */
  1666. /* only Re-enable if diabled by irq */
  1667. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1668. iwl_enable_interrupts(priv);
  1669. spin_unlock(&priv->lock);
  1670. return IRQ_NONE;
  1671. }
  1672. EXPORT_SYMBOL(iwl_isr_legacy);
  1673. int iwl_send_bt_config(struct iwl_priv *priv)
  1674. {
  1675. struct iwl_bt_cmd bt_cmd = {
  1676. .flags = BT_COEX_MODE_4W,
  1677. .lead_time = BT_LEAD_TIME_DEF,
  1678. .max_kill = BT_MAX_KILL_DEF,
  1679. .kill_ack_mask = 0,
  1680. .kill_cts_mask = 0,
  1681. };
  1682. return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1683. sizeof(struct iwl_bt_cmd), &bt_cmd);
  1684. }
  1685. EXPORT_SYMBOL(iwl_send_bt_config);
  1686. int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
  1687. {
  1688. struct iwl_statistics_cmd statistics_cmd = {
  1689. .configuration_flags =
  1690. clear ? IWL_STATS_CONF_CLEAR_STATS : 0,
  1691. };
  1692. if (flags & CMD_ASYNC)
  1693. return iwl_send_cmd_pdu_async(priv, REPLY_STATISTICS_CMD,
  1694. sizeof(struct iwl_statistics_cmd),
  1695. &statistics_cmd, NULL);
  1696. else
  1697. return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD,
  1698. sizeof(struct iwl_statistics_cmd),
  1699. &statistics_cmd);
  1700. }
  1701. EXPORT_SYMBOL(iwl_send_statistics_request);
  1702. /**
  1703. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1704. * using sample data 100 bytes apart. If these sample points are good,
  1705. * it's a pretty good bet that everything between them is good, too.
  1706. */
  1707. static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1708. {
  1709. u32 val;
  1710. int ret = 0;
  1711. u32 errcnt = 0;
  1712. u32 i;
  1713. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1714. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1715. /* read data comes through single port, auto-incr addr */
  1716. /* NOTE: Use the debugless read so we don't flood kernel log
  1717. * if IWL_DL_IO is set */
  1718. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1719. i + IWL49_RTC_INST_LOWER_BOUND);
  1720. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1721. if (val != le32_to_cpu(*image)) {
  1722. ret = -EIO;
  1723. errcnt++;
  1724. if (errcnt >= 3)
  1725. break;
  1726. }
  1727. }
  1728. return ret;
  1729. }
  1730. /**
  1731. * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
  1732. * looking at all data.
  1733. */
  1734. static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
  1735. u32 len)
  1736. {
  1737. u32 val;
  1738. u32 save_len = len;
  1739. int ret = 0;
  1740. u32 errcnt;
  1741. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1742. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1743. IWL49_RTC_INST_LOWER_BOUND);
  1744. errcnt = 0;
  1745. for (; len > 0; len -= sizeof(u32), image++) {
  1746. /* read data comes through single port, auto-incr addr */
  1747. /* NOTE: Use the debugless read so we don't flood kernel log
  1748. * if IWL_DL_IO is set */
  1749. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1750. if (val != le32_to_cpu(*image)) {
  1751. IWL_ERR(priv, "uCode INST section is invalid at "
  1752. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1753. save_len - len, val, le32_to_cpu(*image));
  1754. ret = -EIO;
  1755. errcnt++;
  1756. if (errcnt >= 20)
  1757. break;
  1758. }
  1759. }
  1760. if (!errcnt)
  1761. IWL_DEBUG_INFO(priv,
  1762. "ucode image in INSTRUCTION memory is good\n");
  1763. return ret;
  1764. }
  1765. /**
  1766. * iwl_verify_ucode - determine which instruction image is in SRAM,
  1767. * and verify its contents
  1768. */
  1769. int iwl_verify_ucode(struct iwl_priv *priv)
  1770. {
  1771. __le32 *image;
  1772. u32 len;
  1773. int ret;
  1774. /* Try bootstrap */
  1775. image = (__le32 *)priv->ucode_boot.v_addr;
  1776. len = priv->ucode_boot.len;
  1777. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1778. if (!ret) {
  1779. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1780. return 0;
  1781. }
  1782. /* Try initialize */
  1783. image = (__le32 *)priv->ucode_init.v_addr;
  1784. len = priv->ucode_init.len;
  1785. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1786. if (!ret) {
  1787. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1788. return 0;
  1789. }
  1790. /* Try runtime/protocol */
  1791. image = (__le32 *)priv->ucode_code.v_addr;
  1792. len = priv->ucode_code.len;
  1793. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1794. if (!ret) {
  1795. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1796. return 0;
  1797. }
  1798. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1799. /* Since nothing seems to match, show first several data entries in
  1800. * instruction SRAM, so maybe visual inspection will give a clue.
  1801. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1802. image = (__le32 *)priv->ucode_boot.v_addr;
  1803. len = priv->ucode_boot.len;
  1804. ret = iwl_verify_inst_full(priv, image, len);
  1805. return ret;
  1806. }
  1807. EXPORT_SYMBOL(iwl_verify_ucode);
  1808. void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1809. {
  1810. struct iwl_ct_kill_config cmd;
  1811. struct iwl_ct_kill_throttling_config adv_cmd;
  1812. unsigned long flags;
  1813. int ret = 0;
  1814. spin_lock_irqsave(&priv->lock, flags);
  1815. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1816. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1817. spin_unlock_irqrestore(&priv->lock, flags);
  1818. priv->thermal_throttle.ct_kill_toggle = false;
  1819. if (priv->cfg->support_ct_kill_exit) {
  1820. adv_cmd.critical_temperature_enter =
  1821. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1822. adv_cmd.critical_temperature_exit =
  1823. cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
  1824. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1825. sizeof(adv_cmd), &adv_cmd);
  1826. if (ret)
  1827. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1828. else
  1829. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1830. "succeeded, "
  1831. "critical temperature enter is %d,"
  1832. "exit is %d\n",
  1833. priv->hw_params.ct_kill_threshold,
  1834. priv->hw_params.ct_kill_exit_threshold);
  1835. } else {
  1836. cmd.critical_temperature_R =
  1837. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1838. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1839. sizeof(cmd), &cmd);
  1840. if (ret)
  1841. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1842. else
  1843. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1844. "succeeded, "
  1845. "critical temperature is %d\n",
  1846. priv->hw_params.ct_kill_threshold);
  1847. }
  1848. }
  1849. EXPORT_SYMBOL(iwl_rf_kill_ct_config);
  1850. /*
  1851. * CARD_STATE_CMD
  1852. *
  1853. * Use: Sets the device's internal card state to enable, disable, or halt
  1854. *
  1855. * When in the 'enable' state the card operates as normal.
  1856. * When in the 'disable' state, the card enters into a low power mode.
  1857. * When in the 'halt' state, the card is shut down and must be fully
  1858. * restarted to come back on.
  1859. */
  1860. int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  1861. {
  1862. struct iwl_host_cmd cmd = {
  1863. .id = REPLY_CARD_STATE_CMD,
  1864. .len = sizeof(u32),
  1865. .data = &flags,
  1866. .flags = meta_flag,
  1867. };
  1868. return iwl_send_cmd(priv, &cmd);
  1869. }
  1870. void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
  1871. struct iwl_rx_mem_buffer *rxb)
  1872. {
  1873. #ifdef CONFIG_IWLWIFI_DEBUG
  1874. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1875. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  1876. IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
  1877. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  1878. #endif
  1879. }
  1880. EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
  1881. void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  1882. struct iwl_rx_mem_buffer *rxb)
  1883. {
  1884. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1885. u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1886. IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
  1887. "notification for %s:\n", len,
  1888. get_cmd_string(pkt->hdr.cmd));
  1889. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
  1890. }
  1891. EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
  1892. void iwl_rx_reply_error(struct iwl_priv *priv,
  1893. struct iwl_rx_mem_buffer *rxb)
  1894. {
  1895. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1896. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  1897. "seq 0x%04X ser 0x%08X\n",
  1898. le32_to_cpu(pkt->u.err_resp.error_type),
  1899. get_cmd_string(pkt->u.err_resp.cmd_id),
  1900. pkt->u.err_resp.cmd_id,
  1901. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  1902. le32_to_cpu(pkt->u.err_resp.error_info));
  1903. }
  1904. EXPORT_SYMBOL(iwl_rx_reply_error);
  1905. void iwl_clear_isr_stats(struct iwl_priv *priv)
  1906. {
  1907. memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
  1908. }
  1909. int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1910. const struct ieee80211_tx_queue_params *params)
  1911. {
  1912. struct iwl_priv *priv = hw->priv;
  1913. unsigned long flags;
  1914. int q;
  1915. IWL_DEBUG_MAC80211(priv, "enter\n");
  1916. if (!iwl_is_ready_rf(priv)) {
  1917. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  1918. return -EIO;
  1919. }
  1920. if (queue >= AC_NUM) {
  1921. IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
  1922. return 0;
  1923. }
  1924. q = AC_NUM - 1 - queue;
  1925. spin_lock_irqsave(&priv->lock, flags);
  1926. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  1927. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  1928. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  1929. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  1930. cpu_to_le16((params->txop * 32));
  1931. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  1932. priv->qos_data.qos_active = 1;
  1933. if (priv->iw_mode == NL80211_IFTYPE_AP)
  1934. iwl_activate_qos(priv, 1);
  1935. else if (priv->assoc_id && iwl_is_associated(priv))
  1936. iwl_activate_qos(priv, 0);
  1937. spin_unlock_irqrestore(&priv->lock, flags);
  1938. IWL_DEBUG_MAC80211(priv, "leave\n");
  1939. return 0;
  1940. }
  1941. EXPORT_SYMBOL(iwl_mac_conf_tx);
  1942. static void iwl_ht_conf(struct iwl_priv *priv,
  1943. struct ieee80211_bss_conf *bss_conf)
  1944. {
  1945. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  1946. struct ieee80211_sta *sta;
  1947. IWL_DEBUG_MAC80211(priv, "enter: \n");
  1948. if (!ht_conf->is_ht)
  1949. return;
  1950. ht_conf->ht_protection =
  1951. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  1952. ht_conf->non_GF_STA_present =
  1953. !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  1954. ht_conf->single_chain_sufficient = false;
  1955. switch (priv->iw_mode) {
  1956. case NL80211_IFTYPE_STATION:
  1957. rcu_read_lock();
  1958. sta = ieee80211_find_sta(priv->vif, priv->bssid);
  1959. if (sta) {
  1960. struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
  1961. int maxstreams;
  1962. maxstreams = (ht_cap->mcs.tx_params &
  1963. IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  1964. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  1965. maxstreams += 1;
  1966. if ((ht_cap->mcs.rx_mask[1] == 0) &&
  1967. (ht_cap->mcs.rx_mask[2] == 0))
  1968. ht_conf->single_chain_sufficient = true;
  1969. if (maxstreams <= 1)
  1970. ht_conf->single_chain_sufficient = true;
  1971. } else {
  1972. /*
  1973. * If at all, this can only happen through a race
  1974. * when the AP disconnects us while we're still
  1975. * setting up the connection, in that case mac80211
  1976. * will soon tell us about that.
  1977. */
  1978. ht_conf->single_chain_sufficient = true;
  1979. }
  1980. rcu_read_unlock();
  1981. break;
  1982. case NL80211_IFTYPE_ADHOC:
  1983. ht_conf->single_chain_sufficient = true;
  1984. break;
  1985. default:
  1986. break;
  1987. }
  1988. IWL_DEBUG_MAC80211(priv, "leave\n");
  1989. }
  1990. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  1991. void iwl_bss_info_changed(struct ieee80211_hw *hw,
  1992. struct ieee80211_vif *vif,
  1993. struct ieee80211_bss_conf *bss_conf,
  1994. u32 changes)
  1995. {
  1996. struct iwl_priv *priv = hw->priv;
  1997. int ret;
  1998. IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
  1999. if (!iwl_is_alive(priv))
  2000. return;
  2001. mutex_lock(&priv->mutex);
  2002. if (changes & BSS_CHANGED_BEACON &&
  2003. priv->iw_mode == NL80211_IFTYPE_AP) {
  2004. dev_kfree_skb(priv->ibss_beacon);
  2005. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  2006. }
  2007. if (changes & BSS_CHANGED_BEACON_INT) {
  2008. priv->beacon_int = bss_conf->beacon_int;
  2009. /* TODO: in AP mode, do something to make this take effect */
  2010. }
  2011. if (changes & BSS_CHANGED_BSSID) {
  2012. IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
  2013. /*
  2014. * If there is currently a HW scan going on in the
  2015. * background then we need to cancel it else the RXON
  2016. * below/in post_associate will fail.
  2017. */
  2018. if (iwl_scan_cancel_timeout(priv, 100)) {
  2019. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  2020. IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
  2021. mutex_unlock(&priv->mutex);
  2022. return;
  2023. }
  2024. /* mac80211 only sets assoc when in STATION mode */
  2025. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  2026. bss_conf->assoc) {
  2027. memcpy(priv->staging_rxon.bssid_addr,
  2028. bss_conf->bssid, ETH_ALEN);
  2029. /* currently needed in a few places */
  2030. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  2031. } else {
  2032. priv->staging_rxon.filter_flags &=
  2033. ~RXON_FILTER_ASSOC_MSK;
  2034. }
  2035. }
  2036. /*
  2037. * This needs to be after setting the BSSID in case
  2038. * mac80211 decides to do both changes at once because
  2039. * it will invoke post_associate.
  2040. */
  2041. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2042. changes & BSS_CHANGED_BEACON) {
  2043. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  2044. if (beacon)
  2045. iwl_mac_beacon_update(hw, beacon);
  2046. }
  2047. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  2048. IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
  2049. bss_conf->use_short_preamble);
  2050. if (bss_conf->use_short_preamble)
  2051. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2052. else
  2053. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2054. }
  2055. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  2056. IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
  2057. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  2058. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  2059. else
  2060. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  2061. }
  2062. if (changes & BSS_CHANGED_BASIC_RATES) {
  2063. /* XXX use this information
  2064. *
  2065. * To do that, remove code from iwl_set_rate() and put something
  2066. * like this here:
  2067. *
  2068. if (A-band)
  2069. priv->staging_rxon.ofdm_basic_rates =
  2070. bss_conf->basic_rates;
  2071. else
  2072. priv->staging_rxon.ofdm_basic_rates =
  2073. bss_conf->basic_rates >> 4;
  2074. priv->staging_rxon.cck_basic_rates =
  2075. bss_conf->basic_rates & 0xF;
  2076. */
  2077. }
  2078. if (changes & BSS_CHANGED_HT) {
  2079. iwl_ht_conf(priv, bss_conf);
  2080. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2081. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2082. }
  2083. if (changes & BSS_CHANGED_ASSOC) {
  2084. IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
  2085. if (bss_conf->assoc) {
  2086. priv->assoc_id = bss_conf->aid;
  2087. priv->beacon_int = bss_conf->beacon_int;
  2088. priv->timestamp = bss_conf->timestamp;
  2089. priv->assoc_capability = bss_conf->assoc_capability;
  2090. iwl_led_associate(priv);
  2091. /*
  2092. * We have just associated, don't start scan too early
  2093. * leave time for EAPOL exchange to complete.
  2094. *
  2095. * XXX: do this in mac80211
  2096. */
  2097. priv->next_scan_jiffies = jiffies +
  2098. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  2099. if (!iwl_is_rfkill(priv))
  2100. priv->cfg->ops->lib->post_associate(priv);
  2101. } else {
  2102. priv->assoc_id = 0;
  2103. iwl_led_disassociate(priv);
  2104. }
  2105. }
  2106. if (changes && iwl_is_associated(priv) && priv->assoc_id) {
  2107. IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
  2108. changes);
  2109. ret = iwl_send_rxon_assoc(priv);
  2110. if (!ret) {
  2111. /* Sync active_rxon with latest change. */
  2112. memcpy((void *)&priv->active_rxon,
  2113. &priv->staging_rxon,
  2114. sizeof(struct iwl_rxon_cmd));
  2115. }
  2116. }
  2117. if ((changes & BSS_CHANGED_BEACON_ENABLED) &&
  2118. vif->bss_conf.enable_beacon) {
  2119. memcpy(priv->staging_rxon.bssid_addr,
  2120. bss_conf->bssid, ETH_ALEN);
  2121. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  2122. iwlcore_config_ap(priv);
  2123. }
  2124. mutex_unlock(&priv->mutex);
  2125. IWL_DEBUG_MAC80211(priv, "leave\n");
  2126. }
  2127. EXPORT_SYMBOL(iwl_bss_info_changed);
  2128. int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  2129. {
  2130. struct iwl_priv *priv = hw->priv;
  2131. unsigned long flags;
  2132. __le64 timestamp;
  2133. IWL_DEBUG_MAC80211(priv, "enter\n");
  2134. if (!iwl_is_ready_rf(priv)) {
  2135. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2136. return -EIO;
  2137. }
  2138. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2139. IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
  2140. return -EIO;
  2141. }
  2142. spin_lock_irqsave(&priv->lock, flags);
  2143. if (priv->ibss_beacon)
  2144. dev_kfree_skb(priv->ibss_beacon);
  2145. priv->ibss_beacon = skb;
  2146. priv->assoc_id = 0;
  2147. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  2148. priv->timestamp = le64_to_cpu(timestamp);
  2149. IWL_DEBUG_MAC80211(priv, "leave\n");
  2150. spin_unlock_irqrestore(&priv->lock, flags);
  2151. iwl_reset_qos(priv);
  2152. priv->cfg->ops->lib->post_associate(priv);
  2153. return 0;
  2154. }
  2155. EXPORT_SYMBOL(iwl_mac_beacon_update);
  2156. int iwl_set_mode(struct iwl_priv *priv, int mode)
  2157. {
  2158. if (mode == NL80211_IFTYPE_ADHOC) {
  2159. const struct iwl_channel_info *ch_info;
  2160. ch_info = iwl_get_channel_info(priv,
  2161. priv->band,
  2162. le16_to_cpu(priv->staging_rxon.channel));
  2163. if (!ch_info || !is_channel_ibss(ch_info)) {
  2164. IWL_ERR(priv, "channel %d not IBSS channel\n",
  2165. le16_to_cpu(priv->staging_rxon.channel));
  2166. return -EINVAL;
  2167. }
  2168. }
  2169. iwl_connection_init_rx_config(priv, mode);
  2170. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2171. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2172. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2173. iwl_clear_stations_table(priv);
  2174. /* dont commit rxon if rf-kill is on*/
  2175. if (!iwl_is_ready_rf(priv))
  2176. return -EAGAIN;
  2177. iwlcore_commit_rxon(priv);
  2178. return 0;
  2179. }
  2180. EXPORT_SYMBOL(iwl_set_mode);
  2181. int iwl_mac_add_interface(struct ieee80211_hw *hw,
  2182. struct ieee80211_if_init_conf *conf)
  2183. {
  2184. struct iwl_priv *priv = hw->priv;
  2185. unsigned long flags;
  2186. IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
  2187. if (priv->vif) {
  2188. IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
  2189. return -EOPNOTSUPP;
  2190. }
  2191. spin_lock_irqsave(&priv->lock, flags);
  2192. priv->vif = conf->vif;
  2193. priv->iw_mode = conf->type;
  2194. spin_unlock_irqrestore(&priv->lock, flags);
  2195. mutex_lock(&priv->mutex);
  2196. if (conf->mac_addr) {
  2197. IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
  2198. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  2199. }
  2200. if (iwl_set_mode(priv, conf->type) == -EAGAIN)
  2201. /* we are not ready, will run again when ready */
  2202. set_bit(STATUS_MODE_PENDING, &priv->status);
  2203. mutex_unlock(&priv->mutex);
  2204. IWL_DEBUG_MAC80211(priv, "leave\n");
  2205. return 0;
  2206. }
  2207. EXPORT_SYMBOL(iwl_mac_add_interface);
  2208. void iwl_mac_remove_interface(struct ieee80211_hw *hw,
  2209. struct ieee80211_if_init_conf *conf)
  2210. {
  2211. struct iwl_priv *priv = hw->priv;
  2212. IWL_DEBUG_MAC80211(priv, "enter\n");
  2213. mutex_lock(&priv->mutex);
  2214. if (iwl_is_ready_rf(priv)) {
  2215. iwl_scan_cancel_timeout(priv, 100);
  2216. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2217. iwlcore_commit_rxon(priv);
  2218. }
  2219. if (priv->vif == conf->vif) {
  2220. priv->vif = NULL;
  2221. memset(priv->bssid, 0, ETH_ALEN);
  2222. }
  2223. mutex_unlock(&priv->mutex);
  2224. IWL_DEBUG_MAC80211(priv, "leave\n");
  2225. }
  2226. EXPORT_SYMBOL(iwl_mac_remove_interface);
  2227. /**
  2228. * iwl_mac_config - mac80211 config callback
  2229. *
  2230. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  2231. * be set inappropriately and the driver currently sets the hardware up to
  2232. * use it whenever needed.
  2233. */
  2234. int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
  2235. {
  2236. struct iwl_priv *priv = hw->priv;
  2237. const struct iwl_channel_info *ch_info;
  2238. struct ieee80211_conf *conf = &hw->conf;
  2239. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  2240. unsigned long flags = 0;
  2241. int ret = 0;
  2242. u16 ch;
  2243. int scan_active = 0;
  2244. mutex_lock(&priv->mutex);
  2245. IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
  2246. conf->channel->hw_value, changed);
  2247. if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
  2248. test_bit(STATUS_SCANNING, &priv->status))) {
  2249. scan_active = 1;
  2250. IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
  2251. }
  2252. /* during scanning mac80211 will delay channel setting until
  2253. * scan finish with changed = 0
  2254. */
  2255. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  2256. if (scan_active)
  2257. goto set_ch_out;
  2258. ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
  2259. ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
  2260. if (!is_channel_valid(ch_info)) {
  2261. IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
  2262. ret = -EINVAL;
  2263. goto set_ch_out;
  2264. }
  2265. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2266. !is_channel_ibss(ch_info)) {
  2267. IWL_ERR(priv, "channel %d in band %d not "
  2268. "IBSS channel\n",
  2269. conf->channel->hw_value, conf->channel->band);
  2270. ret = -EINVAL;
  2271. goto set_ch_out;
  2272. }
  2273. spin_lock_irqsave(&priv->lock, flags);
  2274. /* Configure HT40 channels */
  2275. ht_conf->is_ht = conf_is_ht(conf);
  2276. if (ht_conf->is_ht) {
  2277. if (conf_is_ht40_minus(conf)) {
  2278. ht_conf->extension_chan_offset =
  2279. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2280. ht_conf->is_40mhz = true;
  2281. } else if (conf_is_ht40_plus(conf)) {
  2282. ht_conf->extension_chan_offset =
  2283. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2284. ht_conf->is_40mhz = true;
  2285. } else {
  2286. ht_conf->extension_chan_offset =
  2287. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2288. ht_conf->is_40mhz = false;
  2289. }
  2290. } else
  2291. ht_conf->is_40mhz = false;
  2292. /* Default to no protection. Protection mode will later be set
  2293. * from BSS config in iwl_ht_conf */
  2294. ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  2295. /* if we are switching from ht to 2.4 clear flags
  2296. * from any ht related info since 2.4 does not
  2297. * support ht */
  2298. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  2299. priv->staging_rxon.flags = 0;
  2300. iwl_set_rxon_channel(priv, conf->channel);
  2301. iwl_set_flags_for_band(priv, conf->channel->band);
  2302. spin_unlock_irqrestore(&priv->lock, flags);
  2303. if (iwl_is_associated(priv) &&
  2304. (le16_to_cpu(priv->active_rxon.channel) != ch) &&
  2305. priv->cfg->ops->lib->set_channel_switch) {
  2306. iwl_set_rate(priv);
  2307. /*
  2308. * at this point, staging_rxon has the
  2309. * configuration for channel switch
  2310. */
  2311. ret = priv->cfg->ops->lib->set_channel_switch(priv,
  2312. ch);
  2313. if (!ret) {
  2314. iwl_print_rx_config_cmd(priv);
  2315. goto out;
  2316. }
  2317. priv->switch_rxon.switch_in_progress = false;
  2318. }
  2319. set_ch_out:
  2320. /* The list of supported rates and rate mask can be different
  2321. * for each band; since the band may have changed, reset
  2322. * the rate mask to what mac80211 lists */
  2323. iwl_set_rate(priv);
  2324. }
  2325. if (changed & (IEEE80211_CONF_CHANGE_PS |
  2326. IEEE80211_CONF_CHANGE_IDLE)) {
  2327. ret = iwl_power_update_mode(priv, false);
  2328. if (ret)
  2329. IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
  2330. }
  2331. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  2332. IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
  2333. priv->tx_power_user_lmt, conf->power_level);
  2334. iwl_set_tx_power(priv, conf->power_level, false);
  2335. }
  2336. /* call to ensure that 4965 rx_chain is set properly in monitor mode */
  2337. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2338. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2339. if (!iwl_is_ready(priv)) {
  2340. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2341. goto out;
  2342. }
  2343. if (scan_active)
  2344. goto out;
  2345. if (memcmp(&priv->active_rxon,
  2346. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  2347. iwlcore_commit_rxon(priv);
  2348. else
  2349. IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
  2350. out:
  2351. IWL_DEBUG_MAC80211(priv, "leave\n");
  2352. mutex_unlock(&priv->mutex);
  2353. return ret;
  2354. }
  2355. EXPORT_SYMBOL(iwl_mac_config);
  2356. int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
  2357. struct ieee80211_tx_queue_stats *stats)
  2358. {
  2359. struct iwl_priv *priv = hw->priv;
  2360. int i, avail;
  2361. struct iwl_tx_queue *txq;
  2362. struct iwl_queue *q;
  2363. unsigned long flags;
  2364. IWL_DEBUG_MAC80211(priv, "enter\n");
  2365. if (!iwl_is_ready_rf(priv)) {
  2366. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2367. return -EIO;
  2368. }
  2369. spin_lock_irqsave(&priv->lock, flags);
  2370. for (i = 0; i < AC_NUM; i++) {
  2371. txq = &priv->txq[i];
  2372. q = &txq->q;
  2373. avail = iwl_queue_space(q);
  2374. stats[i].len = q->n_window - avail;
  2375. stats[i].limit = q->n_window - q->high_mark;
  2376. stats[i].count = q->n_window;
  2377. }
  2378. spin_unlock_irqrestore(&priv->lock, flags);
  2379. IWL_DEBUG_MAC80211(priv, "leave\n");
  2380. return 0;
  2381. }
  2382. EXPORT_SYMBOL(iwl_mac_get_tx_stats);
  2383. void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
  2384. {
  2385. struct iwl_priv *priv = hw->priv;
  2386. unsigned long flags;
  2387. mutex_lock(&priv->mutex);
  2388. IWL_DEBUG_MAC80211(priv, "enter\n");
  2389. spin_lock_irqsave(&priv->lock, flags);
  2390. memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
  2391. spin_unlock_irqrestore(&priv->lock, flags);
  2392. iwl_reset_qos(priv);
  2393. spin_lock_irqsave(&priv->lock, flags);
  2394. priv->assoc_id = 0;
  2395. priv->assoc_capability = 0;
  2396. priv->assoc_station_added = 0;
  2397. /* new association get rid of ibss beacon skb */
  2398. if (priv->ibss_beacon)
  2399. dev_kfree_skb(priv->ibss_beacon);
  2400. priv->ibss_beacon = NULL;
  2401. priv->beacon_int = priv->vif->bss_conf.beacon_int;
  2402. priv->timestamp = 0;
  2403. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  2404. priv->beacon_int = 0;
  2405. spin_unlock_irqrestore(&priv->lock, flags);
  2406. if (!iwl_is_ready_rf(priv)) {
  2407. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2408. mutex_unlock(&priv->mutex);
  2409. return;
  2410. }
  2411. /* we are restarting association process
  2412. * clear RXON_FILTER_ASSOC_MSK bit
  2413. */
  2414. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2415. iwl_scan_cancel_timeout(priv, 100);
  2416. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2417. iwlcore_commit_rxon(priv);
  2418. }
  2419. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2420. IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
  2421. mutex_unlock(&priv->mutex);
  2422. return;
  2423. }
  2424. iwl_set_rate(priv);
  2425. mutex_unlock(&priv->mutex);
  2426. IWL_DEBUG_MAC80211(priv, "leave\n");
  2427. }
  2428. EXPORT_SYMBOL(iwl_mac_reset_tsf);
  2429. int iwl_alloc_txq_mem(struct iwl_priv *priv)
  2430. {
  2431. if (!priv->txq)
  2432. priv->txq = kzalloc(
  2433. sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
  2434. GFP_KERNEL);
  2435. if (!priv->txq) {
  2436. IWL_ERR(priv, "Not enough memory for txq \n");
  2437. return -ENOMEM;
  2438. }
  2439. return 0;
  2440. }
  2441. EXPORT_SYMBOL(iwl_alloc_txq_mem);
  2442. void iwl_free_txq_mem(struct iwl_priv *priv)
  2443. {
  2444. kfree(priv->txq);
  2445. priv->txq = NULL;
  2446. }
  2447. EXPORT_SYMBOL(iwl_free_txq_mem);
  2448. int iwl_send_wimax_coex(struct iwl_priv *priv)
  2449. {
  2450. struct iwl_wimax_coex_cmd uninitialized_var(coex_cmd);
  2451. if (priv->cfg->support_wimax_coexist) {
  2452. /* UnMask wake up src at associated sleep */
  2453. coex_cmd.flags |= COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
  2454. /* UnMask wake up src at unassociated sleep */
  2455. coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
  2456. memcpy(coex_cmd.sta_prio, cu_priorities,
  2457. sizeof(struct iwl_wimax_coex_event_entry) *
  2458. COEX_NUM_OF_EVENTS);
  2459. /* enabling the coexistence feature */
  2460. coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
  2461. /* enabling the priorities tables */
  2462. coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
  2463. } else {
  2464. /* coexistence is disabled */
  2465. memset(&coex_cmd, 0, sizeof(coex_cmd));
  2466. }
  2467. return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
  2468. sizeof(coex_cmd), &coex_cmd);
  2469. }
  2470. EXPORT_SYMBOL(iwl_send_wimax_coex);
  2471. #ifdef CONFIG_IWLWIFI_DEBUGFS
  2472. #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
  2473. void iwl_reset_traffic_log(struct iwl_priv *priv)
  2474. {
  2475. priv->tx_traffic_idx = 0;
  2476. priv->rx_traffic_idx = 0;
  2477. if (priv->tx_traffic)
  2478. memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2479. if (priv->rx_traffic)
  2480. memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2481. }
  2482. int iwl_alloc_traffic_mem(struct iwl_priv *priv)
  2483. {
  2484. u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
  2485. if (iwl_debug_level & IWL_DL_TX) {
  2486. if (!priv->tx_traffic) {
  2487. priv->tx_traffic =
  2488. kzalloc(traffic_size, GFP_KERNEL);
  2489. if (!priv->tx_traffic)
  2490. return -ENOMEM;
  2491. }
  2492. }
  2493. if (iwl_debug_level & IWL_DL_RX) {
  2494. if (!priv->rx_traffic) {
  2495. priv->rx_traffic =
  2496. kzalloc(traffic_size, GFP_KERNEL);
  2497. if (!priv->rx_traffic)
  2498. return -ENOMEM;
  2499. }
  2500. }
  2501. iwl_reset_traffic_log(priv);
  2502. return 0;
  2503. }
  2504. EXPORT_SYMBOL(iwl_alloc_traffic_mem);
  2505. void iwl_free_traffic_mem(struct iwl_priv *priv)
  2506. {
  2507. kfree(priv->tx_traffic);
  2508. priv->tx_traffic = NULL;
  2509. kfree(priv->rx_traffic);
  2510. priv->rx_traffic = NULL;
  2511. }
  2512. EXPORT_SYMBOL(iwl_free_traffic_mem);
  2513. void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
  2514. u16 length, struct ieee80211_hdr *header)
  2515. {
  2516. __le16 fc;
  2517. u16 len;
  2518. if (likely(!(iwl_debug_level & IWL_DL_TX)))
  2519. return;
  2520. if (!priv->tx_traffic)
  2521. return;
  2522. fc = header->frame_control;
  2523. if (ieee80211_is_data(fc)) {
  2524. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2525. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2526. memcpy((priv->tx_traffic +
  2527. (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2528. header, len);
  2529. priv->tx_traffic_idx =
  2530. (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2531. }
  2532. }
  2533. EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
  2534. void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
  2535. u16 length, struct ieee80211_hdr *header)
  2536. {
  2537. __le16 fc;
  2538. u16 len;
  2539. if (likely(!(iwl_debug_level & IWL_DL_RX)))
  2540. return;
  2541. if (!priv->rx_traffic)
  2542. return;
  2543. fc = header->frame_control;
  2544. if (ieee80211_is_data(fc)) {
  2545. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2546. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2547. memcpy((priv->rx_traffic +
  2548. (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2549. header, len);
  2550. priv->rx_traffic_idx =
  2551. (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2552. }
  2553. }
  2554. EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
  2555. const char *get_mgmt_string(int cmd)
  2556. {
  2557. switch (cmd) {
  2558. IWL_CMD(MANAGEMENT_ASSOC_REQ);
  2559. IWL_CMD(MANAGEMENT_ASSOC_RESP);
  2560. IWL_CMD(MANAGEMENT_REASSOC_REQ);
  2561. IWL_CMD(MANAGEMENT_REASSOC_RESP);
  2562. IWL_CMD(MANAGEMENT_PROBE_REQ);
  2563. IWL_CMD(MANAGEMENT_PROBE_RESP);
  2564. IWL_CMD(MANAGEMENT_BEACON);
  2565. IWL_CMD(MANAGEMENT_ATIM);
  2566. IWL_CMD(MANAGEMENT_DISASSOC);
  2567. IWL_CMD(MANAGEMENT_AUTH);
  2568. IWL_CMD(MANAGEMENT_DEAUTH);
  2569. IWL_CMD(MANAGEMENT_ACTION);
  2570. default:
  2571. return "UNKNOWN";
  2572. }
  2573. }
  2574. const char *get_ctrl_string(int cmd)
  2575. {
  2576. switch (cmd) {
  2577. IWL_CMD(CONTROL_BACK_REQ);
  2578. IWL_CMD(CONTROL_BACK);
  2579. IWL_CMD(CONTROL_PSPOLL);
  2580. IWL_CMD(CONTROL_RTS);
  2581. IWL_CMD(CONTROL_CTS);
  2582. IWL_CMD(CONTROL_ACK);
  2583. IWL_CMD(CONTROL_CFEND);
  2584. IWL_CMD(CONTROL_CFENDACK);
  2585. default:
  2586. return "UNKNOWN";
  2587. }
  2588. }
  2589. void iwl_clear_tx_stats(struct iwl_priv *priv)
  2590. {
  2591. memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
  2592. }
  2593. void iwl_clear_rx_stats(struct iwl_priv *priv)
  2594. {
  2595. memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
  2596. }
  2597. /*
  2598. * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
  2599. * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
  2600. * Use debugFs to display the rx/rx_statistics
  2601. * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
  2602. * information will be recorded, but DATA pkt still will be recorded
  2603. * for the reason of iwl_led.c need to control the led blinking based on
  2604. * number of tx and rx data.
  2605. *
  2606. */
  2607. void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
  2608. {
  2609. struct traffic_stats *stats;
  2610. if (is_tx)
  2611. stats = &priv->tx_stats;
  2612. else
  2613. stats = &priv->rx_stats;
  2614. if (ieee80211_is_mgmt(fc)) {
  2615. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2616. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  2617. stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
  2618. break;
  2619. case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
  2620. stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
  2621. break;
  2622. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  2623. stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
  2624. break;
  2625. case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
  2626. stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
  2627. break;
  2628. case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
  2629. stats->mgmt[MANAGEMENT_PROBE_REQ]++;
  2630. break;
  2631. case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
  2632. stats->mgmt[MANAGEMENT_PROBE_RESP]++;
  2633. break;
  2634. case cpu_to_le16(IEEE80211_STYPE_BEACON):
  2635. stats->mgmt[MANAGEMENT_BEACON]++;
  2636. break;
  2637. case cpu_to_le16(IEEE80211_STYPE_ATIM):
  2638. stats->mgmt[MANAGEMENT_ATIM]++;
  2639. break;
  2640. case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
  2641. stats->mgmt[MANAGEMENT_DISASSOC]++;
  2642. break;
  2643. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  2644. stats->mgmt[MANAGEMENT_AUTH]++;
  2645. break;
  2646. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  2647. stats->mgmt[MANAGEMENT_DEAUTH]++;
  2648. break;
  2649. case cpu_to_le16(IEEE80211_STYPE_ACTION):
  2650. stats->mgmt[MANAGEMENT_ACTION]++;
  2651. break;
  2652. }
  2653. } else if (ieee80211_is_ctl(fc)) {
  2654. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2655. case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
  2656. stats->ctrl[CONTROL_BACK_REQ]++;
  2657. break;
  2658. case cpu_to_le16(IEEE80211_STYPE_BACK):
  2659. stats->ctrl[CONTROL_BACK]++;
  2660. break;
  2661. case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
  2662. stats->ctrl[CONTROL_PSPOLL]++;
  2663. break;
  2664. case cpu_to_le16(IEEE80211_STYPE_RTS):
  2665. stats->ctrl[CONTROL_RTS]++;
  2666. break;
  2667. case cpu_to_le16(IEEE80211_STYPE_CTS):
  2668. stats->ctrl[CONTROL_CTS]++;
  2669. break;
  2670. case cpu_to_le16(IEEE80211_STYPE_ACK):
  2671. stats->ctrl[CONTROL_ACK]++;
  2672. break;
  2673. case cpu_to_le16(IEEE80211_STYPE_CFEND):
  2674. stats->ctrl[CONTROL_CFEND]++;
  2675. break;
  2676. case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
  2677. stats->ctrl[CONTROL_CFENDACK]++;
  2678. break;
  2679. }
  2680. } else {
  2681. /* data */
  2682. stats->data_cnt++;
  2683. stats->data_bytes += len;
  2684. }
  2685. }
  2686. EXPORT_SYMBOL(iwl_update_stats);
  2687. #endif
  2688. #ifdef CONFIG_PM
  2689. int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  2690. {
  2691. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2692. /*
  2693. * This function is called when system goes into suspend state
  2694. * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
  2695. * first but since iwl_mac_stop() has no knowledge of who the caller is,
  2696. * it will not call apm_ops.stop() to stop the DMA operation.
  2697. * Calling apm_ops.stop here to make sure we stop the DMA.
  2698. */
  2699. priv->cfg->ops->lib->apm_ops.stop(priv);
  2700. pci_save_state(pdev);
  2701. pci_disable_device(pdev);
  2702. pci_set_power_state(pdev, PCI_D3hot);
  2703. return 0;
  2704. }
  2705. EXPORT_SYMBOL(iwl_pci_suspend);
  2706. int iwl_pci_resume(struct pci_dev *pdev)
  2707. {
  2708. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2709. int ret;
  2710. pci_set_power_state(pdev, PCI_D0);
  2711. ret = pci_enable_device(pdev);
  2712. if (ret)
  2713. return ret;
  2714. pci_restore_state(pdev);
  2715. iwl_enable_interrupts(priv);
  2716. return 0;
  2717. }
  2718. EXPORT_SYMBOL(iwl_pci_resume);
  2719. #endif /* CONFIG_PM */