imx23.dtsi 10 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. serial0 = &auart0;
  19. serial1 = &auart1;
  20. };
  21. cpus {
  22. cpu@0 {
  23. compatible = "arm,arm926ejs";
  24. };
  25. };
  26. apb@80000000 {
  27. compatible = "simple-bus";
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. reg = <0x80000000 0x80000>;
  31. ranges;
  32. apbh@80000000 {
  33. compatible = "simple-bus";
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. reg = <0x80000000 0x40000>;
  37. ranges;
  38. icoll: interrupt-controller@80000000 {
  39. compatible = "fsl,imx23-icoll", "fsl,mxs-icoll";
  40. interrupt-controller;
  41. #interrupt-cells = <1>;
  42. reg = <0x80000000 0x2000>;
  43. };
  44. dma-apbh@80004000 {
  45. compatible = "fsl,imx23-dma-apbh";
  46. reg = <0x80004000 0x2000>;
  47. };
  48. ecc@80008000 {
  49. reg = <0x80008000 0x2000>;
  50. status = "disabled";
  51. };
  52. gpmi-nand@8000c000 {
  53. compatible = "fsl,imx23-gpmi-nand";
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
  57. reg-names = "gpmi-nand", "bch";
  58. interrupts = <13>, <56>;
  59. interrupt-names = "gpmi-dma", "bch";
  60. fsl,gpmi-dma-channel = <4>;
  61. status = "disabled";
  62. };
  63. ssp0: ssp@80010000 {
  64. reg = <0x80010000 0x2000>;
  65. interrupts = <15 14>;
  66. fsl,ssp-dma-channel = <1>;
  67. status = "disabled";
  68. };
  69. etm@80014000 {
  70. reg = <0x80014000 0x2000>;
  71. status = "disabled";
  72. };
  73. pinctrl@80018000 {
  74. #address-cells = <1>;
  75. #size-cells = <0>;
  76. compatible = "fsl,imx23-pinctrl", "simple-bus";
  77. reg = <0x80018000 0x2000>;
  78. gpio0: gpio@0 {
  79. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  80. interrupts = <16>;
  81. gpio-controller;
  82. #gpio-cells = <2>;
  83. interrupt-controller;
  84. #interrupt-cells = <2>;
  85. };
  86. gpio1: gpio@1 {
  87. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  88. interrupts = <17>;
  89. gpio-controller;
  90. #gpio-cells = <2>;
  91. interrupt-controller;
  92. #interrupt-cells = <2>;
  93. };
  94. gpio2: gpio@2 {
  95. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  96. interrupts = <18>;
  97. gpio-controller;
  98. #gpio-cells = <2>;
  99. interrupt-controller;
  100. #interrupt-cells = <2>;
  101. };
  102. duart_pins_a: duart@0 {
  103. reg = <0>;
  104. fsl,pinmux-ids = <
  105. 0x11a2 /* MX23_PAD_PWM0__DUART_RX */
  106. 0x11b2 /* MX23_PAD_PWM1__DUART_TX */
  107. >;
  108. fsl,drive-strength = <0>;
  109. fsl,voltage = <1>;
  110. fsl,pull-up = <0>;
  111. };
  112. auart0_pins_a: auart0@0 {
  113. reg = <0>;
  114. fsl,pinmux-ids = <
  115. 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
  116. 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
  117. 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
  118. 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
  119. >;
  120. fsl,drive-strength = <0>;
  121. fsl,voltage = <1>;
  122. fsl,pull-up = <0>;
  123. };
  124. auart0_2pins_a: auart0-2pins@0 {
  125. reg = <0>;
  126. fsl,pinmux-ids = <
  127. 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
  128. 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
  129. >;
  130. fsl,drive-strength = <0>;
  131. fsl,voltage = <1>;
  132. fsl,pull-up = <0>;
  133. };
  134. gpmi_pins_a: gpmi-nand@0 {
  135. reg = <0>;
  136. fsl,pinmux-ids = <
  137. 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
  138. 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
  139. 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
  140. 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
  141. 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
  142. 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
  143. 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
  144. 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
  145. 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
  146. 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
  147. 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
  148. 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
  149. 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
  150. 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
  151. 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
  152. 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
  153. 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
  154. >;
  155. fsl,drive-strength = <0>;
  156. fsl,voltage = <1>;
  157. fsl,pull-up = <0>;
  158. };
  159. gpmi_pins_fixup: gpmi-pins-fixup {
  160. fsl,pinmux-ids = <
  161. 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
  162. 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
  163. 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
  164. >;
  165. fsl,drive-strength = <2>;
  166. };
  167. mmc0_4bit_pins_a: mmc0-4bit@0 {
  168. reg = <0>;
  169. fsl,pinmux-ids = <
  170. 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
  171. 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
  172. 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
  173. 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
  174. 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
  175. 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
  176. >;
  177. fsl,drive-strength = <1>;
  178. fsl,voltage = <1>;
  179. fsl,pull-up = <1>;
  180. };
  181. mmc0_8bit_pins_a: mmc0-8bit@0 {
  182. reg = <0>;
  183. fsl,pinmux-ids = <
  184. 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
  185. 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
  186. 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
  187. 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
  188. 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
  189. 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
  190. 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
  191. 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
  192. 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
  193. 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
  194. 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
  195. >;
  196. fsl,drive-strength = <1>;
  197. fsl,voltage = <1>;
  198. fsl,pull-up = <1>;
  199. };
  200. mmc0_pins_fixup: mmc0-pins-fixup {
  201. fsl,pinmux-ids = <
  202. 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
  203. 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
  204. >;
  205. fsl,pull-up = <0>;
  206. };
  207. pwm2_pins_a: pwm2@0 {
  208. reg = <0>;
  209. fsl,pinmux-ids = <
  210. 0x11c0 /* MX23_PAD_PWM2__PWM2 */
  211. >;
  212. fsl,drive-strength = <0>;
  213. fsl,voltage = <1>;
  214. fsl,pull-up = <0>;
  215. };
  216. lcdif_24bit_pins_a: lcdif-24bit@0 {
  217. reg = <0>;
  218. fsl,pinmux-ids = <
  219. 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
  220. 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
  221. 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
  222. 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
  223. 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
  224. 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
  225. 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
  226. 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
  227. 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
  228. 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
  229. 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
  230. 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
  231. 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
  232. 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
  233. 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
  234. 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
  235. 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
  236. 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
  237. 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
  238. 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
  239. 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
  240. 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
  241. 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
  242. 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
  243. 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
  244. 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
  245. 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
  246. 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
  247. >;
  248. fsl,drive-strength = <0>;
  249. fsl,voltage = <1>;
  250. fsl,pull-up = <0>;
  251. };
  252. };
  253. digctl@8001c000 {
  254. reg = <0x8001c000 2000>;
  255. status = "disabled";
  256. };
  257. emi@80020000 {
  258. reg = <0x80020000 0x2000>;
  259. status = "disabled";
  260. };
  261. dma-apbx@80024000 {
  262. compatible = "fsl,imx23-dma-apbx";
  263. reg = <0x80024000 0x2000>;
  264. };
  265. dcp@80028000 {
  266. reg = <0x80028000 0x2000>;
  267. status = "disabled";
  268. };
  269. pxp@8002a000 {
  270. reg = <0x8002a000 0x2000>;
  271. status = "disabled";
  272. };
  273. ocotp@8002c000 {
  274. reg = <0x8002c000 0x2000>;
  275. status = "disabled";
  276. };
  277. axi-ahb@8002e000 {
  278. reg = <0x8002e000 0x2000>;
  279. status = "disabled";
  280. };
  281. lcdif@80030000 {
  282. compatible = "fsl,imx23-lcdif";
  283. reg = <0x80030000 2000>;
  284. interrupts = <46 45>;
  285. status = "disabled";
  286. };
  287. ssp1: ssp@80034000 {
  288. reg = <0x80034000 0x2000>;
  289. interrupts = <2 20>;
  290. fsl,ssp-dma-channel = <2>;
  291. status = "disabled";
  292. };
  293. tvenc@80038000 {
  294. reg = <0x80038000 0x2000>;
  295. status = "disabled";
  296. };
  297. };
  298. apbx@80040000 {
  299. compatible = "simple-bus";
  300. #address-cells = <1>;
  301. #size-cells = <1>;
  302. reg = <0x80040000 0x40000>;
  303. ranges;
  304. clkctl@80040000 {
  305. reg = <0x80040000 0x2000>;
  306. status = "disabled";
  307. };
  308. saif0: saif@80042000 {
  309. reg = <0x80042000 0x2000>;
  310. status = "disabled";
  311. };
  312. power@80044000 {
  313. reg = <0x80044000 0x2000>;
  314. status = "disabled";
  315. };
  316. saif1: saif@80046000 {
  317. reg = <0x80046000 0x2000>;
  318. status = "disabled";
  319. };
  320. audio-out@80048000 {
  321. reg = <0x80048000 0x2000>;
  322. status = "disabled";
  323. };
  324. audio-in@8004c000 {
  325. reg = <0x8004c000 0x2000>;
  326. status = "disabled";
  327. };
  328. lradc@80050000 {
  329. reg = <0x80050000 0x2000>;
  330. status = "disabled";
  331. };
  332. spdif@80054000 {
  333. reg = <0x80054000 2000>;
  334. status = "disabled";
  335. };
  336. i2c@80058000 {
  337. reg = <0x80058000 0x2000>;
  338. status = "disabled";
  339. };
  340. rtc@8005c000 {
  341. compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
  342. reg = <0x8005c000 0x2000>;
  343. interrupts = <22>;
  344. };
  345. pwm: pwm@80064000 {
  346. compatible = "fsl,imx23-pwm";
  347. reg = <0x80064000 0x2000>;
  348. #pwm-cells = <2>;
  349. fsl,pwm-number = <5>;
  350. status = "disabled";
  351. };
  352. timrot@80068000 {
  353. reg = <0x80068000 0x2000>;
  354. status = "disabled";
  355. };
  356. auart0: serial@8006c000 {
  357. compatible = "fsl,imx23-auart";
  358. reg = <0x8006c000 0x2000>;
  359. interrupts = <24 25 23>;
  360. status = "disabled";
  361. };
  362. auart1: serial@8006e000 {
  363. compatible = "fsl,imx23-auart";
  364. reg = <0x8006e000 0x2000>;
  365. interrupts = <59 60 58>;
  366. status = "disabled";
  367. };
  368. duart: serial@80070000 {
  369. compatible = "arm,pl011", "arm,primecell";
  370. reg = <0x80070000 0x2000>;
  371. interrupts = <0>;
  372. status = "disabled";
  373. };
  374. usbphy@8007c000 {
  375. reg = <0x8007c000 0x2000>;
  376. status = "disabled";
  377. };
  378. };
  379. };
  380. ahb@80080000 {
  381. compatible = "simple-bus";
  382. #address-cells = <1>;
  383. #size-cells = <1>;
  384. reg = <0x80080000 0x80000>;
  385. ranges;
  386. usbctrl@80080000 {
  387. reg = <0x80080000 0x40000>;
  388. status = "disabled";
  389. };
  390. };
  391. };