mr.c 24 KB

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  1. /*
  2. * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/kref.h>
  33. #include <linux/random.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/export.h>
  36. #include <linux/delay.h>
  37. #include <rdma/ib_umem.h>
  38. #include "mlx5_ib.h"
  39. enum {
  40. DEF_CACHE_SIZE = 10,
  41. MAX_PENDING_REG_MR = 8,
  42. };
  43. enum {
  44. MLX5_UMR_ALIGN = 2048
  45. };
  46. static __be64 *mr_align(__be64 *ptr, int align)
  47. {
  48. unsigned long mask = align - 1;
  49. return (__be64 *)(((unsigned long)ptr + mask) & ~mask);
  50. }
  51. static int order2idx(struct mlx5_ib_dev *dev, int order)
  52. {
  53. struct mlx5_mr_cache *cache = &dev->cache;
  54. if (order < cache->ent[0].order)
  55. return 0;
  56. else
  57. return order - cache->ent[0].order;
  58. }
  59. static void reg_mr_callback(int status, void *context)
  60. {
  61. struct mlx5_ib_mr *mr = context;
  62. struct mlx5_ib_dev *dev = mr->dev;
  63. struct mlx5_mr_cache *cache = &dev->cache;
  64. int c = order2idx(dev, mr->order);
  65. struct mlx5_cache_ent *ent = &cache->ent[c];
  66. u8 key;
  67. unsigned long delta = jiffies - mr->start;
  68. unsigned long index;
  69. unsigned long flags;
  70. index = find_last_bit(&delta, 8 * sizeof(delta));
  71. if (index == 64)
  72. index = 0;
  73. spin_lock_irqsave(&ent->lock, flags);
  74. ent->pending--;
  75. spin_unlock_irqrestore(&ent->lock, flags);
  76. if (status) {
  77. mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status);
  78. kfree(mr);
  79. dev->fill_delay = 1;
  80. mod_timer(&dev->delay_timer, jiffies + HZ);
  81. return;
  82. }
  83. if (mr->out.hdr.status) {
  84. mlx5_ib_warn(dev, "failed - status %d, syndorme 0x%x\n",
  85. mr->out.hdr.status,
  86. be32_to_cpu(mr->out.hdr.syndrome));
  87. kfree(mr);
  88. dev->fill_delay = 1;
  89. mod_timer(&dev->delay_timer, jiffies + HZ);
  90. return;
  91. }
  92. spin_lock_irqsave(&dev->mdev.priv.mkey_lock, flags);
  93. key = dev->mdev.priv.mkey_key++;
  94. spin_unlock_irqrestore(&dev->mdev.priv.mkey_lock, flags);
  95. mr->mmr.key = mlx5_idx_to_mkey(be32_to_cpu(mr->out.mkey) & 0xffffff) | key;
  96. cache->last_add = jiffies;
  97. spin_lock_irqsave(&ent->lock, flags);
  98. list_add_tail(&mr->list, &ent->head);
  99. ent->cur++;
  100. ent->size++;
  101. spin_unlock_irqrestore(&ent->lock, flags);
  102. }
  103. static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
  104. {
  105. struct mlx5_mr_cache *cache = &dev->cache;
  106. struct mlx5_cache_ent *ent = &cache->ent[c];
  107. struct mlx5_create_mkey_mbox_in *in;
  108. struct mlx5_ib_mr *mr;
  109. int npages = 1 << ent->order;
  110. int err = 0;
  111. int i;
  112. in = kzalloc(sizeof(*in), GFP_KERNEL);
  113. if (!in)
  114. return -ENOMEM;
  115. for (i = 0; i < num; i++) {
  116. if (ent->pending >= MAX_PENDING_REG_MR) {
  117. err = -EAGAIN;
  118. break;
  119. }
  120. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  121. if (!mr) {
  122. err = -ENOMEM;
  123. break;
  124. }
  125. mr->order = ent->order;
  126. mr->umred = 1;
  127. mr->dev = dev;
  128. in->seg.status = 1 << 6;
  129. in->seg.xlt_oct_size = cpu_to_be32((npages + 1) / 2);
  130. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  131. in->seg.flags = MLX5_ACCESS_MODE_MTT | MLX5_PERM_UMR_EN;
  132. in->seg.log2_page_size = 12;
  133. spin_lock_irq(&ent->lock);
  134. ent->pending++;
  135. spin_unlock_irq(&ent->lock);
  136. mr->start = jiffies;
  137. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in,
  138. sizeof(*in), reg_mr_callback,
  139. mr, &mr->out);
  140. if (err) {
  141. mlx5_ib_warn(dev, "create mkey failed %d\n", err);
  142. kfree(mr);
  143. break;
  144. }
  145. }
  146. kfree(in);
  147. return err;
  148. }
  149. static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
  150. {
  151. struct mlx5_mr_cache *cache = &dev->cache;
  152. struct mlx5_cache_ent *ent = &cache->ent[c];
  153. struct mlx5_ib_mr *mr;
  154. int err;
  155. int i;
  156. for (i = 0; i < num; i++) {
  157. spin_lock_irq(&ent->lock);
  158. if (list_empty(&ent->head)) {
  159. spin_unlock_irq(&ent->lock);
  160. return;
  161. }
  162. mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
  163. list_del(&mr->list);
  164. ent->cur--;
  165. ent->size--;
  166. spin_unlock_irq(&ent->lock);
  167. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  168. if (err)
  169. mlx5_ib_warn(dev, "failed destroy mkey\n");
  170. else
  171. kfree(mr);
  172. }
  173. }
  174. static ssize_t size_write(struct file *filp, const char __user *buf,
  175. size_t count, loff_t *pos)
  176. {
  177. struct mlx5_cache_ent *ent = filp->private_data;
  178. struct mlx5_ib_dev *dev = ent->dev;
  179. char lbuf[20];
  180. u32 var;
  181. int err;
  182. int c;
  183. if (copy_from_user(lbuf, buf, sizeof(lbuf)))
  184. return -EFAULT;
  185. c = order2idx(dev, ent->order);
  186. lbuf[sizeof(lbuf) - 1] = 0;
  187. if (sscanf(lbuf, "%u", &var) != 1)
  188. return -EINVAL;
  189. if (var < ent->limit)
  190. return -EINVAL;
  191. if (var > ent->size) {
  192. do {
  193. err = add_keys(dev, c, var - ent->size);
  194. if (err && err != -EAGAIN)
  195. return err;
  196. usleep_range(3000, 5000);
  197. } while (err);
  198. } else if (var < ent->size) {
  199. remove_keys(dev, c, ent->size - var);
  200. }
  201. return count;
  202. }
  203. static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
  204. loff_t *pos)
  205. {
  206. struct mlx5_cache_ent *ent = filp->private_data;
  207. char lbuf[20];
  208. int err;
  209. if (*pos)
  210. return 0;
  211. err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
  212. if (err < 0)
  213. return err;
  214. if (copy_to_user(buf, lbuf, err))
  215. return -EFAULT;
  216. *pos += err;
  217. return err;
  218. }
  219. static const struct file_operations size_fops = {
  220. .owner = THIS_MODULE,
  221. .open = simple_open,
  222. .write = size_write,
  223. .read = size_read,
  224. };
  225. static ssize_t limit_write(struct file *filp, const char __user *buf,
  226. size_t count, loff_t *pos)
  227. {
  228. struct mlx5_cache_ent *ent = filp->private_data;
  229. struct mlx5_ib_dev *dev = ent->dev;
  230. char lbuf[20];
  231. u32 var;
  232. int err;
  233. int c;
  234. if (copy_from_user(lbuf, buf, sizeof(lbuf)))
  235. return -EFAULT;
  236. c = order2idx(dev, ent->order);
  237. lbuf[sizeof(lbuf) - 1] = 0;
  238. if (sscanf(lbuf, "%u", &var) != 1)
  239. return -EINVAL;
  240. if (var > ent->size)
  241. return -EINVAL;
  242. ent->limit = var;
  243. if (ent->cur < ent->limit) {
  244. err = add_keys(dev, c, 2 * ent->limit - ent->cur);
  245. if (err)
  246. return err;
  247. }
  248. return count;
  249. }
  250. static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
  251. loff_t *pos)
  252. {
  253. struct mlx5_cache_ent *ent = filp->private_data;
  254. char lbuf[20];
  255. int err;
  256. if (*pos)
  257. return 0;
  258. err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
  259. if (err < 0)
  260. return err;
  261. if (copy_to_user(buf, lbuf, err))
  262. return -EFAULT;
  263. *pos += err;
  264. return err;
  265. }
  266. static const struct file_operations limit_fops = {
  267. .owner = THIS_MODULE,
  268. .open = simple_open,
  269. .write = limit_write,
  270. .read = limit_read,
  271. };
  272. static int someone_adding(struct mlx5_mr_cache *cache)
  273. {
  274. int i;
  275. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  276. if (cache->ent[i].cur < cache->ent[i].limit)
  277. return 1;
  278. }
  279. return 0;
  280. }
  281. static void __cache_work_func(struct mlx5_cache_ent *ent)
  282. {
  283. struct mlx5_ib_dev *dev = ent->dev;
  284. struct mlx5_mr_cache *cache = &dev->cache;
  285. int i = order2idx(dev, ent->order);
  286. int err;
  287. if (cache->stopped)
  288. return;
  289. ent = &dev->cache.ent[i];
  290. if (ent->cur < 2 * ent->limit && !dev->fill_delay) {
  291. err = add_keys(dev, i, 1);
  292. if (ent->cur < 2 * ent->limit) {
  293. if (err == -EAGAIN) {
  294. mlx5_ib_dbg(dev, "returned eagain, order %d\n",
  295. i + 2);
  296. queue_delayed_work(cache->wq, &ent->dwork,
  297. msecs_to_jiffies(3));
  298. } else if (err) {
  299. mlx5_ib_warn(dev, "command failed order %d, err %d\n",
  300. i + 2, err);
  301. queue_delayed_work(cache->wq, &ent->dwork,
  302. msecs_to_jiffies(1000));
  303. } else {
  304. queue_work(cache->wq, &ent->work);
  305. }
  306. }
  307. } else if (ent->cur > 2 * ent->limit) {
  308. if (!someone_adding(cache) &&
  309. time_after(jiffies, cache->last_add + 300 * HZ)) {
  310. remove_keys(dev, i, 1);
  311. if (ent->cur > ent->limit)
  312. queue_work(cache->wq, &ent->work);
  313. } else {
  314. queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
  315. }
  316. }
  317. }
  318. static void delayed_cache_work_func(struct work_struct *work)
  319. {
  320. struct mlx5_cache_ent *ent;
  321. ent = container_of(work, struct mlx5_cache_ent, dwork.work);
  322. __cache_work_func(ent);
  323. }
  324. static void cache_work_func(struct work_struct *work)
  325. {
  326. struct mlx5_cache_ent *ent;
  327. ent = container_of(work, struct mlx5_cache_ent, work);
  328. __cache_work_func(ent);
  329. }
  330. static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
  331. {
  332. struct mlx5_mr_cache *cache = &dev->cache;
  333. struct mlx5_ib_mr *mr = NULL;
  334. struct mlx5_cache_ent *ent;
  335. int c;
  336. int i;
  337. c = order2idx(dev, order);
  338. if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
  339. mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
  340. return NULL;
  341. }
  342. for (i = c; i < MAX_MR_CACHE_ENTRIES; i++) {
  343. ent = &cache->ent[i];
  344. mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
  345. spin_lock_irq(&ent->lock);
  346. if (!list_empty(&ent->head)) {
  347. mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
  348. list);
  349. list_del(&mr->list);
  350. ent->cur--;
  351. spin_unlock_irq(&ent->lock);
  352. if (ent->cur < ent->limit)
  353. queue_work(cache->wq, &ent->work);
  354. break;
  355. }
  356. spin_unlock_irq(&ent->lock);
  357. queue_work(cache->wq, &ent->work);
  358. if (mr)
  359. break;
  360. }
  361. if (!mr)
  362. cache->ent[c].miss++;
  363. return mr;
  364. }
  365. static void free_cached_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
  366. {
  367. struct mlx5_mr_cache *cache = &dev->cache;
  368. struct mlx5_cache_ent *ent;
  369. int shrink = 0;
  370. int c;
  371. c = order2idx(dev, mr->order);
  372. if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
  373. mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c);
  374. return;
  375. }
  376. ent = &cache->ent[c];
  377. spin_lock_irq(&ent->lock);
  378. list_add_tail(&mr->list, &ent->head);
  379. ent->cur++;
  380. if (ent->cur > 2 * ent->limit)
  381. shrink = 1;
  382. spin_unlock_irq(&ent->lock);
  383. if (shrink)
  384. queue_work(cache->wq, &ent->work);
  385. }
  386. static void clean_keys(struct mlx5_ib_dev *dev, int c)
  387. {
  388. struct mlx5_mr_cache *cache = &dev->cache;
  389. struct mlx5_cache_ent *ent = &cache->ent[c];
  390. struct mlx5_ib_mr *mr;
  391. int err;
  392. cancel_delayed_work(&ent->dwork);
  393. while (1) {
  394. spin_lock_irq(&ent->lock);
  395. if (list_empty(&ent->head)) {
  396. spin_unlock_irq(&ent->lock);
  397. return;
  398. }
  399. mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
  400. list_del(&mr->list);
  401. ent->cur--;
  402. ent->size--;
  403. spin_unlock_irq(&ent->lock);
  404. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  405. if (err)
  406. mlx5_ib_warn(dev, "failed destroy mkey\n");
  407. else
  408. kfree(mr);
  409. }
  410. }
  411. static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
  412. {
  413. struct mlx5_mr_cache *cache = &dev->cache;
  414. struct mlx5_cache_ent *ent;
  415. int i;
  416. if (!mlx5_debugfs_root)
  417. return 0;
  418. cache->root = debugfs_create_dir("mr_cache", dev->mdev.priv.dbg_root);
  419. if (!cache->root)
  420. return -ENOMEM;
  421. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  422. ent = &cache->ent[i];
  423. sprintf(ent->name, "%d", ent->order);
  424. ent->dir = debugfs_create_dir(ent->name, cache->root);
  425. if (!ent->dir)
  426. return -ENOMEM;
  427. ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent,
  428. &size_fops);
  429. if (!ent->fsize)
  430. return -ENOMEM;
  431. ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent,
  432. &limit_fops);
  433. if (!ent->flimit)
  434. return -ENOMEM;
  435. ent->fcur = debugfs_create_u32("cur", 0400, ent->dir,
  436. &ent->cur);
  437. if (!ent->fcur)
  438. return -ENOMEM;
  439. ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir,
  440. &ent->miss);
  441. if (!ent->fmiss)
  442. return -ENOMEM;
  443. }
  444. return 0;
  445. }
  446. static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
  447. {
  448. if (!mlx5_debugfs_root)
  449. return;
  450. debugfs_remove_recursive(dev->cache.root);
  451. }
  452. static void delay_time_func(unsigned long ctx)
  453. {
  454. struct mlx5_ib_dev *dev = (struct mlx5_ib_dev *)ctx;
  455. dev->fill_delay = 0;
  456. }
  457. int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
  458. {
  459. struct mlx5_mr_cache *cache = &dev->cache;
  460. struct mlx5_cache_ent *ent;
  461. int limit;
  462. int size;
  463. int err;
  464. int i;
  465. cache->wq = create_singlethread_workqueue("mkey_cache");
  466. if (!cache->wq) {
  467. mlx5_ib_warn(dev, "failed to create work queue\n");
  468. return -ENOMEM;
  469. }
  470. setup_timer(&dev->delay_timer, delay_time_func, (unsigned long)dev);
  471. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  472. INIT_LIST_HEAD(&cache->ent[i].head);
  473. spin_lock_init(&cache->ent[i].lock);
  474. ent = &cache->ent[i];
  475. INIT_LIST_HEAD(&ent->head);
  476. spin_lock_init(&ent->lock);
  477. ent->order = i + 2;
  478. ent->dev = dev;
  479. if (dev->mdev.profile->mask & MLX5_PROF_MASK_MR_CACHE) {
  480. size = dev->mdev.profile->mr_cache[i].size;
  481. limit = dev->mdev.profile->mr_cache[i].limit;
  482. } else {
  483. size = DEF_CACHE_SIZE;
  484. limit = 0;
  485. }
  486. INIT_WORK(&ent->work, cache_work_func);
  487. INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
  488. ent->limit = limit;
  489. queue_work(cache->wq, &ent->work);
  490. }
  491. err = mlx5_mr_cache_debugfs_init(dev);
  492. if (err)
  493. mlx5_ib_warn(dev, "cache debugfs failure\n");
  494. return 0;
  495. }
  496. int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
  497. {
  498. int i;
  499. dev->cache.stopped = 1;
  500. flush_workqueue(dev->cache.wq);
  501. mlx5_mr_cache_debugfs_cleanup(dev);
  502. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
  503. clean_keys(dev, i);
  504. destroy_workqueue(dev->cache.wq);
  505. del_timer_sync(&dev->delay_timer);
  506. return 0;
  507. }
  508. struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
  509. {
  510. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  511. struct mlx5_core_dev *mdev = &dev->mdev;
  512. struct mlx5_create_mkey_mbox_in *in;
  513. struct mlx5_mkey_seg *seg;
  514. struct mlx5_ib_mr *mr;
  515. int err;
  516. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  517. if (!mr)
  518. return ERR_PTR(-ENOMEM);
  519. in = kzalloc(sizeof(*in), GFP_KERNEL);
  520. if (!in) {
  521. err = -ENOMEM;
  522. goto err_free;
  523. }
  524. seg = &in->seg;
  525. seg->flags = convert_access(acc) | MLX5_ACCESS_MODE_PA;
  526. seg->flags_pd = cpu_to_be32(to_mpd(pd)->pdn | MLX5_MKEY_LEN64);
  527. seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  528. seg->start_addr = 0;
  529. err = mlx5_core_create_mkey(mdev, &mr->mmr, in, sizeof(*in), NULL, NULL,
  530. NULL);
  531. if (err)
  532. goto err_in;
  533. kfree(in);
  534. mr->ibmr.lkey = mr->mmr.key;
  535. mr->ibmr.rkey = mr->mmr.key;
  536. mr->umem = NULL;
  537. return &mr->ibmr;
  538. err_in:
  539. kfree(in);
  540. err_free:
  541. kfree(mr);
  542. return ERR_PTR(err);
  543. }
  544. static int get_octo_len(u64 addr, u64 len, int page_size)
  545. {
  546. u64 offset;
  547. int npages;
  548. offset = addr & (page_size - 1);
  549. npages = ALIGN(len + offset, page_size) >> ilog2(page_size);
  550. return (npages + 1) / 2;
  551. }
  552. static int use_umr(int order)
  553. {
  554. return order <= 17;
  555. }
  556. static void prep_umr_reg_wqe(struct ib_pd *pd, struct ib_send_wr *wr,
  557. struct ib_sge *sg, u64 dma, int n, u32 key,
  558. int page_shift, u64 virt_addr, u64 len,
  559. int access_flags)
  560. {
  561. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  562. struct ib_mr *mr = dev->umrc.mr;
  563. sg->addr = dma;
  564. sg->length = ALIGN(sizeof(u64) * n, 64);
  565. sg->lkey = mr->lkey;
  566. wr->next = NULL;
  567. wr->send_flags = 0;
  568. wr->sg_list = sg;
  569. if (n)
  570. wr->num_sge = 1;
  571. else
  572. wr->num_sge = 0;
  573. wr->opcode = MLX5_IB_WR_UMR;
  574. wr->wr.fast_reg.page_list_len = n;
  575. wr->wr.fast_reg.page_shift = page_shift;
  576. wr->wr.fast_reg.rkey = key;
  577. wr->wr.fast_reg.iova_start = virt_addr;
  578. wr->wr.fast_reg.length = len;
  579. wr->wr.fast_reg.access_flags = access_flags;
  580. wr->wr.fast_reg.page_list = (struct ib_fast_reg_page_list *)pd;
  581. }
  582. static void prep_umr_unreg_wqe(struct mlx5_ib_dev *dev,
  583. struct ib_send_wr *wr, u32 key)
  584. {
  585. wr->send_flags = MLX5_IB_SEND_UMR_UNREG;
  586. wr->opcode = MLX5_IB_WR_UMR;
  587. wr->wr.fast_reg.rkey = key;
  588. }
  589. void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context)
  590. {
  591. struct mlx5_ib_mr *mr;
  592. struct ib_wc wc;
  593. int err;
  594. while (1) {
  595. err = ib_poll_cq(cq, 1, &wc);
  596. if (err < 0) {
  597. pr_warn("poll cq error %d\n", err);
  598. return;
  599. }
  600. if (err == 0)
  601. break;
  602. mr = (struct mlx5_ib_mr *)(unsigned long)wc.wr_id;
  603. mr->status = wc.status;
  604. complete(&mr->done);
  605. }
  606. ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
  607. }
  608. static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem,
  609. u64 virt_addr, u64 len, int npages,
  610. int page_shift, int order, int access_flags)
  611. {
  612. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  613. struct device *ddev = dev->ib_dev.dma_device;
  614. struct umr_common *umrc = &dev->umrc;
  615. struct ib_send_wr wr, *bad;
  616. struct mlx5_ib_mr *mr;
  617. struct ib_sge sg;
  618. int size = sizeof(u64) * npages;
  619. int err;
  620. int i;
  621. for (i = 0; i < 1; i++) {
  622. mr = alloc_cached_mr(dev, order);
  623. if (mr)
  624. break;
  625. err = add_keys(dev, order2idx(dev, order), 1);
  626. if (err && err != -EAGAIN) {
  627. mlx5_ib_warn(dev, "add_keys failed, err %d\n", err);
  628. break;
  629. }
  630. }
  631. if (!mr)
  632. return ERR_PTR(-EAGAIN);
  633. mr->pas = kmalloc(size + MLX5_UMR_ALIGN - 1, GFP_KERNEL);
  634. if (!mr->pas) {
  635. err = -ENOMEM;
  636. goto error;
  637. }
  638. mlx5_ib_populate_pas(dev, umem, page_shift,
  639. mr_align(mr->pas, MLX5_UMR_ALIGN), 1);
  640. mr->dma = dma_map_single(ddev, mr_align(mr->pas, MLX5_UMR_ALIGN), size,
  641. DMA_TO_DEVICE);
  642. if (dma_mapping_error(ddev, mr->dma)) {
  643. kfree(mr->pas);
  644. err = -ENOMEM;
  645. goto error;
  646. }
  647. memset(&wr, 0, sizeof(wr));
  648. wr.wr_id = (u64)(unsigned long)mr;
  649. prep_umr_reg_wqe(pd, &wr, &sg, mr->dma, npages, mr->mmr.key, page_shift, virt_addr, len, access_flags);
  650. /* We serialize polls so one process does not kidnap another's
  651. * completion. This is not a problem since wr is completed in
  652. * around 1 usec
  653. */
  654. down(&umrc->sem);
  655. init_completion(&mr->done);
  656. err = ib_post_send(umrc->qp, &wr, &bad);
  657. if (err) {
  658. mlx5_ib_warn(dev, "post send failed, err %d\n", err);
  659. up(&umrc->sem);
  660. goto error;
  661. }
  662. wait_for_completion(&mr->done);
  663. up(&umrc->sem);
  664. dma_unmap_single(ddev, mr->dma, size, DMA_TO_DEVICE);
  665. kfree(mr->pas);
  666. if (mr->status != IB_WC_SUCCESS) {
  667. mlx5_ib_warn(dev, "reg umr failed\n");
  668. err = -EFAULT;
  669. goto error;
  670. }
  671. return mr;
  672. error:
  673. free_cached_mr(dev, mr);
  674. return ERR_PTR(err);
  675. }
  676. static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, u64 virt_addr,
  677. u64 length, struct ib_umem *umem,
  678. int npages, int page_shift,
  679. int access_flags)
  680. {
  681. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  682. struct mlx5_create_mkey_mbox_in *in;
  683. struct mlx5_ib_mr *mr;
  684. int inlen;
  685. int err;
  686. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  687. if (!mr)
  688. return ERR_PTR(-ENOMEM);
  689. inlen = sizeof(*in) + sizeof(*in->pas) * ((npages + 1) / 2) * 2;
  690. in = mlx5_vzalloc(inlen);
  691. if (!in) {
  692. err = -ENOMEM;
  693. goto err_1;
  694. }
  695. mlx5_ib_populate_pas(dev, umem, page_shift, in->pas, 0);
  696. in->seg.flags = convert_access(access_flags) |
  697. MLX5_ACCESS_MODE_MTT;
  698. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  699. in->seg.start_addr = cpu_to_be64(virt_addr);
  700. in->seg.len = cpu_to_be64(length);
  701. in->seg.bsfs_octo_size = 0;
  702. in->seg.xlt_oct_size = cpu_to_be32(get_octo_len(virt_addr, length, 1 << page_shift));
  703. in->seg.log2_page_size = page_shift;
  704. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  705. in->xlat_oct_act_size = cpu_to_be32(get_octo_len(virt_addr, length,
  706. 1 << page_shift));
  707. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, inlen, NULL,
  708. NULL, NULL);
  709. if (err) {
  710. mlx5_ib_warn(dev, "create mkey failed\n");
  711. goto err_2;
  712. }
  713. mr->umem = umem;
  714. mlx5_vfree(in);
  715. mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmr.key);
  716. return mr;
  717. err_2:
  718. mlx5_vfree(in);
  719. err_1:
  720. kfree(mr);
  721. return ERR_PTR(err);
  722. }
  723. struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
  724. u64 virt_addr, int access_flags,
  725. struct ib_udata *udata)
  726. {
  727. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  728. struct mlx5_ib_mr *mr = NULL;
  729. struct ib_umem *umem;
  730. int page_shift;
  731. int npages;
  732. int ncont;
  733. int order;
  734. int err;
  735. mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx\n",
  736. start, virt_addr, length);
  737. umem = ib_umem_get(pd->uobject->context, start, length, access_flags,
  738. 0);
  739. if (IS_ERR(umem)) {
  740. mlx5_ib_dbg(dev, "umem get failed\n");
  741. return (void *)umem;
  742. }
  743. mlx5_ib_cont_pages(umem, start, &npages, &page_shift, &ncont, &order);
  744. if (!npages) {
  745. mlx5_ib_warn(dev, "avoid zero region\n");
  746. err = -EINVAL;
  747. goto error;
  748. }
  749. mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
  750. npages, ncont, order, page_shift);
  751. if (use_umr(order)) {
  752. mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift,
  753. order, access_flags);
  754. if (PTR_ERR(mr) == -EAGAIN) {
  755. mlx5_ib_dbg(dev, "cache empty for order %d", order);
  756. mr = NULL;
  757. }
  758. }
  759. if (!mr)
  760. mr = reg_create(pd, virt_addr, length, umem, ncont, page_shift,
  761. access_flags);
  762. if (IS_ERR(mr)) {
  763. err = PTR_ERR(mr);
  764. goto error;
  765. }
  766. mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmr.key);
  767. mr->umem = umem;
  768. mr->npages = npages;
  769. spin_lock(&dev->mr_lock);
  770. dev->mdev.priv.reg_pages += npages;
  771. spin_unlock(&dev->mr_lock);
  772. mr->ibmr.lkey = mr->mmr.key;
  773. mr->ibmr.rkey = mr->mmr.key;
  774. return &mr->ibmr;
  775. error:
  776. ib_umem_release(umem);
  777. return ERR_PTR(err);
  778. }
  779. static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
  780. {
  781. struct umr_common *umrc = &dev->umrc;
  782. struct ib_send_wr wr, *bad;
  783. int err;
  784. memset(&wr, 0, sizeof(wr));
  785. wr.wr_id = (u64)(unsigned long)mr;
  786. prep_umr_unreg_wqe(dev, &wr, mr->mmr.key);
  787. down(&umrc->sem);
  788. init_completion(&mr->done);
  789. err = ib_post_send(umrc->qp, &wr, &bad);
  790. if (err) {
  791. up(&umrc->sem);
  792. mlx5_ib_dbg(dev, "err %d\n", err);
  793. goto error;
  794. }
  795. wait_for_completion(&mr->done);
  796. up(&umrc->sem);
  797. if (mr->status != IB_WC_SUCCESS) {
  798. mlx5_ib_warn(dev, "unreg umr failed\n");
  799. err = -EFAULT;
  800. goto error;
  801. }
  802. return 0;
  803. error:
  804. return err;
  805. }
  806. int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
  807. {
  808. struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
  809. struct mlx5_ib_mr *mr = to_mmr(ibmr);
  810. struct ib_umem *umem = mr->umem;
  811. int npages = mr->npages;
  812. int umred = mr->umred;
  813. int err;
  814. if (!umred) {
  815. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  816. if (err) {
  817. mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n",
  818. mr->mmr.key, err);
  819. return err;
  820. }
  821. } else {
  822. err = unreg_umr(dev, mr);
  823. if (err) {
  824. mlx5_ib_warn(dev, "failed unregister\n");
  825. return err;
  826. }
  827. free_cached_mr(dev, mr);
  828. }
  829. if (umem) {
  830. ib_umem_release(umem);
  831. spin_lock(&dev->mr_lock);
  832. dev->mdev.priv.reg_pages -= npages;
  833. spin_unlock(&dev->mr_lock);
  834. }
  835. if (!umred)
  836. kfree(mr);
  837. return 0;
  838. }
  839. struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd,
  840. int max_page_list_len)
  841. {
  842. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  843. struct mlx5_create_mkey_mbox_in *in;
  844. struct mlx5_ib_mr *mr;
  845. int err;
  846. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  847. if (!mr)
  848. return ERR_PTR(-ENOMEM);
  849. in = kzalloc(sizeof(*in), GFP_KERNEL);
  850. if (!in) {
  851. err = -ENOMEM;
  852. goto err_free;
  853. }
  854. in->seg.status = 1 << 6; /* free */
  855. in->seg.xlt_oct_size = cpu_to_be32((max_page_list_len + 1) / 2);
  856. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  857. in->seg.flags = MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
  858. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  859. /*
  860. * TBD not needed - issue 197292 */
  861. in->seg.log2_page_size = PAGE_SHIFT;
  862. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, sizeof(*in), NULL,
  863. NULL, NULL);
  864. kfree(in);
  865. if (err)
  866. goto err_free;
  867. mr->ibmr.lkey = mr->mmr.key;
  868. mr->ibmr.rkey = mr->mmr.key;
  869. mr->umem = NULL;
  870. return &mr->ibmr;
  871. err_free:
  872. kfree(mr);
  873. return ERR_PTR(err);
  874. }
  875. struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
  876. int page_list_len)
  877. {
  878. struct mlx5_ib_fast_reg_page_list *mfrpl;
  879. int size = page_list_len * sizeof(u64);
  880. mfrpl = kmalloc(sizeof(*mfrpl), GFP_KERNEL);
  881. if (!mfrpl)
  882. return ERR_PTR(-ENOMEM);
  883. mfrpl->ibfrpl.page_list = kmalloc(size, GFP_KERNEL);
  884. if (!mfrpl->ibfrpl.page_list)
  885. goto err_free;
  886. mfrpl->mapped_page_list = dma_alloc_coherent(ibdev->dma_device,
  887. size, &mfrpl->map,
  888. GFP_KERNEL);
  889. if (!mfrpl->mapped_page_list)
  890. goto err_free;
  891. WARN_ON(mfrpl->map & 0x3f);
  892. return &mfrpl->ibfrpl;
  893. err_free:
  894. kfree(mfrpl->ibfrpl.page_list);
  895. kfree(mfrpl);
  896. return ERR_PTR(-ENOMEM);
  897. }
  898. void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list)
  899. {
  900. struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(page_list);
  901. struct mlx5_ib_dev *dev = to_mdev(page_list->device);
  902. int size = page_list->max_page_list_len * sizeof(u64);
  903. dma_free_coherent(&dev->mdev.pdev->dev, size, mfrpl->mapped_page_list,
  904. mfrpl->map);
  905. kfree(mfrpl->ibfrpl.page_list);
  906. kfree(mfrpl);
  907. }