main.c 38 KB

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  1. /*
  2. * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <asm-generic/kmap_types.h>
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/errno.h>
  36. #include <linux/pci.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/slab.h>
  39. #include <linux/io-mapping.h>
  40. #include <linux/sched.h>
  41. #include <rdma/ib_user_verbs.h>
  42. #include <rdma/ib_smi.h>
  43. #include <rdma/ib_umem.h>
  44. #include "user.h"
  45. #include "mlx5_ib.h"
  46. #define DRIVER_NAME "mlx5_ib"
  47. #define DRIVER_VERSION "1.0"
  48. #define DRIVER_RELDATE "June 2013"
  49. MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  50. MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  51. MODULE_LICENSE("Dual BSD/GPL");
  52. MODULE_VERSION(DRIVER_VERSION);
  53. static int prof_sel = 2;
  54. module_param_named(prof_sel, prof_sel, int, 0444);
  55. MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
  56. static char mlx5_version[] =
  57. DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  58. DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  59. static struct mlx5_profile profile[] = {
  60. [0] = {
  61. .mask = 0,
  62. },
  63. [1] = {
  64. .mask = MLX5_PROF_MASK_QP_SIZE,
  65. .log_max_qp = 12,
  66. },
  67. [2] = {
  68. .mask = MLX5_PROF_MASK_QP_SIZE |
  69. MLX5_PROF_MASK_MR_CACHE,
  70. .log_max_qp = 17,
  71. .mr_cache[0] = {
  72. .size = 500,
  73. .limit = 250
  74. },
  75. .mr_cache[1] = {
  76. .size = 500,
  77. .limit = 250
  78. },
  79. .mr_cache[2] = {
  80. .size = 500,
  81. .limit = 250
  82. },
  83. .mr_cache[3] = {
  84. .size = 500,
  85. .limit = 250
  86. },
  87. .mr_cache[4] = {
  88. .size = 500,
  89. .limit = 250
  90. },
  91. .mr_cache[5] = {
  92. .size = 500,
  93. .limit = 250
  94. },
  95. .mr_cache[6] = {
  96. .size = 500,
  97. .limit = 250
  98. },
  99. .mr_cache[7] = {
  100. .size = 500,
  101. .limit = 250
  102. },
  103. .mr_cache[8] = {
  104. .size = 500,
  105. .limit = 250
  106. },
  107. .mr_cache[9] = {
  108. .size = 500,
  109. .limit = 250
  110. },
  111. .mr_cache[10] = {
  112. .size = 500,
  113. .limit = 250
  114. },
  115. .mr_cache[11] = {
  116. .size = 500,
  117. .limit = 250
  118. },
  119. .mr_cache[12] = {
  120. .size = 64,
  121. .limit = 32
  122. },
  123. .mr_cache[13] = {
  124. .size = 32,
  125. .limit = 16
  126. },
  127. .mr_cache[14] = {
  128. .size = 16,
  129. .limit = 8
  130. },
  131. .mr_cache[15] = {
  132. .size = 8,
  133. .limit = 4
  134. },
  135. },
  136. };
  137. int mlx5_vector2eqn(struct mlx5_ib_dev *dev, int vector, int *eqn, int *irqn)
  138. {
  139. struct mlx5_eq_table *table = &dev->mdev.priv.eq_table;
  140. struct mlx5_eq *eq, *n;
  141. int err = -ENOENT;
  142. spin_lock(&table->lock);
  143. list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
  144. if (eq->index == vector) {
  145. *eqn = eq->eqn;
  146. *irqn = eq->irqn;
  147. err = 0;
  148. break;
  149. }
  150. }
  151. spin_unlock(&table->lock);
  152. return err;
  153. }
  154. static int alloc_comp_eqs(struct mlx5_ib_dev *dev)
  155. {
  156. struct mlx5_eq_table *table = &dev->mdev.priv.eq_table;
  157. char name[MLX5_MAX_EQ_NAME];
  158. struct mlx5_eq *eq, *n;
  159. int ncomp_vec;
  160. int nent;
  161. int err;
  162. int i;
  163. INIT_LIST_HEAD(&dev->eqs_list);
  164. ncomp_vec = table->num_comp_vectors;
  165. nent = MLX5_COMP_EQ_SIZE;
  166. for (i = 0; i < ncomp_vec; i++) {
  167. eq = kzalloc(sizeof(*eq), GFP_KERNEL);
  168. if (!eq) {
  169. err = -ENOMEM;
  170. goto clean;
  171. }
  172. snprintf(name, MLX5_MAX_EQ_NAME, "mlx5_comp%d", i);
  173. err = mlx5_create_map_eq(&dev->mdev, eq,
  174. i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
  175. name, &dev->mdev.priv.uuari.uars[0]);
  176. if (err) {
  177. kfree(eq);
  178. goto clean;
  179. }
  180. mlx5_ib_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
  181. eq->index = i;
  182. spin_lock(&table->lock);
  183. list_add_tail(&eq->list, &dev->eqs_list);
  184. spin_unlock(&table->lock);
  185. }
  186. dev->num_comp_vectors = ncomp_vec;
  187. return 0;
  188. clean:
  189. spin_lock(&table->lock);
  190. list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
  191. list_del(&eq->list);
  192. spin_unlock(&table->lock);
  193. if (mlx5_destroy_unmap_eq(&dev->mdev, eq))
  194. mlx5_ib_warn(dev, "failed to destroy EQ 0x%x\n", eq->eqn);
  195. kfree(eq);
  196. spin_lock(&table->lock);
  197. }
  198. spin_unlock(&table->lock);
  199. return err;
  200. }
  201. static void free_comp_eqs(struct mlx5_ib_dev *dev)
  202. {
  203. struct mlx5_eq_table *table = &dev->mdev.priv.eq_table;
  204. struct mlx5_eq *eq, *n;
  205. spin_lock(&table->lock);
  206. list_for_each_entry_safe(eq, n, &dev->eqs_list, list) {
  207. list_del(&eq->list);
  208. spin_unlock(&table->lock);
  209. if (mlx5_destroy_unmap_eq(&dev->mdev, eq))
  210. mlx5_ib_warn(dev, "failed to destroy EQ 0x%x\n", eq->eqn);
  211. kfree(eq);
  212. spin_lock(&table->lock);
  213. }
  214. spin_unlock(&table->lock);
  215. }
  216. static int mlx5_ib_query_device(struct ib_device *ibdev,
  217. struct ib_device_attr *props)
  218. {
  219. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  220. struct ib_smp *in_mad = NULL;
  221. struct ib_smp *out_mad = NULL;
  222. int err = -ENOMEM;
  223. int max_rq_sg;
  224. int max_sq_sg;
  225. u64 flags;
  226. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  227. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  228. if (!in_mad || !out_mad)
  229. goto out;
  230. init_query_mad(in_mad);
  231. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  232. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, 1, NULL, NULL, in_mad, out_mad);
  233. if (err)
  234. goto out;
  235. memset(props, 0, sizeof(*props));
  236. props->fw_ver = ((u64)fw_rev_maj(&dev->mdev) << 32) |
  237. (fw_rev_min(&dev->mdev) << 16) |
  238. fw_rev_sub(&dev->mdev);
  239. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  240. IB_DEVICE_PORT_ACTIVE_EVENT |
  241. IB_DEVICE_SYS_IMAGE_GUID |
  242. IB_DEVICE_RC_RNR_NAK_GEN |
  243. IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
  244. flags = dev->mdev.caps.flags;
  245. if (flags & MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR)
  246. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  247. if (flags & MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR)
  248. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  249. if (flags & MLX5_DEV_CAP_FLAG_APM)
  250. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  251. props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
  252. if (flags & MLX5_DEV_CAP_FLAG_XRC)
  253. props->device_cap_flags |= IB_DEVICE_XRC;
  254. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  255. props->vendor_id = be32_to_cpup((__be32 *)(out_mad->data + 36)) &
  256. 0xffffff;
  257. props->vendor_part_id = be16_to_cpup((__be16 *)(out_mad->data + 30));
  258. props->hw_ver = be32_to_cpup((__be32 *)(out_mad->data + 32));
  259. memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
  260. props->max_mr_size = ~0ull;
  261. props->page_size_cap = dev->mdev.caps.min_page_sz;
  262. props->max_qp = 1 << dev->mdev.caps.log_max_qp;
  263. props->max_qp_wr = dev->mdev.caps.max_wqes;
  264. max_rq_sg = dev->mdev.caps.max_rq_desc_sz / sizeof(struct mlx5_wqe_data_seg);
  265. max_sq_sg = (dev->mdev.caps.max_sq_desc_sz - sizeof(struct mlx5_wqe_ctrl_seg)) /
  266. sizeof(struct mlx5_wqe_data_seg);
  267. props->max_sge = min(max_rq_sg, max_sq_sg);
  268. props->max_cq = 1 << dev->mdev.caps.log_max_cq;
  269. props->max_cqe = dev->mdev.caps.max_cqes - 1;
  270. props->max_mr = 1 << dev->mdev.caps.log_max_mkey;
  271. props->max_pd = 1 << dev->mdev.caps.log_max_pd;
  272. props->max_qp_rd_atom = dev->mdev.caps.max_ra_req_qp;
  273. props->max_qp_init_rd_atom = dev->mdev.caps.max_ra_res_qp;
  274. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  275. props->max_srq = 1 << dev->mdev.caps.log_max_srq;
  276. props->max_srq_wr = dev->mdev.caps.max_srq_wqes - 1;
  277. props->max_srq_sge = max_rq_sg - 1;
  278. props->max_fast_reg_page_list_len = (unsigned int)-1;
  279. props->local_ca_ack_delay = dev->mdev.caps.local_ca_ack_delay;
  280. props->atomic_cap = IB_ATOMIC_NONE;
  281. props->masked_atomic_cap = IB_ATOMIC_NONE;
  282. props->max_pkeys = be16_to_cpup((__be16 *)(out_mad->data + 28));
  283. props->max_mcast_grp = 1 << dev->mdev.caps.log_max_mcg;
  284. props->max_mcast_qp_attach = dev->mdev.caps.max_qp_mcg;
  285. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  286. props->max_mcast_grp;
  287. props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
  288. out:
  289. kfree(in_mad);
  290. kfree(out_mad);
  291. return err;
  292. }
  293. int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
  294. struct ib_port_attr *props)
  295. {
  296. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  297. struct ib_smp *in_mad = NULL;
  298. struct ib_smp *out_mad = NULL;
  299. int ext_active_speed;
  300. int err = -ENOMEM;
  301. if (port < 1 || port > dev->mdev.caps.num_ports) {
  302. mlx5_ib_warn(dev, "invalid port number %d\n", port);
  303. return -EINVAL;
  304. }
  305. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  306. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  307. if (!in_mad || !out_mad)
  308. goto out;
  309. memset(props, 0, sizeof(*props));
  310. init_query_mad(in_mad);
  311. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  312. in_mad->attr_mod = cpu_to_be32(port);
  313. err = mlx5_MAD_IFC(dev, 1, 1, port, NULL, NULL, in_mad, out_mad);
  314. if (err) {
  315. mlx5_ib_warn(dev, "err %d\n", err);
  316. goto out;
  317. }
  318. props->lid = be16_to_cpup((__be16 *)(out_mad->data + 16));
  319. props->lmc = out_mad->data[34] & 0x7;
  320. props->sm_lid = be16_to_cpup((__be16 *)(out_mad->data + 18));
  321. props->sm_sl = out_mad->data[36] & 0xf;
  322. props->state = out_mad->data[32] & 0xf;
  323. props->phys_state = out_mad->data[33] >> 4;
  324. props->port_cap_flags = be32_to_cpup((__be32 *)(out_mad->data + 20));
  325. props->gid_tbl_len = out_mad->data[50];
  326. props->max_msg_sz = 1 << to_mdev(ibdev)->mdev.caps.log_max_msg;
  327. props->pkey_tbl_len = to_mdev(ibdev)->mdev.caps.port[port - 1].pkey_table_len;
  328. props->bad_pkey_cntr = be16_to_cpup((__be16 *)(out_mad->data + 46));
  329. props->qkey_viol_cntr = be16_to_cpup((__be16 *)(out_mad->data + 48));
  330. props->active_width = out_mad->data[31] & 0xf;
  331. props->active_speed = out_mad->data[35] >> 4;
  332. props->max_mtu = out_mad->data[41] & 0xf;
  333. props->active_mtu = out_mad->data[36] >> 4;
  334. props->subnet_timeout = out_mad->data[51] & 0x1f;
  335. props->max_vl_num = out_mad->data[37] >> 4;
  336. props->init_type_reply = out_mad->data[41] >> 4;
  337. /* Check if extended speeds (EDR/FDR/...) are supported */
  338. if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
  339. ext_active_speed = out_mad->data[62] >> 4;
  340. switch (ext_active_speed) {
  341. case 1:
  342. props->active_speed = 16; /* FDR */
  343. break;
  344. case 2:
  345. props->active_speed = 32; /* EDR */
  346. break;
  347. }
  348. }
  349. /* If reported active speed is QDR, check if is FDR-10 */
  350. if (props->active_speed == 4) {
  351. if (dev->mdev.caps.ext_port_cap[port - 1] &
  352. MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO) {
  353. init_query_mad(in_mad);
  354. in_mad->attr_id = MLX5_ATTR_EXTENDED_PORT_INFO;
  355. in_mad->attr_mod = cpu_to_be32(port);
  356. err = mlx5_MAD_IFC(dev, 1, 1, port,
  357. NULL, NULL, in_mad, out_mad);
  358. if (err)
  359. goto out;
  360. /* Checking LinkSpeedActive for FDR-10 */
  361. if (out_mad->data[15] & 0x1)
  362. props->active_speed = 8;
  363. }
  364. }
  365. out:
  366. kfree(in_mad);
  367. kfree(out_mad);
  368. return err;
  369. }
  370. static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  371. union ib_gid *gid)
  372. {
  373. struct ib_smp *in_mad = NULL;
  374. struct ib_smp *out_mad = NULL;
  375. int err = -ENOMEM;
  376. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  377. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  378. if (!in_mad || !out_mad)
  379. goto out;
  380. init_query_mad(in_mad);
  381. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  382. in_mad->attr_mod = cpu_to_be32(port);
  383. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
  384. if (err)
  385. goto out;
  386. memcpy(gid->raw, out_mad->data + 8, 8);
  387. init_query_mad(in_mad);
  388. in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
  389. in_mad->attr_mod = cpu_to_be32(index / 8);
  390. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
  391. if (err)
  392. goto out;
  393. memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
  394. out:
  395. kfree(in_mad);
  396. kfree(out_mad);
  397. return err;
  398. }
  399. static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  400. u16 *pkey)
  401. {
  402. struct ib_smp *in_mad = NULL;
  403. struct ib_smp *out_mad = NULL;
  404. int err = -ENOMEM;
  405. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  406. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  407. if (!in_mad || !out_mad)
  408. goto out;
  409. init_query_mad(in_mad);
  410. in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
  411. in_mad->attr_mod = cpu_to_be32(index / 32);
  412. err = mlx5_MAD_IFC(to_mdev(ibdev), 1, 1, port, NULL, NULL, in_mad, out_mad);
  413. if (err)
  414. goto out;
  415. *pkey = be16_to_cpu(((__be16 *)out_mad->data)[index % 32]);
  416. out:
  417. kfree(in_mad);
  418. kfree(out_mad);
  419. return err;
  420. }
  421. struct mlx5_reg_node_desc {
  422. u8 desc[64];
  423. };
  424. static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
  425. struct ib_device_modify *props)
  426. {
  427. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  428. struct mlx5_reg_node_desc in;
  429. struct mlx5_reg_node_desc out;
  430. int err;
  431. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  432. return -EOPNOTSUPP;
  433. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  434. return 0;
  435. /*
  436. * If possible, pass node desc to FW, so it can generate
  437. * a 144 trap. If cmd fails, just ignore.
  438. */
  439. memcpy(&in, props->node_desc, 64);
  440. err = mlx5_core_access_reg(&dev->mdev, &in, sizeof(in), &out,
  441. sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
  442. if (err)
  443. return err;
  444. memcpy(ibdev->node_desc, props->node_desc, 64);
  445. return err;
  446. }
  447. static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  448. struct ib_port_modify *props)
  449. {
  450. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  451. struct ib_port_attr attr;
  452. u32 tmp;
  453. int err;
  454. mutex_lock(&dev->cap_mask_mutex);
  455. err = mlx5_ib_query_port(ibdev, port, &attr);
  456. if (err)
  457. goto out;
  458. tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
  459. ~props->clr_port_cap_mask;
  460. err = mlx5_set_port_caps(&dev->mdev, port, tmp);
  461. out:
  462. mutex_unlock(&dev->cap_mask_mutex);
  463. return err;
  464. }
  465. static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
  466. struct ib_udata *udata)
  467. {
  468. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  469. struct mlx5_ib_alloc_ucontext_req req;
  470. struct mlx5_ib_alloc_ucontext_resp resp;
  471. struct mlx5_ib_ucontext *context;
  472. struct mlx5_uuar_info *uuari;
  473. struct mlx5_uar *uars;
  474. int num_uars;
  475. int uuarn;
  476. int err;
  477. int i;
  478. if (!dev->ib_active)
  479. return ERR_PTR(-EAGAIN);
  480. err = ib_copy_from_udata(&req, udata, sizeof(req));
  481. if (err)
  482. return ERR_PTR(err);
  483. if (req.total_num_uuars > MLX5_MAX_UUARS)
  484. return ERR_PTR(-ENOMEM);
  485. if (req.total_num_uuars == 0)
  486. return ERR_PTR(-EINVAL);
  487. req.total_num_uuars = ALIGN(req.total_num_uuars, MLX5_BF_REGS_PER_PAGE);
  488. if (req.num_low_latency_uuars > req.total_num_uuars - 1)
  489. return ERR_PTR(-EINVAL);
  490. num_uars = req.total_num_uuars / MLX5_BF_REGS_PER_PAGE;
  491. resp.qp_tab_size = 1 << dev->mdev.caps.log_max_qp;
  492. resp.bf_reg_size = dev->mdev.caps.bf_reg_size;
  493. resp.cache_line_size = L1_CACHE_BYTES;
  494. resp.max_sq_desc_sz = dev->mdev.caps.max_sq_desc_sz;
  495. resp.max_rq_desc_sz = dev->mdev.caps.max_rq_desc_sz;
  496. resp.max_send_wqebb = dev->mdev.caps.max_wqes;
  497. resp.max_recv_wr = dev->mdev.caps.max_wqes;
  498. resp.max_srq_recv_wr = dev->mdev.caps.max_srq_wqes;
  499. context = kzalloc(sizeof(*context), GFP_KERNEL);
  500. if (!context)
  501. return ERR_PTR(-ENOMEM);
  502. uuari = &context->uuari;
  503. mutex_init(&uuari->lock);
  504. uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
  505. if (!uars) {
  506. err = -ENOMEM;
  507. goto out_ctx;
  508. }
  509. uuari->bitmap = kcalloc(BITS_TO_LONGS(req.total_num_uuars),
  510. sizeof(*uuari->bitmap),
  511. GFP_KERNEL);
  512. if (!uuari->bitmap) {
  513. err = -ENOMEM;
  514. goto out_uar_ctx;
  515. }
  516. /*
  517. * clear all fast path uuars
  518. */
  519. for (i = 0; i < req.total_num_uuars; i++) {
  520. uuarn = i & 3;
  521. if (uuarn == 2 || uuarn == 3)
  522. set_bit(i, uuari->bitmap);
  523. }
  524. uuari->count = kcalloc(req.total_num_uuars, sizeof(*uuari->count), GFP_KERNEL);
  525. if (!uuari->count) {
  526. err = -ENOMEM;
  527. goto out_bitmap;
  528. }
  529. for (i = 0; i < num_uars; i++) {
  530. err = mlx5_cmd_alloc_uar(&dev->mdev, &uars[i].index);
  531. if (err)
  532. goto out_count;
  533. }
  534. INIT_LIST_HEAD(&context->db_page_list);
  535. mutex_init(&context->db_page_mutex);
  536. resp.tot_uuars = req.total_num_uuars;
  537. resp.num_ports = dev->mdev.caps.num_ports;
  538. err = ib_copy_to_udata(udata, &resp,
  539. sizeof(resp) - sizeof(resp.reserved));
  540. if (err)
  541. goto out_uars;
  542. uuari->num_low_latency_uuars = req.num_low_latency_uuars;
  543. uuari->uars = uars;
  544. uuari->num_uars = num_uars;
  545. return &context->ibucontext;
  546. out_uars:
  547. for (i--; i >= 0; i--)
  548. mlx5_cmd_free_uar(&dev->mdev, uars[i].index);
  549. out_count:
  550. kfree(uuari->count);
  551. out_bitmap:
  552. kfree(uuari->bitmap);
  553. out_uar_ctx:
  554. kfree(uars);
  555. out_ctx:
  556. kfree(context);
  557. return ERR_PTR(err);
  558. }
  559. static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  560. {
  561. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  562. struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
  563. struct mlx5_uuar_info *uuari = &context->uuari;
  564. int i;
  565. for (i = 0; i < uuari->num_uars; i++) {
  566. if (mlx5_cmd_free_uar(&dev->mdev, uuari->uars[i].index))
  567. mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
  568. }
  569. kfree(uuari->count);
  570. kfree(uuari->bitmap);
  571. kfree(uuari->uars);
  572. kfree(context);
  573. return 0;
  574. }
  575. static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
  576. {
  577. return (pci_resource_start(dev->mdev.pdev, 0) >> PAGE_SHIFT) + index;
  578. }
  579. static int get_command(unsigned long offset)
  580. {
  581. return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
  582. }
  583. static int get_arg(unsigned long offset)
  584. {
  585. return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
  586. }
  587. static int get_index(unsigned long offset)
  588. {
  589. return get_arg(offset);
  590. }
  591. static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
  592. {
  593. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  594. struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
  595. struct mlx5_uuar_info *uuari = &context->uuari;
  596. unsigned long command;
  597. unsigned long idx;
  598. phys_addr_t pfn;
  599. command = get_command(vma->vm_pgoff);
  600. switch (command) {
  601. case MLX5_IB_MMAP_REGULAR_PAGE:
  602. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  603. return -EINVAL;
  604. idx = get_index(vma->vm_pgoff);
  605. pfn = uar_index2pfn(dev, uuari->uars[idx].index);
  606. mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
  607. (unsigned long long)pfn);
  608. if (idx >= uuari->num_uars)
  609. return -EINVAL;
  610. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  611. if (io_remap_pfn_range(vma, vma->vm_start, pfn,
  612. PAGE_SIZE, vma->vm_page_prot))
  613. return -EAGAIN;
  614. mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
  615. vma->vm_start,
  616. (unsigned long long)pfn << PAGE_SHIFT);
  617. break;
  618. case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
  619. return -ENOSYS;
  620. default:
  621. return -EINVAL;
  622. }
  623. return 0;
  624. }
  625. static int alloc_pa_mkey(struct mlx5_ib_dev *dev, u32 *key, u32 pdn)
  626. {
  627. struct mlx5_create_mkey_mbox_in *in;
  628. struct mlx5_mkey_seg *seg;
  629. struct mlx5_core_mr mr;
  630. int err;
  631. in = kzalloc(sizeof(*in), GFP_KERNEL);
  632. if (!in)
  633. return -ENOMEM;
  634. seg = &in->seg;
  635. seg->flags = MLX5_PERM_LOCAL_READ | MLX5_ACCESS_MODE_PA;
  636. seg->flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
  637. seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  638. seg->start_addr = 0;
  639. err = mlx5_core_create_mkey(&dev->mdev, &mr, in, sizeof(*in),
  640. NULL, NULL, NULL);
  641. if (err) {
  642. mlx5_ib_warn(dev, "failed to create mkey, %d\n", err);
  643. goto err_in;
  644. }
  645. kfree(in);
  646. *key = mr.key;
  647. return 0;
  648. err_in:
  649. kfree(in);
  650. return err;
  651. }
  652. static void free_pa_mkey(struct mlx5_ib_dev *dev, u32 key)
  653. {
  654. struct mlx5_core_mr mr;
  655. int err;
  656. memset(&mr, 0, sizeof(mr));
  657. mr.key = key;
  658. err = mlx5_core_destroy_mkey(&dev->mdev, &mr);
  659. if (err)
  660. mlx5_ib_warn(dev, "failed to destroy mkey 0x%x\n", key);
  661. }
  662. static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
  663. struct ib_ucontext *context,
  664. struct ib_udata *udata)
  665. {
  666. struct mlx5_ib_alloc_pd_resp resp;
  667. struct mlx5_ib_pd *pd;
  668. int err;
  669. pd = kmalloc(sizeof(*pd), GFP_KERNEL);
  670. if (!pd)
  671. return ERR_PTR(-ENOMEM);
  672. err = mlx5_core_alloc_pd(&to_mdev(ibdev)->mdev, &pd->pdn);
  673. if (err) {
  674. kfree(pd);
  675. return ERR_PTR(err);
  676. }
  677. if (context) {
  678. resp.pdn = pd->pdn;
  679. if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
  680. mlx5_core_dealloc_pd(&to_mdev(ibdev)->mdev, pd->pdn);
  681. kfree(pd);
  682. return ERR_PTR(-EFAULT);
  683. }
  684. } else {
  685. err = alloc_pa_mkey(to_mdev(ibdev), &pd->pa_lkey, pd->pdn);
  686. if (err) {
  687. mlx5_core_dealloc_pd(&to_mdev(ibdev)->mdev, pd->pdn);
  688. kfree(pd);
  689. return ERR_PTR(err);
  690. }
  691. }
  692. return &pd->ibpd;
  693. }
  694. static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
  695. {
  696. struct mlx5_ib_dev *mdev = to_mdev(pd->device);
  697. struct mlx5_ib_pd *mpd = to_mpd(pd);
  698. if (!pd->uobject)
  699. free_pa_mkey(mdev, mpd->pa_lkey);
  700. mlx5_core_dealloc_pd(&mdev->mdev, mpd->pdn);
  701. kfree(mpd);
  702. return 0;
  703. }
  704. static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  705. {
  706. struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
  707. int err;
  708. err = mlx5_core_attach_mcg(&dev->mdev, gid, ibqp->qp_num);
  709. if (err)
  710. mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
  711. ibqp->qp_num, gid->raw);
  712. return err;
  713. }
  714. static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  715. {
  716. struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
  717. int err;
  718. err = mlx5_core_detach_mcg(&dev->mdev, gid, ibqp->qp_num);
  719. if (err)
  720. mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
  721. ibqp->qp_num, gid->raw);
  722. return err;
  723. }
  724. static int init_node_data(struct mlx5_ib_dev *dev)
  725. {
  726. struct ib_smp *in_mad = NULL;
  727. struct ib_smp *out_mad = NULL;
  728. int err = -ENOMEM;
  729. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  730. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  731. if (!in_mad || !out_mad)
  732. goto out;
  733. init_query_mad(in_mad);
  734. in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
  735. err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
  736. if (err)
  737. goto out;
  738. memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
  739. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  740. err = mlx5_MAD_IFC(dev, 1, 1, 1, NULL, NULL, in_mad, out_mad);
  741. if (err)
  742. goto out;
  743. dev->mdev.rev_id = be32_to_cpup((__be32 *)(out_mad->data + 32));
  744. memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
  745. out:
  746. kfree(in_mad);
  747. kfree(out_mad);
  748. return err;
  749. }
  750. static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
  751. char *buf)
  752. {
  753. struct mlx5_ib_dev *dev =
  754. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  755. return sprintf(buf, "%d\n", dev->mdev.priv.fw_pages);
  756. }
  757. static ssize_t show_reg_pages(struct device *device,
  758. struct device_attribute *attr, char *buf)
  759. {
  760. struct mlx5_ib_dev *dev =
  761. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  762. return sprintf(buf, "%d\n", dev->mdev.priv.reg_pages);
  763. }
  764. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  765. char *buf)
  766. {
  767. struct mlx5_ib_dev *dev =
  768. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  769. return sprintf(buf, "MT%d\n", dev->mdev.pdev->device);
  770. }
  771. static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
  772. char *buf)
  773. {
  774. struct mlx5_ib_dev *dev =
  775. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  776. return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(&dev->mdev),
  777. fw_rev_min(&dev->mdev), fw_rev_sub(&dev->mdev));
  778. }
  779. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  780. char *buf)
  781. {
  782. struct mlx5_ib_dev *dev =
  783. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  784. return sprintf(buf, "%x\n", dev->mdev.rev_id);
  785. }
  786. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  787. char *buf)
  788. {
  789. struct mlx5_ib_dev *dev =
  790. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  791. return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
  792. dev->mdev.board_id);
  793. }
  794. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  795. static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
  796. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  797. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  798. static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
  799. static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
  800. static struct device_attribute *mlx5_class_attributes[] = {
  801. &dev_attr_hw_rev,
  802. &dev_attr_fw_ver,
  803. &dev_attr_hca_type,
  804. &dev_attr_board_id,
  805. &dev_attr_fw_pages,
  806. &dev_attr_reg_pages,
  807. };
  808. static void mlx5_ib_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
  809. void *data)
  810. {
  811. struct mlx5_ib_dev *ibdev = container_of(dev, struct mlx5_ib_dev, mdev);
  812. struct ib_event ibev;
  813. u8 port = 0;
  814. switch (event) {
  815. case MLX5_DEV_EVENT_SYS_ERROR:
  816. ibdev->ib_active = false;
  817. ibev.event = IB_EVENT_DEVICE_FATAL;
  818. break;
  819. case MLX5_DEV_EVENT_PORT_UP:
  820. ibev.event = IB_EVENT_PORT_ACTIVE;
  821. port = *(u8 *)data;
  822. break;
  823. case MLX5_DEV_EVENT_PORT_DOWN:
  824. ibev.event = IB_EVENT_PORT_ERR;
  825. port = *(u8 *)data;
  826. break;
  827. case MLX5_DEV_EVENT_PORT_INITIALIZED:
  828. /* not used by ULPs */
  829. return;
  830. case MLX5_DEV_EVENT_LID_CHANGE:
  831. ibev.event = IB_EVENT_LID_CHANGE;
  832. port = *(u8 *)data;
  833. break;
  834. case MLX5_DEV_EVENT_PKEY_CHANGE:
  835. ibev.event = IB_EVENT_PKEY_CHANGE;
  836. port = *(u8 *)data;
  837. break;
  838. case MLX5_DEV_EVENT_GUID_CHANGE:
  839. ibev.event = IB_EVENT_GID_CHANGE;
  840. port = *(u8 *)data;
  841. break;
  842. case MLX5_DEV_EVENT_CLIENT_REREG:
  843. ibev.event = IB_EVENT_CLIENT_REREGISTER;
  844. port = *(u8 *)data;
  845. break;
  846. }
  847. ibev.device = &ibdev->ib_dev;
  848. ibev.element.port_num = port;
  849. if (port < 1 || port > ibdev->num_ports) {
  850. mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
  851. return;
  852. }
  853. if (ibdev->ib_active)
  854. ib_dispatch_event(&ibev);
  855. }
  856. static void get_ext_port_caps(struct mlx5_ib_dev *dev)
  857. {
  858. int port;
  859. for (port = 1; port <= dev->mdev.caps.num_ports; port++)
  860. mlx5_query_ext_port_caps(dev, port);
  861. }
  862. static int get_port_caps(struct mlx5_ib_dev *dev)
  863. {
  864. struct ib_device_attr *dprops = NULL;
  865. struct ib_port_attr *pprops = NULL;
  866. int err = 0;
  867. int port;
  868. pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
  869. if (!pprops)
  870. goto out;
  871. dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
  872. if (!dprops)
  873. goto out;
  874. err = mlx5_ib_query_device(&dev->ib_dev, dprops);
  875. if (err) {
  876. mlx5_ib_warn(dev, "query_device failed %d\n", err);
  877. goto out;
  878. }
  879. for (port = 1; port <= dev->mdev.caps.num_ports; port++) {
  880. err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
  881. if (err) {
  882. mlx5_ib_warn(dev, "query_port %d failed %d\n", port, err);
  883. break;
  884. }
  885. dev->mdev.caps.port[port - 1].pkey_table_len = dprops->max_pkeys;
  886. dev->mdev.caps.port[port - 1].gid_table_len = pprops->gid_tbl_len;
  887. mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
  888. dprops->max_pkeys, pprops->gid_tbl_len);
  889. }
  890. out:
  891. kfree(pprops);
  892. kfree(dprops);
  893. return err;
  894. }
  895. static void destroy_umrc_res(struct mlx5_ib_dev *dev)
  896. {
  897. int err;
  898. err = mlx5_mr_cache_cleanup(dev);
  899. if (err)
  900. mlx5_ib_warn(dev, "mr cache cleanup failed\n");
  901. mlx5_ib_destroy_qp(dev->umrc.qp);
  902. ib_destroy_cq(dev->umrc.cq);
  903. ib_dereg_mr(dev->umrc.mr);
  904. ib_dealloc_pd(dev->umrc.pd);
  905. }
  906. enum {
  907. MAX_UMR_WR = 128,
  908. };
  909. static int create_umr_res(struct mlx5_ib_dev *dev)
  910. {
  911. struct ib_qp_init_attr *init_attr = NULL;
  912. struct ib_qp_attr *attr = NULL;
  913. struct ib_pd *pd;
  914. struct ib_cq *cq;
  915. struct ib_qp *qp;
  916. struct ib_mr *mr;
  917. int ret;
  918. attr = kzalloc(sizeof(*attr), GFP_KERNEL);
  919. init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
  920. if (!attr || !init_attr) {
  921. ret = -ENOMEM;
  922. goto error_0;
  923. }
  924. pd = ib_alloc_pd(&dev->ib_dev);
  925. if (IS_ERR(pd)) {
  926. mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
  927. ret = PTR_ERR(pd);
  928. goto error_0;
  929. }
  930. mr = ib_get_dma_mr(pd, IB_ACCESS_LOCAL_WRITE);
  931. if (IS_ERR(mr)) {
  932. mlx5_ib_dbg(dev, "Couldn't create DMA MR for sync UMR QP\n");
  933. ret = PTR_ERR(mr);
  934. goto error_1;
  935. }
  936. cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL, 128,
  937. 0);
  938. if (IS_ERR(cq)) {
  939. mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
  940. ret = PTR_ERR(cq);
  941. goto error_2;
  942. }
  943. ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
  944. init_attr->send_cq = cq;
  945. init_attr->recv_cq = cq;
  946. init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
  947. init_attr->cap.max_send_wr = MAX_UMR_WR;
  948. init_attr->cap.max_send_sge = 1;
  949. init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
  950. init_attr->port_num = 1;
  951. qp = mlx5_ib_create_qp(pd, init_attr, NULL);
  952. if (IS_ERR(qp)) {
  953. mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
  954. ret = PTR_ERR(qp);
  955. goto error_3;
  956. }
  957. qp->device = &dev->ib_dev;
  958. qp->real_qp = qp;
  959. qp->uobject = NULL;
  960. qp->qp_type = MLX5_IB_QPT_REG_UMR;
  961. attr->qp_state = IB_QPS_INIT;
  962. attr->port_num = 1;
  963. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
  964. IB_QP_PORT, NULL);
  965. if (ret) {
  966. mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
  967. goto error_4;
  968. }
  969. memset(attr, 0, sizeof(*attr));
  970. attr->qp_state = IB_QPS_RTR;
  971. attr->path_mtu = IB_MTU_256;
  972. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
  973. if (ret) {
  974. mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
  975. goto error_4;
  976. }
  977. memset(attr, 0, sizeof(*attr));
  978. attr->qp_state = IB_QPS_RTS;
  979. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
  980. if (ret) {
  981. mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
  982. goto error_4;
  983. }
  984. dev->umrc.qp = qp;
  985. dev->umrc.cq = cq;
  986. dev->umrc.mr = mr;
  987. dev->umrc.pd = pd;
  988. sema_init(&dev->umrc.sem, MAX_UMR_WR);
  989. ret = mlx5_mr_cache_init(dev);
  990. if (ret) {
  991. mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
  992. goto error_4;
  993. }
  994. kfree(attr);
  995. kfree(init_attr);
  996. return 0;
  997. error_4:
  998. mlx5_ib_destroy_qp(qp);
  999. error_3:
  1000. ib_destroy_cq(cq);
  1001. error_2:
  1002. ib_dereg_mr(mr);
  1003. error_1:
  1004. ib_dealloc_pd(pd);
  1005. error_0:
  1006. kfree(attr);
  1007. kfree(init_attr);
  1008. return ret;
  1009. }
  1010. static int create_dev_resources(struct mlx5_ib_resources *devr)
  1011. {
  1012. struct ib_srq_init_attr attr;
  1013. struct mlx5_ib_dev *dev;
  1014. int ret = 0;
  1015. dev = container_of(devr, struct mlx5_ib_dev, devr);
  1016. devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
  1017. if (IS_ERR(devr->p0)) {
  1018. ret = PTR_ERR(devr->p0);
  1019. goto error0;
  1020. }
  1021. devr->p0->device = &dev->ib_dev;
  1022. devr->p0->uobject = NULL;
  1023. atomic_set(&devr->p0->usecnt, 0);
  1024. devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, 1, 0, NULL, NULL);
  1025. if (IS_ERR(devr->c0)) {
  1026. ret = PTR_ERR(devr->c0);
  1027. goto error1;
  1028. }
  1029. devr->c0->device = &dev->ib_dev;
  1030. devr->c0->uobject = NULL;
  1031. devr->c0->comp_handler = NULL;
  1032. devr->c0->event_handler = NULL;
  1033. devr->c0->cq_context = NULL;
  1034. atomic_set(&devr->c0->usecnt, 0);
  1035. devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
  1036. if (IS_ERR(devr->x0)) {
  1037. ret = PTR_ERR(devr->x0);
  1038. goto error2;
  1039. }
  1040. devr->x0->device = &dev->ib_dev;
  1041. devr->x0->inode = NULL;
  1042. atomic_set(&devr->x0->usecnt, 0);
  1043. mutex_init(&devr->x0->tgt_qp_mutex);
  1044. INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
  1045. devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
  1046. if (IS_ERR(devr->x1)) {
  1047. ret = PTR_ERR(devr->x1);
  1048. goto error3;
  1049. }
  1050. devr->x1->device = &dev->ib_dev;
  1051. devr->x1->inode = NULL;
  1052. atomic_set(&devr->x1->usecnt, 0);
  1053. mutex_init(&devr->x1->tgt_qp_mutex);
  1054. INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
  1055. memset(&attr, 0, sizeof(attr));
  1056. attr.attr.max_sge = 1;
  1057. attr.attr.max_wr = 1;
  1058. attr.srq_type = IB_SRQT_XRC;
  1059. attr.ext.xrc.cq = devr->c0;
  1060. attr.ext.xrc.xrcd = devr->x0;
  1061. devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
  1062. if (IS_ERR(devr->s0)) {
  1063. ret = PTR_ERR(devr->s0);
  1064. goto error4;
  1065. }
  1066. devr->s0->device = &dev->ib_dev;
  1067. devr->s0->pd = devr->p0;
  1068. devr->s0->uobject = NULL;
  1069. devr->s0->event_handler = NULL;
  1070. devr->s0->srq_context = NULL;
  1071. devr->s0->srq_type = IB_SRQT_XRC;
  1072. devr->s0->ext.xrc.xrcd = devr->x0;
  1073. devr->s0->ext.xrc.cq = devr->c0;
  1074. atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
  1075. atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
  1076. atomic_inc(&devr->p0->usecnt);
  1077. atomic_set(&devr->s0->usecnt, 0);
  1078. return 0;
  1079. error4:
  1080. mlx5_ib_dealloc_xrcd(devr->x1);
  1081. error3:
  1082. mlx5_ib_dealloc_xrcd(devr->x0);
  1083. error2:
  1084. mlx5_ib_destroy_cq(devr->c0);
  1085. error1:
  1086. mlx5_ib_dealloc_pd(devr->p0);
  1087. error0:
  1088. return ret;
  1089. }
  1090. static void destroy_dev_resources(struct mlx5_ib_resources *devr)
  1091. {
  1092. mlx5_ib_destroy_srq(devr->s0);
  1093. mlx5_ib_dealloc_xrcd(devr->x0);
  1094. mlx5_ib_dealloc_xrcd(devr->x1);
  1095. mlx5_ib_destroy_cq(devr->c0);
  1096. mlx5_ib_dealloc_pd(devr->p0);
  1097. }
  1098. static int init_one(struct pci_dev *pdev,
  1099. const struct pci_device_id *id)
  1100. {
  1101. struct mlx5_core_dev *mdev;
  1102. struct mlx5_ib_dev *dev;
  1103. int err;
  1104. int i;
  1105. printk_once(KERN_INFO "%s", mlx5_version);
  1106. dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
  1107. if (!dev)
  1108. return -ENOMEM;
  1109. mdev = &dev->mdev;
  1110. mdev->event = mlx5_ib_event;
  1111. if (prof_sel >= ARRAY_SIZE(profile)) {
  1112. pr_warn("selected pofile out of range, selceting default\n");
  1113. prof_sel = 0;
  1114. }
  1115. mdev->profile = &profile[prof_sel];
  1116. err = mlx5_dev_init(mdev, pdev);
  1117. if (err)
  1118. goto err_free;
  1119. err = get_port_caps(dev);
  1120. if (err)
  1121. goto err_cleanup;
  1122. get_ext_port_caps(dev);
  1123. err = alloc_comp_eqs(dev);
  1124. if (err)
  1125. goto err_cleanup;
  1126. MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
  1127. strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
  1128. dev->ib_dev.owner = THIS_MODULE;
  1129. dev->ib_dev.node_type = RDMA_NODE_IB_CA;
  1130. dev->ib_dev.local_dma_lkey = mdev->caps.reserved_lkey;
  1131. dev->num_ports = mdev->caps.num_ports;
  1132. dev->ib_dev.phys_port_cnt = dev->num_ports;
  1133. dev->ib_dev.num_comp_vectors = dev->num_comp_vectors;
  1134. dev->ib_dev.dma_device = &mdev->pdev->dev;
  1135. dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
  1136. dev->ib_dev.uverbs_cmd_mask =
  1137. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  1138. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  1139. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  1140. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  1141. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  1142. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  1143. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  1144. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  1145. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  1146. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  1147. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  1148. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  1149. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  1150. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  1151. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  1152. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  1153. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  1154. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  1155. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  1156. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  1157. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  1158. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  1159. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  1160. dev->ib_dev.query_device = mlx5_ib_query_device;
  1161. dev->ib_dev.query_port = mlx5_ib_query_port;
  1162. dev->ib_dev.query_gid = mlx5_ib_query_gid;
  1163. dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
  1164. dev->ib_dev.modify_device = mlx5_ib_modify_device;
  1165. dev->ib_dev.modify_port = mlx5_ib_modify_port;
  1166. dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
  1167. dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
  1168. dev->ib_dev.mmap = mlx5_ib_mmap;
  1169. dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
  1170. dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
  1171. dev->ib_dev.create_ah = mlx5_ib_create_ah;
  1172. dev->ib_dev.query_ah = mlx5_ib_query_ah;
  1173. dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
  1174. dev->ib_dev.create_srq = mlx5_ib_create_srq;
  1175. dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
  1176. dev->ib_dev.query_srq = mlx5_ib_query_srq;
  1177. dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
  1178. dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
  1179. dev->ib_dev.create_qp = mlx5_ib_create_qp;
  1180. dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
  1181. dev->ib_dev.query_qp = mlx5_ib_query_qp;
  1182. dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
  1183. dev->ib_dev.post_send = mlx5_ib_post_send;
  1184. dev->ib_dev.post_recv = mlx5_ib_post_recv;
  1185. dev->ib_dev.create_cq = mlx5_ib_create_cq;
  1186. dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
  1187. dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
  1188. dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
  1189. dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
  1190. dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
  1191. dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
  1192. dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
  1193. dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
  1194. dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
  1195. dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
  1196. dev->ib_dev.process_mad = mlx5_ib_process_mad;
  1197. dev->ib_dev.alloc_fast_reg_mr = mlx5_ib_alloc_fast_reg_mr;
  1198. dev->ib_dev.alloc_fast_reg_page_list = mlx5_ib_alloc_fast_reg_page_list;
  1199. dev->ib_dev.free_fast_reg_page_list = mlx5_ib_free_fast_reg_page_list;
  1200. if (mdev->caps.flags & MLX5_DEV_CAP_FLAG_XRC) {
  1201. dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
  1202. dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
  1203. dev->ib_dev.uverbs_cmd_mask |=
  1204. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  1205. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  1206. }
  1207. err = init_node_data(dev);
  1208. if (err)
  1209. goto err_eqs;
  1210. mutex_init(&dev->cap_mask_mutex);
  1211. spin_lock_init(&dev->mr_lock);
  1212. err = create_dev_resources(&dev->devr);
  1213. if (err)
  1214. goto err_eqs;
  1215. err = ib_register_device(&dev->ib_dev, NULL);
  1216. if (err)
  1217. goto err_rsrc;
  1218. err = create_umr_res(dev);
  1219. if (err)
  1220. goto err_dev;
  1221. for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
  1222. err = device_create_file(&dev->ib_dev.dev,
  1223. mlx5_class_attributes[i]);
  1224. if (err)
  1225. goto err_umrc;
  1226. }
  1227. dev->ib_active = true;
  1228. return 0;
  1229. err_umrc:
  1230. destroy_umrc_res(dev);
  1231. err_dev:
  1232. ib_unregister_device(&dev->ib_dev);
  1233. err_rsrc:
  1234. destroy_dev_resources(&dev->devr);
  1235. err_eqs:
  1236. free_comp_eqs(dev);
  1237. err_cleanup:
  1238. mlx5_dev_cleanup(mdev);
  1239. err_free:
  1240. ib_dealloc_device((struct ib_device *)dev);
  1241. return err;
  1242. }
  1243. static void remove_one(struct pci_dev *pdev)
  1244. {
  1245. struct mlx5_ib_dev *dev = mlx5_pci2ibdev(pdev);
  1246. destroy_umrc_res(dev);
  1247. ib_unregister_device(&dev->ib_dev);
  1248. destroy_dev_resources(&dev->devr);
  1249. free_comp_eqs(dev);
  1250. mlx5_dev_cleanup(&dev->mdev);
  1251. ib_dealloc_device(&dev->ib_dev);
  1252. }
  1253. static DEFINE_PCI_DEVICE_TABLE(mlx5_ib_pci_table) = {
  1254. { PCI_VDEVICE(MELLANOX, 4113) }, /* MT4113 Connect-IB */
  1255. { 0, }
  1256. };
  1257. MODULE_DEVICE_TABLE(pci, mlx5_ib_pci_table);
  1258. static struct pci_driver mlx5_ib_driver = {
  1259. .name = DRIVER_NAME,
  1260. .id_table = mlx5_ib_pci_table,
  1261. .probe = init_one,
  1262. .remove = remove_one
  1263. };
  1264. static int __init mlx5_ib_init(void)
  1265. {
  1266. return pci_register_driver(&mlx5_ib_driver);
  1267. }
  1268. static void __exit mlx5_ib_cleanup(void)
  1269. {
  1270. pci_unregister_driver(&mlx5_ib_driver);
  1271. }
  1272. module_init(mlx5_ib_init);
  1273. module_exit(mlx5_ib_cleanup);