intc-simr.c 2.0 KB

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  1. /*
  2. * intc-simr.c
  3. *
  4. * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
  5. *
  6. * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file COPYING in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/types.h>
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/irq.h>
  17. #include <linux/io.h>
  18. #include <asm/coldfire.h>
  19. #include <asm/mcfsim.h>
  20. #include <asm/traps.h>
  21. /*
  22. * There maybe one or two interrupt control units, each has 64
  23. * interrupts. If there is no second unit then MCFINTC1_* defines
  24. * will be 0 (and code for them optimized away).
  25. */
  26. static void intc_irq_mask(struct irq_data *d)
  27. {
  28. unsigned int irq = d->irq - MCFINT_VECBASE;
  29. if (MCFINTC1_SIMR && (irq > 64))
  30. __raw_writeb(irq - 64, MCFINTC1_SIMR);
  31. else
  32. __raw_writeb(irq, MCFINTC0_SIMR);
  33. }
  34. static void intc_irq_unmask(struct irq_data *d)
  35. {
  36. unsigned int irq = d->irq - MCFINT_VECBASE;
  37. if (MCFINTC1_CIMR && (irq > 64))
  38. __raw_writeb(irq - 64, MCFINTC1_CIMR);
  39. else
  40. __raw_writeb(irq, MCFINTC0_CIMR);
  41. }
  42. static int intc_irq_set_type(struct irq_data *d, unsigned int type)
  43. {
  44. unsigned int irq = d->irq - MCFINT_VECBASE;
  45. if (MCFINTC1_ICR0 && (irq > 64))
  46. __raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
  47. else
  48. __raw_writeb(5, MCFINTC0_ICR0 + irq);
  49. return 0;
  50. }
  51. static struct irq_chip intc_irq_chip = {
  52. .name = "CF-INTC",
  53. .irq_mask = intc_irq_mask,
  54. .irq_unmask = intc_irq_unmask,
  55. .irq_set_type = intc_irq_set_type,
  56. };
  57. void __init init_IRQ(void)
  58. {
  59. int irq, eirq;
  60. init_vectors();
  61. /* Mask all interrupt sources */
  62. __raw_writeb(0xff, MCFINTC0_SIMR);
  63. if (MCFINTC1_SIMR)
  64. __raw_writeb(0xff, MCFINTC1_SIMR);
  65. eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
  66. for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
  67. set_irq_chip(irq, &intc_irq_chip);
  68. set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
  69. set_irq_handler(irq, handle_level_irq);
  70. }
  71. }