r8a7740.dtsi 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138
  1. /*
  2. * Device Tree Source for the r8a7740 SoC
  3. *
  4. * Copyright (C) 2012 Renesas Solutions Corp.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "renesas,r8a7740";
  13. cpus {
  14. cpu@0 {
  15. compatible = "arm,cortex-a9";
  16. };
  17. };
  18. gic: interrupt-controller@c2800000 {
  19. compatible = "arm,cortex-a9-gic";
  20. #interrupt-cells = <3>;
  21. #address-cells = <1>;
  22. interrupt-controller;
  23. reg = <0xc2800000 0x1000>,
  24. <0xc2000000 0x1000>;
  25. };
  26. /* irqpin0: IRQ0 - IRQ7 */
  27. irqpin0: irqpin@e6900000 {
  28. compatible = "renesas,intc-irqpin";
  29. #interrupt-cells = <2>;
  30. interrupt-controller;
  31. reg = <0xe6900000 4>,
  32. <0xe6900010 4>,
  33. <0xe6900020 1>,
  34. <0xe6900040 1>,
  35. <0xe6900060 1>;
  36. interrupt-parent = <&gic>;
  37. interrupts = <0 149 0x4
  38. 0 149 0x4
  39. 0 149 0x4
  40. 0 149 0x4
  41. 0 149 0x4
  42. 0 149 0x4
  43. 0 149 0x4
  44. 0 149 0x4>;
  45. };
  46. /* irqpin1: IRQ8 - IRQ15 */
  47. irqpin1: irqpin@e6900004 {
  48. compatible = "renesas,intc-irqpin";
  49. #interrupt-cells = <2>;
  50. interrupt-controller;
  51. reg = <0xe6900004 4>,
  52. <0xe6900014 4>,
  53. <0xe6900024 1>,
  54. <0xe6900044 1>,
  55. <0xe6900064 1>;
  56. interrupt-parent = <&gic>;
  57. interrupts = <0 149 0x4
  58. 0 149 0x4
  59. 0 149 0x4
  60. 0 149 0x4
  61. 0 149 0x4
  62. 0 149 0x4
  63. 0 149 0x4
  64. 0 149 0x4>;
  65. };
  66. /* irqpin2: IRQ16 - IRQ23 */
  67. irqpin2: irqpin@e6900008 {
  68. compatible = "renesas,intc-irqpin";
  69. #interrupt-cells = <2>;
  70. interrupt-controller;
  71. reg = <0xe6900008 4>,
  72. <0xe6900018 4>,
  73. <0xe6900028 1>,
  74. <0xe6900048 1>,
  75. <0xe6900068 1>;
  76. interrupt-parent = <&gic>;
  77. interrupts = <0 149 0x4
  78. 0 149 0x4
  79. 0 149 0x4
  80. 0 149 0x4
  81. 0 149 0x4
  82. 0 149 0x4
  83. 0 149 0x4
  84. 0 149 0x4>;
  85. };
  86. /* irqpin3: IRQ24 - IRQ31 */
  87. irqpin3: irqpin@e690000c {
  88. compatible = "renesas,intc-irqpin";
  89. #interrupt-cells = <2>;
  90. interrupt-controller;
  91. reg = <0xe690000c 4>,
  92. <0xe690001c 4>,
  93. <0xe690002c 1>,
  94. <0xe690004c 1>,
  95. <0xe690006c 1>;
  96. interrupt-parent = <&gic>;
  97. interrupts = <0 149 0x4
  98. 0 149 0x4
  99. 0 149 0x4
  100. 0 149 0x4
  101. 0 149 0x4
  102. 0 149 0x4
  103. 0 149 0x4
  104. 0 149 0x4>;
  105. };
  106. i2c0: i2c@fff20000 {
  107. #address-cells = <1>;
  108. #size-cells = <0>;
  109. compatible = "renesas,rmobile-iic";
  110. reg = <0xfff20000 0x425>;
  111. interrupt-parent = <&gic>;
  112. interrupts = <0 201 0x4
  113. 0 202 0x4
  114. 0 203 0x4
  115. 0 204 0x4>;
  116. };
  117. i2c1: i2c@e6c20000 {
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. compatible = "renesas,rmobile-iic";
  121. reg = <0xe6c20000 0x425>;
  122. interrupt-parent = <&gic>;
  123. interrupts = <0 70 0x4
  124. 0 71 0x4
  125. 0 72 0x4
  126. 0 73 0x4>;
  127. };
  128. };