emufx.c 98 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Creative Labs, Inc.
  4. * Routines for effect processor FX8010
  5. *
  6. * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
  7. * Added EMU 1010 support.
  8. *
  9. * BUGS:
  10. * --
  11. *
  12. * TODO:
  13. * --
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  28. *
  29. */
  30. #include <sound/driver.h>
  31. #include <linux/pci.h>
  32. #include <linux/capability.h>
  33. #include <linux/delay.h>
  34. #include <linux/slab.h>
  35. #include <linux/vmalloc.h>
  36. #include <linux/init.h>
  37. #include <linux/mutex.h>
  38. #include <sound/core.h>
  39. #include <sound/tlv.h>
  40. #include <sound/emu10k1.h>
  41. #if 0 /* for testing purposes - digital out -> capture */
  42. #define EMU10K1_CAPTURE_DIGITAL_OUT
  43. #endif
  44. #if 0 /* for testing purposes - set S/PDIF to AC3 output */
  45. #define EMU10K1_SET_AC3_IEC958
  46. #endif
  47. #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
  48. #define EMU10K1_CENTER_LFE_FROM_FRONT
  49. #endif
  50. /*
  51. * Tables
  52. */
  53. static char *fxbuses[16] = {
  54. /* 0x00 */ "PCM Left",
  55. /* 0x01 */ "PCM Right",
  56. /* 0x02 */ "PCM Surround Left",
  57. /* 0x03 */ "PCM Surround Right",
  58. /* 0x04 */ "MIDI Left",
  59. /* 0x05 */ "MIDI Right",
  60. /* 0x06 */ "Center",
  61. /* 0x07 */ "LFE",
  62. /* 0x08 */ NULL,
  63. /* 0x09 */ NULL,
  64. /* 0x0a */ NULL,
  65. /* 0x0b */ NULL,
  66. /* 0x0c */ "MIDI Reverb",
  67. /* 0x0d */ "MIDI Chorus",
  68. /* 0x0e */ NULL,
  69. /* 0x0f */ NULL
  70. };
  71. static char *creative_ins[16] = {
  72. /* 0x00 */ "AC97 Left",
  73. /* 0x01 */ "AC97 Right",
  74. /* 0x02 */ "TTL IEC958 Left",
  75. /* 0x03 */ "TTL IEC958 Right",
  76. /* 0x04 */ "Zoom Video Left",
  77. /* 0x05 */ "Zoom Video Right",
  78. /* 0x06 */ "Optical IEC958 Left",
  79. /* 0x07 */ "Optical IEC958 Right",
  80. /* 0x08 */ "Line/Mic 1 Left",
  81. /* 0x09 */ "Line/Mic 1 Right",
  82. /* 0x0a */ "Coaxial IEC958 Left",
  83. /* 0x0b */ "Coaxial IEC958 Right",
  84. /* 0x0c */ "Line/Mic 2 Left",
  85. /* 0x0d */ "Line/Mic 2 Right",
  86. /* 0x0e */ NULL,
  87. /* 0x0f */ NULL
  88. };
  89. static char *audigy_ins[16] = {
  90. /* 0x00 */ "AC97 Left",
  91. /* 0x01 */ "AC97 Right",
  92. /* 0x02 */ "Audigy CD Left",
  93. /* 0x03 */ "Audigy CD Right",
  94. /* 0x04 */ "Optical IEC958 Left",
  95. /* 0x05 */ "Optical IEC958 Right",
  96. /* 0x06 */ NULL,
  97. /* 0x07 */ NULL,
  98. /* 0x08 */ "Line/Mic 2 Left",
  99. /* 0x09 */ "Line/Mic 2 Right",
  100. /* 0x0a */ "SPDIF Left",
  101. /* 0x0b */ "SPDIF Right",
  102. /* 0x0c */ "Aux2 Left",
  103. /* 0x0d */ "Aux2 Right",
  104. /* 0x0e */ NULL,
  105. /* 0x0f */ NULL
  106. };
  107. static char *creative_outs[32] = {
  108. /* 0x00 */ "AC97 Left",
  109. /* 0x01 */ "AC97 Right",
  110. /* 0x02 */ "Optical IEC958 Left",
  111. /* 0x03 */ "Optical IEC958 Right",
  112. /* 0x04 */ "Center",
  113. /* 0x05 */ "LFE",
  114. /* 0x06 */ "Headphone Left",
  115. /* 0x07 */ "Headphone Right",
  116. /* 0x08 */ "Surround Left",
  117. /* 0x09 */ "Surround Right",
  118. /* 0x0a */ "PCM Capture Left",
  119. /* 0x0b */ "PCM Capture Right",
  120. /* 0x0c */ "MIC Capture",
  121. /* 0x0d */ "AC97 Surround Left",
  122. /* 0x0e */ "AC97 Surround Right",
  123. /* 0x0f */ NULL,
  124. /* 0x10 */ NULL,
  125. /* 0x11 */ "Analog Center",
  126. /* 0x12 */ "Analog LFE",
  127. /* 0x13 */ NULL,
  128. /* 0x14 */ NULL,
  129. /* 0x15 */ NULL,
  130. /* 0x16 */ NULL,
  131. /* 0x17 */ NULL,
  132. /* 0x18 */ NULL,
  133. /* 0x19 */ NULL,
  134. /* 0x1a */ NULL,
  135. /* 0x1b */ NULL,
  136. /* 0x1c */ NULL,
  137. /* 0x1d */ NULL,
  138. /* 0x1e */ NULL,
  139. /* 0x1f */ NULL,
  140. };
  141. static char *audigy_outs[32] = {
  142. /* 0x00 */ "Digital Front Left",
  143. /* 0x01 */ "Digital Front Right",
  144. /* 0x02 */ "Digital Center",
  145. /* 0x03 */ "Digital LEF",
  146. /* 0x04 */ "Headphone Left",
  147. /* 0x05 */ "Headphone Right",
  148. /* 0x06 */ "Digital Rear Left",
  149. /* 0x07 */ "Digital Rear Right",
  150. /* 0x08 */ "Front Left",
  151. /* 0x09 */ "Front Right",
  152. /* 0x0a */ "Center",
  153. /* 0x0b */ "LFE",
  154. /* 0x0c */ NULL,
  155. /* 0x0d */ NULL,
  156. /* 0x0e */ "Rear Left",
  157. /* 0x0f */ "Rear Right",
  158. /* 0x10 */ "AC97 Front Left",
  159. /* 0x11 */ "AC97 Front Right",
  160. /* 0x12 */ "ADC Caputre Left",
  161. /* 0x13 */ "ADC Capture Right",
  162. /* 0x14 */ NULL,
  163. /* 0x15 */ NULL,
  164. /* 0x16 */ NULL,
  165. /* 0x17 */ NULL,
  166. /* 0x18 */ NULL,
  167. /* 0x19 */ NULL,
  168. /* 0x1a */ NULL,
  169. /* 0x1b */ NULL,
  170. /* 0x1c */ NULL,
  171. /* 0x1d */ NULL,
  172. /* 0x1e */ NULL,
  173. /* 0x1f */ NULL,
  174. };
  175. static const u32 bass_table[41][5] = {
  176. { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
  177. { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
  178. { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
  179. { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
  180. { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
  181. { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
  182. { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
  183. { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
  184. { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
  185. { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
  186. { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
  187. { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
  188. { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
  189. { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
  190. { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
  191. { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
  192. { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
  193. { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
  194. { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
  195. { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
  196. { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
  197. { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
  198. { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
  199. { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
  200. { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
  201. { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
  202. { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
  203. { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
  204. { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
  205. { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
  206. { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
  207. { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
  208. { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
  209. { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
  210. { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
  211. { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
  212. { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
  213. { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
  214. { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
  215. { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
  216. { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
  217. };
  218. static const u32 treble_table[41][5] = {
  219. { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
  220. { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
  221. { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
  222. { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
  223. { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
  224. { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
  225. { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
  226. { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
  227. { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
  228. { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
  229. { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
  230. { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
  231. { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
  232. { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
  233. { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
  234. { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
  235. { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
  236. { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
  237. { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
  238. { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
  239. { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
  240. { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
  241. { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
  242. { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
  243. { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
  244. { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
  245. { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
  246. { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
  247. { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
  248. { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
  249. { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
  250. { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
  251. { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
  252. { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
  253. { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
  254. { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
  255. { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
  256. { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
  257. { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
  258. { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
  259. { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
  260. };
  261. /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
  262. static const u32 db_table[101] = {
  263. 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
  264. 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
  265. 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
  266. 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
  267. 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
  268. 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
  269. 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
  270. 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
  271. 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
  272. 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
  273. 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
  274. 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
  275. 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
  276. 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
  277. 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
  278. 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
  279. 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
  280. 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
  281. 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
  282. 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
  283. 0x7fffffff,
  284. };
  285. /* EMU10k1/EMU10k2 DSP control db gain */
  286. static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
  287. static const u32 onoff_table[2] = {
  288. 0x00000000, 0x00000001
  289. };
  290. /*
  291. */
  292. static inline mm_segment_t snd_enter_user(void)
  293. {
  294. mm_segment_t fs = get_fs();
  295. set_fs(get_ds());
  296. return fs;
  297. }
  298. static inline void snd_leave_user(mm_segment_t fs)
  299. {
  300. set_fs(fs);
  301. }
  302. /*
  303. * controls
  304. */
  305. static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  306. {
  307. struct snd_emu10k1_fx8010_ctl *ctl =
  308. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  309. if (ctl->min == 0 && ctl->max == 1)
  310. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  311. else
  312. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  313. uinfo->count = ctl->vcount;
  314. uinfo->value.integer.min = ctl->min;
  315. uinfo->value.integer.max = ctl->max;
  316. return 0;
  317. }
  318. static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  319. {
  320. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  321. struct snd_emu10k1_fx8010_ctl *ctl =
  322. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  323. unsigned long flags;
  324. unsigned int i;
  325. spin_lock_irqsave(&emu->reg_lock, flags);
  326. for (i = 0; i < ctl->vcount; i++)
  327. ucontrol->value.integer.value[i] = ctl->value[i];
  328. spin_unlock_irqrestore(&emu->reg_lock, flags);
  329. return 0;
  330. }
  331. static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  332. {
  333. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  334. struct snd_emu10k1_fx8010_ctl *ctl =
  335. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  336. unsigned long flags;
  337. unsigned int nval, val;
  338. unsigned int i, j;
  339. int change = 0;
  340. spin_lock_irqsave(&emu->reg_lock, flags);
  341. for (i = 0; i < ctl->vcount; i++) {
  342. nval = ucontrol->value.integer.value[i];
  343. if (nval < ctl->min)
  344. nval = ctl->min;
  345. if (nval > ctl->max)
  346. nval = ctl->max;
  347. if (nval != ctl->value[i])
  348. change = 1;
  349. val = ctl->value[i] = nval;
  350. switch (ctl->translation) {
  351. case EMU10K1_GPR_TRANSLATION_NONE:
  352. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
  353. break;
  354. case EMU10K1_GPR_TRANSLATION_TABLE100:
  355. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
  356. break;
  357. case EMU10K1_GPR_TRANSLATION_BASS:
  358. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  359. change = -EIO;
  360. goto __error;
  361. }
  362. for (j = 0; j < 5; j++)
  363. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
  364. break;
  365. case EMU10K1_GPR_TRANSLATION_TREBLE:
  366. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  367. change = -EIO;
  368. goto __error;
  369. }
  370. for (j = 0; j < 5; j++)
  371. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
  372. break;
  373. case EMU10K1_GPR_TRANSLATION_ONOFF:
  374. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
  375. break;
  376. }
  377. }
  378. __error:
  379. spin_unlock_irqrestore(&emu->reg_lock, flags);
  380. return change;
  381. }
  382. /*
  383. * Interrupt handler
  384. */
  385. static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
  386. {
  387. struct snd_emu10k1_fx8010_irq *irq, *nirq;
  388. irq = emu->fx8010.irq_handlers;
  389. while (irq) {
  390. nirq = irq->next; /* irq ptr can be removed from list */
  391. if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
  392. if (irq->handler)
  393. irq->handler(emu, irq->private_data);
  394. snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
  395. }
  396. irq = nirq;
  397. }
  398. }
  399. int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
  400. snd_fx8010_irq_handler_t *handler,
  401. unsigned char gpr_running,
  402. void *private_data,
  403. struct snd_emu10k1_fx8010_irq **r_irq)
  404. {
  405. struct snd_emu10k1_fx8010_irq *irq;
  406. unsigned long flags;
  407. irq = kmalloc(sizeof(*irq), GFP_ATOMIC);
  408. if (irq == NULL)
  409. return -ENOMEM;
  410. irq->handler = handler;
  411. irq->gpr_running = gpr_running;
  412. irq->private_data = private_data;
  413. irq->next = NULL;
  414. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  415. if (emu->fx8010.irq_handlers == NULL) {
  416. emu->fx8010.irq_handlers = irq;
  417. emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
  418. snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
  419. } else {
  420. irq->next = emu->fx8010.irq_handlers;
  421. emu->fx8010.irq_handlers = irq;
  422. }
  423. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  424. if (r_irq)
  425. *r_irq = irq;
  426. return 0;
  427. }
  428. int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
  429. struct snd_emu10k1_fx8010_irq *irq)
  430. {
  431. struct snd_emu10k1_fx8010_irq *tmp;
  432. unsigned long flags;
  433. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  434. if ((tmp = emu->fx8010.irq_handlers) == irq) {
  435. emu->fx8010.irq_handlers = tmp->next;
  436. if (emu->fx8010.irq_handlers == NULL) {
  437. snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
  438. emu->dsp_interrupt = NULL;
  439. }
  440. } else {
  441. while (tmp && tmp->next != irq)
  442. tmp = tmp->next;
  443. if (tmp)
  444. tmp->next = tmp->next->next;
  445. }
  446. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  447. kfree(irq);
  448. return 0;
  449. }
  450. /*************************************************************************
  451. * EMU10K1 effect manager
  452. *************************************************************************/
  453. static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
  454. unsigned int *ptr,
  455. u32 op, u32 r, u32 a, u32 x, u32 y)
  456. {
  457. u_int32_t *code;
  458. snd_assert(*ptr < 512, return);
  459. code = (u_int32_t __force *)icode->code + (*ptr) * 2;
  460. set_bit(*ptr, icode->code_valid);
  461. code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
  462. code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
  463. (*ptr)++;
  464. }
  465. #define OP(icode, ptr, op, r, a, x, y) \
  466. snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
  467. static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
  468. unsigned int *ptr,
  469. u32 op, u32 r, u32 a, u32 x, u32 y)
  470. {
  471. u_int32_t *code;
  472. snd_assert(*ptr < 1024, return);
  473. code = (u_int32_t __force *)icode->code + (*ptr) * 2;
  474. set_bit(*ptr, icode->code_valid);
  475. code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
  476. code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
  477. (*ptr)++;
  478. }
  479. #define A_OP(icode, ptr, op, r, a, x, y) \
  480. snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
  481. static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
  482. {
  483. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  484. snd_emu10k1_ptr_write(emu, pc, 0, data);
  485. }
  486. unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
  487. {
  488. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  489. return snd_emu10k1_ptr_read(emu, pc, 0);
  490. }
  491. static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
  492. struct snd_emu10k1_fx8010_code *icode)
  493. {
  494. int gpr;
  495. u32 val;
  496. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  497. if (!test_bit(gpr, icode->gpr_valid))
  498. continue;
  499. if (get_user(val, &icode->gpr_map[gpr]))
  500. return -EFAULT;
  501. snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
  502. }
  503. return 0;
  504. }
  505. static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
  506. struct snd_emu10k1_fx8010_code *icode)
  507. {
  508. int gpr;
  509. u32 val;
  510. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  511. set_bit(gpr, icode->gpr_valid);
  512. val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
  513. if (put_user(val, &icode->gpr_map[gpr]))
  514. return -EFAULT;
  515. }
  516. return 0;
  517. }
  518. static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
  519. struct snd_emu10k1_fx8010_code *icode)
  520. {
  521. int tram;
  522. u32 addr, val;
  523. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  524. if (!test_bit(tram, icode->tram_valid))
  525. continue;
  526. if (get_user(val, &icode->tram_data_map[tram]) ||
  527. get_user(addr, &icode->tram_addr_map[tram]))
  528. return -EFAULT;
  529. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
  530. if (!emu->audigy) {
  531. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
  532. } else {
  533. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
  534. snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
  535. }
  536. }
  537. return 0;
  538. }
  539. static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
  540. struct snd_emu10k1_fx8010_code *icode)
  541. {
  542. int tram;
  543. u32 val, addr;
  544. memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
  545. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  546. set_bit(tram, icode->tram_valid);
  547. val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
  548. if (!emu->audigy) {
  549. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
  550. } else {
  551. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
  552. addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
  553. }
  554. if (put_user(val, &icode->tram_data_map[tram]) ||
  555. put_user(addr, &icode->tram_addr_map[tram]))
  556. return -EFAULT;
  557. }
  558. return 0;
  559. }
  560. static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
  561. struct snd_emu10k1_fx8010_code *icode)
  562. {
  563. u32 pc, lo, hi;
  564. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  565. if (!test_bit(pc / 2, icode->code_valid))
  566. continue;
  567. if (get_user(lo, &icode->code[pc + 0]) ||
  568. get_user(hi, &icode->code[pc + 1]))
  569. return -EFAULT;
  570. snd_emu10k1_efx_write(emu, pc + 0, lo);
  571. snd_emu10k1_efx_write(emu, pc + 1, hi);
  572. }
  573. return 0;
  574. }
  575. static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
  576. struct snd_emu10k1_fx8010_code *icode)
  577. {
  578. u32 pc;
  579. memset(icode->code_valid, 0, sizeof(icode->code_valid));
  580. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  581. set_bit(pc / 2, icode->code_valid);
  582. if (put_user(snd_emu10k1_efx_read(emu, pc + 0), &icode->code[pc + 0]))
  583. return -EFAULT;
  584. if (put_user(snd_emu10k1_efx_read(emu, pc + 1), &icode->code[pc + 1]))
  585. return -EFAULT;
  586. }
  587. return 0;
  588. }
  589. static struct snd_emu10k1_fx8010_ctl *
  590. snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, struct snd_ctl_elem_id *id)
  591. {
  592. struct snd_emu10k1_fx8010_ctl *ctl;
  593. struct snd_kcontrol *kcontrol;
  594. struct list_head *list;
  595. list_for_each(list, &emu->fx8010.gpr_ctl) {
  596. ctl = emu10k1_gpr_ctl(list);
  597. kcontrol = ctl->kcontrol;
  598. if (kcontrol->id.iface == id->iface &&
  599. !strcmp(kcontrol->id.name, id->name) &&
  600. kcontrol->id.index == id->index)
  601. return ctl;
  602. }
  603. return NULL;
  604. }
  605. #define MAX_TLV_SIZE 256
  606. static unsigned int *copy_tlv(const unsigned int __user *_tlv)
  607. {
  608. unsigned int data[2];
  609. unsigned int *tlv;
  610. if (!_tlv)
  611. return NULL;
  612. if (copy_from_user(data, _tlv, sizeof(data)))
  613. return NULL;
  614. if (data[1] >= MAX_TLV_SIZE)
  615. return NULL;
  616. tlv = kmalloc(data[1] * 4 + sizeof(data), GFP_KERNEL);
  617. if (!tlv)
  618. return NULL;
  619. memcpy(tlv, data, sizeof(data));
  620. if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
  621. kfree(tlv);
  622. return NULL;
  623. }
  624. return tlv;
  625. }
  626. static int copy_gctl(struct snd_emu10k1 *emu,
  627. struct snd_emu10k1_fx8010_control_gpr *gctl,
  628. struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
  629. int idx)
  630. {
  631. struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
  632. if (emu->support_tlv)
  633. return copy_from_user(gctl, &_gctl[idx], sizeof(*gctl));
  634. octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
  635. if (copy_from_user(gctl, &octl[idx], sizeof(*octl)))
  636. return -EFAULT;
  637. gctl->tlv = NULL;
  638. return 0;
  639. }
  640. static int copy_gctl_to_user(struct snd_emu10k1 *emu,
  641. struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
  642. struct snd_emu10k1_fx8010_control_gpr *gctl,
  643. int idx)
  644. {
  645. struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
  646. if (emu->support_tlv)
  647. return copy_to_user(&_gctl[idx], gctl, sizeof(*gctl));
  648. octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
  649. return copy_to_user(&octl[idx], gctl, sizeof(*octl));
  650. }
  651. static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
  652. struct snd_emu10k1_fx8010_code *icode)
  653. {
  654. unsigned int i;
  655. struct snd_ctl_elem_id __user *_id;
  656. struct snd_ctl_elem_id id;
  657. struct snd_emu10k1_fx8010_control_gpr *gctl;
  658. int err;
  659. for (i = 0, _id = icode->gpr_del_controls;
  660. i < icode->gpr_del_control_count; i++, _id++) {
  661. if (copy_from_user(&id, _id, sizeof(id)))
  662. return -EFAULT;
  663. if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
  664. return -ENOENT;
  665. }
  666. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  667. if (! gctl)
  668. return -ENOMEM;
  669. err = 0;
  670. for (i = 0; i < icode->gpr_add_control_count; i++) {
  671. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i)) {
  672. err = -EFAULT;
  673. goto __error;
  674. }
  675. if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
  676. continue;
  677. down_read(&emu->card->controls_rwsem);
  678. if (snd_ctl_find_id(emu->card, &gctl->id) != NULL) {
  679. up_read(&emu->card->controls_rwsem);
  680. err = -EEXIST;
  681. goto __error;
  682. }
  683. up_read(&emu->card->controls_rwsem);
  684. if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  685. gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  686. err = -EINVAL;
  687. goto __error;
  688. }
  689. }
  690. for (i = 0; i < icode->gpr_list_control_count; i++) {
  691. /* FIXME: we need to check the WRITE access */
  692. if (copy_gctl(emu, gctl, icode->gpr_list_controls, i)) {
  693. err = -EFAULT;
  694. goto __error;
  695. }
  696. }
  697. __error:
  698. kfree(gctl);
  699. return err;
  700. }
  701. static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
  702. {
  703. struct snd_emu10k1_fx8010_ctl *ctl;
  704. ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
  705. kctl->private_value = 0;
  706. list_del(&ctl->list);
  707. kfree(ctl);
  708. if (kctl->tlv.p)
  709. kfree(kctl->tlv.p);
  710. }
  711. static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
  712. struct snd_emu10k1_fx8010_code *icode)
  713. {
  714. unsigned int i, j;
  715. struct snd_emu10k1_fx8010_control_gpr *gctl;
  716. struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
  717. struct snd_kcontrol_new knew;
  718. struct snd_kcontrol *kctl;
  719. struct snd_ctl_elem_value *val;
  720. int err = 0;
  721. val = kmalloc(sizeof(*val), GFP_KERNEL);
  722. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  723. nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
  724. if (!val || !gctl || !nctl) {
  725. err = -ENOMEM;
  726. goto __error;
  727. }
  728. for (i = 0; i < icode->gpr_add_control_count; i++) {
  729. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i)) {
  730. err = -EFAULT;
  731. goto __error;
  732. }
  733. if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  734. gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  735. err = -EINVAL;
  736. goto __error;
  737. }
  738. if (! gctl->id.name[0]) {
  739. err = -EINVAL;
  740. goto __error;
  741. }
  742. ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
  743. memset(&knew, 0, sizeof(knew));
  744. knew.iface = gctl->id.iface;
  745. knew.name = gctl->id.name;
  746. knew.index = gctl->id.index;
  747. knew.device = gctl->id.device;
  748. knew.subdevice = gctl->id.subdevice;
  749. knew.info = snd_emu10k1_gpr_ctl_info;
  750. knew.tlv.p = copy_tlv(gctl->tlv);
  751. if (knew.tlv.p)
  752. knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  753. SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  754. knew.get = snd_emu10k1_gpr_ctl_get;
  755. knew.put = snd_emu10k1_gpr_ctl_put;
  756. memset(nctl, 0, sizeof(*nctl));
  757. nctl->vcount = gctl->vcount;
  758. nctl->count = gctl->count;
  759. for (j = 0; j < 32; j++) {
  760. nctl->gpr[j] = gctl->gpr[j];
  761. nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
  762. val->value.integer.value[j] = gctl->value[j];
  763. }
  764. nctl->min = gctl->min;
  765. nctl->max = gctl->max;
  766. nctl->translation = gctl->translation;
  767. if (ctl == NULL) {
  768. ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
  769. if (ctl == NULL) {
  770. err = -ENOMEM;
  771. kfree(knew.tlv.p);
  772. goto __error;
  773. }
  774. knew.private_value = (unsigned long)ctl;
  775. *ctl = *nctl;
  776. if ((err = snd_ctl_add(emu->card, kctl = snd_ctl_new1(&knew, emu))) < 0) {
  777. kfree(ctl);
  778. kfree(knew.tlv.p);
  779. goto __error;
  780. }
  781. kctl->private_free = snd_emu10k1_ctl_private_free;
  782. ctl->kcontrol = kctl;
  783. list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
  784. } else {
  785. /* overwrite */
  786. nctl->list = ctl->list;
  787. nctl->kcontrol = ctl->kcontrol;
  788. *ctl = *nctl;
  789. snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
  790. SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
  791. }
  792. snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
  793. }
  794. __error:
  795. kfree(nctl);
  796. kfree(gctl);
  797. kfree(val);
  798. return err;
  799. }
  800. static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
  801. struct snd_emu10k1_fx8010_code *icode)
  802. {
  803. unsigned int i;
  804. struct snd_ctl_elem_id id;
  805. struct snd_ctl_elem_id __user *_id;
  806. struct snd_emu10k1_fx8010_ctl *ctl;
  807. struct snd_card *card = emu->card;
  808. for (i = 0, _id = icode->gpr_del_controls;
  809. i < icode->gpr_del_control_count; i++, _id++) {
  810. if (copy_from_user(&id, _id, sizeof(id)))
  811. return -EFAULT;
  812. down_write(&card->controls_rwsem);
  813. ctl = snd_emu10k1_look_for_ctl(emu, &id);
  814. if (ctl)
  815. snd_ctl_remove(card, ctl->kcontrol);
  816. up_write(&card->controls_rwsem);
  817. }
  818. return 0;
  819. }
  820. static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
  821. struct snd_emu10k1_fx8010_code *icode)
  822. {
  823. unsigned int i = 0, j;
  824. unsigned int total = 0;
  825. struct snd_emu10k1_fx8010_control_gpr *gctl;
  826. struct snd_emu10k1_fx8010_ctl *ctl;
  827. struct snd_ctl_elem_id *id;
  828. struct list_head *list;
  829. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  830. if (! gctl)
  831. return -ENOMEM;
  832. list_for_each(list, &emu->fx8010.gpr_ctl) {
  833. ctl = emu10k1_gpr_ctl(list);
  834. total++;
  835. if (icode->gpr_list_controls &&
  836. i < icode->gpr_list_control_count) {
  837. memset(gctl, 0, sizeof(*gctl));
  838. id = &ctl->kcontrol->id;
  839. gctl->id.iface = id->iface;
  840. strlcpy(gctl->id.name, id->name, sizeof(gctl->id.name));
  841. gctl->id.index = id->index;
  842. gctl->id.device = id->device;
  843. gctl->id.subdevice = id->subdevice;
  844. gctl->vcount = ctl->vcount;
  845. gctl->count = ctl->count;
  846. for (j = 0; j < 32; j++) {
  847. gctl->gpr[j] = ctl->gpr[j];
  848. gctl->value[j] = ctl->value[j];
  849. }
  850. gctl->min = ctl->min;
  851. gctl->max = ctl->max;
  852. gctl->translation = ctl->translation;
  853. if (copy_gctl_to_user(emu, icode->gpr_list_controls,
  854. gctl, i)) {
  855. kfree(gctl);
  856. return -EFAULT;
  857. }
  858. i++;
  859. }
  860. }
  861. icode->gpr_list_control_total = total;
  862. kfree(gctl);
  863. return 0;
  864. }
  865. static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
  866. struct snd_emu10k1_fx8010_code *icode)
  867. {
  868. int err = 0;
  869. mutex_lock(&emu->fx8010.lock);
  870. if ((err = snd_emu10k1_verify_controls(emu, icode)) < 0)
  871. goto __error;
  872. strlcpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
  873. /* stop FX processor - this may be dangerous, but it's better to miss
  874. some samples than generate wrong ones - [jk] */
  875. if (emu->audigy)
  876. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  877. else
  878. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  879. /* ok, do the main job */
  880. if ((err = snd_emu10k1_del_controls(emu, icode)) < 0 ||
  881. (err = snd_emu10k1_gpr_poke(emu, icode)) < 0 ||
  882. (err = snd_emu10k1_tram_poke(emu, icode)) < 0 ||
  883. (err = snd_emu10k1_code_poke(emu, icode)) < 0 ||
  884. (err = snd_emu10k1_add_controls(emu, icode)) < 0)
  885. goto __error;
  886. /* start FX processor when the DSP code is updated */
  887. if (emu->audigy)
  888. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  889. else
  890. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  891. __error:
  892. mutex_unlock(&emu->fx8010.lock);
  893. return err;
  894. }
  895. static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
  896. struct snd_emu10k1_fx8010_code *icode)
  897. {
  898. int err;
  899. mutex_lock(&emu->fx8010.lock);
  900. strlcpy(icode->name, emu->fx8010.name, sizeof(icode->name));
  901. /* ok, do the main job */
  902. err = snd_emu10k1_gpr_peek(emu, icode);
  903. if (err >= 0)
  904. err = snd_emu10k1_tram_peek(emu, icode);
  905. if (err >= 0)
  906. err = snd_emu10k1_code_peek(emu, icode);
  907. if (err >= 0)
  908. err = snd_emu10k1_list_controls(emu, icode);
  909. mutex_unlock(&emu->fx8010.lock);
  910. return err;
  911. }
  912. static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
  913. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  914. {
  915. unsigned int i;
  916. int err = 0;
  917. struct snd_emu10k1_fx8010_pcm *pcm;
  918. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  919. return -EINVAL;
  920. if (ipcm->channels > 32)
  921. return -EINVAL;
  922. pcm = &emu->fx8010.pcm[ipcm->substream];
  923. mutex_lock(&emu->fx8010.lock);
  924. spin_lock_irq(&emu->reg_lock);
  925. if (pcm->opened) {
  926. err = -EBUSY;
  927. goto __error;
  928. }
  929. if (ipcm->channels == 0) { /* remove */
  930. pcm->valid = 0;
  931. } else {
  932. /* FIXME: we need to add universal code to the PCM transfer routine */
  933. if (ipcm->channels != 2) {
  934. err = -EINVAL;
  935. goto __error;
  936. }
  937. pcm->valid = 1;
  938. pcm->opened = 0;
  939. pcm->channels = ipcm->channels;
  940. pcm->tram_start = ipcm->tram_start;
  941. pcm->buffer_size = ipcm->buffer_size;
  942. pcm->gpr_size = ipcm->gpr_size;
  943. pcm->gpr_count = ipcm->gpr_count;
  944. pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
  945. pcm->gpr_ptr = ipcm->gpr_ptr;
  946. pcm->gpr_trigger = ipcm->gpr_trigger;
  947. pcm->gpr_running = ipcm->gpr_running;
  948. for (i = 0; i < pcm->channels; i++)
  949. pcm->etram[i] = ipcm->etram[i];
  950. }
  951. __error:
  952. spin_unlock_irq(&emu->reg_lock);
  953. mutex_unlock(&emu->fx8010.lock);
  954. return err;
  955. }
  956. static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
  957. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  958. {
  959. unsigned int i;
  960. int err = 0;
  961. struct snd_emu10k1_fx8010_pcm *pcm;
  962. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  963. return -EINVAL;
  964. pcm = &emu->fx8010.pcm[ipcm->substream];
  965. mutex_lock(&emu->fx8010.lock);
  966. spin_lock_irq(&emu->reg_lock);
  967. ipcm->channels = pcm->channels;
  968. ipcm->tram_start = pcm->tram_start;
  969. ipcm->buffer_size = pcm->buffer_size;
  970. ipcm->gpr_size = pcm->gpr_size;
  971. ipcm->gpr_ptr = pcm->gpr_ptr;
  972. ipcm->gpr_count = pcm->gpr_count;
  973. ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
  974. ipcm->gpr_trigger = pcm->gpr_trigger;
  975. ipcm->gpr_running = pcm->gpr_running;
  976. for (i = 0; i < pcm->channels; i++)
  977. ipcm->etram[i] = pcm->etram[i];
  978. ipcm->res1 = ipcm->res2 = 0;
  979. ipcm->pad = 0;
  980. spin_unlock_irq(&emu->reg_lock);
  981. mutex_unlock(&emu->fx8010.lock);
  982. return err;
  983. }
  984. #define SND_EMU10K1_GPR_CONTROLS 44
  985. #define SND_EMU10K1_INPUTS 12
  986. #define SND_EMU10K1_PLAYBACK_CHANNELS 8
  987. #define SND_EMU10K1_CAPTURE_CHANNELS 4
  988. static void __devinit
  989. snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  990. const char *name, int gpr, int defval)
  991. {
  992. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  993. strcpy(ctl->id.name, name);
  994. ctl->vcount = ctl->count = 1;
  995. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  996. ctl->min = 0;
  997. ctl->max = 100;
  998. ctl->tlv = snd_emu10k1_db_scale1;
  999. ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
  1000. }
  1001. static void __devinit
  1002. snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1003. const char *name, int gpr, int defval)
  1004. {
  1005. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1006. strcpy(ctl->id.name, name);
  1007. ctl->vcount = ctl->count = 2;
  1008. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1009. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1010. ctl->min = 0;
  1011. ctl->max = 100;
  1012. ctl->tlv = snd_emu10k1_db_scale1;
  1013. ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
  1014. }
  1015. static void __devinit
  1016. snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1017. const char *name, int gpr, int defval)
  1018. {
  1019. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1020. strcpy(ctl->id.name, name);
  1021. ctl->vcount = ctl->count = 1;
  1022. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1023. ctl->min = 0;
  1024. ctl->max = 1;
  1025. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1026. }
  1027. static void __devinit
  1028. snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1029. const char *name, int gpr, int defval)
  1030. {
  1031. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1032. strcpy(ctl->id.name, name);
  1033. ctl->vcount = ctl->count = 2;
  1034. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1035. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1036. ctl->min = 0;
  1037. ctl->max = 1;
  1038. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1039. }
  1040. /*
  1041. * Used for emu1010 - conversion from 32-bit capture inputs from HANA
  1042. * to 2 x 16-bit registers in audigy - their values are read via DMA.
  1043. * Conversion is performed by Audigy DSP instructions of FX8010.
  1044. */
  1045. static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
  1046. struct snd_emu10k1_fx8010_code *icode,
  1047. u32 *ptr, int tmp, int bit_shifter16,
  1048. int reg_in, int reg_out)
  1049. {
  1050. A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000);
  1051. A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000);
  1052. A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2));
  1053. A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000);
  1054. A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000);
  1055. A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000);
  1056. A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2));
  1057. A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000);
  1058. return 1;
  1059. }
  1060. /*
  1061. * initial DSP configuration for Audigy
  1062. */
  1063. static int __devinit _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
  1064. {
  1065. int err, i, z, gpr, nctl;
  1066. int bit_shifter16;
  1067. const int playback = 10;
  1068. const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */
  1069. const int stereo_mix = capture + 2;
  1070. const int tmp = 0x88;
  1071. u32 ptr;
  1072. struct snd_emu10k1_fx8010_code *icode = NULL;
  1073. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1074. u32 *gpr_map;
  1075. mm_segment_t seg;
  1076. if ((icode = kzalloc(sizeof(*icode), GFP_KERNEL)) == NULL ||
  1077. (icode->gpr_map = (u_int32_t __user *)
  1078. kcalloc(512 + 256 + 256 + 2 * 1024, sizeof(u_int32_t),
  1079. GFP_KERNEL)) == NULL ||
  1080. (controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1081. sizeof(*controls), GFP_KERNEL)) == NULL) {
  1082. err = -ENOMEM;
  1083. goto __err;
  1084. }
  1085. gpr_map = (u32 __force *)icode->gpr_map;
  1086. icode->tram_data_map = icode->gpr_map + 512;
  1087. icode->tram_addr_map = icode->tram_data_map + 256;
  1088. icode->code = icode->tram_addr_map + 256;
  1089. /* clear free GPRs */
  1090. for (i = 0; i < 512; i++)
  1091. set_bit(i, icode->gpr_valid);
  1092. /* clear TRAM data & address lines */
  1093. for (i = 0; i < 256; i++)
  1094. set_bit(i, icode->tram_valid);
  1095. strcpy(icode->name, "Audigy DSP code for ALSA");
  1096. ptr = 0;
  1097. nctl = 0;
  1098. gpr = stereo_mix + 10;
  1099. gpr_map[gpr++] = 0x00007fff;
  1100. gpr_map[gpr++] = 0x00008000;
  1101. gpr_map[gpr++] = 0x0000ffff;
  1102. bit_shifter16 = gpr;
  1103. /* stop FX processor */
  1104. snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);
  1105. #if 1
  1106. /* PCM front Playback Volume (independent from stereo mix)
  1107. * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)
  1108. * where gpr contains attenuation from corresponding mixer control
  1109. * (snd_emu10k1_init_stereo_control)
  1110. */
  1111. A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
  1112. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
  1113. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
  1114. gpr += 2;
  1115. /* PCM Surround Playback (independent from stereo mix) */
  1116. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
  1117. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
  1118. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
  1119. gpr += 2;
  1120. /* PCM Side Playback (independent from stereo mix) */
  1121. if (emu->card_capabilities->spk71) {
  1122. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
  1123. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
  1124. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
  1125. gpr += 2;
  1126. }
  1127. /* PCM Center Playback (independent from stereo mix) */
  1128. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
  1129. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
  1130. gpr++;
  1131. /* PCM LFE Playback (independent from stereo mix) */
  1132. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
  1133. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
  1134. gpr++;
  1135. /*
  1136. * Stereo Mix
  1137. */
  1138. /* Wave (PCM) Playback Volume (will be renamed later) */
  1139. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1140. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1141. snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
  1142. gpr += 2;
  1143. /* Synth Playback */
  1144. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1145. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1146. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
  1147. gpr += 2;
  1148. /* Wave (PCM) Capture */
  1149. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1150. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1151. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
  1152. gpr += 2;
  1153. /* Synth Capture */
  1154. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1155. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1156. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
  1157. gpr += 2;
  1158. /*
  1159. * inputs
  1160. */
  1161. #define A_ADD_VOLUME_IN(var,vol,input) \
  1162. A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
  1163. /* emu1212 DSP 0 and DSP 1 Capture */
  1164. if (emu->card_capabilities->emu1010) {
  1165. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0));
  1166. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1));
  1167. snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
  1168. gpr += 2;
  1169. }
  1170. /* AC'97 Playback Volume - used only for mic (renamed later) */
  1171. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
  1172. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
  1173. snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
  1174. gpr += 2;
  1175. /* AC'97 Capture Volume - used only for mic */
  1176. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
  1177. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
  1178. snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
  1179. gpr += 2;
  1180. /* mic capture buffer */
  1181. A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));
  1182. /* Audigy CD Playback Volume */
  1183. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
  1184. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1185. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1186. emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
  1187. gpr, 0);
  1188. gpr += 2;
  1189. /* Audigy CD Capture Volume */
  1190. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
  1191. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1192. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1193. emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
  1194. gpr, 0);
  1195. gpr += 2;
  1196. /* Optical SPDIF Playback Volume */
  1197. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
  1198. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1199. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
  1200. gpr += 2;
  1201. /* Optical SPDIF Capture Volume */
  1202. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
  1203. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1204. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
  1205. gpr += 2;
  1206. /* Line2 Playback Volume */
  1207. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
  1208. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
  1209. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1210. emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
  1211. gpr, 0);
  1212. gpr += 2;
  1213. /* Line2 Capture Volume */
  1214. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
  1215. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
  1216. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1217. emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
  1218. gpr, 0);
  1219. gpr += 2;
  1220. /* Philips ADC Playback Volume */
  1221. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
  1222. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
  1223. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
  1224. gpr += 2;
  1225. /* Philips ADC Capture Volume */
  1226. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
  1227. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
  1228. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
  1229. gpr += 2;
  1230. /* Aux2 Playback Volume */
  1231. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
  1232. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
  1233. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1234. emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
  1235. gpr, 0);
  1236. gpr += 2;
  1237. /* Aux2 Capture Volume */
  1238. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
  1239. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
  1240. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1241. emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
  1242. gpr, 0);
  1243. gpr += 2;
  1244. /* Stereo Mix Front Playback Volume */
  1245. A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
  1246. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1247. snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
  1248. gpr += 2;
  1249. /* Stereo Mix Surround Playback */
  1250. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
  1251. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1252. snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
  1253. gpr += 2;
  1254. /* Stereo Mix Center Playback */
  1255. /* Center = sub = Left/2 + Right/2 */
  1256. A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));
  1257. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
  1258. snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
  1259. gpr++;
  1260. /* Stereo Mix LFE Playback */
  1261. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
  1262. snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
  1263. gpr++;
  1264. if (emu->card_capabilities->spk71) {
  1265. /* Stereo Mix Side Playback */
  1266. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
  1267. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1268. snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
  1269. gpr += 2;
  1270. }
  1271. /*
  1272. * outputs
  1273. */
  1274. #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
  1275. #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
  1276. {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
  1277. #define _A_SWITCH(icode, ptr, dst, src, sw) \
  1278. A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
  1279. #define A_SWITCH(icode, ptr, dst, src, sw) \
  1280. _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
  1281. #define _A_SWITCH_NEG(icode, ptr, dst, src) \
  1282. A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
  1283. #define A_SWITCH_NEG(icode, ptr, dst, src) \
  1284. _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
  1285. /*
  1286. * Process tone control
  1287. */
  1288. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */
  1289. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */
  1290. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */
  1291. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */
  1292. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */
  1293. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */
  1294. if (emu->card_capabilities->spk71) {
  1295. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */
  1296. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */
  1297. }
  1298. ctl = &controls[nctl + 0];
  1299. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1300. strcpy(ctl->id.name, "Tone Control - Bass");
  1301. ctl->vcount = 2;
  1302. ctl->count = 10;
  1303. ctl->min = 0;
  1304. ctl->max = 40;
  1305. ctl->value[0] = ctl->value[1] = 20;
  1306. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1307. ctl = &controls[nctl + 1];
  1308. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1309. strcpy(ctl->id.name, "Tone Control - Treble");
  1310. ctl->vcount = 2;
  1311. ctl->count = 10;
  1312. ctl->min = 0;
  1313. ctl->max = 40;
  1314. ctl->value[0] = ctl->value[1] = 20;
  1315. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1316. #define BASS_GPR 0x8c
  1317. #define TREBLE_GPR 0x96
  1318. for (z = 0; z < 5; z++) {
  1319. int j;
  1320. for (j = 0; j < 2; j++) {
  1321. controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  1322. controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  1323. }
  1324. }
  1325. for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
  1326. int j, k, l, d;
  1327. for (j = 0; j < 2; j++) { /* left/right */
  1328. k = 0xb0 + (z * 8) + (j * 4);
  1329. l = 0xe0 + (z * 8) + (j * 4);
  1330. d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
  1331. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j));
  1332. A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j));
  1333. A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j));
  1334. A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j));
  1335. A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j));
  1336. A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
  1337. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j));
  1338. A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j));
  1339. A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j));
  1340. A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j));
  1341. A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j));
  1342. A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
  1343. A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
  1344. if (z == 2) /* center */
  1345. break;
  1346. }
  1347. }
  1348. nctl += 2;
  1349. #undef BASS_GPR
  1350. #undef TREBLE_GPR
  1351. for (z = 0; z < 8; z++) {
  1352. A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
  1353. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
  1354. A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  1355. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1356. }
  1357. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
  1358. gpr += 2;
  1359. /* Master volume (will be renamed later) */
  1360. A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS));
  1361. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS));
  1362. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS));
  1363. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS));
  1364. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS));
  1365. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS));
  1366. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS));
  1367. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS));
  1368. snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
  1369. gpr += 2;
  1370. /* analog speakers */
  1371. A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1372. A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1373. A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1374. A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1375. if (emu->card_capabilities->spk71)
  1376. A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1377. /* headphone */
  1378. A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1379. /* digital outputs */
  1380. /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */
  1381. if (emu->card_capabilities->emu1010) {
  1382. /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
  1383. snd_printk("EMU outputs on\n");
  1384. for (z = 0; z < 8; z++) {
  1385. A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
  1386. }
  1387. }
  1388. /* IEC958 Optical Raw Playback Switch */
  1389. gpr_map[gpr++] = 0;
  1390. gpr_map[gpr++] = 0x1008;
  1391. gpr_map[gpr++] = 0xffff0000;
  1392. for (z = 0; z < 2; z++) {
  1393. A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
  1394. A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
  1395. A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
  1396. A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
  1397. A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
  1398. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  1399. A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  1400. if ((z==1) && (emu->card_capabilities->spdif_bug)) {
  1401. /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
  1402. snd_printk(KERN_INFO "Installing spdif_bug patch: %s\n", emu->card_capabilities->name);
  1403. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
  1404. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1405. } else {
  1406. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1407. }
  1408. }
  1409. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  1410. gpr += 2;
  1411. A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1412. A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1413. A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1414. /* ADC buffer */
  1415. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  1416. A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1417. #else
  1418. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
  1419. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
  1420. #endif
  1421. if (emu->card_capabilities->emu1010) {
  1422. snd_printk("EMU inputs on\n");
  1423. /* Capture 16 (originally 8) channels of S32_LE sound */
  1424. /* printk("emufx.c: gpr=0x%x, tmp=0x%x\n",gpr, tmp); */
  1425. /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */
  1426. /* A_P16VIN(0) is delayed by one sample,
  1427. * so all other A_P16VIN channels will need to also be delayed
  1428. */
  1429. /* Left ADC in. 1 of 2 */
  1430. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
  1431. /* Right ADC in 1 of 2 */
  1432. gpr_map[gpr++] = 0x00000000;
  1433. /* Delaying by one sample: instead of copying the input
  1434. * value A_P16VIN to output A_FXBUS2 as in the first channel,
  1435. * we use an auxiliary register, delaying the value by one
  1436. * sample
  1437. */
  1438. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) );
  1439. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
  1440. gpr_map[gpr++] = 0x00000000;
  1441. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) );
  1442. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000);
  1443. gpr_map[gpr++] = 0x00000000;
  1444. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) );
  1445. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000);
  1446. /* For 96kHz mode */
  1447. /* Left ADC in. 2 of 2 */
  1448. gpr_map[gpr++] = 0x00000000;
  1449. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) );
  1450. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000);
  1451. /* Right ADC in 2 of 2 */
  1452. gpr_map[gpr++] = 0x00000000;
  1453. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) );
  1454. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000);
  1455. gpr_map[gpr++] = 0x00000000;
  1456. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) );
  1457. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000);
  1458. gpr_map[gpr++] = 0x00000000;
  1459. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) );
  1460. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000);
  1461. /* Pavel Hofman - we still have voices, A_FXBUS2s, and
  1462. * A_P16VINs available -
  1463. * let's add 8 more capture channels - total of 16
  1464. */
  1465. gpr_map[gpr++] = 0x00000000;
  1466. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1467. bit_shifter16,
  1468. A_GPR(gpr - 1),
  1469. A_FXBUS2(0x10));
  1470. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8),
  1471. A_C_00000000, A_C_00000000);
  1472. gpr_map[gpr++] = 0x00000000;
  1473. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1474. bit_shifter16,
  1475. A_GPR(gpr - 1),
  1476. A_FXBUS2(0x12));
  1477. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9),
  1478. A_C_00000000, A_C_00000000);
  1479. gpr_map[gpr++] = 0x00000000;
  1480. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1481. bit_shifter16,
  1482. A_GPR(gpr - 1),
  1483. A_FXBUS2(0x14));
  1484. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa),
  1485. A_C_00000000, A_C_00000000);
  1486. gpr_map[gpr++] = 0x00000000;
  1487. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1488. bit_shifter16,
  1489. A_GPR(gpr - 1),
  1490. A_FXBUS2(0x16));
  1491. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb),
  1492. A_C_00000000, A_C_00000000);
  1493. gpr_map[gpr++] = 0x00000000;
  1494. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1495. bit_shifter16,
  1496. A_GPR(gpr - 1),
  1497. A_FXBUS2(0x18));
  1498. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc),
  1499. A_C_00000000, A_C_00000000);
  1500. gpr_map[gpr++] = 0x00000000;
  1501. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1502. bit_shifter16,
  1503. A_GPR(gpr - 1),
  1504. A_FXBUS2(0x1a));
  1505. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd),
  1506. A_C_00000000, A_C_00000000);
  1507. gpr_map[gpr++] = 0x00000000;
  1508. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1509. bit_shifter16,
  1510. A_GPR(gpr - 1),
  1511. A_FXBUS2(0x1c));
  1512. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe),
  1513. A_C_00000000, A_C_00000000);
  1514. gpr_map[gpr++] = 0x00000000;
  1515. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1516. bit_shifter16,
  1517. A_GPR(gpr - 1),
  1518. A_FXBUS2(0x1e));
  1519. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf),
  1520. A_C_00000000, A_C_00000000);
  1521. #if 0
  1522. for (z = 4; z < 8; z++) {
  1523. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1524. }
  1525. for (z = 0xc; z < 0x10; z++) {
  1526. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1527. }
  1528. #endif
  1529. } else {
  1530. /* EFX capture - capture the 16 EXTINs */
  1531. /* Capture 16 channels of S16_LE sound */
  1532. for (z = 0; z < 16; z++) {
  1533. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
  1534. }
  1535. }
  1536. #endif /* JCD test */
  1537. /*
  1538. * ok, set up done..
  1539. */
  1540. if (gpr > tmp) {
  1541. snd_BUG();
  1542. err = -EIO;
  1543. goto __err;
  1544. }
  1545. /* clear remaining instruction memory */
  1546. while (ptr < 0x400)
  1547. A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
  1548. seg = snd_enter_user();
  1549. icode->gpr_add_control_count = nctl;
  1550. icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
  1551. emu->support_tlv = 1; /* support TLV */
  1552. err = snd_emu10k1_icode_poke(emu, icode);
  1553. emu->support_tlv = 0; /* clear again */
  1554. snd_leave_user(seg);
  1555. __err:
  1556. kfree(controls);
  1557. if (icode != NULL) {
  1558. kfree((void __force *)icode->gpr_map);
  1559. kfree(icode);
  1560. }
  1561. return err;
  1562. }
  1563. /*
  1564. * initial DSP configuration for Emu10k1
  1565. */
  1566. /* when volume = max, then copy only to avoid volume modification */
  1567. /* with iMAC0 (negative values) */
  1568. static void __devinit _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1569. {
  1570. OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
  1571. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1572. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001);
  1573. OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
  1574. }
  1575. static void __devinit _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1576. {
  1577. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1578. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1579. OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001);
  1580. OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
  1581. OP(icode, ptr, iMAC0, dst, dst, src, vol);
  1582. }
  1583. static void __devinit _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1584. {
  1585. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1586. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1587. OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
  1588. OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
  1589. OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
  1590. }
  1591. #define VOLUME(icode, ptr, dst, src, vol) \
  1592. _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1593. #define VOLUME_IN(icode, ptr, dst, src, vol) \
  1594. _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1595. #define VOLUME_ADD(icode, ptr, dst, src, vol) \
  1596. _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1597. #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
  1598. _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1599. #define VOLUME_OUT(icode, ptr, dst, src, vol) \
  1600. _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
  1601. #define _SWITCH(icode, ptr, dst, src, sw) \
  1602. OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
  1603. #define SWITCH(icode, ptr, dst, src, sw) \
  1604. _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
  1605. #define SWITCH_IN(icode, ptr, dst, src, sw) \
  1606. _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
  1607. #define _SWITCH_NEG(icode, ptr, dst, src) \
  1608. OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
  1609. #define SWITCH_NEG(icode, ptr, dst, src) \
  1610. _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
  1611. static int __devinit _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  1612. {
  1613. int err, i, z, gpr, tmp, playback, capture;
  1614. u32 ptr;
  1615. struct snd_emu10k1_fx8010_code *icode;
  1616. struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
  1617. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1618. u32 *gpr_map;
  1619. mm_segment_t seg;
  1620. if ((icode = kzalloc(sizeof(*icode), GFP_KERNEL)) == NULL)
  1621. return -ENOMEM;
  1622. if ((icode->gpr_map = (u_int32_t __user *)
  1623. kcalloc(256 + 160 + 160 + 2 * 512, sizeof(u_int32_t),
  1624. GFP_KERNEL)) == NULL ||
  1625. (controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1626. sizeof(struct snd_emu10k1_fx8010_control_gpr),
  1627. GFP_KERNEL)) == NULL ||
  1628. (ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL)) == NULL) {
  1629. err = -ENOMEM;
  1630. goto __err;
  1631. }
  1632. gpr_map = (u32 __force *)icode->gpr_map;
  1633. icode->tram_data_map = icode->gpr_map + 256;
  1634. icode->tram_addr_map = icode->tram_data_map + 160;
  1635. icode->code = icode->tram_addr_map + 160;
  1636. /* clear free GPRs */
  1637. for (i = 0; i < 256; i++)
  1638. set_bit(i, icode->gpr_valid);
  1639. /* clear TRAM data & address lines */
  1640. for (i = 0; i < 160; i++)
  1641. set_bit(i, icode->tram_valid);
  1642. strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
  1643. ptr = 0; i = 0;
  1644. /* we have 12 inputs */
  1645. playback = SND_EMU10K1_INPUTS;
  1646. /* we have 6 playback channels and tone control doubles */
  1647. capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);
  1648. gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
  1649. tmp = 0x88; /* we need 4 temporary GPR */
  1650. /* from 0x8c to 0xff is the area for tone control */
  1651. /* stop FX processor */
  1652. snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);
  1653. /*
  1654. * Process FX Buses
  1655. */
  1656. OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004);
  1657. OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004);
  1658. OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004);
  1659. OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004);
  1660. OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004);
  1661. OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004);
  1662. OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004);
  1663. OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004);
  1664. OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
  1665. OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
  1666. OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004);
  1667. OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004);
  1668. /* Raw S/PDIF PCM */
  1669. ipcm->substream = 0;
  1670. ipcm->channels = 2;
  1671. ipcm->tram_start = 0;
  1672. ipcm->buffer_size = (64 * 1024) / 2;
  1673. ipcm->gpr_size = gpr++;
  1674. ipcm->gpr_ptr = gpr++;
  1675. ipcm->gpr_count = gpr++;
  1676. ipcm->gpr_tmpcount = gpr++;
  1677. ipcm->gpr_trigger = gpr++;
  1678. ipcm->gpr_running = gpr++;
  1679. ipcm->etram[0] = 0;
  1680. ipcm->etram[1] = 1;
  1681. gpr_map[gpr + 0] = 0xfffff000;
  1682. gpr_map[gpr + 1] = 0xffff0000;
  1683. gpr_map[gpr + 2] = 0x70000000;
  1684. gpr_map[gpr + 3] = 0x00000007;
  1685. gpr_map[gpr + 4] = 0x001f << 11;
  1686. gpr_map[gpr + 5] = 0x001c << 11;
  1687. gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
  1688. gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
  1689. gpr_map[gpr + 8] = 0x2000000 + (2<<11);
  1690. gpr_map[gpr + 9] = 0x4000000 + (2<<11);
  1691. gpr_map[gpr + 10] = 1<<11;
  1692. gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
  1693. gpr_map[gpr + 12] = 0;
  1694. /* if the trigger flag is not set, skip */
  1695. /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
  1696. /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
  1697. /* if the running flag is set, we're running */
  1698. /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
  1699. /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
  1700. /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
  1701. /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
  1702. /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
  1703. /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
  1704. /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
  1705. /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
  1706. /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
  1707. /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
  1708. /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
  1709. /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
  1710. /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1711. /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1712. /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1713. /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
  1714. /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
  1715. /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1716. /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1717. /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1718. /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
  1719. /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
  1720. /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
  1721. /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
  1722. /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
  1723. /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
  1724. /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
  1725. /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1726. /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
  1727. /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
  1728. /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
  1729. /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
  1730. /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
  1731. /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
  1732. /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
  1733. /* 24: */
  1734. gpr += 13;
  1735. /* Wave Playback Volume */
  1736. for (z = 0; z < 2; z++)
  1737. VOLUME(icode, &ptr, playback + z, z, gpr + z);
  1738. snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
  1739. gpr += 2;
  1740. /* Wave Surround Playback Volume */
  1741. for (z = 0; z < 2; z++)
  1742. VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
  1743. snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
  1744. gpr += 2;
  1745. /* Wave Center/LFE Playback Volume */
  1746. OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
  1747. OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002);
  1748. VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
  1749. snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
  1750. VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
  1751. snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
  1752. /* Wave Capture Volume + Switch */
  1753. for (z = 0; z < 2; z++) {
  1754. SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
  1755. VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1756. }
  1757. snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
  1758. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
  1759. gpr += 4;
  1760. /* Synth Playback Volume */
  1761. for (z = 0; z < 2; z++)
  1762. VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
  1763. snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
  1764. gpr += 2;
  1765. /* Synth Capture Volume + Switch */
  1766. for (z = 0; z < 2; z++) {
  1767. SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
  1768. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1769. }
  1770. snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
  1771. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
  1772. gpr += 4;
  1773. /* Surround Digital Playback Volume (renamed later without Digital) */
  1774. for (z = 0; z < 2; z++)
  1775. VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
  1776. snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
  1777. gpr += 2;
  1778. /* Surround Capture Volume + Switch */
  1779. for (z = 0; z < 2; z++) {
  1780. SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
  1781. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1782. }
  1783. snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
  1784. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
  1785. gpr += 4;
  1786. /* Center Playback Volume (renamed later without Digital) */
  1787. VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
  1788. snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
  1789. /* LFE Playback Volume + Switch (renamed later without Digital) */
  1790. VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
  1791. snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
  1792. /* Front Playback Volume */
  1793. for (z = 0; z < 2; z++)
  1794. VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
  1795. snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
  1796. gpr += 2;
  1797. /* Front Capture Volume + Switch */
  1798. for (z = 0; z < 2; z++) {
  1799. SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
  1800. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1801. }
  1802. snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
  1803. snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
  1804. gpr += 3;
  1805. /*
  1806. * Process inputs
  1807. */
  1808. if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
  1809. /* AC'97 Playback Volume */
  1810. VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
  1811. VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
  1812. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
  1813. /* AC'97 Capture Volume */
  1814. VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
  1815. VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
  1816. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
  1817. }
  1818. if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
  1819. /* IEC958 TTL Playback Volume */
  1820. for (z = 0; z < 2; z++)
  1821. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
  1822. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
  1823. gpr += 2;
  1824. /* IEC958 TTL Capture Volume + Switch */
  1825. for (z = 0; z < 2; z++) {
  1826. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
  1827. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1828. }
  1829. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
  1830. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
  1831. gpr += 4;
  1832. }
  1833. if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
  1834. /* Zoom Video Playback Volume */
  1835. for (z = 0; z < 2; z++)
  1836. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
  1837. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
  1838. gpr += 2;
  1839. /* Zoom Video Capture Volume + Switch */
  1840. for (z = 0; z < 2; z++) {
  1841. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
  1842. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1843. }
  1844. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
  1845. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
  1846. gpr += 4;
  1847. }
  1848. if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
  1849. /* IEC958 Optical Playback Volume */
  1850. for (z = 0; z < 2; z++)
  1851. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
  1852. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
  1853. gpr += 2;
  1854. /* IEC958 Optical Capture Volume */
  1855. for (z = 0; z < 2; z++) {
  1856. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
  1857. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1858. }
  1859. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
  1860. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
  1861. gpr += 4;
  1862. }
  1863. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
  1864. /* Line LiveDrive Playback Volume */
  1865. for (z = 0; z < 2; z++)
  1866. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
  1867. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
  1868. gpr += 2;
  1869. /* Line LiveDrive Capture Volume + Switch */
  1870. for (z = 0; z < 2; z++) {
  1871. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
  1872. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1873. }
  1874. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
  1875. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
  1876. gpr += 4;
  1877. }
  1878. if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
  1879. /* IEC958 Coax Playback Volume */
  1880. for (z = 0; z < 2; z++)
  1881. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
  1882. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
  1883. gpr += 2;
  1884. /* IEC958 Coax Capture Volume + Switch */
  1885. for (z = 0; z < 2; z++) {
  1886. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
  1887. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1888. }
  1889. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
  1890. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
  1891. gpr += 4;
  1892. }
  1893. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
  1894. /* Line LiveDrive Playback Volume */
  1895. for (z = 0; z < 2; z++)
  1896. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
  1897. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
  1898. controls[i-1].id.index = 1;
  1899. gpr += 2;
  1900. /* Line LiveDrive Capture Volume */
  1901. for (z = 0; z < 2; z++) {
  1902. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
  1903. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1904. }
  1905. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
  1906. controls[i-1].id.index = 1;
  1907. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
  1908. controls[i-1].id.index = 1;
  1909. gpr += 4;
  1910. }
  1911. /*
  1912. * Process tone control
  1913. */
  1914. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */
  1915. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */
  1916. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */
  1917. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */
  1918. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */
  1919. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */
  1920. ctl = &controls[i + 0];
  1921. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1922. strcpy(ctl->id.name, "Tone Control - Bass");
  1923. ctl->vcount = 2;
  1924. ctl->count = 10;
  1925. ctl->min = 0;
  1926. ctl->max = 40;
  1927. ctl->value[0] = ctl->value[1] = 20;
  1928. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1929. ctl = &controls[i + 1];
  1930. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1931. strcpy(ctl->id.name, "Tone Control - Treble");
  1932. ctl->vcount = 2;
  1933. ctl->count = 10;
  1934. ctl->min = 0;
  1935. ctl->max = 40;
  1936. ctl->value[0] = ctl->value[1] = 20;
  1937. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1938. #define BASS_GPR 0x8c
  1939. #define TREBLE_GPR 0x96
  1940. for (z = 0; z < 5; z++) {
  1941. int j;
  1942. for (j = 0; j < 2; j++) {
  1943. controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  1944. controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  1945. }
  1946. }
  1947. for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
  1948. int j, k, l, d;
  1949. for (j = 0; j < 2; j++) { /* left/right */
  1950. k = 0xa0 + (z * 8) + (j * 4);
  1951. l = 0xd0 + (z * 8) + (j * 4);
  1952. d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
  1953. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
  1954. OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
  1955. OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
  1956. OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
  1957. OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
  1958. OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
  1959. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
  1960. OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
  1961. OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
  1962. OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
  1963. OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
  1964. OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
  1965. OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
  1966. if (z == 2) /* center */
  1967. break;
  1968. }
  1969. }
  1970. i += 2;
  1971. #undef BASS_GPR
  1972. #undef TREBLE_GPR
  1973. for (z = 0; z < 6; z++) {
  1974. SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
  1975. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
  1976. SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  1977. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  1978. }
  1979. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
  1980. gpr += 2;
  1981. /*
  1982. * Process outputs
  1983. */
  1984. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
  1985. /* AC'97 Playback Volume */
  1986. for (z = 0; z < 2; z++)
  1987. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000);
  1988. }
  1989. if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
  1990. /* IEC958 Optical Raw Playback Switch */
  1991. for (z = 0; z < 2; z++) {
  1992. SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
  1993. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  1994. SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  1995. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  1996. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  1997. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  1998. #endif
  1999. }
  2000. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  2001. gpr += 2;
  2002. }
  2003. if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
  2004. /* Headphone Playback Volume */
  2005. for (z = 0; z < 2; z++) {
  2006. SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z);
  2007. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
  2008. SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  2009. OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2010. VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
  2011. }
  2012. snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
  2013. controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
  2014. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
  2015. controls[i-1].id.index = 1;
  2016. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
  2017. controls[i-1].id.index = 1;
  2018. gpr += 4;
  2019. }
  2020. if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
  2021. for (z = 0; z < 2; z++)
  2022. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
  2023. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
  2024. for (z = 0; z < 2; z++)
  2025. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
  2026. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
  2027. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2028. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
  2029. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
  2030. #else
  2031. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
  2032. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
  2033. #endif
  2034. }
  2035. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
  2036. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2037. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
  2038. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
  2039. #else
  2040. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
  2041. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
  2042. #endif
  2043. }
  2044. #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
  2045. for (z = 0; z < 2; z++)
  2046. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
  2047. #endif
  2048. if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
  2049. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
  2050. /* EFX capture - capture the 16 EXTINS */
  2051. if (emu->card_capabilities->sblive51) {
  2052. /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER
  2053. * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
  2054. *
  2055. * Since only 14 of the 16 EXTINs are used, this is not a big problem.
  2056. * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture
  2057. * 0 and 3, then the rest of the EXTINs to the corresponding FX capture
  2058. * channel. Multitrack recorders will still see the center/lfe output signal
  2059. * on the second and third channels.
  2060. */
  2061. OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0));
  2062. OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1));
  2063. OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2));
  2064. OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3));
  2065. for (z = 4; z < 14; z++)
  2066. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2067. } else {
  2068. for (z = 0; z < 16; z++)
  2069. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2070. }
  2071. if (gpr > tmp) {
  2072. snd_BUG();
  2073. err = -EIO;
  2074. goto __err;
  2075. }
  2076. if (i > SND_EMU10K1_GPR_CONTROLS) {
  2077. snd_BUG();
  2078. err = -EIO;
  2079. goto __err;
  2080. }
  2081. /* clear remaining instruction memory */
  2082. while (ptr < 0x200)
  2083. OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
  2084. if ((err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size)) < 0)
  2085. goto __err;
  2086. seg = snd_enter_user();
  2087. icode->gpr_add_control_count = i;
  2088. icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
  2089. emu->support_tlv = 1; /* support TLV */
  2090. err = snd_emu10k1_icode_poke(emu, icode);
  2091. emu->support_tlv = 0; /* clear again */
  2092. snd_leave_user(seg);
  2093. if (err >= 0)
  2094. err = snd_emu10k1_ipcm_poke(emu, ipcm);
  2095. __err:
  2096. kfree(ipcm);
  2097. kfree(controls);
  2098. if (icode != NULL) {
  2099. kfree((void __force *)icode->gpr_map);
  2100. kfree(icode);
  2101. }
  2102. return err;
  2103. }
  2104. int __devinit snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  2105. {
  2106. spin_lock_init(&emu->fx8010.irq_lock);
  2107. INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
  2108. if (emu->audigy)
  2109. return _snd_emu10k1_audigy_init_efx(emu);
  2110. else
  2111. return _snd_emu10k1_init_efx(emu);
  2112. }
  2113. void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
  2114. {
  2115. /* stop processor */
  2116. if (emu->audigy)
  2117. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
  2118. else
  2119. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
  2120. }
  2121. #if 0 /* FIXME: who use them? */
  2122. int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
  2123. {
  2124. if (output < 0 || output >= 6)
  2125. return -EINVAL;
  2126. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
  2127. return 0;
  2128. }
  2129. int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
  2130. {
  2131. if (output < 0 || output >= 6)
  2132. return -EINVAL;
  2133. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
  2134. return 0;
  2135. }
  2136. #endif
  2137. int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
  2138. {
  2139. u8 size_reg = 0;
  2140. /* size is in samples */
  2141. if (size != 0) {
  2142. size = (size - 1) >> 13;
  2143. while (size) {
  2144. size >>= 1;
  2145. size_reg++;
  2146. }
  2147. size = 0x2000 << size_reg;
  2148. }
  2149. if ((emu->fx8010.etram_pages.bytes / 2) == size)
  2150. return 0;
  2151. spin_lock_irq(&emu->emu_lock);
  2152. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2153. spin_unlock_irq(&emu->emu_lock);
  2154. snd_emu10k1_ptr_write(emu, TCB, 0, 0);
  2155. snd_emu10k1_ptr_write(emu, TCBS, 0, 0);
  2156. if (emu->fx8010.etram_pages.area != NULL) {
  2157. snd_dma_free_pages(&emu->fx8010.etram_pages);
  2158. emu->fx8010.etram_pages.area = NULL;
  2159. emu->fx8010.etram_pages.bytes = 0;
  2160. }
  2161. if (size > 0) {
  2162. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(emu->pci),
  2163. size * 2, &emu->fx8010.etram_pages) < 0)
  2164. return -ENOMEM;
  2165. memset(emu->fx8010.etram_pages.area, 0, size * 2);
  2166. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2167. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2168. spin_lock_irq(&emu->emu_lock);
  2169. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2170. spin_unlock_irq(&emu->emu_lock);
  2171. }
  2172. return 0;
  2173. }
  2174. static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
  2175. {
  2176. return 0;
  2177. }
  2178. static void copy_string(char *dst, char *src, char *null, int idx)
  2179. {
  2180. if (src == NULL)
  2181. sprintf(dst, "%s %02X", null, idx);
  2182. else
  2183. strcpy(dst, src);
  2184. }
  2185. static int snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
  2186. struct snd_emu10k1_fx8010_info *info)
  2187. {
  2188. char **fxbus, **extin, **extout;
  2189. unsigned short fxbus_mask, extin_mask, extout_mask;
  2190. int res;
  2191. memset(info, 0, sizeof(info));
  2192. info->internal_tram_size = emu->fx8010.itram_size;
  2193. info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
  2194. fxbus = fxbuses;
  2195. extin = emu->audigy ? audigy_ins : creative_ins;
  2196. extout = emu->audigy ? audigy_outs : creative_outs;
  2197. fxbus_mask = emu->fx8010.fxbus_mask;
  2198. extin_mask = emu->fx8010.extin_mask;
  2199. extout_mask = emu->fx8010.extout_mask;
  2200. for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
  2201. copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res);
  2202. copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
  2203. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2204. }
  2205. for (res = 16; res < 32; res++, extout++)
  2206. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2207. info->gpr_controls = emu->fx8010.gpr_count;
  2208. return 0;
  2209. }
  2210. static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
  2211. {
  2212. struct snd_emu10k1 *emu = hw->private_data;
  2213. struct snd_emu10k1_fx8010_info *info;
  2214. struct snd_emu10k1_fx8010_code *icode;
  2215. struct snd_emu10k1_fx8010_pcm_rec *ipcm;
  2216. unsigned int addr;
  2217. void __user *argp = (void __user *)arg;
  2218. int res;
  2219. switch (cmd) {
  2220. case SNDRV_EMU10K1_IOCTL_PVERSION:
  2221. emu->support_tlv = 1;
  2222. return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
  2223. case SNDRV_EMU10K1_IOCTL_INFO:
  2224. info = kmalloc(sizeof(*info), GFP_KERNEL);
  2225. if (!info)
  2226. return -ENOMEM;
  2227. if ((res = snd_emu10k1_fx8010_info(emu, info)) < 0) {
  2228. kfree(info);
  2229. return res;
  2230. }
  2231. if (copy_to_user(argp, info, sizeof(*info))) {
  2232. kfree(info);
  2233. return -EFAULT;
  2234. }
  2235. kfree(info);
  2236. return 0;
  2237. case SNDRV_EMU10K1_IOCTL_CODE_POKE:
  2238. if (!capable(CAP_SYS_ADMIN))
  2239. return -EPERM;
  2240. icode = kmalloc(sizeof(*icode), GFP_KERNEL);
  2241. if (icode == NULL)
  2242. return -ENOMEM;
  2243. if (copy_from_user(icode, argp, sizeof(*icode))) {
  2244. kfree(icode);
  2245. return -EFAULT;
  2246. }
  2247. res = snd_emu10k1_icode_poke(emu, icode);
  2248. kfree(icode);
  2249. return res;
  2250. case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
  2251. icode = kmalloc(sizeof(*icode), GFP_KERNEL);
  2252. if (icode == NULL)
  2253. return -ENOMEM;
  2254. if (copy_from_user(icode, argp, sizeof(*icode))) {
  2255. kfree(icode);
  2256. return -EFAULT;
  2257. }
  2258. res = snd_emu10k1_icode_peek(emu, icode);
  2259. if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
  2260. kfree(icode);
  2261. return -EFAULT;
  2262. }
  2263. kfree(icode);
  2264. return res;
  2265. case SNDRV_EMU10K1_IOCTL_PCM_POKE:
  2266. ipcm = kmalloc(sizeof(*ipcm), GFP_KERNEL);
  2267. if (ipcm == NULL)
  2268. return -ENOMEM;
  2269. if (copy_from_user(ipcm, argp, sizeof(*ipcm))) {
  2270. kfree(ipcm);
  2271. return -EFAULT;
  2272. }
  2273. res = snd_emu10k1_ipcm_poke(emu, ipcm);
  2274. kfree(ipcm);
  2275. return res;
  2276. case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
  2277. ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);
  2278. if (ipcm == NULL)
  2279. return -ENOMEM;
  2280. if (copy_from_user(ipcm, argp, sizeof(*ipcm))) {
  2281. kfree(ipcm);
  2282. return -EFAULT;
  2283. }
  2284. res = snd_emu10k1_ipcm_peek(emu, ipcm);
  2285. if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
  2286. kfree(ipcm);
  2287. return -EFAULT;
  2288. }
  2289. kfree(ipcm);
  2290. return res;
  2291. case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
  2292. if (!capable(CAP_SYS_ADMIN))
  2293. return -EPERM;
  2294. if (get_user(addr, (unsigned int __user *)argp))
  2295. return -EFAULT;
  2296. mutex_lock(&emu->fx8010.lock);
  2297. res = snd_emu10k1_fx8010_tram_setup(emu, addr);
  2298. mutex_unlock(&emu->fx8010.lock);
  2299. return res;
  2300. case SNDRV_EMU10K1_IOCTL_STOP:
  2301. if (!capable(CAP_SYS_ADMIN))
  2302. return -EPERM;
  2303. if (emu->audigy)
  2304. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
  2305. else
  2306. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
  2307. return 0;
  2308. case SNDRV_EMU10K1_IOCTL_CONTINUE:
  2309. if (!capable(CAP_SYS_ADMIN))
  2310. return -EPERM;
  2311. if (emu->audigy)
  2312. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
  2313. else
  2314. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
  2315. return 0;
  2316. case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
  2317. if (!capable(CAP_SYS_ADMIN))
  2318. return -EPERM;
  2319. if (emu->audigy)
  2320. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
  2321. else
  2322. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
  2323. udelay(10);
  2324. if (emu->audigy)
  2325. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2326. else
  2327. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2328. return 0;
  2329. case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
  2330. if (!capable(CAP_SYS_ADMIN))
  2331. return -EPERM;
  2332. if (get_user(addr, (unsigned int __user *)argp))
  2333. return -EFAULT;
  2334. if (addr > 0x1ff)
  2335. return -EINVAL;
  2336. if (emu->audigy)
  2337. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr);
  2338. else
  2339. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr);
  2340. udelay(10);
  2341. if (emu->audigy)
  2342. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr);
  2343. else
  2344. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr);
  2345. return 0;
  2346. case SNDRV_EMU10K1_IOCTL_DBG_READ:
  2347. if (emu->audigy)
  2348. addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
  2349. else
  2350. addr = snd_emu10k1_ptr_read(emu, DBG, 0);
  2351. if (put_user(addr, (unsigned int __user *)argp))
  2352. return -EFAULT;
  2353. return 0;
  2354. }
  2355. return -ENOTTY;
  2356. }
  2357. static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
  2358. {
  2359. return 0;
  2360. }
  2361. int __devinit snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep)
  2362. {
  2363. struct snd_hwdep *hw;
  2364. int err;
  2365. if (rhwdep)
  2366. *rhwdep = NULL;
  2367. if ((err = snd_hwdep_new(emu->card, "FX8010", device, &hw)) < 0)
  2368. return err;
  2369. strcpy(hw->name, "EMU10K1 (FX8010)");
  2370. hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
  2371. hw->ops.open = snd_emu10k1_fx8010_open;
  2372. hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
  2373. hw->ops.release = snd_emu10k1_fx8010_release;
  2374. hw->private_data = emu;
  2375. if (rhwdep)
  2376. *rhwdep = hw;
  2377. return 0;
  2378. }
  2379. #ifdef CONFIG_PM
  2380. int __devinit snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
  2381. {
  2382. int len;
  2383. len = emu->audigy ? 0x200 : 0x100;
  2384. emu->saved_gpr = kmalloc(len * 4, GFP_KERNEL);
  2385. if (! emu->saved_gpr)
  2386. return -ENOMEM;
  2387. len = emu->audigy ? 0x100 : 0xa0;
  2388. emu->tram_val_saved = kmalloc(len * 4, GFP_KERNEL);
  2389. emu->tram_addr_saved = kmalloc(len * 4, GFP_KERNEL);
  2390. if (! emu->tram_val_saved || ! emu->tram_addr_saved)
  2391. return -ENOMEM;
  2392. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2393. emu->saved_icode = vmalloc(len * 4);
  2394. if (! emu->saved_icode)
  2395. return -ENOMEM;
  2396. return 0;
  2397. }
  2398. void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
  2399. {
  2400. kfree(emu->saved_gpr);
  2401. kfree(emu->tram_val_saved);
  2402. kfree(emu->tram_addr_saved);
  2403. vfree(emu->saved_icode);
  2404. }
  2405. /*
  2406. * save/restore GPR, TRAM and codes
  2407. */
  2408. void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
  2409. {
  2410. int i, len;
  2411. len = emu->audigy ? 0x200 : 0x100;
  2412. for (i = 0; i < len; i++)
  2413. emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
  2414. len = emu->audigy ? 0x100 : 0xa0;
  2415. for (i = 0; i < len; i++) {
  2416. emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
  2417. emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
  2418. if (emu->audigy) {
  2419. emu->tram_addr_saved[i] >>= 12;
  2420. emu->tram_addr_saved[i] |=
  2421. snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
  2422. }
  2423. }
  2424. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2425. for (i = 0; i < len; i++)
  2426. emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
  2427. }
  2428. void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
  2429. {
  2430. int i, len;
  2431. /* set up TRAM */
  2432. if (emu->fx8010.etram_pages.bytes > 0) {
  2433. unsigned size, size_reg = 0;
  2434. size = emu->fx8010.etram_pages.bytes / 2;
  2435. size = (size - 1) >> 13;
  2436. while (size) {
  2437. size >>= 1;
  2438. size_reg++;
  2439. }
  2440. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2441. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2442. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2443. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2444. }
  2445. if (emu->audigy)
  2446. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  2447. else
  2448. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  2449. len = emu->audigy ? 0x200 : 0x100;
  2450. for (i = 0; i < len; i++)
  2451. snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
  2452. len = emu->audigy ? 0x100 : 0xa0;
  2453. for (i = 0; i < len; i++) {
  2454. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
  2455. emu->tram_val_saved[i]);
  2456. if (! emu->audigy)
  2457. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2458. emu->tram_addr_saved[i]);
  2459. else {
  2460. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2461. emu->tram_addr_saved[i] << 12);
  2462. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2463. emu->tram_addr_saved[i] >> 20);
  2464. }
  2465. }
  2466. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2467. for (i = 0; i < len; i++)
  2468. snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
  2469. /* start FX processor when the DSP code is updated */
  2470. if (emu->audigy)
  2471. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2472. else
  2473. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2474. }
  2475. #endif