hw_irq.h 2.6 KB

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  1. #ifndef __ASM_SH_HW_IRQ_H
  2. #define __ASM_SH_HW_IRQ_H
  3. #include <linux/init.h>
  4. #include <asm/atomic.h>
  5. extern atomic_t irq_err_count;
  6. struct ipr_data {
  7. unsigned char irq;
  8. unsigned char ipr_idx; /* Index for the IPR registered */
  9. unsigned char shift; /* Number of bits to shift the data */
  10. unsigned char priority; /* The priority */
  11. };
  12. struct ipr_desc {
  13. unsigned long *ipr_offsets;
  14. unsigned int nr_offsets;
  15. struct ipr_data *ipr_data;
  16. unsigned int nr_irqs;
  17. struct irq_chip chip;
  18. };
  19. void register_ipr_controller(struct ipr_desc *);
  20. typedef unsigned char intc_enum;
  21. struct intc_vect {
  22. intc_enum enum_id;
  23. unsigned short vect;
  24. };
  25. #define INTC_VECT(enum_id, vect) { enum_id, vect }
  26. #define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
  27. struct intc_prio {
  28. intc_enum enum_id;
  29. unsigned char priority;
  30. };
  31. #define INTC_PRIO(enum_id, prio) { enum_id, prio }
  32. struct intc_group {
  33. intc_enum enum_id;
  34. intc_enum enum_ids[32];
  35. };
  36. #define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
  37. struct intc_mask_reg {
  38. unsigned long set_reg, clr_reg, reg_width;
  39. intc_enum enum_ids[32];
  40. #ifdef CONFIG_SMP
  41. unsigned long smp;
  42. #endif
  43. };
  44. struct intc_prio_reg {
  45. unsigned long set_reg, clr_reg, reg_width, field_width;
  46. intc_enum enum_ids[16];
  47. #ifdef CONFIG_SMP
  48. unsigned long smp;
  49. #endif
  50. };
  51. struct intc_sense_reg {
  52. unsigned long reg, reg_width, field_width;
  53. intc_enum enum_ids[16];
  54. };
  55. #ifdef CONFIG_SMP
  56. #define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
  57. #else
  58. #define INTC_SMP(stride, nr)
  59. #endif
  60. struct intc_desc {
  61. struct intc_vect *vectors;
  62. unsigned int nr_vectors;
  63. struct intc_group *groups;
  64. unsigned int nr_groups;
  65. struct intc_prio *priorities;
  66. unsigned int nr_priorities;
  67. struct intc_mask_reg *mask_regs;
  68. unsigned int nr_mask_regs;
  69. struct intc_prio_reg *prio_regs;
  70. unsigned int nr_prio_regs;
  71. struct intc_sense_reg *sense_regs;
  72. unsigned int nr_sense_regs;
  73. char *name;
  74. };
  75. #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
  76. #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
  77. priorities, mask_regs, prio_regs, sense_regs) \
  78. struct intc_desc symbol __initdata = { \
  79. _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
  80. _INTC_ARRAY(priorities), \
  81. _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
  82. _INTC_ARRAY(sense_regs), \
  83. chipname, \
  84. }
  85. void __init register_intc_controller(struct intc_desc *desc);
  86. int intc_set_priority(unsigned int irq, unsigned int prio);
  87. void __init plat_irq_setup(void);
  88. enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
  89. IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
  90. IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
  91. void __init plat_irq_setup_pins(int mode);
  92. #endif /* __ASM_SH_HW_IRQ_H */