gpio.h 1.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566
  1. /*
  2. * include/asm-sh/cpu-sh3/gpio.h
  3. *
  4. * Copyright (C) 2007 Markus Brunner, Mark Jonas
  5. *
  6. * Addresses for the Pin Function Controller
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #ifndef _CPU_SH3_GPIO_H
  13. #define _CPU_SH3_GPIO_H
  14. #if defined(CONFIG_CPU_SUBTYPE_SH7720)
  15. /* Control registers */
  16. #define PORT_PACR 0xA4050100UL
  17. #define PORT_PBCR 0xA4050102UL
  18. #define PORT_PCCR 0xA4050104UL
  19. #define PORT_PDCR 0xA4050106UL
  20. #define PORT_PECR 0xA4050108UL
  21. #define PORT_PFCR 0xA405010AUL
  22. #define PORT_PGCR 0xA405010CUL
  23. #define PORT_PHCR 0xA405010EUL
  24. #define PORT_PJCR 0xA4050110UL
  25. #define PORT_PKCR 0xA4050112UL
  26. #define PORT_PLCR 0xA4050114UL
  27. #define PORT_PMCR 0xA4050116UL
  28. #define PORT_PPCR 0xA4050118UL
  29. #define PORT_PRCR 0xA405011AUL
  30. #define PORT_PSCR 0xA405011CUL
  31. #define PORT_PTCR 0xA405011EUL
  32. #define PORT_PUCR 0xA4050120UL
  33. #define PORT_PVCR 0xA4050122UL
  34. /* Data registers */
  35. #define PORT_PADR 0xA4050140UL
  36. /* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
  37. #define PORT_PBDR 0xA4050142UL
  38. #define PORT_PCDR 0xA4050144UL
  39. #define PORT_PDDR 0xA4050146UL
  40. #define PORT_PEDR 0xA4050148UL
  41. #define PORT_PFDR 0xA405014AUL
  42. #define PORT_PGDR 0xA405014CUL
  43. #define PORT_PHDR 0xA405014EUL
  44. #define PORT_PJDR 0xA4050150UL
  45. #define PORT_PKDR 0xA4050152UL
  46. #define PORT_PLDR 0xA4050154UL
  47. #define PORT_PMDR 0xA4050156UL
  48. #define PORT_PPDR 0xA4050158UL
  49. #define PORT_PRDR 0xA405015AUL
  50. #define PORT_PSDR 0xA405015CUL
  51. #define PORT_PTDR 0xA405015EUL
  52. #define PORT_PUDR 0xA4050160UL
  53. #define PORT_PVDR 0xA4050162UL
  54. /* Pin Select Registers */
  55. #define PORT_PSELA 0xA4050124UL
  56. #define PORT_PSELB 0xA4050126UL
  57. #define PORT_PSELC 0xA4050128UL
  58. #define PORT_PSELD 0xA405012AUL
  59. #endif
  60. #endif