pgtable-64k.h 3.9 KB

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  1. #ifndef _ASM_POWERPC_PGTABLE_64K_H
  2. #define _ASM_POWERPC_PGTABLE_64K_H
  3. #include <asm-generic/pgtable-nopud.h>
  4. #define PTE_INDEX_SIZE 12
  5. #define PMD_INDEX_SIZE 12
  6. #define PUD_INDEX_SIZE 0
  7. #define PGD_INDEX_SIZE 4
  8. #ifndef __ASSEMBLY__
  9. #define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
  10. #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
  11. #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
  12. #endif /* __ASSEMBLY__ */
  13. #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
  14. #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
  15. #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
  16. /* With 4k base page size, hugepage PTEs go at the PMD level */
  17. #define MIN_HUGEPTE_SHIFT PAGE_SHIFT
  18. /* PMD_SHIFT determines what a second-level page table entry can map */
  19. #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
  20. #define PMD_SIZE (1UL << PMD_SHIFT)
  21. #define PMD_MASK (~(PMD_SIZE-1))
  22. /* PGDIR_SHIFT determines what a third-level page table entry can map */
  23. #define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
  24. #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
  25. #define PGDIR_MASK (~(PGDIR_SIZE-1))
  26. /* Additional PTE bits (don't change without checking asm in hash_low.S) */
  27. #define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
  28. #define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
  29. #define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
  30. #define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */
  31. /* Note the full page bits must be in the same location as for normal
  32. * 4k pages as the same asssembly will be used to insert 64K pages
  33. * wether the kernel has CONFIG_PPC_64K_PAGES or not
  34. */
  35. #define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
  36. #define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
  37. /* PTE flags to conserve for HPTE identification */
  38. #define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\
  39. _PAGE_COMBO)
  40. /* Shift to put page number into pte.
  41. *
  42. * That gives us a max RPN of 34 bits, which means a max of 50 bits
  43. * of addressable physical space, or 46 bits for the special 4k PFNs.
  44. */
  45. #define PTE_RPN_SHIFT (30)
  46. #define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
  47. #define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
  48. /* _PAGE_CHG_MASK masks of bits that are to be preserved accross
  49. * pgprot changes
  50. */
  51. #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
  52. _PAGE_ACCESSED)
  53. /* Bits to mask out from a PMD to get to the PTE page */
  54. #define PMD_MASKED_BITS 0x1ff
  55. /* Bits to mask out from a PGD/PUD to get to the PMD page */
  56. #define PUD_MASKED_BITS 0x1ff
  57. /* Manipulate "rpte" values */
  58. #define __real_pte(e,p) ((real_pte_t) { \
  59. (e), pte_val(*((p) + PTRS_PER_PTE)) })
  60. #define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
  61. (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
  62. #define __rpte_to_pte(r) ((r).pte)
  63. #define __rpte_sub_valid(rpte, index) \
  64. (pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
  65. /* Trick: we set __end to va + 64k, which happens works for
  66. * a 16M page as well as we want only one iteration
  67. */
  68. #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
  69. do { \
  70. unsigned long __end = va + PAGE_SIZE; \
  71. unsigned __split = (psize == MMU_PAGE_4K || \
  72. psize == MMU_PAGE_64K_AP); \
  73. shift = mmu_psize_defs[psize].shift; \
  74. for (index = 0; va < __end; index++, va += (1 << shift)) { \
  75. if (!__split || __rpte_sub_valid(rpte, index)) do { \
  76. #define pte_iterate_hashed_end() } while(0); } } while(0)
  77. #define pte_pagesize_index(mm, addr, pte) \
  78. (((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
  79. #define remap_4k_pfn(vma, addr, pfn, prot) \
  80. remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
  81. __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
  82. #endif /* _ASM_POWERPC_PGTABLE_64K_H */