dma-mapping.h 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400
  1. /*
  2. * Copyright (C) 2004 IBM
  3. *
  4. * Implements the generic device dma API for powerpc.
  5. * the pci and vio busses
  6. */
  7. #ifndef _ASM_DMA_MAPPING_H
  8. #define _ASM_DMA_MAPPING_H
  9. #ifdef __KERNEL__
  10. #include <linux/types.h>
  11. #include <linux/cache.h>
  12. /* need struct page definitions */
  13. #include <linux/mm.h>
  14. #include <asm/scatterlist.h>
  15. #include <asm/io.h>
  16. #define DMA_ERROR_CODE (~(dma_addr_t)0x0)
  17. #ifdef CONFIG_NOT_COHERENT_CACHE
  18. /*
  19. * DMA-consistent mapping functions for PowerPCs that don't support
  20. * cache snooping. These allocate/free a region of uncached mapped
  21. * memory space for use with DMA devices. Alternatively, you could
  22. * allocate the space "normally" and use the cache management functions
  23. * to ensure it is consistent.
  24. */
  25. extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp);
  26. extern void __dma_free_coherent(size_t size, void *vaddr);
  27. extern void __dma_sync(void *vaddr, size_t size, int direction);
  28. extern void __dma_sync_page(struct page *page, unsigned long offset,
  29. size_t size, int direction);
  30. #else /* ! CONFIG_NOT_COHERENT_CACHE */
  31. /*
  32. * Cache coherent cores.
  33. */
  34. #define __dma_alloc_coherent(gfp, size, handle) NULL
  35. #define __dma_free_coherent(size, addr) ((void)0)
  36. #define __dma_sync(addr, size, rw) ((void)0)
  37. #define __dma_sync_page(pg, off, sz, rw) ((void)0)
  38. #endif /* ! CONFIG_NOT_COHERENT_CACHE */
  39. #ifdef CONFIG_PPC64
  40. /*
  41. * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
  42. */
  43. struct dma_mapping_ops {
  44. void * (*alloc_coherent)(struct device *dev, size_t size,
  45. dma_addr_t *dma_handle, gfp_t flag);
  46. void (*free_coherent)(struct device *dev, size_t size,
  47. void *vaddr, dma_addr_t dma_handle);
  48. dma_addr_t (*map_single)(struct device *dev, void *ptr,
  49. size_t size, enum dma_data_direction direction);
  50. void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
  51. size_t size, enum dma_data_direction direction);
  52. int (*map_sg)(struct device *dev, struct scatterlist *sg,
  53. int nents, enum dma_data_direction direction);
  54. void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
  55. int nents, enum dma_data_direction direction);
  56. int (*dma_supported)(struct device *dev, u64 mask);
  57. int (*set_dma_mask)(struct device *dev, u64 dma_mask);
  58. };
  59. static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
  60. {
  61. /* We don't handle the NULL dev case for ISA for now. We could
  62. * do it via an out of line call but it is not needed for now. The
  63. * only ISA DMA device we support is the floppy and we have a hack
  64. * in the floppy driver directly to get a device for us.
  65. */
  66. if (unlikely(dev == NULL || dev->archdata.dma_ops == NULL))
  67. return NULL;
  68. return dev->archdata.dma_ops;
  69. }
  70. static inline int dma_supported(struct device *dev, u64 mask)
  71. {
  72. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  73. if (unlikely(dma_ops == NULL))
  74. return 0;
  75. if (dma_ops->dma_supported == NULL)
  76. return 1;
  77. return dma_ops->dma_supported(dev, mask);
  78. }
  79. static inline int dma_set_mask(struct device *dev, u64 dma_mask)
  80. {
  81. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  82. if (unlikely(dma_ops == NULL))
  83. return -EIO;
  84. if (dma_ops->set_dma_mask != NULL)
  85. return dma_ops->set_dma_mask(dev, dma_mask);
  86. if (!dev->dma_mask || !dma_supported(dev, dma_mask))
  87. return -EIO;
  88. *dev->dma_mask = dma_mask;
  89. return 0;
  90. }
  91. static inline void *dma_alloc_coherent(struct device *dev, size_t size,
  92. dma_addr_t *dma_handle, gfp_t flag)
  93. {
  94. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  95. BUG_ON(!dma_ops);
  96. return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
  97. }
  98. static inline void dma_free_coherent(struct device *dev, size_t size,
  99. void *cpu_addr, dma_addr_t dma_handle)
  100. {
  101. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  102. BUG_ON(!dma_ops);
  103. dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
  104. }
  105. static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
  106. size_t size,
  107. enum dma_data_direction direction)
  108. {
  109. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  110. BUG_ON(!dma_ops);
  111. return dma_ops->map_single(dev, cpu_addr, size, direction);
  112. }
  113. static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
  114. size_t size,
  115. enum dma_data_direction direction)
  116. {
  117. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  118. BUG_ON(!dma_ops);
  119. dma_ops->unmap_single(dev, dma_addr, size, direction);
  120. }
  121. static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
  122. unsigned long offset, size_t size,
  123. enum dma_data_direction direction)
  124. {
  125. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  126. BUG_ON(!dma_ops);
  127. return dma_ops->map_single(dev, page_address(page) + offset, size,
  128. direction);
  129. }
  130. static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
  131. size_t size,
  132. enum dma_data_direction direction)
  133. {
  134. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  135. BUG_ON(!dma_ops);
  136. dma_ops->unmap_single(dev, dma_address, size, direction);
  137. }
  138. static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
  139. int nents, enum dma_data_direction direction)
  140. {
  141. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  142. BUG_ON(!dma_ops);
  143. return dma_ops->map_sg(dev, sg, nents, direction);
  144. }
  145. static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
  146. int nhwentries,
  147. enum dma_data_direction direction)
  148. {
  149. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  150. BUG_ON(!dma_ops);
  151. dma_ops->unmap_sg(dev, sg, nhwentries, direction);
  152. }
  153. /*
  154. * Available generic sets of operations
  155. */
  156. extern struct dma_mapping_ops dma_iommu_ops;
  157. extern struct dma_mapping_ops dma_direct_ops;
  158. extern unsigned long dma_direct_offset;
  159. #else /* CONFIG_PPC64 */
  160. #define dma_supported(dev, mask) (1)
  161. static inline int dma_set_mask(struct device *dev, u64 dma_mask)
  162. {
  163. if (!dev->dma_mask || !dma_supported(dev, mask))
  164. return -EIO;
  165. *dev->dma_mask = dma_mask;
  166. return 0;
  167. }
  168. static inline void *dma_alloc_coherent(struct device *dev, size_t size,
  169. dma_addr_t * dma_handle,
  170. gfp_t gfp)
  171. {
  172. #ifdef CONFIG_NOT_COHERENT_CACHE
  173. return __dma_alloc_coherent(size, dma_handle, gfp);
  174. #else
  175. void *ret;
  176. /* ignore region specifiers */
  177. gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
  178. if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
  179. gfp |= GFP_DMA;
  180. ret = (void *)__get_free_pages(gfp, get_order(size));
  181. if (ret != NULL) {
  182. memset(ret, 0, size);
  183. *dma_handle = virt_to_bus(ret);
  184. }
  185. return ret;
  186. #endif
  187. }
  188. static inline void
  189. dma_free_coherent(struct device *dev, size_t size, void *vaddr,
  190. dma_addr_t dma_handle)
  191. {
  192. #ifdef CONFIG_NOT_COHERENT_CACHE
  193. __dma_free_coherent(size, vaddr);
  194. #else
  195. free_pages((unsigned long)vaddr, get_order(size));
  196. #endif
  197. }
  198. static inline dma_addr_t
  199. dma_map_single(struct device *dev, void *ptr, size_t size,
  200. enum dma_data_direction direction)
  201. {
  202. BUG_ON(direction == DMA_NONE);
  203. __dma_sync(ptr, size, direction);
  204. return virt_to_bus(ptr);
  205. }
  206. static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
  207. size_t size,
  208. enum dma_data_direction direction)
  209. {
  210. /* We do nothing. */
  211. }
  212. static inline dma_addr_t
  213. dma_map_page(struct device *dev, struct page *page,
  214. unsigned long offset, size_t size,
  215. enum dma_data_direction direction)
  216. {
  217. BUG_ON(direction == DMA_NONE);
  218. __dma_sync_page(page, offset, size, direction);
  219. return page_to_bus(page) + offset;
  220. }
  221. static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
  222. size_t size,
  223. enum dma_data_direction direction)
  224. {
  225. /* We do nothing. */
  226. }
  227. static inline int
  228. dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
  229. enum dma_data_direction direction)
  230. {
  231. int i;
  232. BUG_ON(direction == DMA_NONE);
  233. for (i = 0; i < nents; i++, sg++) {
  234. BUG_ON(!sg->page);
  235. __dma_sync_page(sg->page, sg->offset, sg->length, direction);
  236. sg->dma_address = page_to_bus(sg->page) + sg->offset;
  237. }
  238. return nents;
  239. }
  240. static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
  241. int nhwentries,
  242. enum dma_data_direction direction)
  243. {
  244. /* We don't do anything here. */
  245. }
  246. #endif /* CONFIG_PPC64 */
  247. static inline void dma_sync_single_for_cpu(struct device *dev,
  248. dma_addr_t dma_handle, size_t size,
  249. enum dma_data_direction direction)
  250. {
  251. BUG_ON(direction == DMA_NONE);
  252. __dma_sync(bus_to_virt(dma_handle), size, direction);
  253. }
  254. static inline void dma_sync_single_for_device(struct device *dev,
  255. dma_addr_t dma_handle, size_t size,
  256. enum dma_data_direction direction)
  257. {
  258. BUG_ON(direction == DMA_NONE);
  259. __dma_sync(bus_to_virt(dma_handle), size, direction);
  260. }
  261. static inline void dma_sync_sg_for_cpu(struct device *dev,
  262. struct scatterlist *sg, int nents,
  263. enum dma_data_direction direction)
  264. {
  265. int i;
  266. BUG_ON(direction == DMA_NONE);
  267. for (i = 0; i < nents; i++, sg++)
  268. __dma_sync_page(sg->page, sg->offset, sg->length, direction);
  269. }
  270. static inline void dma_sync_sg_for_device(struct device *dev,
  271. struct scatterlist *sg, int nents,
  272. enum dma_data_direction direction)
  273. {
  274. int i;
  275. BUG_ON(direction == DMA_NONE);
  276. for (i = 0; i < nents; i++, sg++)
  277. __dma_sync_page(sg->page, sg->offset, sg->length, direction);
  278. }
  279. static inline int dma_mapping_error(dma_addr_t dma_addr)
  280. {
  281. #ifdef CONFIG_PPC64
  282. return (dma_addr == DMA_ERROR_CODE);
  283. #else
  284. return 0;
  285. #endif
  286. }
  287. #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
  288. #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
  289. #ifdef CONFIG_NOT_COHERENT_CACHE
  290. #define dma_is_consistent(d, h) (0)
  291. #else
  292. #define dma_is_consistent(d, h) (1)
  293. #endif
  294. static inline int dma_get_cache_alignment(void)
  295. {
  296. #ifdef CONFIG_PPC64
  297. /* no easy way to get cache size on all processors, so return
  298. * the maximum possible, to be safe */
  299. return (1 << INTERNODE_CACHE_SHIFT);
  300. #else
  301. /*
  302. * Each processor family will define its own L1_CACHE_SHIFT,
  303. * L1_CACHE_BYTES wraps to this, so this is always safe.
  304. */
  305. return L1_CACHE_BYTES;
  306. #endif
  307. }
  308. static inline void dma_sync_single_range_for_cpu(struct device *dev,
  309. dma_addr_t dma_handle, unsigned long offset, size_t size,
  310. enum dma_data_direction direction)
  311. {
  312. /* just sync everything for now */
  313. dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
  314. }
  315. static inline void dma_sync_single_range_for_device(struct device *dev,
  316. dma_addr_t dma_handle, unsigned long offset, size_t size,
  317. enum dma_data_direction direction)
  318. {
  319. /* just sync everything for now */
  320. dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
  321. }
  322. static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
  323. enum dma_data_direction direction)
  324. {
  325. BUG_ON(direction == DMA_NONE);
  326. __dma_sync(vaddr, size, (int)direction);
  327. }
  328. #endif /* __KERNEL__ */
  329. #endif /* _ASM_DMA_MAPPING_H */