system.h 8.7 KB

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  1. #ifndef _ASM_IA64_SYSTEM_H
  2. #define _ASM_IA64_SYSTEM_H
  3. /*
  4. * System defines. Note that this is included both from .c and .S
  5. * files, so it does only defines, not any C code. This is based
  6. * on information published in the Processor Abstraction Layer
  7. * and the System Abstraction Layer manual.
  8. *
  9. * Copyright (C) 1998-2003 Hewlett-Packard Co
  10. * David Mosberger-Tang <davidm@hpl.hp.com>
  11. * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
  12. * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  13. */
  14. #include <asm/kregs.h>
  15. #include <asm/page.h>
  16. #include <asm/pal.h>
  17. #include <asm/percpu.h>
  18. #define GATE_ADDR RGN_BASE(RGN_GATE)
  19. /*
  20. * 0xa000000000000000+2*PERCPU_PAGE_SIZE
  21. * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
  22. */
  23. #define KERNEL_START (GATE_ADDR+__IA64_UL_CONST(0x100000000))
  24. #define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
  25. #ifndef __ASSEMBLY__
  26. #include <linux/kernel.h>
  27. #include <linux/types.h>
  28. struct pci_vector_struct {
  29. __u16 segment; /* PCI Segment number */
  30. __u16 bus; /* PCI Bus number */
  31. __u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
  32. __u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
  33. __u32 irq; /* IRQ assigned */
  34. };
  35. extern struct ia64_boot_param {
  36. __u64 command_line; /* physical address of command line arguments */
  37. __u64 efi_systab; /* physical address of EFI system table */
  38. __u64 efi_memmap; /* physical address of EFI memory map */
  39. __u64 efi_memmap_size; /* size of EFI memory map */
  40. __u64 efi_memdesc_size; /* size of an EFI memory map descriptor */
  41. __u32 efi_memdesc_version; /* memory descriptor version */
  42. struct {
  43. __u16 num_cols; /* number of columns on console output device */
  44. __u16 num_rows; /* number of rows on console output device */
  45. __u16 orig_x; /* cursor's x position */
  46. __u16 orig_y; /* cursor's y position */
  47. } console_info;
  48. __u64 fpswa; /* physical address of the fpswa interface */
  49. __u64 initrd_start;
  50. __u64 initrd_size;
  51. } *ia64_boot_param;
  52. /*
  53. * Macros to force memory ordering. In these descriptions, "previous"
  54. * and "subsequent" refer to program order; "visible" means that all
  55. * architecturally visible effects of a memory access have occurred
  56. * (at a minimum, this means the memory has been read or written).
  57. *
  58. * wmb(): Guarantees that all preceding stores to memory-
  59. * like regions are visible before any subsequent
  60. * stores and that all following stores will be
  61. * visible only after all previous stores.
  62. * rmb(): Like wmb(), but for reads.
  63. * mb(): wmb()/rmb() combo, i.e., all previous memory
  64. * accesses are visible before all subsequent
  65. * accesses and vice versa. This is also known as
  66. * a "fence."
  67. *
  68. * Note: "mb()" and its variants cannot be used as a fence to order
  69. * accesses to memory mapped I/O registers. For that, mf.a needs to
  70. * be used. However, we don't want to always use mf.a because (a)
  71. * it's (presumably) much slower than mf and (b) mf.a is supported for
  72. * sequential memory pages only.
  73. */
  74. #define mb() ia64_mf()
  75. #define rmb() mb()
  76. #define wmb() mb()
  77. #define read_barrier_depends() do { } while(0)
  78. #ifdef CONFIG_SMP
  79. # define smp_mb() mb()
  80. # define smp_rmb() rmb()
  81. # define smp_wmb() wmb()
  82. # define smp_read_barrier_depends() read_barrier_depends()
  83. #else
  84. # define smp_mb() barrier()
  85. # define smp_rmb() barrier()
  86. # define smp_wmb() barrier()
  87. # define smp_read_barrier_depends() do { } while(0)
  88. #endif
  89. /*
  90. * XXX check on this ---I suspect what Linus really wants here is
  91. * acquire vs release semantics but we can't discuss this stuff with
  92. * Linus just yet. Grrr...
  93. */
  94. #define set_mb(var, value) do { (var) = (value); mb(); } while (0)
  95. #define safe_halt() ia64_pal_halt_light() /* PAL_HALT_LIGHT */
  96. /*
  97. * The group barrier in front of the rsm & ssm are necessary to ensure
  98. * that none of the previous instructions in the same group are
  99. * affected by the rsm/ssm.
  100. */
  101. /* For spinlocks etc */
  102. /*
  103. * - clearing psr.i is implicitly serialized (visible by next insn)
  104. * - setting psr.i requires data serialization
  105. * - we need a stop-bit before reading PSR because we sometimes
  106. * write a floating-point register right before reading the PSR
  107. * and that writes to PSR.mfl
  108. */
  109. #define __local_irq_save(x) \
  110. do { \
  111. ia64_stop(); \
  112. (x) = ia64_getreg(_IA64_REG_PSR); \
  113. ia64_stop(); \
  114. ia64_rsm(IA64_PSR_I); \
  115. } while (0)
  116. #define __local_irq_disable() \
  117. do { \
  118. ia64_stop(); \
  119. ia64_rsm(IA64_PSR_I); \
  120. } while (0)
  121. #define __local_irq_restore(x) ia64_intrin_local_irq_restore((x) & IA64_PSR_I)
  122. #ifdef CONFIG_IA64_DEBUG_IRQ
  123. extern unsigned long last_cli_ip;
  124. # define __save_ip() last_cli_ip = ia64_getreg(_IA64_REG_IP)
  125. # define local_irq_save(x) \
  126. do { \
  127. unsigned long psr; \
  128. \
  129. __local_irq_save(psr); \
  130. if (psr & IA64_PSR_I) \
  131. __save_ip(); \
  132. (x) = psr; \
  133. } while (0)
  134. # define local_irq_disable() do { unsigned long x; local_irq_save(x); } while (0)
  135. # define local_irq_restore(x) \
  136. do { \
  137. unsigned long old_psr, psr = (x); \
  138. \
  139. local_save_flags(old_psr); \
  140. __local_irq_restore(psr); \
  141. if ((old_psr & IA64_PSR_I) && !(psr & IA64_PSR_I)) \
  142. __save_ip(); \
  143. } while (0)
  144. #else /* !CONFIG_IA64_DEBUG_IRQ */
  145. # define local_irq_save(x) __local_irq_save(x)
  146. # define local_irq_disable() __local_irq_disable()
  147. # define local_irq_restore(x) __local_irq_restore(x)
  148. #endif /* !CONFIG_IA64_DEBUG_IRQ */
  149. #define local_irq_enable() ({ ia64_stop(); ia64_ssm(IA64_PSR_I); ia64_srlz_d(); })
  150. #define local_save_flags(flags) ({ ia64_stop(); (flags) = ia64_getreg(_IA64_REG_PSR); })
  151. #define irqs_disabled() \
  152. ({ \
  153. unsigned long __ia64_id_flags; \
  154. local_save_flags(__ia64_id_flags); \
  155. (__ia64_id_flags & IA64_PSR_I) == 0; \
  156. })
  157. #ifdef __KERNEL__
  158. #ifdef CONFIG_IA32_SUPPORT
  159. # define IS_IA32_PROCESS(regs) (ia64_psr(regs)->is != 0)
  160. #else
  161. # define IS_IA32_PROCESS(regs) 0
  162. struct task_struct;
  163. static inline void ia32_save_state(struct task_struct *t __attribute__((unused))){}
  164. static inline void ia32_load_state(struct task_struct *t __attribute__((unused))){}
  165. #endif
  166. /*
  167. * Context switch from one thread to another. If the two threads have
  168. * different address spaces, schedule() has already taken care of
  169. * switching to the new address space by calling switch_mm().
  170. *
  171. * Disabling access to the fph partition and the debug-register
  172. * context switch MUST be done before calling ia64_switch_to() since a
  173. * newly created thread returns directly to
  174. * ia64_ret_from_syscall_clear_r8.
  175. */
  176. extern struct task_struct *ia64_switch_to (void *next_task);
  177. struct task_struct;
  178. extern void ia64_save_extra (struct task_struct *task);
  179. extern void ia64_load_extra (struct task_struct *task);
  180. #ifdef CONFIG_PERFMON
  181. DECLARE_PER_CPU(unsigned long, pfm_syst_info);
  182. # define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
  183. #else
  184. # define PERFMON_IS_SYSWIDE() (0)
  185. #endif
  186. #define IA64_HAS_EXTRA_STATE(t) \
  187. ((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \
  188. || IS_IA32_PROCESS(task_pt_regs(t)) || PERFMON_IS_SYSWIDE())
  189. #define __switch_to(prev,next,last) do { \
  190. if (IA64_HAS_EXTRA_STATE(prev)) \
  191. ia64_save_extra(prev); \
  192. if (IA64_HAS_EXTRA_STATE(next)) \
  193. ia64_load_extra(next); \
  194. ia64_psr(task_pt_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
  195. (last) = ia64_switch_to((next)); \
  196. } while (0)
  197. #ifdef CONFIG_SMP
  198. /*
  199. * In the SMP case, we save the fph state when context-switching away from a thread that
  200. * modified fph. This way, when the thread gets scheduled on another CPU, the CPU can
  201. * pick up the state from task->thread.fph, avoiding the complication of having to fetch
  202. * the latest fph state from another CPU. In other words: eager save, lazy restore.
  203. */
  204. # define switch_to(prev,next,last) do { \
  205. if (ia64_psr(task_pt_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \
  206. ia64_psr(task_pt_regs(prev))->mfh = 0; \
  207. (prev)->thread.flags |= IA64_THREAD_FPH_VALID; \
  208. __ia64_save_fpu((prev)->thread.fph); \
  209. } \
  210. __switch_to(prev, next, last); \
  211. /* "next" in old context is "current" in new context */ \
  212. if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) && \
  213. (task_cpu(current) != \
  214. task_thread_info(current)->last_cpu))) { \
  215. platform_migrate(current); \
  216. task_thread_info(current)->last_cpu = task_cpu(current); \
  217. } \
  218. } while (0)
  219. #else
  220. # define switch_to(prev,next,last) __switch_to(prev, next, last)
  221. #endif
  222. #define __ARCH_WANT_UNLOCKED_CTXSW
  223. #define ARCH_HAS_PREFETCH_SWITCH_STACK
  224. #define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
  225. void cpu_idle_wait(void);
  226. #define arch_align_stack(x) (x)
  227. void default_idle(void);
  228. #endif /* __KERNEL__ */
  229. #endif /* __ASSEMBLY__ */
  230. #endif /* _ASM_IA64_SYSTEM_H */