pxa2xx_udc.h 6.8 KB

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  1. /*
  2. * linux/drivers/usb/gadget/pxa2xx_udc.h
  3. * Intel PXA2xx on-chip full speed USB device controller
  4. *
  5. * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
  6. * Copyright (C) 2003 David Brownell
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #ifndef __LINUX_USB_GADGET_PXA2XX_H
  24. #define __LINUX_USB_GADGET_PXA2XX_H
  25. #include <linux/types.h>
  26. /*-------------------------------------------------------------------------*/
  27. /* pxa2xx has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
  28. #define UFNRH_SIR (1 << 7) /* SOF interrupt request */
  29. #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */
  30. #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */
  31. #define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */
  32. #define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */
  33. /* pxa255 has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
  34. #define UDCCFR UDC_RES2 /* UDC Control Function Register */
  35. #define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */
  36. #define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */
  37. /* latest pxa255 errata define new "must be one" bits in UDCCFR */
  38. #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN|UDCCFR_ACM))
  39. /*-------------------------------------------------------------------------*/
  40. struct pxa2xx_udc;
  41. struct pxa2xx_ep {
  42. struct usb_ep ep;
  43. struct pxa2xx_udc *dev;
  44. const struct usb_endpoint_descriptor *desc;
  45. struct list_head queue;
  46. unsigned long pio_irqs;
  47. unsigned short fifo_size;
  48. u8 bEndpointAddress;
  49. u8 bmAttributes;
  50. unsigned stopped : 1;
  51. unsigned dma_fixup : 1;
  52. /* UDCCS = UDC Control/Status for this EP
  53. * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
  54. * UDDR = UDC Endpoint Data Register (the fifo)
  55. * DRCM = DMA Request Channel Map
  56. */
  57. volatile u32 *reg_udccs;
  58. volatile u32 *reg_ubcr;
  59. volatile u32 *reg_uddr;
  60. };
  61. struct pxa2xx_request {
  62. struct usb_request req;
  63. struct list_head queue;
  64. };
  65. enum ep0_state {
  66. EP0_IDLE,
  67. EP0_IN_DATA_PHASE,
  68. EP0_OUT_DATA_PHASE,
  69. EP0_END_XFER,
  70. EP0_STALL,
  71. };
  72. #define EP0_FIFO_SIZE ((unsigned)16)
  73. #define BULK_FIFO_SIZE ((unsigned)64)
  74. #define ISO_FIFO_SIZE ((unsigned)256)
  75. #define INT_FIFO_SIZE ((unsigned)8)
  76. struct udc_stats {
  77. struct ep0stats {
  78. unsigned long ops;
  79. unsigned long bytes;
  80. } read, write;
  81. unsigned long irqs;
  82. };
  83. #ifdef CONFIG_USB_PXA2XX_SMALL
  84. /* when memory's tight, SMALL config saves code+data. */
  85. #define PXA_UDC_NUM_ENDPOINTS 3
  86. #endif
  87. #ifndef PXA_UDC_NUM_ENDPOINTS
  88. #define PXA_UDC_NUM_ENDPOINTS 16
  89. #endif
  90. struct pxa2xx_udc {
  91. struct usb_gadget gadget;
  92. struct usb_gadget_driver *driver;
  93. enum ep0_state ep0state;
  94. struct udc_stats stats;
  95. unsigned got_irq : 1,
  96. vbus : 1,
  97. pullup : 1,
  98. has_cfr : 1,
  99. req_pending : 1,
  100. req_std : 1,
  101. req_config : 1;
  102. #define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200))
  103. struct timer_list timer;
  104. struct device *dev;
  105. struct pxa2xx_udc_mach_info *mach;
  106. u64 dma_mask;
  107. struct pxa2xx_ep ep [PXA_UDC_NUM_ENDPOINTS];
  108. };
  109. /*-------------------------------------------------------------------------*/
  110. #ifdef CONFIG_ARCH_LUBBOCK
  111. #include <asm/arch/lubbock.h>
  112. /* lubbock can also report usb connect/disconnect irqs */
  113. #endif
  114. static struct pxa2xx_udc *the_controller;
  115. /*-------------------------------------------------------------------------*/
  116. /*
  117. * Debugging support vanishes in non-debug builds. DBG_NORMAL should be
  118. * mostly silent during normal use/testing, with no timing side-effects.
  119. */
  120. #define DBG_NORMAL 1 /* error paths, device state transitions */
  121. #define DBG_VERBOSE 2 /* add some success path trace info */
  122. #define DBG_NOISY 3 /* ... even more: request level */
  123. #define DBG_VERY_NOISY 4 /* ... even more: packet level */
  124. #ifdef DEBUG
  125. static const char *state_name[] = {
  126. "EP0_IDLE",
  127. "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
  128. "EP0_END_XFER", "EP0_STALL"
  129. };
  130. #define DMSG(stuff...) printk(KERN_DEBUG "udc: " stuff)
  131. #ifdef VERBOSE
  132. # define UDC_DEBUG DBG_VERBOSE
  133. #else
  134. # define UDC_DEBUG DBG_NORMAL
  135. #endif
  136. static void __maybe_unused
  137. dump_udccr(const char *label)
  138. {
  139. u32 udccr = UDCCR;
  140. DMSG("%s %02X =%s%s%s%s%s%s%s%s\n",
  141. label, udccr,
  142. (udccr & UDCCR_REM) ? " rem" : "",
  143. (udccr & UDCCR_RSTIR) ? " rstir" : "",
  144. (udccr & UDCCR_SRM) ? " srm" : "",
  145. (udccr & UDCCR_SUSIR) ? " susir" : "",
  146. (udccr & UDCCR_RESIR) ? " resir" : "",
  147. (udccr & UDCCR_RSM) ? " rsm" : "",
  148. (udccr & UDCCR_UDA) ? " uda" : "",
  149. (udccr & UDCCR_UDE) ? " ude" : "");
  150. }
  151. static void __maybe_unused
  152. dump_udccs0(const char *label)
  153. {
  154. u32 udccs0 = UDCCS0;
  155. DMSG("%s %s %02X =%s%s%s%s%s%s%s%s\n",
  156. label, state_name[the_controller->ep0state], udccs0,
  157. (udccs0 & UDCCS0_SA) ? " sa" : "",
  158. (udccs0 & UDCCS0_RNE) ? " rne" : "",
  159. (udccs0 & UDCCS0_FST) ? " fst" : "",
  160. (udccs0 & UDCCS0_SST) ? " sst" : "",
  161. (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
  162. (udccs0 & UDCCS0_FTF) ? " ftf" : "",
  163. (udccs0 & UDCCS0_IPR) ? " ipr" : "",
  164. (udccs0 & UDCCS0_OPR) ? " opr" : "");
  165. }
  166. static void __maybe_unused
  167. dump_state(struct pxa2xx_udc *dev)
  168. {
  169. u32 tmp;
  170. unsigned i;
  171. DMSG("%s %s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
  172. is_usb_connected() ? "host " : "disconnected",
  173. state_name[dev->ep0state],
  174. UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
  175. dump_udccr("udccr");
  176. if (dev->has_cfr) {
  177. tmp = UDCCFR;
  178. DMSG("udccfr %02X =%s%s\n", tmp,
  179. (tmp & UDCCFR_AREN) ? " aren" : "",
  180. (tmp & UDCCFR_ACM) ? " acm" : "");
  181. }
  182. if (!dev->driver) {
  183. DMSG("no gadget driver bound\n");
  184. return;
  185. } else
  186. DMSG("ep0 driver '%s'\n", dev->driver->driver.name);
  187. if (!is_usb_connected())
  188. return;
  189. dump_udccs0 ("udccs0");
  190. DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n",
  191. dev->stats.write.bytes, dev->stats.write.ops,
  192. dev->stats.read.bytes, dev->stats.read.ops);
  193. for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
  194. if (dev->ep [i].desc == 0)
  195. continue;
  196. DMSG ("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
  197. }
  198. }
  199. #else
  200. #define DMSG(stuff...) do{}while(0)
  201. #define dump_udccr(x) do{}while(0)
  202. #define dump_udccs0(x) do{}while(0)
  203. #define dump_state(x) do{}while(0)
  204. #define UDC_DEBUG ((unsigned)0)
  205. #endif
  206. #define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0)
  207. #define WARN(stuff...) printk(KERN_WARNING "udc: " stuff)
  208. #define INFO(stuff...) printk(KERN_INFO "udc: " stuff)
  209. #endif /* __LINUX_USB_GADGET_PXA2XX_H */