gdth.c 201 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.4.x, 2.6.x supported *
  31. * *
  32. * $Log: gdth.c,v $
  33. * Revision 1.74 2006/04/10 13:44:47 achim
  34. * Community changes for 2.6.x
  35. * Kernel 2.2.x no longer supported
  36. * scsi_request interface removed, thanks to Christoph Hellwig
  37. *
  38. * Revision 1.73 2004/03/31 13:33:03 achim
  39. * Special command 0xfd implemented to detect 64-bit DMA support
  40. *
  41. * Revision 1.72 2004/03/17 08:56:04 achim
  42. * 64-bit DMA only enabled if FW >= x.43
  43. *
  44. * Revision 1.71 2004/03/05 15:51:29 achim
  45. * Screen service: separate message buffer, bugfixes
  46. *
  47. * Revision 1.70 2004/02/27 12:19:07 achim
  48. * Bugfix: Reset bit in config (0xfe) call removed
  49. *
  50. * Revision 1.69 2004/02/20 09:50:24 achim
  51. * Compatibility changes for kernels < 2.4.20
  52. * Bugfix screen service command size
  53. * pci_set_dma_mask() error handling added
  54. *
  55. * Revision 1.68 2004/02/19 15:46:54 achim
  56. * 64-bit DMA bugfixes
  57. * Drive size bugfix for drives > 1TB
  58. *
  59. * Revision 1.67 2004/01/14 13:11:57 achim
  60. * Tool access over /proc no longer supported
  61. * Bugfixes IOCTLs
  62. *
  63. * Revision 1.66 2003/12/19 15:04:06 achim
  64. * Bugfixes support for drives > 2TB
  65. *
  66. * Revision 1.65 2003/12/15 11:21:56 achim
  67. * 64-bit DMA support added
  68. * Support for drives > 2 TB implemented
  69. * Kernels 2.2.x, 2.4.x, 2.6.x supported
  70. *
  71. * Revision 1.64 2003/09/17 08:30:26 achim
  72. * EISA/ISA controller scan disabled
  73. * Command line switch probe_eisa_isa added
  74. *
  75. * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
  76. * Minor cleanups in gdth_ioctl.
  77. *
  78. * Revision 1.62 2003/02/27 15:01:59 achim
  79. * Dynamic DMA mapping implemented
  80. * New (character device) IOCTL interface added
  81. * Other controller related changes made
  82. *
  83. * Revision 1.61 2002/11/08 13:09:52 boji
  84. * Added support for XSCALE based RAID Controllers
  85. * Fixed SCREENSERVICE initialization in SMP cases
  86. * Added checks for gdth_polling before GDTH_HA_LOCK
  87. *
  88. * Revision 1.60 2002/02/05 09:35:22 achim
  89. * MODULE_LICENSE only if kernel >= 2.4.11
  90. *
  91. * Revision 1.59 2002/01/30 09:46:33 achim
  92. * Small changes
  93. *
  94. * Revision 1.58 2002/01/29 15:30:02 achim
  95. * Set default value of shared_access to Y
  96. * New status S_CACHE_RESERV for clustering added
  97. *
  98. * Revision 1.57 2001/08/21 11:16:35 achim
  99. * Bugfix free_irq()
  100. *
  101. * Revision 1.56 2001/08/09 11:19:39 achim
  102. * Scsi_Host_Template changes
  103. *
  104. * Revision 1.55 2001/08/09 10:11:28 achim
  105. * Command HOST_UNFREEZE_IO before cache service init.
  106. *
  107. * Revision 1.54 2001/07/20 13:48:12 achim
  108. * Expand: gdth_analyse_hdrive() removed
  109. *
  110. * Revision 1.53 2001/07/17 09:52:49 achim
  111. * Small OEM related change
  112. *
  113. * Revision 1.52 2001/06/19 15:06:20 achim
  114. * New host command GDT_UNFREEZE_IO added
  115. *
  116. * Revision 1.51 2001/05/22 06:42:37 achim
  117. * PCI: Subdevice ID added
  118. *
  119. * Revision 1.50 2001/05/17 13:42:16 achim
  120. * Support for Intel Storage RAID Controllers added
  121. *
  122. * Revision 1.50 2001/05/17 12:12:34 achim
  123. * Support for Intel Storage RAID Controllers added
  124. *
  125. * Revision 1.49 2001/03/15 15:07:17 achim
  126. * New __setup interface for boot command line options added
  127. *
  128. * Revision 1.48 2001/02/06 12:36:28 achim
  129. * Bugfix Cluster protocol
  130. *
  131. * Revision 1.47 2001/01/10 14:42:06 achim
  132. * New switch shared_access added
  133. *
  134. * Revision 1.46 2001/01/09 08:11:35 achim
  135. * gdth_command() removed
  136. * meaning of Scsi_Pointer members changed
  137. *
  138. * Revision 1.45 2000/11/16 12:02:24 achim
  139. * Changes for kernel 2.4
  140. *
  141. * Revision 1.44 2000/10/11 08:44:10 achim
  142. * Clustering changes: New flag media_changed added
  143. *
  144. * Revision 1.43 2000/09/20 12:59:01 achim
  145. * DPMEM remap functions for all PCI controller types implemented
  146. * Small changes for ia64 platform
  147. *
  148. * Revision 1.42 2000/07/20 09:04:50 achim
  149. * Small changes for kernel 2.4
  150. *
  151. * Revision 1.41 2000/07/04 14:11:11 achim
  152. * gdth_analyse_hdrive() added to rescan drives after online expansion
  153. *
  154. * Revision 1.40 2000/06/27 11:24:16 achim
  155. * Changes Clustering, Screenservice
  156. *
  157. * Revision 1.39 2000/06/15 13:09:04 achim
  158. * Changes for gdth_do_cmd()
  159. *
  160. * Revision 1.38 2000/06/15 12:08:43 achim
  161. * Bugfix gdth_sync_event(), service SCREENSERVICE
  162. * Data direction for command 0xc2 changed to DOU
  163. *
  164. * Revision 1.37 2000/05/25 13:50:10 achim
  165. * New driver parameter virt_ctr added
  166. *
  167. * Revision 1.36 2000/05/04 08:50:46 achim
  168. * Event buffer now in gdth_ha_str
  169. *
  170. * Revision 1.35 2000/03/03 10:44:08 achim
  171. * New event_string only valid for the RP controller family
  172. *
  173. * Revision 1.34 2000/03/02 14:55:29 achim
  174. * New mechanism for async. event handling implemented
  175. *
  176. * Revision 1.33 2000/02/21 15:37:37 achim
  177. * Bugfix Alpha platform + DPMEM above 4GB
  178. *
  179. * Revision 1.32 2000/02/14 16:17:37 achim
  180. * Bugfix sense_buffer[] + raw devices
  181. *
  182. * Revision 1.31 2000/02/10 10:29:00 achim
  183. * Delete sense_buffer[0], if command OK
  184. *
  185. * Revision 1.30 1999/11/02 13:42:39 achim
  186. * ARRAY_DRV_LIST2 implemented
  187. * Now 255 log. and 100 host drives supported
  188. *
  189. * Revision 1.29 1999/10/05 13:28:47 achim
  190. * GDT_CLUST_RESET added
  191. *
  192. * Revision 1.28 1999/08/12 13:44:54 achim
  193. * MOUNTALL removed
  194. * Cluster drives -> removeable drives
  195. *
  196. * Revision 1.27 1999/06/22 07:22:38 achim
  197. * Small changes
  198. *
  199. * Revision 1.26 1999/06/10 16:09:12 achim
  200. * Cluster Host Drive support: Bugfixes
  201. *
  202. * Revision 1.25 1999/06/01 16:03:56 achim
  203. * gdth_init_pci(): Manipulate config. space to start RP controller
  204. *
  205. * Revision 1.24 1999/05/26 11:53:06 achim
  206. * Cluster Host Drive support added
  207. *
  208. * Revision 1.23 1999/03/26 09:12:31 achim
  209. * Default value for hdr_channel set to 0
  210. *
  211. * Revision 1.22 1999/03/22 16:27:16 achim
  212. * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
  213. *
  214. * Revision 1.21 1999/03/16 13:40:34 achim
  215. * Problems with reserved drives solved
  216. * gdth_eh_bus_reset() implemented
  217. *
  218. * Revision 1.20 1999/03/10 09:08:13 achim
  219. * Bugfix: Corrections in gdth_direction_tab[] made
  220. * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
  221. *
  222. * Revision 1.19 1999/03/05 14:38:16 achim
  223. * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
  224. * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
  225. * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
  226. * with BIOS disabled and memory test set to Intensive
  227. * Enhanced /proc support
  228. *
  229. * Revision 1.18 1999/02/24 09:54:33 achim
  230. * Command line parameter hdr_channel implemented
  231. * Bugfix for EISA controllers + Linux 2.2.x
  232. *
  233. * Revision 1.17 1998/12/17 15:58:11 achim
  234. * Command line parameters implemented
  235. * Changes for Alpha platforms
  236. * PCI controller scan changed
  237. * SMP support improved (spin_lock_irqsave(),...)
  238. * New async. events, new scan/reserve commands included
  239. *
  240. * Revision 1.16 1998/09/28 16:08:46 achim
  241. * GDT_PCIMPR: DPMEM remapping, if required
  242. * mdelay() added
  243. *
  244. * Revision 1.15 1998/06/03 14:54:06 achim
  245. * gdth_delay(), gdth_flush() implemented
  246. * Bugfix: gdth_release() changed
  247. *
  248. * Revision 1.14 1998/05/22 10:01:17 achim
  249. * mj: pcibios_strerror() removed
  250. * Improved SMP support (if version >= 2.1.95)
  251. * gdth_halt(): halt_called flag added (if version < 2.1)
  252. *
  253. * Revision 1.13 1998/04/16 09:14:57 achim
  254. * Reserve drives (for raw service) implemented
  255. * New error handling code enabled
  256. * Get controller name from board_info() IOCTL
  257. * Final round of PCI device driver patches by Martin Mares
  258. *
  259. * Revision 1.12 1998/03/03 09:32:37 achim
  260. * Fibre channel controller support added
  261. *
  262. * Revision 1.11 1998/01/27 16:19:14 achim
  263. * SA_SHIRQ added
  264. * add_timer()/del_timer() instead of GDTH_TIMER
  265. * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
  266. * New error handling included
  267. *
  268. * Revision 1.10 1997/10/31 12:29:57 achim
  269. * Read heads/sectors from host drive
  270. *
  271. * Revision 1.9 1997/09/04 10:07:25 achim
  272. * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
  273. * register_reboot_notifier() to get a notify on shutown used
  274. *
  275. * Revision 1.8 1997/04/02 12:14:30 achim
  276. * Version 1.00 (see gdth.h), tested with kernel 2.0.29
  277. *
  278. * Revision 1.7 1997/03/12 13:33:37 achim
  279. * gdth_reset() changed, new async. events
  280. *
  281. * Revision 1.6 1997/03/04 14:01:11 achim
  282. * Shutdown routine gdth_halt() implemented
  283. *
  284. * Revision 1.5 1997/02/21 09:08:36 achim
  285. * New controller included (RP, RP1, RP2 series)
  286. * IOCTL interface implemented
  287. *
  288. * Revision 1.4 1996/07/05 12:48:55 achim
  289. * Function gdth_bios_param() implemented
  290. * New constant GDTH_MAXC_P_L inserted
  291. * GDT_WRITE_THR, GDT_EXT_INFO implemented
  292. * Function gdth_reset() changed
  293. *
  294. * Revision 1.3 1996/05/10 09:04:41 achim
  295. * Small changes for Linux 1.2.13
  296. *
  297. * Revision 1.2 1996/05/09 12:45:27 achim
  298. * Loadable module support implemented
  299. * /proc support corrections made
  300. *
  301. * Revision 1.1 1996/04/11 07:35:57 achim
  302. * Initial revision
  303. *
  304. ************************************************************************/
  305. /* All GDT Disk Array Controllers are fully supported by this driver.
  306. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  307. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  308. * list of all controller types.
  309. *
  310. * If you have one or more GDT3000/3020 EISA controllers with
  311. * controller BIOS disabled, you have to set the IRQ values with the
  312. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  313. * the IRQ values for the EISA controllers.
  314. *
  315. * After the optional list of IRQ values, other possible
  316. * command line options are:
  317. * disable:Y disable driver
  318. * disable:N enable driver
  319. * reserve_mode:0 reserve no drives for the raw service
  320. * reserve_mode:1 reserve all not init., removable drives
  321. * reserve_mode:2 reserve all not init. drives
  322. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  323. * h- controller no., b- channel no.,
  324. * t- target ID, l- LUN
  325. * reverse_scan:Y reverse scan order for PCI controllers
  326. * reverse_scan:N scan PCI controllers like BIOS
  327. * max_ids:x x - target ID count per channel (1..MAXID)
  328. * rescan:Y rescan all channels/IDs
  329. * rescan:N use all devices found until now
  330. * virt_ctr:Y map every channel to a virtual controller
  331. * virt_ctr:N use multi channel support
  332. * hdr_channel:x x - number of virtual bus for host drives
  333. * shared_access:Y disable driver reserve/release protocol to
  334. * access a shared resource from several nodes,
  335. * appropriate controller firmware required
  336. * shared_access:N enable driver reserve/release protocol
  337. * probe_eisa_isa:Y scan for EISA/ISA controllers
  338. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  339. * force_dma32:Y use only 32 bit DMA mode
  340. * force_dma32:N use 64 bit DMA mode, if supported
  341. *
  342. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  343. * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
  344. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  345. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  346. *
  347. * When loading the gdth driver as a module, the same options are available.
  348. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  349. * options changes slightly. You must replace all ',' between options
  350. * with ' ' and all ':' with '=' and you must use
  351. * '1' in place of 'Y' and '0' in place of 'N'.
  352. *
  353. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  354. * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
  355. * probe_eisa_isa=0 force_dma32=0"
  356. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  357. */
  358. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  359. * ptr: Chaining
  360. * this_residual: Command priority
  361. * buffer: phys. DMA sense buffer
  362. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  363. * buffers_residual: Timeout value
  364. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  365. * Message: Additional info (gdth_do_cmd()), DMA direction
  366. * have_data_in: Flag for gdth_wait_completion()
  367. * sent_command: Opcode special command
  368. * phase: Service/parameter/return code special command
  369. */
  370. /* interrupt coalescing */
  371. /* #define INT_COAL */
  372. /* statistics */
  373. #define GDTH_STATISTICS
  374. #include <linux/module.h>
  375. #include <linux/version.h>
  376. #include <linux/kernel.h>
  377. #include <linux/types.h>
  378. #include <linux/pci.h>
  379. #include <linux/string.h>
  380. #include <linux/ctype.h>
  381. #include <linux/ioport.h>
  382. #include <linux/delay.h>
  383. #include <linux/interrupt.h>
  384. #include <linux/in.h>
  385. #include <linux/proc_fs.h>
  386. #include <linux/time.h>
  387. #include <linux/timer.h>
  388. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
  389. #include <linux/dma-mapping.h>
  390. #else
  391. #define DMA_32BIT_MASK 0x00000000ffffffffULL
  392. #define DMA_64BIT_MASK 0xffffffffffffffffULL
  393. #endif
  394. #ifdef GDTH_RTC
  395. #include <linux/mc146818rtc.h>
  396. #endif
  397. #include <linux/reboot.h>
  398. #include <asm/dma.h>
  399. #include <asm/system.h>
  400. #include <asm/io.h>
  401. #include <asm/uaccess.h>
  402. #include <linux/spinlock.h>
  403. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  404. #include <linux/blkdev.h>
  405. #else
  406. #include <linux/blk.h>
  407. #include "sd.h"
  408. #endif
  409. #include "scsi.h"
  410. #include <scsi/scsi_host.h>
  411. #include "gdth_kcompat.h"
  412. #include "gdth.h"
  413. static void gdth_delay(int milliseconds);
  414. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  415. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  416. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
  417. static int gdth_async_event(int hanum);
  418. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  419. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
  420. static void gdth_next(int hanum);
  421. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
  422. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
  423. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  424. ushort idx, gdth_evt_data *evt);
  425. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  426. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  427. gdth_evt_str *estr);
  428. static void gdth_clear_events(void);
  429. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  430. char *buffer,ushort count);
  431. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
  432. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
  433. static int gdth_search_eisa(ushort eisa_adr);
  434. static int gdth_search_isa(ulong32 bios_adr);
  435. static int gdth_search_pci(gdth_pci_str *pcistr);
  436. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  437. ushort vendor, ushort dev);
  438. static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
  439. static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
  440. static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
  441. static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
  442. static void gdth_enable_int(int hanum);
  443. static int gdth_get_status(unchar *pIStatus,int irq);
  444. static int gdth_test_busy(int hanum);
  445. static int gdth_get_cmd_index(int hanum);
  446. static void gdth_release_event(int hanum);
  447. static int gdth_wait(int hanum,int index,ulong32 time);
  448. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  449. ulong64 p2,ulong64 p3);
  450. static int gdth_search_drives(int hanum);
  451. static int gdth_analyse_hdrive(int hanum, ushort hdrive);
  452. static const char *gdth_ctr_name(int hanum);
  453. static int gdth_open(struct inode *inode, struct file *filep);
  454. static int gdth_close(struct inode *inode, struct file *filep);
  455. static int gdth_ioctl(struct inode *inode, struct file *filep,
  456. unsigned int cmd, unsigned long arg);
  457. static void gdth_flush(int hanum);
  458. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  459. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  460. static void gdth_scsi_done(struct scsi_cmnd *scp);
  461. #ifdef DEBUG_GDTH
  462. static unchar DebugState = DEBUG_GDTH;
  463. #ifdef __SERIAL__
  464. #define MAX_SERBUF 160
  465. static void ser_init(void);
  466. static void ser_puts(char *str);
  467. static void ser_putc(char c);
  468. static int ser_printk(const char *fmt, ...);
  469. static char strbuf[MAX_SERBUF+1];
  470. #ifdef __COM2__
  471. #define COM_BASE 0x2f8
  472. #else
  473. #define COM_BASE 0x3f8
  474. #endif
  475. static void ser_init()
  476. {
  477. unsigned port=COM_BASE;
  478. outb(0x80,port+3);
  479. outb(0,port+1);
  480. /* 19200 Baud, if 9600: outb(12,port) */
  481. outb(6, port);
  482. outb(3,port+3);
  483. outb(0,port+1);
  484. /*
  485. ser_putc('I');
  486. ser_putc(' ');
  487. */
  488. }
  489. static void ser_puts(char *str)
  490. {
  491. char *ptr;
  492. ser_init();
  493. for (ptr=str;*ptr;++ptr)
  494. ser_putc(*ptr);
  495. }
  496. static void ser_putc(char c)
  497. {
  498. unsigned port=COM_BASE;
  499. while ((inb(port+5) & 0x20)==0);
  500. outb(c,port);
  501. if (c==0x0a)
  502. {
  503. while ((inb(port+5) & 0x20)==0);
  504. outb(0x0d,port);
  505. }
  506. }
  507. static int ser_printk(const char *fmt, ...)
  508. {
  509. va_list args;
  510. int i;
  511. va_start(args,fmt);
  512. i = vsprintf(strbuf,fmt,args);
  513. ser_puts(strbuf);
  514. va_end(args);
  515. return i;
  516. }
  517. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  518. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  519. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  520. #else /* !__SERIAL__ */
  521. #define TRACE(a) {if (DebugState==1) {printk a;}}
  522. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  523. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  524. #endif
  525. #else /* !DEBUG */
  526. #define TRACE(a)
  527. #define TRACE2(a)
  528. #define TRACE3(a)
  529. #endif
  530. #ifdef GDTH_STATISTICS
  531. static ulong32 max_rq=0, max_index=0, max_sg=0;
  532. #ifdef INT_COAL
  533. static ulong32 max_int_coal=0;
  534. #endif
  535. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  536. static struct timer_list gdth_timer;
  537. #endif
  538. #define PTR2USHORT(a) (ushort)(ulong)(a)
  539. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  540. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  541. #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
  542. #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
  543. #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
  544. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  545. #define gdth_readb(addr) readb(addr)
  546. #define gdth_readw(addr) readw(addr)
  547. #define gdth_readl(addr) readl(addr)
  548. #define gdth_writeb(b,addr) writeb((b),(addr))
  549. #define gdth_writew(b,addr) writew((b),(addr))
  550. #define gdth_writel(b,addr) writel((b),(addr))
  551. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  552. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  553. static unchar gdth_polling; /* polling if TRUE */
  554. static unchar gdth_from_wait = FALSE; /* gdth_wait() */
  555. static int wait_index,wait_hanum; /* gdth_wait() */
  556. static int gdth_ctr_count = 0; /* controller count */
  557. static int gdth_ctr_vcount = 0; /* virt. ctr. count */
  558. static int gdth_ctr_released = 0; /* gdth_release() */
  559. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  560. static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
  561. static unchar gdth_write_through = FALSE; /* write through */
  562. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  563. static int elastidx;
  564. static int eoldidx;
  565. static int major;
  566. #define DIN 1 /* IN data direction */
  567. #define DOU 2 /* OUT data direction */
  568. #define DNO DIN /* no data transfer */
  569. #define DUN DIN /* unknown data direction */
  570. static unchar gdth_direction_tab[0x100] = {
  571. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  572. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  573. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  574. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  575. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  576. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  577. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  578. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  579. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  580. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  581. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  582. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  583. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  584. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  585. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  586. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  587. };
  588. /* LILO and modprobe/insmod parameters */
  589. /* IRQ list for GDT3000/3020 EISA controllers */
  590. static int irq[MAXHA] __initdata =
  591. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  592. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  593. /* disable driver flag */
  594. static int disable __initdata = 0;
  595. /* reserve flag */
  596. static int reserve_mode = 1;
  597. /* reserve list */
  598. static int reserve_list[MAX_RES_ARGS] =
  599. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  600. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  601. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  602. /* scan order for PCI controllers */
  603. static int reverse_scan = 0;
  604. /* virtual channel for the host drives */
  605. static int hdr_channel = 0;
  606. /* max. IDs per channel */
  607. static int max_ids = MAXID;
  608. /* rescan all IDs */
  609. static int rescan = 0;
  610. /* map channels to virtual controllers */
  611. static int virt_ctr = 0;
  612. /* shared access */
  613. static int shared_access = 1;
  614. /* enable support for EISA and ISA controllers */
  615. static int probe_eisa_isa = 0;
  616. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  617. static int force_dma32 = 0;
  618. /* parameters for modprobe/insmod */
  619. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
  620. module_param_array(irq, int, NULL, 0);
  621. module_param(disable, int, 0);
  622. module_param(reserve_mode, int, 0);
  623. module_param_array(reserve_list, int, NULL, 0);
  624. module_param(reverse_scan, int, 0);
  625. module_param(hdr_channel, int, 0);
  626. module_param(max_ids, int, 0);
  627. module_param(rescan, int, 0);
  628. module_param(virt_ctr, int, 0);
  629. module_param(shared_access, int, 0);
  630. module_param(probe_eisa_isa, int, 0);
  631. module_param(force_dma32, int, 0);
  632. #else
  633. MODULE_PARM(irq, "i");
  634. MODULE_PARM(disable, "i");
  635. MODULE_PARM(reserve_mode, "i");
  636. MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
  637. MODULE_PARM(reverse_scan, "i");
  638. MODULE_PARM(hdr_channel, "i");
  639. MODULE_PARM(max_ids, "i");
  640. MODULE_PARM(rescan, "i");
  641. MODULE_PARM(virt_ctr, "i");
  642. MODULE_PARM(shared_access, "i");
  643. MODULE_PARM(probe_eisa_isa, "i");
  644. MODULE_PARM(force_dma32, "i");
  645. #endif
  646. MODULE_AUTHOR("Achim Leubner");
  647. MODULE_LICENSE("GPL");
  648. /* ioctl interface */
  649. static const struct file_operations gdth_fops = {
  650. .ioctl = gdth_ioctl,
  651. .open = gdth_open,
  652. .release = gdth_close,
  653. };
  654. #include "gdth_proc.h"
  655. #include "gdth_proc.c"
  656. /* notifier block to get a notify on system shutdown/halt/reboot */
  657. static struct notifier_block gdth_notifier = {
  658. gdth_halt, NULL, 0
  659. };
  660. static int notifier_disabled = 0;
  661. static void gdth_delay(int milliseconds)
  662. {
  663. if (milliseconds == 0) {
  664. udelay(1);
  665. } else {
  666. mdelay(milliseconds);
  667. }
  668. }
  669. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  670. static void gdth_scsi_done(struct scsi_cmnd *scp)
  671. {
  672. TRACE2(("gdth_scsi_done()\n"));
  673. if (scp->request)
  674. complete((struct completion *)scp->request);
  675. }
  676. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  677. int timeout, u32 *info)
  678. {
  679. Scsi_Cmnd *scp;
  680. DECLARE_COMPLETION_ONSTACK(wait);
  681. int rval;
  682. scp = kmalloc(sizeof(*scp), GFP_KERNEL);
  683. if (!scp)
  684. return -ENOMEM;
  685. memset(scp, 0, sizeof(*scp));
  686. scp->device = sdev;
  687. /* use request field to save the ptr. to completion struct. */
  688. scp->request = (struct request *)&wait;
  689. scp->timeout_per_command = timeout*HZ;
  690. scp->request_buffer = gdtcmd;
  691. scp->cmd_len = 12;
  692. memcpy(scp->cmnd, cmnd, 12);
  693. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  694. scp->done = gdth_scsi_done; /* some fn. test this */
  695. gdth_queuecommand(scp, gdth_scsi_done);
  696. wait_for_completion(&wait);
  697. rval = scp->SCp.Status;
  698. if (info)
  699. *info = scp->SCp.Message;
  700. kfree(scp);
  701. return rval;
  702. }
  703. #else
  704. static void gdth_scsi_done(Scsi_Cmnd *scp)
  705. {
  706. TRACE2(("gdth_scsi_done()\n"));
  707. scp->request.rq_status = RQ_SCSI_DONE;
  708. if (scp->request.waiting)
  709. complete(scp->request.waiting);
  710. }
  711. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  712. int timeout, u32 *info)
  713. {
  714. Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
  715. unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
  716. DECLARE_COMPLETION_ONSTACK(wait);
  717. int rval;
  718. if (!scp)
  719. return -ENOMEM;
  720. scp->cmd_len = 12;
  721. scp->use_sg = 0;
  722. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  723. scp->request.rq_status = RQ_SCSI_BUSY;
  724. scp->request.waiting = &wait;
  725. scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
  726. wait_for_completion(&wait);
  727. rval = scp->SCp.Status;
  728. if (info)
  729. *info = scp->SCp.Message;
  730. scsi_release_command(scp);
  731. return rval;
  732. }
  733. #endif
  734. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  735. int timeout, u32 *info)
  736. {
  737. struct scsi_device *sdev = scsi_get_host_dev(shost);
  738. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  739. scsi_free_host_dev(sdev);
  740. return rval;
  741. }
  742. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  743. {
  744. *cyls = size /HEADS/SECS;
  745. if (*cyls <= MAXCYLS) {
  746. *heads = HEADS;
  747. *secs = SECS;
  748. } else { /* too high for 64*32 */
  749. *cyls = size /MEDHEADS/MEDSECS;
  750. if (*cyls <= MAXCYLS) {
  751. *heads = MEDHEADS;
  752. *secs = MEDSECS;
  753. } else { /* too high for 127*63 */
  754. *cyls = size /BIGHEADS/BIGSECS;
  755. *heads = BIGHEADS;
  756. *secs = BIGSECS;
  757. }
  758. }
  759. }
  760. /* controller search and initialization functions */
  761. static int __init gdth_search_eisa(ushort eisa_adr)
  762. {
  763. ulong32 id;
  764. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  765. id = inl(eisa_adr+ID0REG);
  766. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  767. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  768. return 0; /* not EISA configured */
  769. return 1;
  770. }
  771. if (id == GDT3_ID) /* GDT3000 */
  772. return 1;
  773. return 0;
  774. }
  775. static int __init gdth_search_isa(ulong32 bios_adr)
  776. {
  777. void __iomem *addr;
  778. ulong32 id;
  779. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  780. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  781. id = gdth_readl(addr);
  782. iounmap(addr);
  783. if (id == GDT2_ID) /* GDT2000 */
  784. return 1;
  785. }
  786. return 0;
  787. }
  788. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  789. {
  790. ushort device, cnt;
  791. TRACE(("gdth_search_pci()\n"));
  792. cnt = 0;
  793. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  794. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  795. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  796. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  797. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  798. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  799. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  800. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  801. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  802. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  803. PCI_DEVICE_ID_INTEL_SRC);
  804. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  805. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  806. return cnt;
  807. }
  808. /* Vortex only makes RAID controllers.
  809. * We do not really want to specify all 550 ids here, so wildcard match.
  810. */
  811. static struct pci_device_id gdthtable[] __maybe_unused = {
  812. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  813. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  814. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  815. {0}
  816. };
  817. MODULE_DEVICE_TABLE(pci,gdthtable);
  818. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  819. ushort vendor, ushort device)
  820. {
  821. ulong base0, base1, base2;
  822. struct pci_dev *pdev;
  823. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  824. *cnt, vendor, device));
  825. pdev = NULL;
  826. while ((pdev = pci_find_device(vendor, device, pdev))
  827. != NULL) {
  828. if (pci_enable_device(pdev))
  829. continue;
  830. if (*cnt >= MAXHA)
  831. return;
  832. /* GDT PCI controller found, resources are already in pdev */
  833. pcistr[*cnt].pdev = pdev;
  834. pcistr[*cnt].irq = pdev->irq;
  835. base0 = pci_resource_flags(pdev, 0);
  836. base1 = pci_resource_flags(pdev, 1);
  837. base2 = pci_resource_flags(pdev, 2);
  838. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  839. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  840. if (!(base0 & IORESOURCE_MEM))
  841. continue;
  842. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  843. } else { /* GDT6110, GDT6120, .. */
  844. if (!(base0 & IORESOURCE_MEM) ||
  845. !(base2 & IORESOURCE_MEM) ||
  846. !(base1 & IORESOURCE_IO))
  847. continue;
  848. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  849. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  850. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  851. }
  852. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  853. pcistr[*cnt].pdev->bus->number,
  854. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  855. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  856. (*cnt)++;
  857. }
  858. }
  859. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  860. {
  861. gdth_pci_str temp;
  862. int i, changed;
  863. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  864. if (cnt == 0)
  865. return;
  866. do {
  867. changed = FALSE;
  868. for (i = 0; i < cnt-1; ++i) {
  869. if (!reverse_scan) {
  870. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  871. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  872. PCI_SLOT(pcistr[i].pdev->devfn) >
  873. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  874. temp = pcistr[i];
  875. pcistr[i] = pcistr[i+1];
  876. pcistr[i+1] = temp;
  877. changed = TRUE;
  878. }
  879. } else {
  880. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  881. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  882. PCI_SLOT(pcistr[i].pdev->devfn) <
  883. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  884. temp = pcistr[i];
  885. pcistr[i] = pcistr[i+1];
  886. pcistr[i+1] = temp;
  887. changed = TRUE;
  888. }
  889. }
  890. }
  891. } while (changed);
  892. }
  893. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  894. {
  895. ulong32 retries,id;
  896. unchar prot_ver,eisacf,i,irq_found;
  897. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  898. /* disable board interrupts, deinitialize services */
  899. outb(0xff,eisa_adr+EDOORREG);
  900. outb(0x00,eisa_adr+EDENABREG);
  901. outb(0x00,eisa_adr+EINTENABREG);
  902. outb(0xff,eisa_adr+LDOORREG);
  903. retries = INIT_RETRIES;
  904. gdth_delay(20);
  905. while (inb(eisa_adr+EDOORREG) != 0xff) {
  906. if (--retries == 0) {
  907. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  908. return 0;
  909. }
  910. gdth_delay(1);
  911. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  912. }
  913. prot_ver = inb(eisa_adr+MAILBOXREG);
  914. outb(0xff,eisa_adr+EDOORREG);
  915. if (prot_ver != PROTOCOL_VERSION) {
  916. printk("GDT-EISA: Illegal protocol version\n");
  917. return 0;
  918. }
  919. ha->bmic = eisa_adr;
  920. ha->brd_phys = (ulong32)eisa_adr >> 12;
  921. outl(0,eisa_adr+MAILBOXREG);
  922. outl(0,eisa_adr+MAILBOXREG+4);
  923. outl(0,eisa_adr+MAILBOXREG+8);
  924. outl(0,eisa_adr+MAILBOXREG+12);
  925. /* detect IRQ */
  926. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  927. ha->oem_id = OEM_ID_ICP;
  928. ha->type = GDT_EISA;
  929. ha->stype = id;
  930. outl(1,eisa_adr+MAILBOXREG+8);
  931. outb(0xfe,eisa_adr+LDOORREG);
  932. retries = INIT_RETRIES;
  933. gdth_delay(20);
  934. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  935. if (--retries == 0) {
  936. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  937. return 0;
  938. }
  939. gdth_delay(1);
  940. }
  941. ha->irq = inb(eisa_adr+MAILBOXREG);
  942. outb(0xff,eisa_adr+EDOORREG);
  943. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  944. /* check the result */
  945. if (ha->irq == 0) {
  946. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  947. for (i = 0, irq_found = FALSE;
  948. i < MAXHA && irq[i] != 0xff; ++i) {
  949. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  950. irq_found = TRUE;
  951. break;
  952. }
  953. }
  954. if (irq_found) {
  955. ha->irq = irq[i];
  956. irq[i] = 0;
  957. printk("GDT-EISA: Can not detect controller IRQ,\n");
  958. printk("Use IRQ setting from command line (IRQ = %d)\n",
  959. ha->irq);
  960. } else {
  961. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  962. printk("the controller BIOS or use command line parameters\n");
  963. return 0;
  964. }
  965. }
  966. } else {
  967. eisacf = inb(eisa_adr+EISAREG) & 7;
  968. if (eisacf > 4) /* level triggered */
  969. eisacf -= 4;
  970. ha->irq = gdth_irq_tab[eisacf];
  971. ha->oem_id = OEM_ID_ICP;
  972. ha->type = GDT_EISA;
  973. ha->stype = id;
  974. }
  975. ha->dma64_support = 0;
  976. return 1;
  977. }
  978. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  979. {
  980. register gdt2_dpram_str __iomem *dp2_ptr;
  981. int i;
  982. unchar irq_drq,prot_ver;
  983. ulong32 retries;
  984. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  985. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  986. if (ha->brd == NULL) {
  987. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  988. return 0;
  989. }
  990. dp2_ptr = ha->brd;
  991. gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  992. /* reset interface area */
  993. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  994. if (gdth_readl(&dp2_ptr->u) != 0) {
  995. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  996. iounmap(ha->brd);
  997. return 0;
  998. }
  999. /* disable board interrupts, read DRQ and IRQ */
  1000. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1001. gdth_writeb(0x00, &dp2_ptr->io.irqen);
  1002. gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
  1003. gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  1004. irq_drq = gdth_readb(&dp2_ptr->io.rq);
  1005. for (i=0; i<3; ++i) {
  1006. if ((irq_drq & 1)==0)
  1007. break;
  1008. irq_drq >>= 1;
  1009. }
  1010. ha->drq = gdth_drq_tab[i];
  1011. irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
  1012. for (i=1; i<5; ++i) {
  1013. if ((irq_drq & 1)==0)
  1014. break;
  1015. irq_drq >>= 1;
  1016. }
  1017. ha->irq = gdth_irq_tab[i];
  1018. /* deinitialize services */
  1019. gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  1020. gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  1021. gdth_writeb(0, &dp2_ptr->io.event);
  1022. retries = INIT_RETRIES;
  1023. gdth_delay(20);
  1024. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  1025. if (--retries == 0) {
  1026. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  1027. iounmap(ha->brd);
  1028. return 0;
  1029. }
  1030. gdth_delay(1);
  1031. }
  1032. prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
  1033. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1034. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1035. if (prot_ver != PROTOCOL_VERSION) {
  1036. printk("GDT-ISA: Illegal protocol version\n");
  1037. iounmap(ha->brd);
  1038. return 0;
  1039. }
  1040. ha->oem_id = OEM_ID_ICP;
  1041. ha->type = GDT_ISA;
  1042. ha->ic_all_size = sizeof(dp2_ptr->u);
  1043. ha->stype= GDT2_ID;
  1044. ha->brd_phys = bios_adr >> 4;
  1045. /* special request to controller BIOS */
  1046. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  1047. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  1048. gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  1049. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  1050. gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  1051. gdth_writeb(0, &dp2_ptr->io.event);
  1052. retries = INIT_RETRIES;
  1053. gdth_delay(20);
  1054. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  1055. if (--retries == 0) {
  1056. printk("GDT-ISA: Initialization error\n");
  1057. iounmap(ha->brd);
  1058. return 0;
  1059. }
  1060. gdth_delay(1);
  1061. }
  1062. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1063. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1064. ha->dma64_support = 0;
  1065. return 1;
  1066. }
  1067. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  1068. {
  1069. register gdt6_dpram_str __iomem *dp6_ptr;
  1070. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1071. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1072. ulong32 retries;
  1073. unchar prot_ver;
  1074. ushort command;
  1075. int i, found = FALSE;
  1076. TRACE(("gdth_init_pci()\n"));
  1077. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  1078. ha->oem_id = OEM_ID_INTEL;
  1079. else
  1080. ha->oem_id = OEM_ID_ICP;
  1081. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  1082. ha->stype = (ulong32)pcistr->pdev->device;
  1083. ha->irq = pcistr->irq;
  1084. ha->pdev = pcistr->pdev;
  1085. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  1086. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1087. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  1088. if (ha->brd == NULL) {
  1089. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1090. return 0;
  1091. }
  1092. /* check and reset interface area */
  1093. dp6_ptr = ha->brd;
  1094. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1095. if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  1096. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1097. pcistr->dpmem);
  1098. found = FALSE;
  1099. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1100. iounmap(ha->brd);
  1101. ha->brd = ioremap(i, sizeof(ushort));
  1102. if (ha->brd == NULL) {
  1103. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1104. return 0;
  1105. }
  1106. if (gdth_readw(ha->brd) != 0xffff) {
  1107. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  1108. continue;
  1109. }
  1110. iounmap(ha->brd);
  1111. pci_write_config_dword(pcistr->pdev,
  1112. PCI_BASE_ADDRESS_0, i);
  1113. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  1114. if (ha->brd == NULL) {
  1115. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1116. return 0;
  1117. }
  1118. dp6_ptr = ha->brd;
  1119. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1120. if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  1121. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1122. found = TRUE;
  1123. break;
  1124. }
  1125. }
  1126. if (!found) {
  1127. printk("GDT-PCI: No free address found!\n");
  1128. iounmap(ha->brd);
  1129. return 0;
  1130. }
  1131. }
  1132. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  1133. if (gdth_readl(&dp6_ptr->u) != 0) {
  1134. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1135. iounmap(ha->brd);
  1136. return 0;
  1137. }
  1138. /* disable board interrupts, deinit services */
  1139. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1140. gdth_writeb(0x00, &dp6_ptr->io.irqen);
  1141. gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
  1142. gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  1143. gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  1144. gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  1145. gdth_writeb(0, &dp6_ptr->io.event);
  1146. retries = INIT_RETRIES;
  1147. gdth_delay(20);
  1148. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  1149. if (--retries == 0) {
  1150. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1151. iounmap(ha->brd);
  1152. return 0;
  1153. }
  1154. gdth_delay(1);
  1155. }
  1156. prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
  1157. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1158. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1159. if (prot_ver != PROTOCOL_VERSION) {
  1160. printk("GDT-PCI: Illegal protocol version\n");
  1161. iounmap(ha->brd);
  1162. return 0;
  1163. }
  1164. ha->type = GDT_PCI;
  1165. ha->ic_all_size = sizeof(dp6_ptr->u);
  1166. /* special command to controller BIOS */
  1167. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  1168. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  1169. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  1170. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  1171. gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  1172. gdth_writeb(0, &dp6_ptr->io.event);
  1173. retries = INIT_RETRIES;
  1174. gdth_delay(20);
  1175. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  1176. if (--retries == 0) {
  1177. printk("GDT-PCI: Initialization error\n");
  1178. iounmap(ha->brd);
  1179. return 0;
  1180. }
  1181. gdth_delay(1);
  1182. }
  1183. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1184. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1185. ha->dma64_support = 0;
  1186. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  1187. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  1188. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  1189. pcistr->dpmem,ha->irq));
  1190. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  1191. if (ha->brd == NULL) {
  1192. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1193. iounmap(ha->brd);
  1194. return 0;
  1195. }
  1196. /* check and reset interface area */
  1197. dp6c_ptr = ha->brd;
  1198. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1199. if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  1200. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1201. pcistr->dpmem);
  1202. found = FALSE;
  1203. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1204. iounmap(ha->brd);
  1205. ha->brd = ioremap(i, sizeof(ushort));
  1206. if (ha->brd == NULL) {
  1207. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1208. return 0;
  1209. }
  1210. if (gdth_readw(ha->brd) != 0xffff) {
  1211. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  1212. continue;
  1213. }
  1214. iounmap(ha->brd);
  1215. pci_write_config_dword(pcistr->pdev,
  1216. PCI_BASE_ADDRESS_2, i);
  1217. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  1218. if (ha->brd == NULL) {
  1219. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1220. return 0;
  1221. }
  1222. dp6c_ptr = ha->brd;
  1223. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1224. if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  1225. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1226. found = TRUE;
  1227. break;
  1228. }
  1229. }
  1230. if (!found) {
  1231. printk("GDT-PCI: No free address found!\n");
  1232. iounmap(ha->brd);
  1233. return 0;
  1234. }
  1235. }
  1236. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  1237. if (gdth_readl(&dp6c_ptr->u) != 0) {
  1238. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1239. iounmap(ha->brd);
  1240. return 0;
  1241. }
  1242. /* disable board interrupts, deinit services */
  1243. outb(0x00,PTR2USHORT(&ha->plx->control1));
  1244. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  1245. gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  1246. gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  1247. gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  1248. gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1249. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1250. retries = INIT_RETRIES;
  1251. gdth_delay(20);
  1252. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  1253. if (--retries == 0) {
  1254. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1255. iounmap(ha->brd);
  1256. return 0;
  1257. }
  1258. gdth_delay(1);
  1259. }
  1260. prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
  1261. gdth_writeb(0, &dp6c_ptr->u.ic.Status);
  1262. if (prot_ver != PROTOCOL_VERSION) {
  1263. printk("GDT-PCI: Illegal protocol version\n");
  1264. iounmap(ha->brd);
  1265. return 0;
  1266. }
  1267. ha->type = GDT_PCINEW;
  1268. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1269. /* special command to controller BIOS */
  1270. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1271. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1272. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1273. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1274. gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1275. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1276. retries = INIT_RETRIES;
  1277. gdth_delay(20);
  1278. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1279. if (--retries == 0) {
  1280. printk("GDT-PCI: Initialization error\n");
  1281. iounmap(ha->brd);
  1282. return 0;
  1283. }
  1284. gdth_delay(1);
  1285. }
  1286. gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
  1287. ha->dma64_support = 0;
  1288. } else { /* MPR */
  1289. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1290. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1291. if (ha->brd == NULL) {
  1292. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1293. return 0;
  1294. }
  1295. /* manipulate config. space to enable DPMEM, start RP controller */
  1296. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1297. command |= 6;
  1298. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1299. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1300. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1301. i = 0xFEFF0001UL;
  1302. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1303. gdth_delay(1);
  1304. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1305. pci_resource_start(pcistr->pdev, 8));
  1306. dp6m_ptr = ha->brd;
  1307. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1308. * Aditional check needed for Xscale based RAID controllers */
  1309. while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1310. gdth_delay(1);
  1311. /* check and reset interface area */
  1312. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1313. if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1314. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1315. pcistr->dpmem);
  1316. found = FALSE;
  1317. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1318. iounmap(ha->brd);
  1319. ha->brd = ioremap(i, sizeof(ushort));
  1320. if (ha->brd == NULL) {
  1321. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1322. return 0;
  1323. }
  1324. if (gdth_readw(ha->brd) != 0xffff) {
  1325. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1326. continue;
  1327. }
  1328. iounmap(ha->brd);
  1329. pci_write_config_dword(pcistr->pdev,
  1330. PCI_BASE_ADDRESS_0, i);
  1331. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1332. if (ha->brd == NULL) {
  1333. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1334. return 0;
  1335. }
  1336. dp6m_ptr = ha->brd;
  1337. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1338. if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1339. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1340. found = TRUE;
  1341. break;
  1342. }
  1343. }
  1344. if (!found) {
  1345. printk("GDT-PCI: No free address found!\n");
  1346. iounmap(ha->brd);
  1347. return 0;
  1348. }
  1349. }
  1350. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1351. /* disable board interrupts, deinit services */
  1352. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1353. &dp6m_ptr->i960r.edoor_en_reg);
  1354. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1355. gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1356. gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1357. gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1358. gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1359. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1360. retries = INIT_RETRIES;
  1361. gdth_delay(20);
  1362. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1363. if (--retries == 0) {
  1364. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1365. iounmap(ha->brd);
  1366. return 0;
  1367. }
  1368. gdth_delay(1);
  1369. }
  1370. prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
  1371. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1372. if (prot_ver != PROTOCOL_VERSION) {
  1373. printk("GDT-PCI: Illegal protocol version\n");
  1374. iounmap(ha->brd);
  1375. return 0;
  1376. }
  1377. ha->type = GDT_PCIMPR;
  1378. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1379. /* special command to controller BIOS */
  1380. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1381. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1382. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1383. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1384. gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1385. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1386. retries = INIT_RETRIES;
  1387. gdth_delay(20);
  1388. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1389. if (--retries == 0) {
  1390. printk("GDT-PCI: Initialization error\n");
  1391. iounmap(ha->brd);
  1392. return 0;
  1393. }
  1394. gdth_delay(1);
  1395. }
  1396. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1397. /* read FW version to detect 64-bit DMA support */
  1398. gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1399. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1400. retries = INIT_RETRIES;
  1401. gdth_delay(20);
  1402. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1403. if (--retries == 0) {
  1404. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1405. iounmap(ha->brd);
  1406. return 0;
  1407. }
  1408. gdth_delay(1);
  1409. }
  1410. prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1411. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1412. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1413. ha->dma64_support = 0;
  1414. else
  1415. ha->dma64_support = 1;
  1416. }
  1417. return 1;
  1418. }
  1419. /* controller protocol functions */
  1420. static void __init gdth_enable_int(int hanum)
  1421. {
  1422. gdth_ha_str *ha;
  1423. ulong flags;
  1424. gdt2_dpram_str __iomem *dp2_ptr;
  1425. gdt6_dpram_str __iomem *dp6_ptr;
  1426. gdt6m_dpram_str __iomem *dp6m_ptr;
  1427. TRACE(("gdth_enable_int() hanum %d\n",hanum));
  1428. ha = HADATA(gdth_ctr_tab[hanum]);
  1429. spin_lock_irqsave(&ha->smp_lock, flags);
  1430. if (ha->type == GDT_EISA) {
  1431. outb(0xff, ha->bmic + EDOORREG);
  1432. outb(0xff, ha->bmic + EDENABREG);
  1433. outb(0x01, ha->bmic + EINTENABREG);
  1434. } else if (ha->type == GDT_ISA) {
  1435. dp2_ptr = ha->brd;
  1436. gdth_writeb(1, &dp2_ptr->io.irqdel);
  1437. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1438. gdth_writeb(1, &dp2_ptr->io.irqen);
  1439. } else if (ha->type == GDT_PCI) {
  1440. dp6_ptr = ha->brd;
  1441. gdth_writeb(1, &dp6_ptr->io.irqdel);
  1442. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1443. gdth_writeb(1, &dp6_ptr->io.irqen);
  1444. } else if (ha->type == GDT_PCINEW) {
  1445. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1446. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1447. } else if (ha->type == GDT_PCIMPR) {
  1448. dp6m_ptr = ha->brd;
  1449. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1450. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1451. &dp6m_ptr->i960r.edoor_en_reg);
  1452. }
  1453. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1454. }
  1455. static int gdth_get_status(unchar *pIStatus,int irq)
  1456. {
  1457. register gdth_ha_str *ha;
  1458. int i;
  1459. TRACE(("gdth_get_status() irq %d ctr_count %d\n",
  1460. irq,gdth_ctr_count));
  1461. *pIStatus = 0;
  1462. for (i=0; i<gdth_ctr_count; ++i) {
  1463. ha = HADATA(gdth_ctr_tab[i]);
  1464. if (ha->irq != (unchar)irq) /* check IRQ */
  1465. continue;
  1466. if (ha->type == GDT_EISA)
  1467. *pIStatus = inb((ushort)ha->bmic + EDOORREG);
  1468. else if (ha->type == GDT_ISA)
  1469. *pIStatus =
  1470. gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1471. else if (ha->type == GDT_PCI)
  1472. *pIStatus =
  1473. gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1474. else if (ha->type == GDT_PCINEW)
  1475. *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1476. else if (ha->type == GDT_PCIMPR)
  1477. *pIStatus =
  1478. gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1479. if (*pIStatus)
  1480. return i; /* board found */
  1481. }
  1482. return -1;
  1483. }
  1484. static int gdth_test_busy(int hanum)
  1485. {
  1486. register gdth_ha_str *ha;
  1487. register int gdtsema0 = 0;
  1488. TRACE(("gdth_test_busy() hanum %d\n",hanum));
  1489. ha = HADATA(gdth_ctr_tab[hanum]);
  1490. if (ha->type == GDT_EISA)
  1491. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1492. else if (ha->type == GDT_ISA)
  1493. gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1494. else if (ha->type == GDT_PCI)
  1495. gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1496. else if (ha->type == GDT_PCINEW)
  1497. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1498. else if (ha->type == GDT_PCIMPR)
  1499. gdtsema0 =
  1500. (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1501. return (gdtsema0 & 1);
  1502. }
  1503. static int gdth_get_cmd_index(int hanum)
  1504. {
  1505. register gdth_ha_str *ha;
  1506. int i;
  1507. TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
  1508. ha = HADATA(gdth_ctr_tab[hanum]);
  1509. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1510. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1511. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1512. ha->cmd_tab[i].service = ha->pccb->Service;
  1513. ha->pccb->CommandIndex = (ulong32)i+2;
  1514. return (i+2);
  1515. }
  1516. }
  1517. return 0;
  1518. }
  1519. static void gdth_set_sema0(int hanum)
  1520. {
  1521. register gdth_ha_str *ha;
  1522. TRACE(("gdth_set_sema0() hanum %d\n",hanum));
  1523. ha = HADATA(gdth_ctr_tab[hanum]);
  1524. if (ha->type == GDT_EISA) {
  1525. outb(1, ha->bmic + SEMA0REG);
  1526. } else if (ha->type == GDT_ISA) {
  1527. gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1528. } else if (ha->type == GDT_PCI) {
  1529. gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1530. } else if (ha->type == GDT_PCINEW) {
  1531. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1532. } else if (ha->type == GDT_PCIMPR) {
  1533. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1534. }
  1535. }
  1536. static void gdth_copy_command(int hanum)
  1537. {
  1538. register gdth_ha_str *ha;
  1539. register gdth_cmd_str *cmd_ptr;
  1540. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1541. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1542. gdt6_dpram_str __iomem *dp6_ptr;
  1543. gdt2_dpram_str __iomem *dp2_ptr;
  1544. ushort cp_count,dp_offset,cmd_no;
  1545. TRACE(("gdth_copy_command() hanum %d\n",hanum));
  1546. ha = HADATA(gdth_ctr_tab[hanum]);
  1547. cp_count = ha->cmd_len;
  1548. dp_offset= ha->cmd_offs_dpmem;
  1549. cmd_no = ha->cmd_cnt;
  1550. cmd_ptr = ha->pccb;
  1551. ++ha->cmd_cnt;
  1552. if (ha->type == GDT_EISA)
  1553. return; /* no DPMEM, no copy */
  1554. /* set cpcount dword aligned */
  1555. if (cp_count & 3)
  1556. cp_count += (4 - (cp_count & 3));
  1557. ha->cmd_offs_dpmem += cp_count;
  1558. /* set offset and service, copy command to DPMEM */
  1559. if (ha->type == GDT_ISA) {
  1560. dp2_ptr = ha->brd;
  1561. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1562. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1563. gdth_writew((ushort)cmd_ptr->Service,
  1564. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1565. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1566. } else if (ha->type == GDT_PCI) {
  1567. dp6_ptr = ha->brd;
  1568. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1569. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1570. gdth_writew((ushort)cmd_ptr->Service,
  1571. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1572. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1573. } else if (ha->type == GDT_PCINEW) {
  1574. dp6c_ptr = ha->brd;
  1575. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1576. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1577. gdth_writew((ushort)cmd_ptr->Service,
  1578. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1579. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1580. } else if (ha->type == GDT_PCIMPR) {
  1581. dp6m_ptr = ha->brd;
  1582. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1583. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1584. gdth_writew((ushort)cmd_ptr->Service,
  1585. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1586. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1587. }
  1588. }
  1589. static void gdth_release_event(int hanum)
  1590. {
  1591. register gdth_ha_str *ha;
  1592. TRACE(("gdth_release_event() hanum %d\n",hanum));
  1593. ha = HADATA(gdth_ctr_tab[hanum]);
  1594. #ifdef GDTH_STATISTICS
  1595. {
  1596. ulong32 i,j;
  1597. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1598. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1599. ++i;
  1600. }
  1601. if (max_index < i) {
  1602. max_index = i;
  1603. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1604. }
  1605. }
  1606. #endif
  1607. if (ha->pccb->OpCode == GDT_INIT)
  1608. ha->pccb->Service |= 0x80;
  1609. if (ha->type == GDT_EISA) {
  1610. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1611. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1612. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1613. } else if (ha->type == GDT_ISA) {
  1614. gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1615. } else if (ha->type == GDT_PCI) {
  1616. gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1617. } else if (ha->type == GDT_PCINEW) {
  1618. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1619. } else if (ha->type == GDT_PCIMPR) {
  1620. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1621. }
  1622. }
  1623. static int gdth_wait(int hanum,int index,ulong32 time)
  1624. {
  1625. gdth_ha_str *ha;
  1626. int answer_found = FALSE;
  1627. TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
  1628. ha = HADATA(gdth_ctr_tab[hanum]);
  1629. if (index == 0)
  1630. return 1; /* no wait required */
  1631. gdth_from_wait = TRUE;
  1632. do {
  1633. gdth_interrupt((int)ha->irq,ha);
  1634. if (wait_hanum==hanum && wait_index==index) {
  1635. answer_found = TRUE;
  1636. break;
  1637. }
  1638. gdth_delay(1);
  1639. } while (--time);
  1640. gdth_from_wait = FALSE;
  1641. while (gdth_test_busy(hanum))
  1642. gdth_delay(0);
  1643. return (answer_found);
  1644. }
  1645. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  1646. ulong64 p2,ulong64 p3)
  1647. {
  1648. register gdth_ha_str *ha;
  1649. register gdth_cmd_str *cmd_ptr;
  1650. int retries,index;
  1651. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1652. ha = HADATA(gdth_ctr_tab[hanum]);
  1653. cmd_ptr = ha->pccb;
  1654. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1655. /* make command */
  1656. for (retries = INIT_RETRIES;;) {
  1657. cmd_ptr->Service = service;
  1658. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1659. if (!(index=gdth_get_cmd_index(hanum))) {
  1660. TRACE(("GDT: No free command index found\n"));
  1661. return 0;
  1662. }
  1663. gdth_set_sema0(hanum);
  1664. cmd_ptr->OpCode = opcode;
  1665. cmd_ptr->BoardNode = LOCALBOARD;
  1666. if (service == CACHESERVICE) {
  1667. if (opcode == GDT_IOCTL) {
  1668. cmd_ptr->u.ioctl.subfunc = p1;
  1669. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1670. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1671. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1672. } else {
  1673. if (ha->cache_feat & GDT_64BIT) {
  1674. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1675. cmd_ptr->u.cache64.BlockNo = p2;
  1676. } else {
  1677. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1678. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1679. }
  1680. }
  1681. } else if (service == SCSIRAWSERVICE) {
  1682. if (ha->raw_feat & GDT_64BIT) {
  1683. cmd_ptr->u.raw64.direction = p1;
  1684. cmd_ptr->u.raw64.bus = (unchar)p2;
  1685. cmd_ptr->u.raw64.target = (unchar)p3;
  1686. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1687. } else {
  1688. cmd_ptr->u.raw.direction = p1;
  1689. cmd_ptr->u.raw.bus = (unchar)p2;
  1690. cmd_ptr->u.raw.target = (unchar)p3;
  1691. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1692. }
  1693. } else if (service == SCREENSERVICE) {
  1694. if (opcode == GDT_REALTIME) {
  1695. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1696. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1697. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1698. }
  1699. }
  1700. ha->cmd_len = sizeof(gdth_cmd_str);
  1701. ha->cmd_offs_dpmem = 0;
  1702. ha->cmd_cnt = 0;
  1703. gdth_copy_command(hanum);
  1704. gdth_release_event(hanum);
  1705. gdth_delay(20);
  1706. if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
  1707. printk("GDT: Initialization error (timeout service %d)\n",service);
  1708. return 0;
  1709. }
  1710. if (ha->status != S_BSY || --retries == 0)
  1711. break;
  1712. gdth_delay(1);
  1713. }
  1714. return (ha->status != S_OK ? 0:1);
  1715. }
  1716. /* search for devices */
  1717. static int __init gdth_search_drives(int hanum)
  1718. {
  1719. register gdth_ha_str *ha;
  1720. ushort cdev_cnt, i;
  1721. int ok;
  1722. ulong32 bus_no, drv_cnt, drv_no, j;
  1723. gdth_getch_str *chn;
  1724. gdth_drlist_str *drl;
  1725. gdth_iochan_str *ioc;
  1726. gdth_raw_iochan_str *iocr;
  1727. gdth_arcdl_str *alst;
  1728. gdth_alist_str *alst2;
  1729. gdth_oem_str_ioctl *oemstr;
  1730. #ifdef INT_COAL
  1731. gdth_perf_modes *pmod;
  1732. #endif
  1733. #ifdef GDTH_RTC
  1734. unchar rtc[12];
  1735. ulong flags;
  1736. #endif
  1737. TRACE(("gdth_search_drives() hanum %d\n",hanum));
  1738. ha = HADATA(gdth_ctr_tab[hanum]);
  1739. ok = 0;
  1740. /* initialize controller services, at first: screen service */
  1741. ha->screen_feat = 0;
  1742. if (!force_dma32) {
  1743. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
  1744. if (ok)
  1745. ha->screen_feat = GDT_64BIT;
  1746. }
  1747. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1748. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
  1749. if (!ok) {
  1750. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1751. hanum, ha->status);
  1752. return 0;
  1753. }
  1754. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1755. #ifdef GDTH_RTC
  1756. /* read realtime clock info, send to controller */
  1757. /* 1. wait for the falling edge of update flag */
  1758. spin_lock_irqsave(&rtc_lock, flags);
  1759. for (j = 0; j < 1000000; ++j)
  1760. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1761. break;
  1762. for (j = 0; j < 1000000; ++j)
  1763. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1764. break;
  1765. /* 2. read info */
  1766. do {
  1767. for (j = 0; j < 12; ++j)
  1768. rtc[j] = CMOS_READ(j);
  1769. } while (rtc[0] != CMOS_READ(0));
  1770. spin_unlock_irqrestore(&rtc_lock, flags);
  1771. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1772. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1773. /* 3. send to controller firmware */
  1774. gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
  1775. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1776. #endif
  1777. /* unfreeze all IOs */
  1778. gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
  1779. /* initialize cache service */
  1780. ha->cache_feat = 0;
  1781. if (!force_dma32) {
  1782. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
  1783. if (ok)
  1784. ha->cache_feat = GDT_64BIT;
  1785. }
  1786. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1787. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
  1788. if (!ok) {
  1789. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1790. hanum, ha->status);
  1791. return 0;
  1792. }
  1793. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1794. cdev_cnt = (ushort)ha->info;
  1795. ha->fw_vers = ha->service;
  1796. #ifdef INT_COAL
  1797. if (ha->type == GDT_PCIMPR) {
  1798. /* set perf. modes */
  1799. pmod = (gdth_perf_modes *)ha->pscratch;
  1800. pmod->version = 1;
  1801. pmod->st_mode = 1; /* enable one status buffer */
  1802. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1803. pmod->st_buff_indx1 = COALINDEX;
  1804. pmod->st_buff_addr2 = 0;
  1805. pmod->st_buff_u_addr2 = 0;
  1806. pmod->st_buff_indx2 = 0;
  1807. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1808. pmod->cmd_mode = 0; // disable all cmd buffers
  1809. pmod->cmd_buff_addr1 = 0;
  1810. pmod->cmd_buff_u_addr1 = 0;
  1811. pmod->cmd_buff_indx1 = 0;
  1812. pmod->cmd_buff_addr2 = 0;
  1813. pmod->cmd_buff_u_addr2 = 0;
  1814. pmod->cmd_buff_indx2 = 0;
  1815. pmod->cmd_buff_size = 0;
  1816. pmod->reserved1 = 0;
  1817. pmod->reserved2 = 0;
  1818. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
  1819. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1820. printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
  1821. }
  1822. }
  1823. #endif
  1824. /* detect number of buses - try new IOCTL */
  1825. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1826. iocr->hdr.version = 0xffffffff;
  1827. iocr->hdr.list_entries = MAXBUS;
  1828. iocr->hdr.first_chan = 0;
  1829. iocr->hdr.last_chan = MAXBUS-1;
  1830. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1831. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
  1832. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1833. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1834. ha->bus_cnt = iocr->hdr.chan_count;
  1835. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1836. if (iocr->list[bus_no].proc_id < MAXID)
  1837. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1838. else
  1839. ha->bus_id[bus_no] = 0xff;
  1840. }
  1841. } else {
  1842. /* old method */
  1843. chn = (gdth_getch_str *)ha->pscratch;
  1844. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1845. chn->channel_no = bus_no;
  1846. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1847. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1848. IO_CHANNEL | INVALID_CHANNEL,
  1849. sizeof(gdth_getch_str))) {
  1850. if (bus_no == 0) {
  1851. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1852. hanum, ha->status);
  1853. return 0;
  1854. }
  1855. break;
  1856. }
  1857. if (chn->siop_id < MAXID)
  1858. ha->bus_id[bus_no] = chn->siop_id;
  1859. else
  1860. ha->bus_id[bus_no] = 0xff;
  1861. }
  1862. ha->bus_cnt = (unchar)bus_no;
  1863. }
  1864. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1865. /* read cache configuration */
  1866. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
  1867. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1868. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1869. hanum, ha->status);
  1870. return 0;
  1871. }
  1872. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1873. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1874. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1875. ha->cpar.write_back,ha->cpar.block_size));
  1876. /* read board info and features */
  1877. ha->more_proc = FALSE;
  1878. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
  1879. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1880. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1881. sizeof(gdth_binfo_str));
  1882. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
  1883. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1884. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1885. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1886. ha->more_proc = TRUE;
  1887. }
  1888. } else {
  1889. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1890. strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
  1891. }
  1892. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1893. /* read more informations */
  1894. if (ha->more_proc) {
  1895. /* physical drives, channel addresses */
  1896. ioc = (gdth_iochan_str *)ha->pscratch;
  1897. ioc->hdr.version = 0xffffffff;
  1898. ioc->hdr.list_entries = MAXBUS;
  1899. ioc->hdr.first_chan = 0;
  1900. ioc->hdr.last_chan = MAXBUS-1;
  1901. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1902. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
  1903. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1904. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1905. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1906. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1907. }
  1908. } else {
  1909. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1910. ha->raw[bus_no].address = IO_CHANNEL;
  1911. ha->raw[bus_no].local_no = bus_no;
  1912. }
  1913. }
  1914. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1915. chn = (gdth_getch_str *)ha->pscratch;
  1916. chn->channel_no = ha->raw[bus_no].local_no;
  1917. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1918. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1919. ha->raw[bus_no].address | INVALID_CHANNEL,
  1920. sizeof(gdth_getch_str))) {
  1921. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1922. TRACE2(("Channel %d: %d phys. drives\n",
  1923. bus_no,chn->drive_cnt));
  1924. }
  1925. if (ha->raw[bus_no].pdev_cnt > 0) {
  1926. drl = (gdth_drlist_str *)ha->pscratch;
  1927. drl->sc_no = ha->raw[bus_no].local_no;
  1928. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1929. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1930. SCSI_DR_LIST | L_CTRL_PATTERN,
  1931. ha->raw[bus_no].address | INVALID_CHANNEL,
  1932. sizeof(gdth_drlist_str))) {
  1933. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1934. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1935. } else {
  1936. ha->raw[bus_no].pdev_cnt = 0;
  1937. }
  1938. }
  1939. }
  1940. /* logical drives */
  1941. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
  1942. INVALID_CHANNEL,sizeof(ulong32))) {
  1943. drv_cnt = *(ulong32 *)ha->pscratch;
  1944. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
  1945. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1946. for (j = 0; j < drv_cnt; ++j) {
  1947. drv_no = ((ulong32 *)ha->pscratch)[j];
  1948. if (drv_no < MAX_LDRIVES) {
  1949. ha->hdr[drv_no].is_logdrv = TRUE;
  1950. TRACE2(("Drive %d is log. drive\n",drv_no));
  1951. }
  1952. }
  1953. }
  1954. alst = (gdth_arcdl_str *)ha->pscratch;
  1955. alst->entries_avail = MAX_LDRIVES;
  1956. alst->first_entry = 0;
  1957. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1958. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1959. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1960. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1961. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1962. for (j = 0; j < alst->entries_init; ++j) {
  1963. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1964. ha->hdr[j].is_master = alst->list[j].is_master;
  1965. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1966. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1967. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1968. }
  1969. } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1970. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1971. 0, 35 * sizeof(gdth_alist_str))) {
  1972. for (j = 0; j < 35; ++j) {
  1973. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1974. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1975. ha->hdr[j].is_master = alst2->is_master;
  1976. ha->hdr[j].is_parity = alst2->is_parity;
  1977. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1978. ha->hdr[j].master_no = alst2->cd_handle;
  1979. }
  1980. }
  1981. }
  1982. }
  1983. /* initialize raw service */
  1984. ha->raw_feat = 0;
  1985. if (!force_dma32) {
  1986. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
  1987. if (ok)
  1988. ha->raw_feat = GDT_64BIT;
  1989. }
  1990. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1991. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
  1992. if (!ok) {
  1993. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1994. hanum, ha->status);
  1995. return 0;
  1996. }
  1997. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1998. /* set/get features raw service (scatter/gather) */
  1999. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
  2000. 0,0)) {
  2001. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  2002. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
  2003. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  2004. ha->info));
  2005. ha->raw_feat |= (ushort)ha->info;
  2006. }
  2007. }
  2008. /* set/get features cache service (equal to raw service) */
  2009. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
  2010. SCATTER_GATHER,0)) {
  2011. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  2012. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
  2013. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  2014. ha->info));
  2015. ha->cache_feat |= (ushort)ha->info;
  2016. }
  2017. }
  2018. /* reserve drives for raw service */
  2019. if (reserve_mode != 0) {
  2020. gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
  2021. reserve_mode == 1 ? 1 : 3, 0, 0);
  2022. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  2023. ha->status));
  2024. }
  2025. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  2026. if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
  2027. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  2028. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  2029. reserve_list[i], reserve_list[i+1],
  2030. reserve_list[i+2], reserve_list[i+3]));
  2031. if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
  2032. reserve_list[i+1], reserve_list[i+2] |
  2033. (reserve_list[i+3] << 8))) {
  2034. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  2035. hanum, ha->status);
  2036. }
  2037. }
  2038. }
  2039. /* Determine OEM string using IOCTL */
  2040. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  2041. oemstr->params.ctl_version = 0x01;
  2042. oemstr->params.buffer_size = sizeof(oemstr->text);
  2043. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  2044. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  2045. sizeof(gdth_oem_str_ioctl))) {
  2046. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  2047. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  2048. hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
  2049. /* Save the Host Drive inquiry data */
  2050. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2051. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  2052. sizeof(ha->oem_name));
  2053. #else
  2054. strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
  2055. ha->oem_name[7] = '\0';
  2056. #endif
  2057. } else {
  2058. /* Old method, based on PCI ID */
  2059. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  2060. printk("GDT-HA %d: Name: %s\n",
  2061. hanum,ha->binfo.type_string);
  2062. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2063. if (ha->oem_id == OEM_ID_INTEL)
  2064. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  2065. else
  2066. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  2067. #else
  2068. if (ha->oem_id == OEM_ID_INTEL)
  2069. strcpy(ha->oem_name,"Intel ");
  2070. else
  2071. strcpy(ha->oem_name,"ICP ");
  2072. #endif
  2073. }
  2074. /* scanning for host drives */
  2075. for (i = 0; i < cdev_cnt; ++i)
  2076. gdth_analyse_hdrive(hanum,i);
  2077. TRACE(("gdth_search_drives() OK\n"));
  2078. return 1;
  2079. }
  2080. static int gdth_analyse_hdrive(int hanum,ushort hdrive)
  2081. {
  2082. register gdth_ha_str *ha;
  2083. ulong32 drv_cyls;
  2084. int drv_hds, drv_secs;
  2085. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
  2086. if (hdrive >= MAX_HDRIVES)
  2087. return 0;
  2088. ha = HADATA(gdth_ctr_tab[hanum]);
  2089. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
  2090. return 0;
  2091. ha->hdr[hdrive].present = TRUE;
  2092. ha->hdr[hdrive].size = ha->info;
  2093. /* evaluate mapping (sectors per head, heads per cylinder) */
  2094. ha->hdr[hdrive].size &= ~SECS32;
  2095. if (ha->info2 == 0) {
  2096. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  2097. } else {
  2098. drv_hds = ha->info2 & 0xff;
  2099. drv_secs = (ha->info2 >> 8) & 0xff;
  2100. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  2101. }
  2102. ha->hdr[hdrive].heads = (unchar)drv_hds;
  2103. ha->hdr[hdrive].secs = (unchar)drv_secs;
  2104. /* round size */
  2105. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  2106. if (ha->cache_feat & GDT_64BIT) {
  2107. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
  2108. && ha->info2 != 0) {
  2109. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  2110. }
  2111. }
  2112. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  2113. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  2114. /* get informations about device */
  2115. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
  2116. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  2117. hdrive,ha->info));
  2118. ha->hdr[hdrive].devtype = (ushort)ha->info;
  2119. }
  2120. /* cluster info */
  2121. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
  2122. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  2123. hdrive,ha->info));
  2124. if (!shared_access)
  2125. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  2126. }
  2127. /* R/W attributes */
  2128. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
  2129. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  2130. hdrive,ha->info));
  2131. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  2132. }
  2133. return 1;
  2134. }
  2135. /* command queueing/sending functions */
  2136. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
  2137. {
  2138. register gdth_ha_str *ha;
  2139. register Scsi_Cmnd *pscp;
  2140. register Scsi_Cmnd *nscp;
  2141. ulong flags;
  2142. unchar b, t;
  2143. TRACE(("gdth_putq() priority %d\n",priority));
  2144. ha = HADATA(gdth_ctr_tab[hanum]);
  2145. spin_lock_irqsave(&ha->smp_lock, flags);
  2146. if (scp->done != gdth_scsi_done) {
  2147. scp->SCp.this_residual = (int)priority;
  2148. b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
  2149. t = scp->device->id;
  2150. if (priority >= DEFAULT_PRI) {
  2151. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2152. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  2153. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  2154. scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
  2155. }
  2156. }
  2157. }
  2158. if (ha->req_first==NULL) {
  2159. ha->req_first = scp; /* queue was empty */
  2160. scp->SCp.ptr = NULL;
  2161. } else { /* queue not empty */
  2162. pscp = ha->req_first;
  2163. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2164. /* priority: 0-highest,..,0xff-lowest */
  2165. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  2166. pscp = nscp;
  2167. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2168. }
  2169. pscp->SCp.ptr = (char *)scp;
  2170. scp->SCp.ptr = (char *)nscp;
  2171. }
  2172. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2173. #ifdef GDTH_STATISTICS
  2174. flags = 0;
  2175. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  2176. ++flags;
  2177. if (max_rq < flags) {
  2178. max_rq = flags;
  2179. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  2180. }
  2181. #endif
  2182. }
  2183. static void gdth_next(int hanum)
  2184. {
  2185. register gdth_ha_str *ha;
  2186. register Scsi_Cmnd *pscp;
  2187. register Scsi_Cmnd *nscp;
  2188. unchar b, t, l, firsttime;
  2189. unchar this_cmd, next_cmd;
  2190. ulong flags = 0;
  2191. int cmd_index;
  2192. TRACE(("gdth_next() hanum %d\n",hanum));
  2193. ha = HADATA(gdth_ctr_tab[hanum]);
  2194. if (!gdth_polling)
  2195. spin_lock_irqsave(&ha->smp_lock, flags);
  2196. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  2197. this_cmd = firsttime = TRUE;
  2198. next_cmd = gdth_polling ? FALSE:TRUE;
  2199. cmd_index = 0;
  2200. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  2201. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  2202. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2203. if (nscp->done != gdth_scsi_done) {
  2204. b = virt_ctr ?
  2205. NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
  2206. t = nscp->device->id;
  2207. l = nscp->device->lun;
  2208. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  2209. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2210. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  2211. continue;
  2212. }
  2213. } else
  2214. b = t = l = 0;
  2215. if (firsttime) {
  2216. if (gdth_test_busy(hanum)) { /* controller busy ? */
  2217. TRACE(("gdth_next() controller %d busy !\n",hanum));
  2218. if (!gdth_polling) {
  2219. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2220. return;
  2221. }
  2222. while (gdth_test_busy(hanum))
  2223. gdth_delay(1);
  2224. }
  2225. firsttime = FALSE;
  2226. }
  2227. if (nscp->done != gdth_scsi_done) {
  2228. if (nscp->SCp.phase == -1) {
  2229. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  2230. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  2231. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  2232. b, t, l));
  2233. /* TEST_UNIT_READY -> set scan mode */
  2234. if ((ha->scan_mode & 0x0f) == 0) {
  2235. if (b == 0 && t == 0 && l == 0) {
  2236. ha->scan_mode |= 1;
  2237. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2238. }
  2239. } else if ((ha->scan_mode & 0x0f) == 1) {
  2240. if (b == 0 && ((t == 0 && l == 1) ||
  2241. (t == 1 && l == 0))) {
  2242. nscp->SCp.sent_command = GDT_SCAN_START;
  2243. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  2244. | SCSIRAWSERVICE;
  2245. ha->scan_mode = 0x12;
  2246. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  2247. ha->scan_mode));
  2248. } else {
  2249. ha->scan_mode &= 0x10;
  2250. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2251. }
  2252. } else if (ha->scan_mode == 0x12) {
  2253. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  2254. nscp->SCp.phase = SCSIRAWSERVICE;
  2255. nscp->SCp.sent_command = GDT_SCAN_END;
  2256. ha->scan_mode &= 0x10;
  2257. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  2258. ha->scan_mode));
  2259. }
  2260. }
  2261. }
  2262. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  2263. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  2264. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  2265. /* always GDT_CLUST_INFO! */
  2266. nscp->SCp.sent_command = GDT_CLUST_INFO;
  2267. }
  2268. }
  2269. }
  2270. if (nscp->SCp.sent_command != -1) {
  2271. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  2272. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2273. this_cmd = FALSE;
  2274. next_cmd = FALSE;
  2275. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  2276. if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2277. this_cmd = FALSE;
  2278. next_cmd = FALSE;
  2279. } else {
  2280. memset((char*)nscp->sense_buffer,0,16);
  2281. nscp->sense_buffer[0] = 0x70;
  2282. nscp->sense_buffer[2] = NOT_READY;
  2283. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2284. if (!nscp->SCp.have_data_in)
  2285. nscp->SCp.have_data_in++;
  2286. else
  2287. nscp->scsi_done(nscp);
  2288. }
  2289. } else if (nscp->done == gdth_scsi_done) {
  2290. if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
  2291. this_cmd = FALSE;
  2292. next_cmd = FALSE;
  2293. } else if (b != ha->virt_bus) {
  2294. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  2295. !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2296. this_cmd = FALSE;
  2297. else
  2298. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  2299. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2300. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2301. nscp->cmnd[0], b, t, l));
  2302. nscp->result = DID_BAD_TARGET << 16;
  2303. if (!nscp->SCp.have_data_in)
  2304. nscp->SCp.have_data_in++;
  2305. else
  2306. nscp->scsi_done(nscp);
  2307. } else {
  2308. switch (nscp->cmnd[0]) {
  2309. case TEST_UNIT_READY:
  2310. case INQUIRY:
  2311. case REQUEST_SENSE:
  2312. case READ_CAPACITY:
  2313. case VERIFY:
  2314. case START_STOP:
  2315. case MODE_SENSE:
  2316. case SERVICE_ACTION_IN:
  2317. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2318. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2319. nscp->cmnd[4],nscp->cmnd[5]));
  2320. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2321. /* return UNIT_ATTENTION */
  2322. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2323. nscp->cmnd[0], t));
  2324. ha->hdr[t].media_changed = FALSE;
  2325. memset((char*)nscp->sense_buffer,0,16);
  2326. nscp->sense_buffer[0] = 0x70;
  2327. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2328. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2329. if (!nscp->SCp.have_data_in)
  2330. nscp->SCp.have_data_in++;
  2331. else
  2332. nscp->scsi_done(nscp);
  2333. } else if (gdth_internal_cache_cmd(hanum,nscp))
  2334. nscp->scsi_done(nscp);
  2335. break;
  2336. case ALLOW_MEDIUM_REMOVAL:
  2337. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2338. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2339. nscp->cmnd[4],nscp->cmnd[5]));
  2340. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2341. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2342. nscp->result = DID_OK << 16;
  2343. nscp->sense_buffer[0] = 0;
  2344. if (!nscp->SCp.have_data_in)
  2345. nscp->SCp.have_data_in++;
  2346. else
  2347. nscp->scsi_done(nscp);
  2348. } else {
  2349. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2350. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2351. nscp->cmnd[4],nscp->cmnd[3]));
  2352. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2353. this_cmd = FALSE;
  2354. }
  2355. break;
  2356. case RESERVE:
  2357. case RELEASE:
  2358. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2359. "RESERVE" : "RELEASE"));
  2360. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2361. this_cmd = FALSE;
  2362. break;
  2363. case READ_6:
  2364. case WRITE_6:
  2365. case READ_10:
  2366. case WRITE_10:
  2367. case READ_16:
  2368. case WRITE_16:
  2369. if (ha->hdr[t].media_changed) {
  2370. /* return UNIT_ATTENTION */
  2371. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2372. nscp->cmnd[0], t));
  2373. ha->hdr[t].media_changed = FALSE;
  2374. memset((char*)nscp->sense_buffer,0,16);
  2375. nscp->sense_buffer[0] = 0x70;
  2376. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2377. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2378. if (!nscp->SCp.have_data_in)
  2379. nscp->SCp.have_data_in++;
  2380. else
  2381. nscp->scsi_done(nscp);
  2382. } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2383. this_cmd = FALSE;
  2384. break;
  2385. default:
  2386. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2387. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2388. nscp->cmnd[4],nscp->cmnd[5]));
  2389. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2390. hanum, nscp->cmnd[0]);
  2391. nscp->result = DID_ABORT << 16;
  2392. if (!nscp->SCp.have_data_in)
  2393. nscp->SCp.have_data_in++;
  2394. else
  2395. nscp->scsi_done(nscp);
  2396. break;
  2397. }
  2398. }
  2399. if (!this_cmd)
  2400. break;
  2401. if (nscp == ha->req_first)
  2402. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2403. else
  2404. pscp->SCp.ptr = nscp->SCp.ptr;
  2405. if (!next_cmd)
  2406. break;
  2407. }
  2408. if (ha->cmd_cnt > 0) {
  2409. gdth_release_event(hanum);
  2410. }
  2411. if (!gdth_polling)
  2412. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2413. if (gdth_polling && ha->cmd_cnt > 0) {
  2414. if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
  2415. printk("GDT-HA %d: Command %d timed out !\n",
  2416. hanum,cmd_index);
  2417. }
  2418. }
  2419. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  2420. char *buffer,ushort count)
  2421. {
  2422. ushort cpcount,i;
  2423. ushort cpsum,cpnow;
  2424. struct scatterlist *sl;
  2425. gdth_ha_str *ha;
  2426. char *address;
  2427. cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
  2428. ha = HADATA(gdth_ctr_tab[hanum]);
  2429. if (scp->use_sg) {
  2430. sl = (struct scatterlist *)scp->request_buffer;
  2431. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2432. unsigned long flags;
  2433. cpnow = (ushort)sl->length;
  2434. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2435. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2436. if (cpsum+cpnow > cpcount)
  2437. cpnow = cpcount - cpsum;
  2438. cpsum += cpnow;
  2439. if (!sl->page) {
  2440. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2441. hanum);
  2442. return;
  2443. }
  2444. local_irq_save(flags);
  2445. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2446. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2447. memcpy(address,buffer,cpnow);
  2448. flush_dcache_page(sl->page);
  2449. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2450. #else
  2451. address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
  2452. memcpy(address,buffer,cpnow);
  2453. flush_dcache_page(sl->page);
  2454. kunmap_atomic(address, KM_BH_IRQ);
  2455. #endif
  2456. local_irq_restore(flags);
  2457. if (cpsum == cpcount)
  2458. break;
  2459. buffer += cpnow;
  2460. }
  2461. } else {
  2462. TRACE(("copy_internal() count %d\n",cpcount));
  2463. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2464. }
  2465. }
  2466. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
  2467. {
  2468. register gdth_ha_str *ha;
  2469. unchar t;
  2470. gdth_inq_data inq;
  2471. gdth_rdcap_data rdc;
  2472. gdth_sense_data sd;
  2473. gdth_modep_data mpd;
  2474. ha = HADATA(gdth_ctr_tab[hanum]);
  2475. t = scp->device->id;
  2476. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2477. scp->cmnd[0],t));
  2478. scp->result = DID_OK << 16;
  2479. scp->sense_buffer[0] = 0;
  2480. switch (scp->cmnd[0]) {
  2481. case TEST_UNIT_READY:
  2482. case VERIFY:
  2483. case START_STOP:
  2484. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2485. break;
  2486. case INQUIRY:
  2487. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2488. t,ha->hdr[t].devtype));
  2489. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2490. /* you can here set all disks to removable, if you want to do
  2491. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2492. inq.modif_rmb = 0x00;
  2493. if ((ha->hdr[t].devtype & 1) ||
  2494. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2495. inq.modif_rmb = 0x80;
  2496. inq.version = 2;
  2497. inq.resp_aenc = 2;
  2498. inq.add_length= 32;
  2499. strcpy(inq.vendor,ha->oem_name);
  2500. sprintf(inq.product,"Host Drive #%02d",t);
  2501. strcpy(inq.revision," ");
  2502. gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
  2503. break;
  2504. case REQUEST_SENSE:
  2505. TRACE2(("Request sense hdrive %d\n",t));
  2506. sd.errorcode = 0x70;
  2507. sd.segno = 0x00;
  2508. sd.key = NO_SENSE;
  2509. sd.info = 0;
  2510. sd.add_length= 0;
  2511. gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
  2512. break;
  2513. case MODE_SENSE:
  2514. TRACE2(("Mode sense hdrive %d\n",t));
  2515. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2516. mpd.hd.data_length = sizeof(gdth_modep_data);
  2517. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2518. mpd.hd.bd_length = sizeof(mpd.bd);
  2519. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2520. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2521. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2522. gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
  2523. break;
  2524. case READ_CAPACITY:
  2525. TRACE2(("Read capacity hdrive %d\n",t));
  2526. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2527. rdc.last_block_no = 0xffffffff;
  2528. else
  2529. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2530. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2531. gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
  2532. break;
  2533. case SERVICE_ACTION_IN:
  2534. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2535. (ha->cache_feat & GDT_64BIT)) {
  2536. gdth_rdcap16_data rdc16;
  2537. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2538. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2539. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2540. gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
  2541. } else {
  2542. scp->result = DID_ABORT << 16;
  2543. }
  2544. break;
  2545. default:
  2546. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2547. break;
  2548. }
  2549. if (!scp->SCp.have_data_in)
  2550. scp->SCp.have_data_in++;
  2551. else
  2552. return 1;
  2553. return 0;
  2554. }
  2555. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
  2556. {
  2557. register gdth_ha_str *ha;
  2558. register gdth_cmd_str *cmdp;
  2559. struct scatterlist *sl;
  2560. ulong32 cnt, blockcnt;
  2561. ulong64 no, blockno;
  2562. dma_addr_t phys_addr;
  2563. int i, cmd_index, read_write, sgcnt, mode64;
  2564. struct page *page;
  2565. ulong offset;
  2566. ha = HADATA(gdth_ctr_tab[hanum]);
  2567. cmdp = ha->pccb;
  2568. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2569. scp->cmnd[0],scp->cmd_len,hdrive));
  2570. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2571. return 0;
  2572. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2573. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2574. not required, should not occur due to error return on
  2575. READ_CAPACITY_16 */
  2576. cmdp->Service = CACHESERVICE;
  2577. cmdp->RequestBuffer = scp;
  2578. /* search free command index */
  2579. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2580. TRACE(("GDT: No free command index found\n"));
  2581. return 0;
  2582. }
  2583. /* if it's the first command, set command semaphore */
  2584. if (ha->cmd_cnt == 0)
  2585. gdth_set_sema0(hanum);
  2586. /* fill command */
  2587. read_write = 0;
  2588. if (scp->SCp.sent_command != -1)
  2589. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2590. else if (scp->cmnd[0] == RESERVE)
  2591. cmdp->OpCode = GDT_RESERVE_DRV;
  2592. else if (scp->cmnd[0] == RELEASE)
  2593. cmdp->OpCode = GDT_RELEASE_DRV;
  2594. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2595. if (scp->cmnd[4] & 1) /* prevent ? */
  2596. cmdp->OpCode = GDT_MOUNT;
  2597. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2598. cmdp->OpCode = GDT_UNMOUNT;
  2599. else
  2600. cmdp->OpCode = GDT_FLUSH;
  2601. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2602. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2603. ) {
  2604. read_write = 1;
  2605. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2606. (ha->cache_feat & GDT_WR_THROUGH)))
  2607. cmdp->OpCode = GDT_WRITE_THR;
  2608. else
  2609. cmdp->OpCode = GDT_WRITE;
  2610. } else {
  2611. read_write = 2;
  2612. cmdp->OpCode = GDT_READ;
  2613. }
  2614. cmdp->BoardNode = LOCALBOARD;
  2615. if (mode64) {
  2616. cmdp->u.cache64.DeviceNo = hdrive;
  2617. cmdp->u.cache64.BlockNo = 1;
  2618. cmdp->u.cache64.sg_canz = 0;
  2619. } else {
  2620. cmdp->u.cache.DeviceNo = hdrive;
  2621. cmdp->u.cache.BlockNo = 1;
  2622. cmdp->u.cache.sg_canz = 0;
  2623. }
  2624. if (read_write) {
  2625. if (scp->cmd_len == 16) {
  2626. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2627. blockno = be64_to_cpu(no);
  2628. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2629. blockcnt = be32_to_cpu(cnt);
  2630. } else if (scp->cmd_len == 10) {
  2631. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2632. blockno = be32_to_cpu(no);
  2633. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2634. blockcnt = be16_to_cpu(cnt);
  2635. } else {
  2636. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2637. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2638. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2639. }
  2640. if (mode64) {
  2641. cmdp->u.cache64.BlockNo = blockno;
  2642. cmdp->u.cache64.BlockCnt = blockcnt;
  2643. } else {
  2644. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2645. cmdp->u.cache.BlockCnt = blockcnt;
  2646. }
  2647. if (scp->use_sg) {
  2648. sl = (struct scatterlist *)scp->request_buffer;
  2649. sgcnt = scp->use_sg;
  2650. scp->SCp.Status = GDTH_MAP_SG;
  2651. scp->SCp.Message = (read_write == 1 ?
  2652. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2653. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2654. if (mode64) {
  2655. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2656. cmdp->u.cache64.sg_canz = sgcnt;
  2657. for (i=0; i<sgcnt; ++i,++sl) {
  2658. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2659. #ifdef GDTH_DMA_STATISTICS
  2660. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2661. ha->dma64_cnt++;
  2662. else
  2663. ha->dma32_cnt++;
  2664. #endif
  2665. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2666. }
  2667. } else {
  2668. cmdp->u.cache.DestAddr= 0xffffffff;
  2669. cmdp->u.cache.sg_canz = sgcnt;
  2670. for (i=0; i<sgcnt; ++i,++sl) {
  2671. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2672. #ifdef GDTH_DMA_STATISTICS
  2673. ha->dma32_cnt++;
  2674. #endif
  2675. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2676. }
  2677. }
  2678. #ifdef GDTH_STATISTICS
  2679. if (max_sg < (ulong32)sgcnt) {
  2680. max_sg = (ulong32)sgcnt;
  2681. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2682. }
  2683. #endif
  2684. } else if (scp->request_bufflen) {
  2685. scp->SCp.Status = GDTH_MAP_SINGLE;
  2686. scp->SCp.Message = (read_write == 1 ?
  2687. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2688. page = virt_to_page(scp->request_buffer);
  2689. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2690. phys_addr = pci_map_page(ha->pdev,page,offset,
  2691. scp->request_bufflen,scp->SCp.Message);
  2692. scp->SCp.dma_handle = phys_addr;
  2693. if (mode64) {
  2694. if (ha->cache_feat & SCATTER_GATHER) {
  2695. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2696. cmdp->u.cache64.sg_canz = 1;
  2697. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2698. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2699. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2700. } else {
  2701. cmdp->u.cache64.DestAddr = phys_addr;
  2702. cmdp->u.cache64.sg_canz= 0;
  2703. }
  2704. } else {
  2705. if (ha->cache_feat & SCATTER_GATHER) {
  2706. cmdp->u.cache.DestAddr = 0xffffffff;
  2707. cmdp->u.cache.sg_canz = 1;
  2708. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2709. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2710. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2711. } else {
  2712. cmdp->u.cache.DestAddr = phys_addr;
  2713. cmdp->u.cache.sg_canz= 0;
  2714. }
  2715. }
  2716. }
  2717. }
  2718. /* evaluate command size, check space */
  2719. if (mode64) {
  2720. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2721. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2722. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2723. cmdp->u.cache64.sg_lst[0].sg_len));
  2724. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2725. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2726. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2727. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2728. } else {
  2729. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2730. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2731. cmdp->u.cache.sg_lst[0].sg_ptr,
  2732. cmdp->u.cache.sg_lst[0].sg_len));
  2733. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2734. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2735. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2736. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2737. }
  2738. if (ha->cmd_len & 3)
  2739. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2740. if (ha->cmd_cnt > 0) {
  2741. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2742. ha->ic_all_size) {
  2743. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2744. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2745. return 0;
  2746. }
  2747. }
  2748. /* copy command */
  2749. gdth_copy_command(hanum);
  2750. return cmd_index;
  2751. }
  2752. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
  2753. {
  2754. register gdth_ha_str *ha;
  2755. register gdth_cmd_str *cmdp;
  2756. struct scatterlist *sl;
  2757. ushort i;
  2758. dma_addr_t phys_addr, sense_paddr;
  2759. int cmd_index, sgcnt, mode64;
  2760. unchar t,l;
  2761. struct page *page;
  2762. ulong offset;
  2763. ha = HADATA(gdth_ctr_tab[hanum]);
  2764. t = scp->device->id;
  2765. l = scp->device->lun;
  2766. cmdp = ha->pccb;
  2767. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2768. scp->cmnd[0],b,t,l));
  2769. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2770. return 0;
  2771. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2772. cmdp->Service = SCSIRAWSERVICE;
  2773. cmdp->RequestBuffer = scp;
  2774. /* search free command index */
  2775. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2776. TRACE(("GDT: No free command index found\n"));
  2777. return 0;
  2778. }
  2779. /* if it's the first command, set command semaphore */
  2780. if (ha->cmd_cnt == 0)
  2781. gdth_set_sema0(hanum);
  2782. /* fill command */
  2783. if (scp->SCp.sent_command != -1) {
  2784. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2785. cmdp->BoardNode = LOCALBOARD;
  2786. if (mode64) {
  2787. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2788. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2789. cmdp->OpCode, cmdp->u.raw64.direction));
  2790. /* evaluate command size */
  2791. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2792. } else {
  2793. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2794. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2795. cmdp->OpCode, cmdp->u.raw.direction));
  2796. /* evaluate command size */
  2797. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2798. }
  2799. } else {
  2800. page = virt_to_page(scp->sense_buffer);
  2801. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2802. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2803. 16,PCI_DMA_FROMDEVICE);
  2804. *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
  2805. /* high part, if 64bit */
  2806. *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
  2807. cmdp->OpCode = GDT_WRITE; /* always */
  2808. cmdp->BoardNode = LOCALBOARD;
  2809. if (mode64) {
  2810. cmdp->u.raw64.reserved = 0;
  2811. cmdp->u.raw64.mdisc_time = 0;
  2812. cmdp->u.raw64.mcon_time = 0;
  2813. cmdp->u.raw64.clen = scp->cmd_len;
  2814. cmdp->u.raw64.target = t;
  2815. cmdp->u.raw64.lun = l;
  2816. cmdp->u.raw64.bus = b;
  2817. cmdp->u.raw64.priority = 0;
  2818. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2819. cmdp->u.raw64.sense_len = 16;
  2820. cmdp->u.raw64.sense_data = sense_paddr;
  2821. cmdp->u.raw64.direction =
  2822. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2823. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2824. cmdp->u.raw64.sg_ranz = 0;
  2825. } else {
  2826. cmdp->u.raw.reserved = 0;
  2827. cmdp->u.raw.mdisc_time = 0;
  2828. cmdp->u.raw.mcon_time = 0;
  2829. cmdp->u.raw.clen = scp->cmd_len;
  2830. cmdp->u.raw.target = t;
  2831. cmdp->u.raw.lun = l;
  2832. cmdp->u.raw.bus = b;
  2833. cmdp->u.raw.priority = 0;
  2834. cmdp->u.raw.link_p = 0;
  2835. cmdp->u.raw.sdlen = scp->request_bufflen;
  2836. cmdp->u.raw.sense_len = 16;
  2837. cmdp->u.raw.sense_data = sense_paddr;
  2838. cmdp->u.raw.direction =
  2839. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2840. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2841. cmdp->u.raw.sg_ranz = 0;
  2842. }
  2843. if (scp->use_sg) {
  2844. sl = (struct scatterlist *)scp->request_buffer;
  2845. sgcnt = scp->use_sg;
  2846. scp->SCp.Status = GDTH_MAP_SG;
  2847. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2848. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2849. if (mode64) {
  2850. cmdp->u.raw64.sdata = (ulong64)-1;
  2851. cmdp->u.raw64.sg_ranz = sgcnt;
  2852. for (i=0; i<sgcnt; ++i,++sl) {
  2853. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2854. #ifdef GDTH_DMA_STATISTICS
  2855. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2856. ha->dma64_cnt++;
  2857. else
  2858. ha->dma32_cnt++;
  2859. #endif
  2860. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2861. }
  2862. } else {
  2863. cmdp->u.raw.sdata = 0xffffffff;
  2864. cmdp->u.raw.sg_ranz = sgcnt;
  2865. for (i=0; i<sgcnt; ++i,++sl) {
  2866. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2867. #ifdef GDTH_DMA_STATISTICS
  2868. ha->dma32_cnt++;
  2869. #endif
  2870. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2871. }
  2872. }
  2873. #ifdef GDTH_STATISTICS
  2874. if (max_sg < sgcnt) {
  2875. max_sg = sgcnt;
  2876. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2877. }
  2878. #endif
  2879. } else if (scp->request_bufflen) {
  2880. scp->SCp.Status = GDTH_MAP_SINGLE;
  2881. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2882. page = virt_to_page(scp->request_buffer);
  2883. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2884. phys_addr = pci_map_page(ha->pdev,page,offset,
  2885. scp->request_bufflen,scp->SCp.Message);
  2886. scp->SCp.dma_handle = phys_addr;
  2887. if (mode64) {
  2888. if (ha->raw_feat & SCATTER_GATHER) {
  2889. cmdp->u.raw64.sdata = (ulong64)-1;
  2890. cmdp->u.raw64.sg_ranz= 1;
  2891. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2892. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2893. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2894. } else {
  2895. cmdp->u.raw64.sdata = phys_addr;
  2896. cmdp->u.raw64.sg_ranz= 0;
  2897. }
  2898. } else {
  2899. if (ha->raw_feat & SCATTER_GATHER) {
  2900. cmdp->u.raw.sdata = 0xffffffff;
  2901. cmdp->u.raw.sg_ranz= 1;
  2902. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2903. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2904. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2905. } else {
  2906. cmdp->u.raw.sdata = phys_addr;
  2907. cmdp->u.raw.sg_ranz= 0;
  2908. }
  2909. }
  2910. }
  2911. if (mode64) {
  2912. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2913. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2914. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2915. cmdp->u.raw64.sg_lst[0].sg_len));
  2916. /* evaluate command size */
  2917. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2918. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2919. } else {
  2920. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2921. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2922. cmdp->u.raw.sg_lst[0].sg_ptr,
  2923. cmdp->u.raw.sg_lst[0].sg_len));
  2924. /* evaluate command size */
  2925. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2926. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2927. }
  2928. }
  2929. /* check space */
  2930. if (ha->cmd_len & 3)
  2931. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2932. if (ha->cmd_cnt > 0) {
  2933. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2934. ha->ic_all_size) {
  2935. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2936. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2937. return 0;
  2938. }
  2939. }
  2940. /* copy command */
  2941. gdth_copy_command(hanum);
  2942. return cmd_index;
  2943. }
  2944. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
  2945. {
  2946. register gdth_ha_str *ha;
  2947. register gdth_cmd_str *cmdp;
  2948. int cmd_index;
  2949. ha = HADATA(gdth_ctr_tab[hanum]);
  2950. cmdp= ha->pccb;
  2951. TRACE2(("gdth_special_cmd(): "));
  2952. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2953. return 0;
  2954. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2955. cmdp->RequestBuffer = scp;
  2956. /* search free command index */
  2957. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2958. TRACE(("GDT: No free command index found\n"));
  2959. return 0;
  2960. }
  2961. /* if it's the first command, set command semaphore */
  2962. if (ha->cmd_cnt == 0)
  2963. gdth_set_sema0(hanum);
  2964. /* evaluate command size, check space */
  2965. if (cmdp->OpCode == GDT_IOCTL) {
  2966. TRACE2(("IOCTL\n"));
  2967. ha->cmd_len =
  2968. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2969. } else if (cmdp->Service == CACHESERVICE) {
  2970. TRACE2(("cache command %d\n",cmdp->OpCode));
  2971. if (ha->cache_feat & GDT_64BIT)
  2972. ha->cmd_len =
  2973. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2974. else
  2975. ha->cmd_len =
  2976. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2977. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2978. TRACE2(("raw command %d\n",cmdp->OpCode));
  2979. if (ha->raw_feat & GDT_64BIT)
  2980. ha->cmd_len =
  2981. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2982. else
  2983. ha->cmd_len =
  2984. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2985. }
  2986. if (ha->cmd_len & 3)
  2987. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2988. if (ha->cmd_cnt > 0) {
  2989. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2990. ha->ic_all_size) {
  2991. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2992. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2993. return 0;
  2994. }
  2995. }
  2996. /* copy command */
  2997. gdth_copy_command(hanum);
  2998. return cmd_index;
  2999. }
  3000. /* Controller event handling functions */
  3001. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  3002. ushort idx, gdth_evt_data *evt)
  3003. {
  3004. gdth_evt_str *e;
  3005. struct timeval tv;
  3006. /* no GDTH_LOCK_HA() ! */
  3007. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  3008. if (source == 0) /* no source -> no event */
  3009. return NULL;
  3010. if (ebuffer[elastidx].event_source == source &&
  3011. ebuffer[elastidx].event_idx == idx &&
  3012. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  3013. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  3014. (char *)&evt->eu, evt->size)) ||
  3015. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  3016. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  3017. (char *)&evt->event_string)))) {
  3018. e = &ebuffer[elastidx];
  3019. do_gettimeofday(&tv);
  3020. e->last_stamp = tv.tv_sec;
  3021. ++e->same_count;
  3022. } else {
  3023. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  3024. ++elastidx;
  3025. if (elastidx == MAX_EVENTS)
  3026. elastidx = 0;
  3027. if (elastidx == eoldidx) { /* reached mark ? */
  3028. ++eoldidx;
  3029. if (eoldidx == MAX_EVENTS)
  3030. eoldidx = 0;
  3031. }
  3032. }
  3033. e = &ebuffer[elastidx];
  3034. e->event_source = source;
  3035. e->event_idx = idx;
  3036. do_gettimeofday(&tv);
  3037. e->first_stamp = e->last_stamp = tv.tv_sec;
  3038. e->same_count = 1;
  3039. e->event_data = *evt;
  3040. e->application = 0;
  3041. }
  3042. return e;
  3043. }
  3044. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  3045. {
  3046. gdth_evt_str *e;
  3047. int eindex;
  3048. ulong flags;
  3049. TRACE2(("gdth_read_event() handle %d\n", handle));
  3050. spin_lock_irqsave(&ha->smp_lock, flags);
  3051. if (handle == -1)
  3052. eindex = eoldidx;
  3053. else
  3054. eindex = handle;
  3055. estr->event_source = 0;
  3056. if (eindex >= MAX_EVENTS) {
  3057. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3058. return eindex;
  3059. }
  3060. e = &ebuffer[eindex];
  3061. if (e->event_source != 0) {
  3062. if (eindex != elastidx) {
  3063. if (++eindex == MAX_EVENTS)
  3064. eindex = 0;
  3065. } else {
  3066. eindex = -1;
  3067. }
  3068. memcpy(estr, e, sizeof(gdth_evt_str));
  3069. }
  3070. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3071. return eindex;
  3072. }
  3073. static void gdth_readapp_event(gdth_ha_str *ha,
  3074. unchar application, gdth_evt_str *estr)
  3075. {
  3076. gdth_evt_str *e;
  3077. int eindex;
  3078. ulong flags;
  3079. unchar found = FALSE;
  3080. TRACE2(("gdth_readapp_event() app. %d\n", application));
  3081. spin_lock_irqsave(&ha->smp_lock, flags);
  3082. eindex = eoldidx;
  3083. for (;;) {
  3084. e = &ebuffer[eindex];
  3085. if (e->event_source == 0)
  3086. break;
  3087. if ((e->application & application) == 0) {
  3088. e->application |= application;
  3089. found = TRUE;
  3090. break;
  3091. }
  3092. if (eindex == elastidx)
  3093. break;
  3094. if (++eindex == MAX_EVENTS)
  3095. eindex = 0;
  3096. }
  3097. if (found)
  3098. memcpy(estr, e, sizeof(gdth_evt_str));
  3099. else
  3100. estr->event_source = 0;
  3101. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3102. }
  3103. static void gdth_clear_events(void)
  3104. {
  3105. TRACE(("gdth_clear_events()"));
  3106. eoldidx = elastidx = 0;
  3107. ebuffer[0].event_source = 0;
  3108. }
  3109. /* SCSI interface functions */
  3110. static irqreturn_t gdth_interrupt(int irq,void *dev_id)
  3111. {
  3112. gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
  3113. register gdth_ha_str *ha;
  3114. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  3115. gdt6_dpram_str __iomem *dp6_ptr;
  3116. gdt2_dpram_str __iomem *dp2_ptr;
  3117. Scsi_Cmnd *scp;
  3118. int hanum, rval, i;
  3119. unchar IStatus;
  3120. ushort Service;
  3121. ulong flags = 0;
  3122. #ifdef INT_COAL
  3123. int coalesced = FALSE;
  3124. int next = FALSE;
  3125. gdth_coal_status *pcs = NULL;
  3126. int act_int_coal = 0;
  3127. #endif
  3128. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  3129. /* if polling and not from gdth_wait() -> return */
  3130. if (gdth_polling) {
  3131. if (!gdth_from_wait) {
  3132. return IRQ_HANDLED;
  3133. }
  3134. }
  3135. if (!gdth_polling)
  3136. spin_lock_irqsave(&ha2->smp_lock, flags);
  3137. wait_index = 0;
  3138. /* search controller */
  3139. if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
  3140. /* spurious interrupt */
  3141. if (!gdth_polling)
  3142. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3143. return IRQ_HANDLED;
  3144. }
  3145. ha = HADATA(gdth_ctr_tab[hanum]);
  3146. #ifdef GDTH_STATISTICS
  3147. ++act_ints;
  3148. #endif
  3149. #ifdef INT_COAL
  3150. /* See if the fw is returning coalesced status */
  3151. if (IStatus == COALINDEX) {
  3152. /* Coalesced status. Setup the initial status
  3153. buffer pointer and flags */
  3154. pcs = ha->coal_stat;
  3155. coalesced = TRUE;
  3156. next = TRUE;
  3157. }
  3158. do {
  3159. if (coalesced) {
  3160. /* For coalesced requests all status
  3161. information is found in the status buffer */
  3162. IStatus = (unchar)(pcs->status & 0xff);
  3163. }
  3164. #endif
  3165. if (ha->type == GDT_EISA) {
  3166. if (IStatus & 0x80) { /* error flag */
  3167. IStatus &= ~0x80;
  3168. ha->status = inw(ha->bmic + MAILBOXREG+8);
  3169. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3170. } else /* no error */
  3171. ha->status = S_OK;
  3172. ha->info = inl(ha->bmic + MAILBOXREG+12);
  3173. ha->service = inw(ha->bmic + MAILBOXREG+10);
  3174. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  3175. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  3176. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  3177. } else if (ha->type == GDT_ISA) {
  3178. dp2_ptr = ha->brd;
  3179. if (IStatus & 0x80) { /* error flag */
  3180. IStatus &= ~0x80;
  3181. ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
  3182. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3183. } else /* no error */
  3184. ha->status = S_OK;
  3185. ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
  3186. ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
  3187. ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
  3188. gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  3189. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  3190. gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  3191. } else if (ha->type == GDT_PCI) {
  3192. dp6_ptr = ha->brd;
  3193. if (IStatus & 0x80) { /* error flag */
  3194. IStatus &= ~0x80;
  3195. ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
  3196. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3197. } else /* no error */
  3198. ha->status = S_OK;
  3199. ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
  3200. ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
  3201. ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
  3202. gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  3203. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  3204. gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  3205. } else if (ha->type == GDT_PCINEW) {
  3206. if (IStatus & 0x80) { /* error flag */
  3207. IStatus &= ~0x80;
  3208. ha->status = inw(PTR2USHORT(&ha->plx->status));
  3209. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3210. } else
  3211. ha->status = S_OK;
  3212. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  3213. ha->service = inw(PTR2USHORT(&ha->plx->service));
  3214. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  3215. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  3216. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  3217. } else if (ha->type == GDT_PCIMPR) {
  3218. dp6m_ptr = ha->brd;
  3219. if (IStatus & 0x80) { /* error flag */
  3220. IStatus &= ~0x80;
  3221. #ifdef INT_COAL
  3222. if (coalesced)
  3223. ha->status = pcs->ext_status & 0xffff;
  3224. else
  3225. #endif
  3226. ha->status = gdth_readw(&dp6m_ptr->i960r.status);
  3227. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3228. } else /* no error */
  3229. ha->status = S_OK;
  3230. #ifdef INT_COAL
  3231. /* get information */
  3232. if (coalesced) {
  3233. ha->info = pcs->info0;
  3234. ha->info2 = pcs->info1;
  3235. ha->service = (pcs->ext_status >> 16) & 0xffff;
  3236. } else
  3237. #endif
  3238. {
  3239. ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
  3240. ha->service = gdth_readw(&dp6m_ptr->i960r.service);
  3241. ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
  3242. }
  3243. /* event string */
  3244. if (IStatus == ASYNCINDEX) {
  3245. if (ha->service != SCREENSERVICE &&
  3246. (ha->fw_vers & 0xff) >= 0x1a) {
  3247. ha->dvr.severity = gdth_readb
  3248. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  3249. for (i = 0; i < 256; ++i) {
  3250. ha->dvr.event_string[i] = gdth_readb
  3251. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  3252. if (ha->dvr.event_string[i] == 0)
  3253. break;
  3254. }
  3255. }
  3256. }
  3257. #ifdef INT_COAL
  3258. /* Make sure that non coalesced interrupts get cleared
  3259. before being handled by gdth_async_event/gdth_sync_event */
  3260. if (!coalesced)
  3261. #endif
  3262. {
  3263. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3264. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3265. }
  3266. } else {
  3267. TRACE2(("gdth_interrupt() unknown controller type\n"));
  3268. if (!gdth_polling)
  3269. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3270. return IRQ_HANDLED;
  3271. }
  3272. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  3273. IStatus,ha->status,ha->info));
  3274. if (gdth_from_wait) {
  3275. wait_hanum = hanum;
  3276. wait_index = (int)IStatus;
  3277. }
  3278. if (IStatus == ASYNCINDEX) {
  3279. TRACE2(("gdth_interrupt() async. event\n"));
  3280. gdth_async_event(hanum);
  3281. if (!gdth_polling)
  3282. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3283. gdth_next(hanum);
  3284. return IRQ_HANDLED;
  3285. }
  3286. if (IStatus == SPEZINDEX) {
  3287. TRACE2(("Service unknown or not initialized !\n"));
  3288. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3289. ha->dvr.eu.driver.ionode = hanum;
  3290. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  3291. if (!gdth_polling)
  3292. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3293. return IRQ_HANDLED;
  3294. }
  3295. scp = ha->cmd_tab[IStatus-2].cmnd;
  3296. Service = ha->cmd_tab[IStatus-2].service;
  3297. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  3298. if (scp == UNUSED_CMND) {
  3299. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  3300. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3301. ha->dvr.eu.driver.ionode = hanum;
  3302. ha->dvr.eu.driver.index = IStatus;
  3303. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  3304. if (!gdth_polling)
  3305. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3306. return IRQ_HANDLED;
  3307. }
  3308. if (scp == INTERNAL_CMND) {
  3309. TRACE(("gdth_interrupt() answer to internal command\n"));
  3310. if (!gdth_polling)
  3311. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3312. return IRQ_HANDLED;
  3313. }
  3314. TRACE(("gdth_interrupt() sync. status\n"));
  3315. rval = gdth_sync_event(hanum,Service,IStatus,scp);
  3316. if (!gdth_polling)
  3317. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3318. if (rval == 2) {
  3319. gdth_putq(hanum,scp,scp->SCp.this_residual);
  3320. } else if (rval == 1) {
  3321. scp->scsi_done(scp);
  3322. }
  3323. #ifdef INT_COAL
  3324. if (coalesced) {
  3325. /* go to the next status in the status buffer */
  3326. ++pcs;
  3327. #ifdef GDTH_STATISTICS
  3328. ++act_int_coal;
  3329. if (act_int_coal > max_int_coal) {
  3330. max_int_coal = act_int_coal;
  3331. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  3332. }
  3333. #endif
  3334. /* see if there is another status */
  3335. if (pcs->status == 0)
  3336. /* Stop the coalesce loop */
  3337. next = FALSE;
  3338. }
  3339. } while (next);
  3340. /* coalescing only for new GDT_PCIMPR controllers available */
  3341. if (ha->type == GDT_PCIMPR && coalesced) {
  3342. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3343. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3344. }
  3345. #endif
  3346. gdth_next(hanum);
  3347. return IRQ_HANDLED;
  3348. }
  3349. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
  3350. {
  3351. register gdth_ha_str *ha;
  3352. gdth_msg_str *msg;
  3353. gdth_cmd_str *cmdp;
  3354. unchar b, t;
  3355. ha = HADATA(gdth_ctr_tab[hanum]);
  3356. cmdp = ha->pccb;
  3357. TRACE(("gdth_sync_event() serv %d status %d\n",
  3358. service,ha->status));
  3359. if (service == SCREENSERVICE) {
  3360. msg = ha->pmsg;
  3361. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3362. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3363. if (msg->msg_len > MSGLEN+1)
  3364. msg->msg_len = MSGLEN+1;
  3365. if (msg->msg_len)
  3366. if (!(msg->msg_answer && msg->msg_ext)) {
  3367. msg->msg_text[msg->msg_len] = '\0';
  3368. printk("%s",msg->msg_text);
  3369. }
  3370. if (msg->msg_ext && !msg->msg_answer) {
  3371. while (gdth_test_busy(hanum))
  3372. gdth_delay(0);
  3373. cmdp->Service = SCREENSERVICE;
  3374. cmdp->RequestBuffer = SCREEN_CMND;
  3375. gdth_get_cmd_index(hanum);
  3376. gdth_set_sema0(hanum);
  3377. cmdp->OpCode = GDT_READ;
  3378. cmdp->BoardNode = LOCALBOARD;
  3379. cmdp->u.screen.reserved = 0;
  3380. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3381. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3382. ha->cmd_offs_dpmem = 0;
  3383. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3384. + sizeof(ulong64);
  3385. ha->cmd_cnt = 0;
  3386. gdth_copy_command(hanum);
  3387. gdth_release_event(hanum);
  3388. return 0;
  3389. }
  3390. if (msg->msg_answer && msg->msg_alen) {
  3391. /* default answers (getchar() not possible) */
  3392. if (msg->msg_alen == 1) {
  3393. msg->msg_alen = 0;
  3394. msg->msg_len = 1;
  3395. msg->msg_text[0] = 0;
  3396. } else {
  3397. msg->msg_alen -= 2;
  3398. msg->msg_len = 2;
  3399. msg->msg_text[0] = 1;
  3400. msg->msg_text[1] = 0;
  3401. }
  3402. msg->msg_ext = 0;
  3403. msg->msg_answer = 0;
  3404. while (gdth_test_busy(hanum))
  3405. gdth_delay(0);
  3406. cmdp->Service = SCREENSERVICE;
  3407. cmdp->RequestBuffer = SCREEN_CMND;
  3408. gdth_get_cmd_index(hanum);
  3409. gdth_set_sema0(hanum);
  3410. cmdp->OpCode = GDT_WRITE;
  3411. cmdp->BoardNode = LOCALBOARD;
  3412. cmdp->u.screen.reserved = 0;
  3413. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3414. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3415. ha->cmd_offs_dpmem = 0;
  3416. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3417. + sizeof(ulong64);
  3418. ha->cmd_cnt = 0;
  3419. gdth_copy_command(hanum);
  3420. gdth_release_event(hanum);
  3421. return 0;
  3422. }
  3423. printk("\n");
  3424. } else {
  3425. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  3426. t = scp->device->id;
  3427. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3428. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3429. }
  3430. /* cache or raw service */
  3431. if (ha->status == S_BSY) {
  3432. TRACE2(("Controller busy -> retry !\n"));
  3433. if (scp->SCp.sent_command == GDT_MOUNT)
  3434. scp->SCp.sent_command = GDT_CLUST_INFO;
  3435. /* retry */
  3436. return 2;
  3437. }
  3438. if (scp->SCp.Status == GDTH_MAP_SG)
  3439. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3440. scp->use_sg,scp->SCp.Message);
  3441. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3442. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3443. scp->request_bufflen,scp->SCp.Message);
  3444. if (scp->SCp.buffer) {
  3445. dma_addr_t addr;
  3446. addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
  3447. if (scp->host_scribble)
  3448. addr += (dma_addr_t)
  3449. ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
  3450. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3451. }
  3452. if (ha->status == S_OK) {
  3453. scp->SCp.Status = S_OK;
  3454. scp->SCp.Message = ha->info;
  3455. if (scp->SCp.sent_command != -1) {
  3456. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3457. scp->SCp.sent_command));
  3458. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3459. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3460. ha->hdr[t].cluster_type = (unchar)ha->info;
  3461. if (!(ha->hdr[t].cluster_type &
  3462. CLUSTER_MOUNTED)) {
  3463. /* NOT MOUNTED -> MOUNT */
  3464. scp->SCp.sent_command = GDT_MOUNT;
  3465. if (ha->hdr[t].cluster_type &
  3466. CLUSTER_RESERVED) {
  3467. /* cluster drive RESERVED (on the other node) */
  3468. scp->SCp.phase = -2; /* reservation conflict */
  3469. }
  3470. } else {
  3471. scp->SCp.sent_command = -1;
  3472. }
  3473. } else {
  3474. if (scp->SCp.sent_command == GDT_MOUNT) {
  3475. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3476. ha->hdr[t].media_changed = TRUE;
  3477. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3478. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3479. ha->hdr[t].media_changed = TRUE;
  3480. }
  3481. scp->SCp.sent_command = -1;
  3482. }
  3483. /* retry */
  3484. scp->SCp.this_residual = HIGH_PRI;
  3485. return 2;
  3486. } else {
  3487. /* RESERVE/RELEASE ? */
  3488. if (scp->cmnd[0] == RESERVE) {
  3489. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3490. } else if (scp->cmnd[0] == RELEASE) {
  3491. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3492. }
  3493. scp->result = DID_OK << 16;
  3494. scp->sense_buffer[0] = 0;
  3495. }
  3496. } else {
  3497. scp->SCp.Status = ha->status;
  3498. scp->SCp.Message = ha->info;
  3499. if (scp->SCp.sent_command != -1) {
  3500. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3501. scp->SCp.sent_command, ha->status));
  3502. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3503. scp->SCp.sent_command == GDT_SCAN_END) {
  3504. scp->SCp.sent_command = -1;
  3505. /* retry */
  3506. scp->SCp.this_residual = HIGH_PRI;
  3507. return 2;
  3508. }
  3509. memset((char*)scp->sense_buffer,0,16);
  3510. scp->sense_buffer[0] = 0x70;
  3511. scp->sense_buffer[2] = NOT_READY;
  3512. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3513. } else if (service == CACHESERVICE) {
  3514. if (ha->status == S_CACHE_UNKNOWN &&
  3515. (ha->hdr[t].cluster_type &
  3516. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3517. /* bus reset -> force GDT_CLUST_INFO */
  3518. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3519. }
  3520. memset((char*)scp->sense_buffer,0,16);
  3521. if (ha->status == (ushort)S_CACHE_RESERV) {
  3522. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3523. } else {
  3524. scp->sense_buffer[0] = 0x70;
  3525. scp->sense_buffer[2] = NOT_READY;
  3526. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3527. }
  3528. if (scp->done != gdth_scsi_done) {
  3529. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3530. ha->dvr.eu.sync.ionode = hanum;
  3531. ha->dvr.eu.sync.service = service;
  3532. ha->dvr.eu.sync.status = ha->status;
  3533. ha->dvr.eu.sync.info = ha->info;
  3534. ha->dvr.eu.sync.hostdrive = t;
  3535. if (ha->status >= 0x8000)
  3536. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3537. else
  3538. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3539. }
  3540. } else {
  3541. /* sense buffer filled from controller firmware (DMA) */
  3542. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3543. scp->result = DID_BAD_TARGET << 16;
  3544. } else {
  3545. scp->result = (DID_OK << 16) | ha->info;
  3546. }
  3547. }
  3548. }
  3549. if (!scp->SCp.have_data_in)
  3550. scp->SCp.have_data_in++;
  3551. else
  3552. return 1;
  3553. }
  3554. return 0;
  3555. }
  3556. static char *async_cache_tab[] = {
  3557. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3558. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3559. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3560. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3561. /* 2*/ "\005\000\002\006\004"
  3562. "GDT HA %u, Host Drive %lu not ready",
  3563. /* 3*/ "\005\000\002\006\004"
  3564. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3565. /* 4*/ "\005\000\002\006\004"
  3566. "GDT HA %u, mirror update on Host Drive %lu failed",
  3567. /* 5*/ "\005\000\002\006\004"
  3568. "GDT HA %u, Mirror Drive %lu failed",
  3569. /* 6*/ "\005\000\002\006\004"
  3570. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3571. /* 7*/ "\005\000\002\006\004"
  3572. "GDT HA %u, Host Drive %lu write protected",
  3573. /* 8*/ "\005\000\002\006\004"
  3574. "GDT HA %u, media changed in Host Drive %lu",
  3575. /* 9*/ "\005\000\002\006\004"
  3576. "GDT HA %u, Host Drive %lu is offline",
  3577. /*10*/ "\005\000\002\006\004"
  3578. "GDT HA %u, media change of Mirror Drive %lu",
  3579. /*11*/ "\005\000\002\006\004"
  3580. "GDT HA %u, Mirror Drive %lu is write protected",
  3581. /*12*/ "\005\000\002\006\004"
  3582. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3583. /*13*/ "\007\000\002\006\002\010\002"
  3584. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3585. /*14*/ "\005\000\002\006\002"
  3586. "GDT HA %u, Array Drive %u: FAIL state entered",
  3587. /*15*/ "\005\000\002\006\002"
  3588. "GDT HA %u, Array Drive %u: error",
  3589. /*16*/ "\007\000\002\006\002\010\002"
  3590. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3591. /*17*/ "\005\000\002\006\002"
  3592. "GDT HA %u, Array Drive %u: parity build failed",
  3593. /*18*/ "\005\000\002\006\002"
  3594. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3595. /*19*/ "\005\000\002\010\002"
  3596. "GDT HA %u, Test of Hot Fix %u failed",
  3597. /*20*/ "\005\000\002\006\002"
  3598. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3599. /*21*/ "\005\000\002\006\002"
  3600. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3601. /*22*/ "\007\000\002\006\002\010\002"
  3602. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3603. /*23*/ "\005\000\002\006\002"
  3604. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3605. /*24*/ "\005\000\002\010\002"
  3606. "GDT HA %u, mirror update on Cache Drive %u completed",
  3607. /*25*/ "\005\000\002\010\002"
  3608. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3609. /*26*/ "\005\000\002\006\002"
  3610. "GDT HA %u, Array Drive %u: drive rebuild started",
  3611. /*27*/ "\005\000\002\012\001"
  3612. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3613. /*28*/ "\005\000\002\012\001"
  3614. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3615. /*29*/ "\007\000\002\012\001\013\001"
  3616. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3617. /*30*/ "\007\000\002\012\001\013\001"
  3618. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3619. /*31*/ "\007\000\002\012\001\013\001"
  3620. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3621. /*32*/ "\007\000\002\012\001\013\001"
  3622. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3623. /*33*/ "\007\000\002\012\001\013\001"
  3624. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3625. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3626. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3627. /*35*/ "\007\000\002\012\001\013\001"
  3628. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3629. /*36*/ "\007\000\002\012\001\013\001"
  3630. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3631. /*37*/ "\007\000\002\012\001\006\004"
  3632. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3633. /*38*/ "\007\000\002\012\001\013\001"
  3634. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3635. /*39*/ "\007\000\002\012\001\013\001"
  3636. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3637. /*40*/ "\007\000\002\012\001\013\001"
  3638. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3639. /*41*/ "\007\000\002\012\001\013\001"
  3640. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3641. /*42*/ "\005\000\002\006\002"
  3642. "GDT HA %u, Array Drive %u: drive build started",
  3643. /*43*/ "\003\000\002"
  3644. "GDT HA %u, DRAM parity error detected",
  3645. /*44*/ "\005\000\002\006\002"
  3646. "GDT HA %u, Mirror Drive %u: update started",
  3647. /*45*/ "\007\000\002\006\002\010\002"
  3648. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3649. /*46*/ "\005\000\002\006\002"
  3650. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3651. /*47*/ "\005\000\002\006\002"
  3652. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3653. /*48*/ "\005\000\002\006\002"
  3654. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3655. /*49*/ "\005\000\002\006\002"
  3656. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3657. /*50*/ "\007\000\002\012\001\013\001"
  3658. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3659. /*51*/ "\005\000\002\006\002"
  3660. "GDT HA %u, Array Drive %u: expand started",
  3661. /*52*/ "\005\000\002\006\002"
  3662. "GDT HA %u, Array Drive %u: expand finished successfully",
  3663. /*53*/ "\005\000\002\006\002"
  3664. "GDT HA %u, Array Drive %u: expand failed",
  3665. /*54*/ "\003\000\002"
  3666. "GDT HA %u, CPU temperature critical",
  3667. /*55*/ "\003\000\002"
  3668. "GDT HA %u, CPU temperature OK",
  3669. /*56*/ "\005\000\002\006\004"
  3670. "GDT HA %u, Host drive %lu created",
  3671. /*57*/ "\005\000\002\006\002"
  3672. "GDT HA %u, Array Drive %u: expand restarted",
  3673. /*58*/ "\005\000\002\006\002"
  3674. "GDT HA %u, Array Drive %u: expand stopped",
  3675. /*59*/ "\005\000\002\010\002"
  3676. "GDT HA %u, Mirror Drive %u: drive build quited",
  3677. /*60*/ "\005\000\002\006\002"
  3678. "GDT HA %u, Array Drive %u: parity build quited",
  3679. /*61*/ "\005\000\002\006\002"
  3680. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3681. /*62*/ "\005\000\002\006\002"
  3682. "GDT HA %u, Array Drive %u: parity verify started",
  3683. /*63*/ "\005\000\002\006\002"
  3684. "GDT HA %u, Array Drive %u: parity verify done",
  3685. /*64*/ "\005\000\002\006\002"
  3686. "GDT HA %u, Array Drive %u: parity verify failed",
  3687. /*65*/ "\005\000\002\006\002"
  3688. "GDT HA %u, Array Drive %u: parity error detected",
  3689. /*66*/ "\005\000\002\006\002"
  3690. "GDT HA %u, Array Drive %u: parity verify quited",
  3691. /*67*/ "\005\000\002\006\002"
  3692. "GDT HA %u, Host Drive %u reserved",
  3693. /*68*/ "\005\000\002\006\002"
  3694. "GDT HA %u, Host Drive %u mounted and released",
  3695. /*69*/ "\005\000\002\006\002"
  3696. "GDT HA %u, Host Drive %u released",
  3697. /*70*/ "\003\000\002"
  3698. "GDT HA %u, DRAM error detected and corrected with ECC",
  3699. /*71*/ "\003\000\002"
  3700. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3701. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3702. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3703. /*73*/ "\005\000\002\006\002"
  3704. "GDT HA %u, Host drive %u resetted locally",
  3705. /*74*/ "\005\000\002\006\002"
  3706. "GDT HA %u, Host drive %u resetted remotely",
  3707. /*75*/ "\003\000\002"
  3708. "GDT HA %u, async. status 75 unknown",
  3709. };
  3710. static int gdth_async_event(int hanum)
  3711. {
  3712. gdth_ha_str *ha;
  3713. gdth_cmd_str *cmdp;
  3714. int cmd_index;
  3715. ha = HADATA(gdth_ctr_tab[hanum]);
  3716. cmdp= ha->pccb;
  3717. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3718. hanum,ha->service));
  3719. if (ha->service == SCREENSERVICE) {
  3720. if (ha->status == MSG_REQUEST) {
  3721. while (gdth_test_busy(hanum))
  3722. gdth_delay(0);
  3723. cmdp->Service = SCREENSERVICE;
  3724. cmdp->RequestBuffer = SCREEN_CMND;
  3725. cmd_index = gdth_get_cmd_index(hanum);
  3726. gdth_set_sema0(hanum);
  3727. cmdp->OpCode = GDT_READ;
  3728. cmdp->BoardNode = LOCALBOARD;
  3729. cmdp->u.screen.reserved = 0;
  3730. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3731. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3732. ha->cmd_offs_dpmem = 0;
  3733. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3734. + sizeof(ulong64);
  3735. ha->cmd_cnt = 0;
  3736. gdth_copy_command(hanum);
  3737. if (ha->type == GDT_EISA)
  3738. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3739. else if (ha->type == GDT_ISA)
  3740. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3741. else
  3742. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3743. (ushort)((ha->brd_phys>>3)&0x1f));
  3744. gdth_release_event(hanum);
  3745. }
  3746. } else {
  3747. if (ha->type == GDT_PCIMPR &&
  3748. (ha->fw_vers & 0xff) >= 0x1a) {
  3749. ha->dvr.size = 0;
  3750. ha->dvr.eu.async.ionode = hanum;
  3751. ha->dvr.eu.async.status = ha->status;
  3752. /* severity and event_string already set! */
  3753. } else {
  3754. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3755. ha->dvr.eu.async.ionode = hanum;
  3756. ha->dvr.eu.async.service = ha->service;
  3757. ha->dvr.eu.async.status = ha->status;
  3758. ha->dvr.eu.async.info = ha->info;
  3759. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3760. }
  3761. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3762. gdth_log_event( &ha->dvr, NULL );
  3763. /* new host drive from expand? */
  3764. if (ha->service == CACHESERVICE && ha->status == 56) {
  3765. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3766. (ushort)ha->info));
  3767. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3768. }
  3769. }
  3770. return 1;
  3771. }
  3772. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3773. {
  3774. gdth_stackframe stack;
  3775. char *f = NULL;
  3776. int i,j;
  3777. TRACE2(("gdth_log_event()\n"));
  3778. if (dvr->size == 0) {
  3779. if (buffer == NULL) {
  3780. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3781. } else {
  3782. sprintf(buffer,"Adapter %d: %s\n",
  3783. dvr->eu.async.ionode,dvr->event_string);
  3784. }
  3785. } else if (dvr->eu.async.service == CACHESERVICE &&
  3786. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3787. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3788. dvr->eu.async.status));
  3789. f = async_cache_tab[dvr->eu.async.status];
  3790. /* i: parameter to push, j: stack element to fill */
  3791. for (j=0,i=1; i < f[0]; i+=2) {
  3792. switch (f[i+1]) {
  3793. case 4:
  3794. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3795. break;
  3796. case 2:
  3797. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3798. break;
  3799. case 1:
  3800. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3801. break;
  3802. default:
  3803. break;
  3804. }
  3805. }
  3806. if (buffer == NULL) {
  3807. printk(&f[(int)f[0]],stack);
  3808. printk("\n");
  3809. } else {
  3810. sprintf(buffer,&f[(int)f[0]],stack);
  3811. }
  3812. } else {
  3813. if (buffer == NULL) {
  3814. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3815. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3816. } else {
  3817. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3818. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3819. }
  3820. }
  3821. }
  3822. #ifdef GDTH_STATISTICS
  3823. static void gdth_timeout(ulong data)
  3824. {
  3825. ulong32 i;
  3826. Scsi_Cmnd *nscp;
  3827. gdth_ha_str *ha;
  3828. ulong flags;
  3829. int hanum = 0;
  3830. ha = HADATA(gdth_ctr_tab[hanum]);
  3831. spin_lock_irqsave(&ha->smp_lock, flags);
  3832. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3833. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3834. ++act_stats;
  3835. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3836. ++act_rq;
  3837. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3838. act_ints, act_ios, act_stats, act_rq));
  3839. act_ints = act_ios = 0;
  3840. gdth_timer.expires = jiffies + 30 * HZ;
  3841. add_timer(&gdth_timer);
  3842. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3843. }
  3844. #endif
  3845. static void __init internal_setup(char *str,int *ints)
  3846. {
  3847. int i, argc;
  3848. char *cur_str, *argv;
  3849. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3850. str ? str:"NULL", ints ? ints[0]:0));
  3851. /* read irq[] from ints[] */
  3852. if (ints) {
  3853. argc = ints[0];
  3854. if (argc > 0) {
  3855. if (argc > MAXHA)
  3856. argc = MAXHA;
  3857. for (i = 0; i < argc; ++i)
  3858. irq[i] = ints[i+1];
  3859. }
  3860. }
  3861. /* analyse string */
  3862. argv = str;
  3863. while (argv && (cur_str = strchr(argv, ':'))) {
  3864. int val = 0, c = *++cur_str;
  3865. if (c == 'n' || c == 'N')
  3866. val = 0;
  3867. else if (c == 'y' || c == 'Y')
  3868. val = 1;
  3869. else
  3870. val = (int)simple_strtoul(cur_str, NULL, 0);
  3871. if (!strncmp(argv, "disable:", 8))
  3872. disable = val;
  3873. else if (!strncmp(argv, "reserve_mode:", 13))
  3874. reserve_mode = val;
  3875. else if (!strncmp(argv, "reverse_scan:", 13))
  3876. reverse_scan = val;
  3877. else if (!strncmp(argv, "hdr_channel:", 12))
  3878. hdr_channel = val;
  3879. else if (!strncmp(argv, "max_ids:", 8))
  3880. max_ids = val;
  3881. else if (!strncmp(argv, "rescan:", 7))
  3882. rescan = val;
  3883. else if (!strncmp(argv, "virt_ctr:", 9))
  3884. virt_ctr = val;
  3885. else if (!strncmp(argv, "shared_access:", 14))
  3886. shared_access = val;
  3887. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3888. probe_eisa_isa = val;
  3889. else if (!strncmp(argv, "reserve_list:", 13)) {
  3890. reserve_list[0] = val;
  3891. for (i = 1; i < MAX_RES_ARGS; i++) {
  3892. cur_str = strchr(cur_str, ',');
  3893. if (!cur_str)
  3894. break;
  3895. if (!isdigit((int)*++cur_str)) {
  3896. --cur_str;
  3897. break;
  3898. }
  3899. reserve_list[i] =
  3900. (int)simple_strtoul(cur_str, NULL, 0);
  3901. }
  3902. if (!cur_str)
  3903. break;
  3904. argv = ++cur_str;
  3905. continue;
  3906. }
  3907. if ((argv = strchr(argv, ',')))
  3908. ++argv;
  3909. }
  3910. }
  3911. int __init option_setup(char *str)
  3912. {
  3913. int ints[MAXHA];
  3914. char *cur = str;
  3915. int i = 1;
  3916. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3917. while (cur && isdigit(*cur) && i <= MAXHA) {
  3918. ints[i++] = simple_strtoul(cur, NULL, 0);
  3919. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3920. }
  3921. ints[0] = i - 1;
  3922. internal_setup(cur, ints);
  3923. return 1;
  3924. }
  3925. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  3926. static int __init gdth_detect(struct scsi_host_template *shtp)
  3927. #else
  3928. static int __init gdth_detect(Scsi_Host_Template *shtp)
  3929. #endif
  3930. {
  3931. struct Scsi_Host *shp;
  3932. gdth_pci_str pcistr[MAXHA];
  3933. gdth_ha_str *ha;
  3934. ulong32 isa_bios;
  3935. ushort eisa_slot;
  3936. int i,hanum,cnt,ctr,err;
  3937. unchar b;
  3938. #ifdef DEBUG_GDTH
  3939. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3940. DebugState);
  3941. printk(" Destination of debugging information: ");
  3942. #ifdef __SERIAL__
  3943. #ifdef __COM2__
  3944. printk("Serial port COM2\n");
  3945. #else
  3946. printk("Serial port COM1\n");
  3947. #endif
  3948. #else
  3949. printk("Console\n");
  3950. #endif
  3951. gdth_delay(3000);
  3952. #endif
  3953. TRACE(("gdth_detect()\n"));
  3954. if (disable) {
  3955. printk("GDT-HA: Controller driver disabled from command line !\n");
  3956. return 0;
  3957. }
  3958. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
  3959. /* initializations */
  3960. gdth_polling = TRUE; b = 0;
  3961. gdth_clear_events();
  3962. /* As default we do not probe for EISA or ISA controllers */
  3963. if (probe_eisa_isa) {
  3964. /* scanning for controllers, at first: ISA controller */
  3965. for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
  3966. dma_addr_t scratch_dma_handle;
  3967. scratch_dma_handle = 0;
  3968. if (gdth_ctr_count >= MAXHA)
  3969. break;
  3970. if (gdth_search_isa(isa_bios)) { /* controller found */
  3971. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  3972. if (shp == NULL)
  3973. continue;
  3974. ha = HADATA(shp);
  3975. if (!gdth_init_isa(isa_bios,ha)) {
  3976. scsi_unregister(shp);
  3977. continue;
  3978. }
  3979. #ifdef __ia64__
  3980. break;
  3981. #else
  3982. /* controller found and initialized */
  3983. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  3984. isa_bios,ha->irq,ha->drq);
  3985. if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
  3986. printk("GDT-ISA: Unable to allocate IRQ\n");
  3987. scsi_unregister(shp);
  3988. continue;
  3989. }
  3990. if (request_dma(ha->drq,"gdth")) {
  3991. printk("GDT-ISA: Unable to allocate DMA channel\n");
  3992. free_irq(ha->irq,ha);
  3993. scsi_unregister(shp);
  3994. continue;
  3995. }
  3996. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  3997. enable_dma(ha->drq);
  3998. shp->unchecked_isa_dma = 1;
  3999. shp->irq = ha->irq;
  4000. shp->dma_channel = ha->drq;
  4001. hanum = gdth_ctr_count;
  4002. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4003. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4004. NUMDATA(shp)->hanum = (ushort)hanum;
  4005. NUMDATA(shp)->busnum= 0;
  4006. ha->pccb = CMDDATA(shp);
  4007. ha->ccb_phys = 0L;
  4008. ha->pdev = NULL;
  4009. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4010. &scratch_dma_handle);
  4011. ha->scratch_phys = scratch_dma_handle;
  4012. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4013. &scratch_dma_handle);
  4014. ha->msg_phys = scratch_dma_handle;
  4015. #ifdef INT_COAL
  4016. ha->coal_stat = (gdth_coal_status *)
  4017. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4018. MAXOFFSETS, &scratch_dma_handle);
  4019. ha->coal_stat_phys = scratch_dma_handle;
  4020. #endif
  4021. ha->scratch_busy = FALSE;
  4022. ha->req_first = NULL;
  4023. ha->tid_cnt = MAX_HDRIVES;
  4024. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4025. ha->tid_cnt = max_ids;
  4026. for (i=0; i<GDTH_MAXCMDS; ++i)
  4027. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4028. ha->scan_mode = rescan ? 0x10 : 0;
  4029. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4030. !gdth_search_drives(hanum)) {
  4031. printk("GDT-ISA: Error during device scan\n");
  4032. --gdth_ctr_count;
  4033. --gdth_ctr_vcount;
  4034. #ifdef INT_COAL
  4035. if (ha->coal_stat)
  4036. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4037. MAXOFFSETS, ha->coal_stat,
  4038. ha->coal_stat_phys);
  4039. #endif
  4040. if (ha->pscratch)
  4041. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4042. ha->pscratch, ha->scratch_phys);
  4043. if (ha->pmsg)
  4044. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4045. ha->pmsg, ha->msg_phys);
  4046. free_irq(ha->irq,ha);
  4047. scsi_unregister(shp);
  4048. continue;
  4049. }
  4050. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4051. hdr_channel = ha->bus_cnt;
  4052. ha->virt_bus = hdr_channel;
  4053. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  4054. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4055. shp->highmem_io = 0;
  4056. #endif
  4057. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4058. shp->max_cmd_len = 16;
  4059. shp->max_id = ha->tid_cnt;
  4060. shp->max_lun = MAXLUN;
  4061. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4062. if (virt_ctr) {
  4063. virt_ctr = 1;
  4064. /* register addit. SCSI channels as virtual controllers */
  4065. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4066. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4067. shp->unchecked_isa_dma = 1;
  4068. shp->irq = ha->irq;
  4069. shp->dma_channel = ha->drq;
  4070. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4071. NUMDATA(shp)->hanum = (ushort)hanum;
  4072. NUMDATA(shp)->busnum = b;
  4073. }
  4074. }
  4075. spin_lock_init(&ha->smp_lock);
  4076. gdth_enable_int(hanum);
  4077. #endif /* !__ia64__ */
  4078. }
  4079. }
  4080. /* scanning for EISA controllers */
  4081. for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
  4082. dma_addr_t scratch_dma_handle;
  4083. scratch_dma_handle = 0;
  4084. if (gdth_ctr_count >= MAXHA)
  4085. break;
  4086. if (gdth_search_eisa(eisa_slot)) { /* controller found */
  4087. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4088. if (shp == NULL)
  4089. continue;
  4090. ha = HADATA(shp);
  4091. if (!gdth_init_eisa(eisa_slot,ha)) {
  4092. scsi_unregister(shp);
  4093. continue;
  4094. }
  4095. /* controller found and initialized */
  4096. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4097. eisa_slot>>12,ha->irq);
  4098. if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
  4099. printk("GDT-EISA: Unable to allocate IRQ\n");
  4100. scsi_unregister(shp);
  4101. continue;
  4102. }
  4103. shp->unchecked_isa_dma = 0;
  4104. shp->irq = ha->irq;
  4105. shp->dma_channel = 0xff;
  4106. hanum = gdth_ctr_count;
  4107. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4108. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4109. NUMDATA(shp)->hanum = (ushort)hanum;
  4110. NUMDATA(shp)->busnum= 0;
  4111. TRACE2(("EISA detect Bus 0: hanum %d\n",
  4112. NUMDATA(shp)->hanum));
  4113. ha->pccb = CMDDATA(shp);
  4114. ha->ccb_phys = 0L;
  4115. ha->pdev = NULL;
  4116. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4117. &scratch_dma_handle);
  4118. ha->scratch_phys = scratch_dma_handle;
  4119. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4120. &scratch_dma_handle);
  4121. ha->msg_phys = scratch_dma_handle;
  4122. #ifdef INT_COAL
  4123. ha->coal_stat = (gdth_coal_status *)
  4124. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4125. MAXOFFSETS, &scratch_dma_handle);
  4126. ha->coal_stat_phys = scratch_dma_handle;
  4127. #endif
  4128. ha->ccb_phys =
  4129. pci_map_single(ha->pdev,ha->pccb,
  4130. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4131. ha->scratch_busy = FALSE;
  4132. ha->req_first = NULL;
  4133. ha->tid_cnt = MAX_HDRIVES;
  4134. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4135. ha->tid_cnt = max_ids;
  4136. for (i=0; i<GDTH_MAXCMDS; ++i)
  4137. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4138. ha->scan_mode = rescan ? 0x10 : 0;
  4139. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4140. !gdth_search_drives(hanum)) {
  4141. printk("GDT-EISA: Error during device scan\n");
  4142. --gdth_ctr_count;
  4143. --gdth_ctr_vcount;
  4144. #ifdef INT_COAL
  4145. if (ha->coal_stat)
  4146. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4147. MAXOFFSETS, ha->coal_stat,
  4148. ha->coal_stat_phys);
  4149. #endif
  4150. if (ha->pscratch)
  4151. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4152. ha->pscratch, ha->scratch_phys);
  4153. if (ha->pmsg)
  4154. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4155. ha->pmsg, ha->msg_phys);
  4156. if (ha->ccb_phys)
  4157. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4158. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4159. free_irq(ha->irq,ha);
  4160. scsi_unregister(shp);
  4161. continue;
  4162. }
  4163. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4164. hdr_channel = ha->bus_cnt;
  4165. ha->virt_bus = hdr_channel;
  4166. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  4167. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4168. shp->highmem_io = 0;
  4169. #endif
  4170. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4171. shp->max_cmd_len = 16;
  4172. shp->max_id = ha->tid_cnt;
  4173. shp->max_lun = MAXLUN;
  4174. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4175. if (virt_ctr) {
  4176. virt_ctr = 1;
  4177. /* register addit. SCSI channels as virtual controllers */
  4178. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4179. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4180. shp->unchecked_isa_dma = 0;
  4181. shp->irq = ha->irq;
  4182. shp->dma_channel = 0xff;
  4183. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4184. NUMDATA(shp)->hanum = (ushort)hanum;
  4185. NUMDATA(shp)->busnum = b;
  4186. }
  4187. }
  4188. spin_lock_init(&ha->smp_lock);
  4189. gdth_enable_int(hanum);
  4190. }
  4191. }
  4192. }
  4193. /* scanning for PCI controllers */
  4194. cnt = gdth_search_pci(pcistr);
  4195. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  4196. gdth_sort_pci(pcistr,cnt);
  4197. for (ctr = 0; ctr < cnt; ++ctr) {
  4198. dma_addr_t scratch_dma_handle;
  4199. scratch_dma_handle = 0;
  4200. if (gdth_ctr_count >= MAXHA)
  4201. break;
  4202. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4203. if (shp == NULL)
  4204. continue;
  4205. ha = HADATA(shp);
  4206. if (!gdth_init_pci(&pcistr[ctr],ha)) {
  4207. scsi_unregister(shp);
  4208. continue;
  4209. }
  4210. /* controller found and initialized */
  4211. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4212. pcistr[ctr].pdev->bus->number,
  4213. PCI_SLOT(pcistr[ctr].pdev->devfn), ha->irq);
  4214. if (request_irq(ha->irq, gdth_interrupt,
  4215. IRQF_DISABLED|IRQF_SHARED, "gdth", ha))
  4216. {
  4217. printk("GDT-PCI: Unable to allocate IRQ\n");
  4218. scsi_unregister(shp);
  4219. continue;
  4220. }
  4221. shp->unchecked_isa_dma = 0;
  4222. shp->irq = ha->irq;
  4223. shp->dma_channel = 0xff;
  4224. hanum = gdth_ctr_count;
  4225. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4226. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4227. NUMDATA(shp)->hanum = (ushort)hanum;
  4228. NUMDATA(shp)->busnum= 0;
  4229. ha->pccb = CMDDATA(shp);
  4230. ha->ccb_phys = 0L;
  4231. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4232. &scratch_dma_handle);
  4233. ha->scratch_phys = scratch_dma_handle;
  4234. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4235. &scratch_dma_handle);
  4236. ha->msg_phys = scratch_dma_handle;
  4237. #ifdef INT_COAL
  4238. ha->coal_stat = (gdth_coal_status *)
  4239. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4240. MAXOFFSETS, &scratch_dma_handle);
  4241. ha->coal_stat_phys = scratch_dma_handle;
  4242. #endif
  4243. ha->scratch_busy = FALSE;
  4244. ha->req_first = NULL;
  4245. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4246. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4247. ha->tid_cnt = max_ids;
  4248. for (i=0; i<GDTH_MAXCMDS; ++i)
  4249. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4250. ha->scan_mode = rescan ? 0x10 : 0;
  4251. err = FALSE;
  4252. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4253. !gdth_search_drives(hanum)) {
  4254. err = TRUE;
  4255. } else {
  4256. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4257. hdr_channel = ha->bus_cnt;
  4258. ha->virt_bus = hdr_channel;
  4259. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4260. scsi_set_pci_device(shp, pcistr[ctr].pdev);
  4261. #endif
  4262. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
  4263. /* 64-bit DMA only supported from FW >= x.43 */
  4264. (!ha->dma64_support)) {
  4265. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4266. printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
  4267. err = TRUE;
  4268. }
  4269. } else {
  4270. shp->max_cmd_len = 16;
  4271. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4272. printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
  4273. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4274. printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
  4275. err = TRUE;
  4276. }
  4277. }
  4278. }
  4279. if (err) {
  4280. printk("GDT-PCI %d: Error during device scan\n", hanum);
  4281. --gdth_ctr_count;
  4282. --gdth_ctr_vcount;
  4283. #ifdef INT_COAL
  4284. if (ha->coal_stat)
  4285. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4286. MAXOFFSETS, ha->coal_stat,
  4287. ha->coal_stat_phys);
  4288. #endif
  4289. if (ha->pscratch)
  4290. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4291. ha->pscratch, ha->scratch_phys);
  4292. if (ha->pmsg)
  4293. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4294. ha->pmsg, ha->msg_phys);
  4295. free_irq(ha->irq,ha);
  4296. scsi_unregister(shp);
  4297. continue;
  4298. }
  4299. shp->max_id = ha->tid_cnt;
  4300. shp->max_lun = MAXLUN;
  4301. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4302. if (virt_ctr) {
  4303. virt_ctr = 1;
  4304. /* register addit. SCSI channels as virtual controllers */
  4305. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4306. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4307. shp->unchecked_isa_dma = 0;
  4308. shp->irq = ha->irq;
  4309. shp->dma_channel = 0xff;
  4310. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4311. NUMDATA(shp)->hanum = (ushort)hanum;
  4312. NUMDATA(shp)->busnum = b;
  4313. }
  4314. }
  4315. spin_lock_init(&ha->smp_lock);
  4316. gdth_enable_int(hanum);
  4317. }
  4318. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  4319. if (gdth_ctr_count > 0) {
  4320. #ifdef GDTH_STATISTICS
  4321. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4322. init_timer(&gdth_timer);
  4323. gdth_timer.expires = jiffies + HZ;
  4324. gdth_timer.data = 0L;
  4325. gdth_timer.function = gdth_timeout;
  4326. add_timer(&gdth_timer);
  4327. #endif
  4328. major = register_chrdev(0,"gdth",&gdth_fops);
  4329. notifier_disabled = 0;
  4330. register_reboot_notifier(&gdth_notifier);
  4331. }
  4332. gdth_polling = FALSE;
  4333. return gdth_ctr_vcount;
  4334. }
  4335. static int gdth_release(struct Scsi_Host *shp)
  4336. {
  4337. int hanum;
  4338. gdth_ha_str *ha;
  4339. TRACE2(("gdth_release()\n"));
  4340. if (NUMDATA(shp)->busnum == 0) {
  4341. hanum = NUMDATA(shp)->hanum;
  4342. ha = HADATA(gdth_ctr_tab[hanum]);
  4343. if (ha->sdev) {
  4344. scsi_free_host_dev(ha->sdev);
  4345. ha->sdev = NULL;
  4346. }
  4347. gdth_flush(hanum);
  4348. if (shp->irq) {
  4349. free_irq(shp->irq,ha);
  4350. }
  4351. #ifndef __ia64__
  4352. if (shp->dma_channel != 0xff) {
  4353. free_dma(shp->dma_channel);
  4354. }
  4355. #endif
  4356. #ifdef INT_COAL
  4357. if (ha->coal_stat)
  4358. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4359. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4360. #endif
  4361. if (ha->pscratch)
  4362. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4363. ha->pscratch, ha->scratch_phys);
  4364. if (ha->pmsg)
  4365. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4366. ha->pmsg, ha->msg_phys);
  4367. if (ha->ccb_phys)
  4368. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4369. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4370. gdth_ctr_released++;
  4371. TRACE2(("gdth_release(): HA %d of %d\n",
  4372. gdth_ctr_released, gdth_ctr_count));
  4373. if (gdth_ctr_released == gdth_ctr_count) {
  4374. #ifdef GDTH_STATISTICS
  4375. del_timer(&gdth_timer);
  4376. #endif
  4377. unregister_chrdev(major,"gdth");
  4378. unregister_reboot_notifier(&gdth_notifier);
  4379. }
  4380. }
  4381. scsi_unregister(shp);
  4382. return 0;
  4383. }
  4384. static const char *gdth_ctr_name(int hanum)
  4385. {
  4386. gdth_ha_str *ha;
  4387. TRACE2(("gdth_ctr_name()\n"));
  4388. ha = HADATA(gdth_ctr_tab[hanum]);
  4389. if (ha->type == GDT_EISA) {
  4390. switch (ha->stype) {
  4391. case GDT3_ID:
  4392. return("GDT3000/3020");
  4393. case GDT3A_ID:
  4394. return("GDT3000A/3020A/3050A");
  4395. case GDT3B_ID:
  4396. return("GDT3000B/3010A");
  4397. }
  4398. } else if (ha->type == GDT_ISA) {
  4399. return("GDT2000/2020");
  4400. } else if (ha->type == GDT_PCI) {
  4401. switch (ha->pdev->device) {
  4402. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  4403. return("GDT6000/6020/6050");
  4404. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  4405. return("GDT6000B/6010");
  4406. }
  4407. }
  4408. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  4409. return("");
  4410. }
  4411. static const char *gdth_info(struct Scsi_Host *shp)
  4412. {
  4413. int hanum;
  4414. gdth_ha_str *ha;
  4415. TRACE2(("gdth_info()\n"));
  4416. hanum = NUMDATA(shp)->hanum;
  4417. ha = HADATA(gdth_ctr_tab[hanum]);
  4418. return ((const char *)ha->binfo.type_string);
  4419. }
  4420. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  4421. {
  4422. int i, hanum;
  4423. gdth_ha_str *ha;
  4424. ulong flags;
  4425. Scsi_Cmnd *cmnd;
  4426. unchar b;
  4427. TRACE2(("gdth_eh_bus_reset()\n"));
  4428. hanum = NUMDATA(scp->device->host)->hanum;
  4429. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  4430. ha = HADATA(gdth_ctr_tab[hanum]);
  4431. /* clear command tab */
  4432. spin_lock_irqsave(&ha->smp_lock, flags);
  4433. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  4434. cmnd = ha->cmd_tab[i].cmnd;
  4435. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  4436. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4437. }
  4438. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4439. if (b == ha->virt_bus) {
  4440. /* host drives */
  4441. for (i = 0; i < MAX_HDRIVES; ++i) {
  4442. if (ha->hdr[i].present) {
  4443. spin_lock_irqsave(&ha->smp_lock, flags);
  4444. gdth_polling = TRUE;
  4445. while (gdth_test_busy(hanum))
  4446. gdth_delay(0);
  4447. if (gdth_internal_cmd(hanum, CACHESERVICE,
  4448. GDT_CLUST_RESET, i, 0, 0))
  4449. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  4450. gdth_polling = FALSE;
  4451. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4452. }
  4453. }
  4454. } else {
  4455. /* raw devices */
  4456. spin_lock_irqsave(&ha->smp_lock, flags);
  4457. for (i = 0; i < MAXID; ++i)
  4458. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  4459. gdth_polling = TRUE;
  4460. while (gdth_test_busy(hanum))
  4461. gdth_delay(0);
  4462. gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
  4463. BUS_L2P(ha,b), 0, 0);
  4464. gdth_polling = FALSE;
  4465. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4466. }
  4467. return SUCCESS;
  4468. }
  4469. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4470. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  4471. #else
  4472. static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
  4473. #endif
  4474. {
  4475. unchar b, t;
  4476. int hanum;
  4477. gdth_ha_str *ha;
  4478. struct scsi_device *sd;
  4479. unsigned capacity;
  4480. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4481. sd = sdev;
  4482. capacity = cap;
  4483. #else
  4484. sd = disk->device;
  4485. capacity = disk->capacity;
  4486. #endif
  4487. hanum = NUMDATA(sd->host)->hanum;
  4488. b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
  4489. t = sd->id;
  4490. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
  4491. ha = HADATA(gdth_ctr_tab[hanum]);
  4492. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  4493. /* raw device or host drive without mapping information */
  4494. TRACE2(("Evaluate mapping\n"));
  4495. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  4496. } else {
  4497. ip[0] = ha->hdr[t].heads;
  4498. ip[1] = ha->hdr[t].secs;
  4499. ip[2] = capacity / ip[0] / ip[1];
  4500. }
  4501. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  4502. ip[0],ip[1],ip[2]));
  4503. return 0;
  4504. }
  4505. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
  4506. {
  4507. int hanum;
  4508. int priority;
  4509. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  4510. scp->scsi_done = (void *)done;
  4511. scp->SCp.have_data_in = 1;
  4512. scp->SCp.phase = -1;
  4513. scp->SCp.sent_command = -1;
  4514. scp->SCp.Status = GDTH_MAP_NONE;
  4515. scp->SCp.buffer = (struct scatterlist *)NULL;
  4516. hanum = NUMDATA(scp->device->host)->hanum;
  4517. #ifdef GDTH_STATISTICS
  4518. ++act_ios;
  4519. #endif
  4520. priority = DEFAULT_PRI;
  4521. if (scp->done == gdth_scsi_done)
  4522. priority = scp->SCp.this_residual;
  4523. else
  4524. gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
  4525. gdth_putq( hanum, scp, priority );
  4526. gdth_next( hanum );
  4527. return 0;
  4528. }
  4529. static int gdth_open(struct inode *inode, struct file *filep)
  4530. {
  4531. gdth_ha_str *ha;
  4532. int i;
  4533. for (i = 0; i < gdth_ctr_count; i++) {
  4534. ha = HADATA(gdth_ctr_tab[i]);
  4535. if (!ha->sdev)
  4536. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  4537. }
  4538. TRACE(("gdth_open()\n"));
  4539. return 0;
  4540. }
  4541. static int gdth_close(struct inode *inode, struct file *filep)
  4542. {
  4543. TRACE(("gdth_close()\n"));
  4544. return 0;
  4545. }
  4546. static int ioc_event(void __user *arg)
  4547. {
  4548. gdth_ioctl_event evt;
  4549. gdth_ha_str *ha;
  4550. ulong flags;
  4551. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  4552. evt.ionode >= gdth_ctr_count)
  4553. return -EFAULT;
  4554. ha = HADATA(gdth_ctr_tab[evt.ionode]);
  4555. if (evt.erase == 0xff) {
  4556. if (evt.event.event_source == ES_TEST)
  4557. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  4558. else if (evt.event.event_source == ES_DRIVER)
  4559. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  4560. else if (evt.event.event_source == ES_SYNC)
  4561. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  4562. else
  4563. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  4564. spin_lock_irqsave(&ha->smp_lock, flags);
  4565. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  4566. &evt.event.event_data);
  4567. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4568. } else if (evt.erase == 0xfe) {
  4569. gdth_clear_events();
  4570. } else if (evt.erase == 0) {
  4571. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  4572. } else {
  4573. gdth_readapp_event(ha, evt.erase, &evt.event);
  4574. }
  4575. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  4576. return -EFAULT;
  4577. return 0;
  4578. }
  4579. static int ioc_lockdrv(void __user *arg)
  4580. {
  4581. gdth_ioctl_lockdrv ldrv;
  4582. unchar i, j;
  4583. ulong flags;
  4584. gdth_ha_str *ha;
  4585. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  4586. ldrv.ionode >= gdth_ctr_count)
  4587. return -EFAULT;
  4588. ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
  4589. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  4590. j = ldrv.drives[i];
  4591. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  4592. continue;
  4593. if (ldrv.lock) {
  4594. spin_lock_irqsave(&ha->smp_lock, flags);
  4595. ha->hdr[j].lock = 1;
  4596. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4597. gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
  4598. gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
  4599. } else {
  4600. spin_lock_irqsave(&ha->smp_lock, flags);
  4601. ha->hdr[j].lock = 0;
  4602. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4603. gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
  4604. gdth_next(ldrv.ionode);
  4605. }
  4606. }
  4607. return 0;
  4608. }
  4609. static int ioc_resetdrv(void __user *arg, char *cmnd)
  4610. {
  4611. gdth_ioctl_reset res;
  4612. gdth_cmd_str cmd;
  4613. int hanum;
  4614. gdth_ha_str *ha;
  4615. int rval;
  4616. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  4617. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  4618. return -EFAULT;
  4619. hanum = res.ionode;
  4620. ha = HADATA(gdth_ctr_tab[hanum]);
  4621. if (!ha->hdr[res.number].present)
  4622. return 0;
  4623. memset(&cmd, 0, sizeof(gdth_cmd_str));
  4624. cmd.Service = CACHESERVICE;
  4625. cmd.OpCode = GDT_CLUST_RESET;
  4626. if (ha->cache_feat & GDT_64BIT)
  4627. cmd.u.cache64.DeviceNo = res.number;
  4628. else
  4629. cmd.u.cache.DeviceNo = res.number;
  4630. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  4631. if (rval < 0)
  4632. return rval;
  4633. res.status = rval;
  4634. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  4635. return -EFAULT;
  4636. return 0;
  4637. }
  4638. static int ioc_general(void __user *arg, char *cmnd)
  4639. {
  4640. gdth_ioctl_general gen;
  4641. char *buf = NULL;
  4642. ulong64 paddr;
  4643. int hanum;
  4644. gdth_ha_str *ha;
  4645. int rval;
  4646. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  4647. gen.ionode >= gdth_ctr_count)
  4648. return -EFAULT;
  4649. hanum = gen.ionode;
  4650. ha = HADATA(gdth_ctr_tab[hanum]);
  4651. if (gen.data_len + gen.sense_len != 0) {
  4652. if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
  4653. FALSE, &paddr)))
  4654. return -EFAULT;
  4655. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  4656. gen.data_len + gen.sense_len)) {
  4657. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4658. return -EFAULT;
  4659. }
  4660. if (gen.command.OpCode == GDT_IOCTL) {
  4661. gen.command.u.ioctl.p_param = paddr;
  4662. } else if (gen.command.Service == CACHESERVICE) {
  4663. if (ha->cache_feat & GDT_64BIT) {
  4664. /* copy elements from 32-bit IOCTL structure */
  4665. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  4666. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  4667. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  4668. /* addresses */
  4669. if (ha->cache_feat & SCATTER_GATHER) {
  4670. gen.command.u.cache64.DestAddr = (ulong64)-1;
  4671. gen.command.u.cache64.sg_canz = 1;
  4672. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  4673. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  4674. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  4675. } else {
  4676. gen.command.u.cache64.DestAddr = paddr;
  4677. gen.command.u.cache64.sg_canz = 0;
  4678. }
  4679. } else {
  4680. if (ha->cache_feat & SCATTER_GATHER) {
  4681. gen.command.u.cache.DestAddr = 0xffffffff;
  4682. gen.command.u.cache.sg_canz = 1;
  4683. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  4684. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  4685. gen.command.u.cache.sg_lst[1].sg_len = 0;
  4686. } else {
  4687. gen.command.u.cache.DestAddr = paddr;
  4688. gen.command.u.cache.sg_canz = 0;
  4689. }
  4690. }
  4691. } else if (gen.command.Service == SCSIRAWSERVICE) {
  4692. if (ha->raw_feat & GDT_64BIT) {
  4693. /* copy elements from 32-bit IOCTL structure */
  4694. char cmd[16];
  4695. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  4696. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  4697. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  4698. gen.command.u.raw64.target = gen.command.u.raw.target;
  4699. memcpy(cmd, gen.command.u.raw.cmd, 16);
  4700. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  4701. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  4702. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  4703. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  4704. /* addresses */
  4705. if (ha->raw_feat & SCATTER_GATHER) {
  4706. gen.command.u.raw64.sdata = (ulong64)-1;
  4707. gen.command.u.raw64.sg_ranz = 1;
  4708. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  4709. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  4710. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  4711. } else {
  4712. gen.command.u.raw64.sdata = paddr;
  4713. gen.command.u.raw64.sg_ranz = 0;
  4714. }
  4715. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  4716. } else {
  4717. if (ha->raw_feat & SCATTER_GATHER) {
  4718. gen.command.u.raw.sdata = 0xffffffff;
  4719. gen.command.u.raw.sg_ranz = 1;
  4720. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  4721. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  4722. gen.command.u.raw.sg_lst[1].sg_len = 0;
  4723. } else {
  4724. gen.command.u.raw.sdata = paddr;
  4725. gen.command.u.raw.sg_ranz = 0;
  4726. }
  4727. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  4728. }
  4729. } else {
  4730. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4731. return -EFAULT;
  4732. }
  4733. }
  4734. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  4735. if (rval < 0)
  4736. return rval;
  4737. gen.status = rval;
  4738. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  4739. gen.data_len + gen.sense_len)) {
  4740. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4741. return -EFAULT;
  4742. }
  4743. if (copy_to_user(arg, &gen,
  4744. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  4745. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4746. return -EFAULT;
  4747. }
  4748. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4749. return 0;
  4750. }
  4751. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4752. {
  4753. gdth_ioctl_rescan *rsc;
  4754. gdth_cmd_str *cmd;
  4755. gdth_ha_str *ha;
  4756. unchar i;
  4757. int hanum, rc = -ENOMEM;
  4758. u32 cluster_type = 0;
  4759. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4760. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4761. if (!rsc || !cmd)
  4762. goto free_fail;
  4763. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4764. rsc->ionode >= gdth_ctr_count) {
  4765. rc = -EFAULT;
  4766. goto free_fail;
  4767. }
  4768. hanum = rsc->ionode;
  4769. ha = HADATA(gdth_ctr_tab[hanum]);
  4770. memset(cmd, 0, sizeof(gdth_cmd_str));
  4771. for (i = 0; i < MAX_HDRIVES; ++i) {
  4772. if (!ha->hdr[i].present) {
  4773. rsc->hdr_list[i].bus = 0xff;
  4774. continue;
  4775. }
  4776. rsc->hdr_list[i].bus = ha->virt_bus;
  4777. rsc->hdr_list[i].target = i;
  4778. rsc->hdr_list[i].lun = 0;
  4779. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4780. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4781. cmd->Service = CACHESERVICE;
  4782. cmd->OpCode = GDT_CLUST_INFO;
  4783. if (ha->cache_feat & GDT_64BIT)
  4784. cmd->u.cache64.DeviceNo = i;
  4785. else
  4786. cmd->u.cache.DeviceNo = i;
  4787. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  4788. rsc->hdr_list[i].cluster_type = cluster_type;
  4789. }
  4790. }
  4791. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4792. rc = -EFAULT;
  4793. else
  4794. rc = 0;
  4795. free_fail:
  4796. kfree(rsc);
  4797. kfree(cmd);
  4798. return rc;
  4799. }
  4800. static int ioc_rescan(void __user *arg, char *cmnd)
  4801. {
  4802. gdth_ioctl_rescan *rsc;
  4803. gdth_cmd_str *cmd;
  4804. ushort i, status, hdr_cnt;
  4805. ulong32 info;
  4806. int hanum, cyls, hds, secs;
  4807. int rc = -ENOMEM;
  4808. ulong flags;
  4809. gdth_ha_str *ha;
  4810. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4811. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4812. if (!cmd || !rsc)
  4813. goto free_fail;
  4814. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4815. rsc->ionode >= gdth_ctr_count) {
  4816. rc = -EFAULT;
  4817. goto free_fail;
  4818. }
  4819. hanum = rsc->ionode;
  4820. ha = HADATA(gdth_ctr_tab[hanum]);
  4821. memset(cmd, 0, sizeof(gdth_cmd_str));
  4822. if (rsc->flag == 0) {
  4823. /* old method: re-init. cache service */
  4824. cmd->Service = CACHESERVICE;
  4825. if (ha->cache_feat & GDT_64BIT) {
  4826. cmd->OpCode = GDT_X_INIT_HOST;
  4827. cmd->u.cache64.DeviceNo = LINUX_OS;
  4828. } else {
  4829. cmd->OpCode = GDT_INIT;
  4830. cmd->u.cache.DeviceNo = LINUX_OS;
  4831. }
  4832. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4833. i = 0;
  4834. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4835. } else {
  4836. i = rsc->hdr_no;
  4837. hdr_cnt = i + 1;
  4838. }
  4839. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4840. cmd->Service = CACHESERVICE;
  4841. cmd->OpCode = GDT_INFO;
  4842. if (ha->cache_feat & GDT_64BIT)
  4843. cmd->u.cache64.DeviceNo = i;
  4844. else
  4845. cmd->u.cache.DeviceNo = i;
  4846. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4847. spin_lock_irqsave(&ha->smp_lock, flags);
  4848. rsc->hdr_list[i].bus = ha->virt_bus;
  4849. rsc->hdr_list[i].target = i;
  4850. rsc->hdr_list[i].lun = 0;
  4851. if (status != S_OK) {
  4852. ha->hdr[i].present = FALSE;
  4853. } else {
  4854. ha->hdr[i].present = TRUE;
  4855. ha->hdr[i].size = info;
  4856. /* evaluate mapping */
  4857. ha->hdr[i].size &= ~SECS32;
  4858. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4859. ha->hdr[i].heads = hds;
  4860. ha->hdr[i].secs = secs;
  4861. /* round size */
  4862. ha->hdr[i].size = cyls * hds * secs;
  4863. }
  4864. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4865. if (status != S_OK)
  4866. continue;
  4867. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4868. /* but we need ha->info2, not yet stored in scp->SCp */
  4869. /* devtype, cluster info, R/W attribs */
  4870. cmd->Service = CACHESERVICE;
  4871. cmd->OpCode = GDT_DEVTYPE;
  4872. if (ha->cache_feat & GDT_64BIT)
  4873. cmd->u.cache64.DeviceNo = i;
  4874. else
  4875. cmd->u.cache.DeviceNo = i;
  4876. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4877. spin_lock_irqsave(&ha->smp_lock, flags);
  4878. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4879. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4880. cmd->Service = CACHESERVICE;
  4881. cmd->OpCode = GDT_CLUST_INFO;
  4882. if (ha->cache_feat & GDT_64BIT)
  4883. cmd->u.cache64.DeviceNo = i;
  4884. else
  4885. cmd->u.cache.DeviceNo = i;
  4886. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4887. spin_lock_irqsave(&ha->smp_lock, flags);
  4888. ha->hdr[i].cluster_type =
  4889. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4890. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4891. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4892. cmd->Service = CACHESERVICE;
  4893. cmd->OpCode = GDT_RW_ATTRIBS;
  4894. if (ha->cache_feat & GDT_64BIT)
  4895. cmd->u.cache64.DeviceNo = i;
  4896. else
  4897. cmd->u.cache.DeviceNo = i;
  4898. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4899. spin_lock_irqsave(&ha->smp_lock, flags);
  4900. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4901. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4902. }
  4903. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4904. rc = -EFAULT;
  4905. else
  4906. rc = 0;
  4907. free_fail:
  4908. kfree(rsc);
  4909. kfree(cmd);
  4910. return rc;
  4911. }
  4912. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4913. unsigned int cmd, unsigned long arg)
  4914. {
  4915. gdth_ha_str *ha;
  4916. Scsi_Cmnd *scp;
  4917. ulong flags;
  4918. char cmnd[MAX_COMMAND_SIZE];
  4919. void __user *argp = (void __user *)arg;
  4920. memset(cmnd, 0xff, 12);
  4921. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4922. switch (cmd) {
  4923. case GDTIOCTL_CTRCNT:
  4924. {
  4925. int cnt = gdth_ctr_count;
  4926. if (put_user(cnt, (int __user *)argp))
  4927. return -EFAULT;
  4928. break;
  4929. }
  4930. case GDTIOCTL_DRVERS:
  4931. {
  4932. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4933. if (put_user(ver, (int __user *)argp))
  4934. return -EFAULT;
  4935. break;
  4936. }
  4937. case GDTIOCTL_OSVERS:
  4938. {
  4939. gdth_ioctl_osvers osv;
  4940. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4941. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4942. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4943. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4944. return -EFAULT;
  4945. break;
  4946. }
  4947. case GDTIOCTL_CTRTYPE:
  4948. {
  4949. gdth_ioctl_ctrtype ctrt;
  4950. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4951. ctrt.ionode >= gdth_ctr_count)
  4952. return -EFAULT;
  4953. ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
  4954. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4955. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4956. } else {
  4957. if (ha->type != GDT_PCIMPR) {
  4958. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4959. } else {
  4960. ctrt.type =
  4961. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4962. if (ha->stype >= 0x300)
  4963. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4964. else
  4965. ctrt.ext_type = 0x6000 | ha->stype;
  4966. }
  4967. ctrt.device_id = ha->pdev->device;
  4968. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4969. }
  4970. ctrt.info = ha->brd_phys;
  4971. ctrt.oem_id = ha->oem_id;
  4972. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4973. return -EFAULT;
  4974. break;
  4975. }
  4976. case GDTIOCTL_GENERAL:
  4977. return ioc_general(argp, cmnd);
  4978. case GDTIOCTL_EVENT:
  4979. return ioc_event(argp);
  4980. case GDTIOCTL_LOCKDRV:
  4981. return ioc_lockdrv(argp);
  4982. case GDTIOCTL_LOCKCHN:
  4983. {
  4984. gdth_ioctl_lockchn lchn;
  4985. unchar i, j;
  4986. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4987. lchn.ionode >= gdth_ctr_count)
  4988. return -EFAULT;
  4989. ha = HADATA(gdth_ctr_tab[lchn.ionode]);
  4990. i = lchn.channel;
  4991. if (i < ha->bus_cnt) {
  4992. if (lchn.lock) {
  4993. spin_lock_irqsave(&ha->smp_lock, flags);
  4994. ha->raw[i].lock = 1;
  4995. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4996. for (j = 0; j < ha->tid_cnt; ++j) {
  4997. gdth_wait_completion(lchn.ionode, i, j);
  4998. gdth_stop_timeout(lchn.ionode, i, j);
  4999. }
  5000. } else {
  5001. spin_lock_irqsave(&ha->smp_lock, flags);
  5002. ha->raw[i].lock = 0;
  5003. spin_unlock_irqrestore(&ha->smp_lock, flags);
  5004. for (j = 0; j < ha->tid_cnt; ++j) {
  5005. gdth_start_timeout(lchn.ionode, i, j);
  5006. gdth_next(lchn.ionode);
  5007. }
  5008. }
  5009. }
  5010. break;
  5011. }
  5012. case GDTIOCTL_RESCAN:
  5013. return ioc_rescan(argp, cmnd);
  5014. case GDTIOCTL_HDRLIST:
  5015. return ioc_hdrlist(argp, cmnd);
  5016. case GDTIOCTL_RESET_BUS:
  5017. {
  5018. gdth_ioctl_reset res;
  5019. int hanum, rval;
  5020. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  5021. res.ionode >= gdth_ctr_count)
  5022. return -EFAULT;
  5023. hanum = res.ionode;
  5024. ha = HADATA(gdth_ctr_tab[hanum]);
  5025. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5026. scp = kmalloc(sizeof(*scp), GFP_KERNEL);
  5027. if (!scp)
  5028. return -ENOMEM;
  5029. memset(scp, 0, sizeof(*scp));
  5030. scp->device = ha->sdev;
  5031. scp->cmd_len = 12;
  5032. scp->use_sg = 0;
  5033. scp->device->channel = virt_ctr ? 0 : res.number;
  5034. rval = gdth_eh_bus_reset(scp);
  5035. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5036. kfree(scp);
  5037. #else
  5038. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  5039. if (!scp)
  5040. return -ENOMEM;
  5041. scp->cmd_len = 12;
  5042. scp->use_sg = 0;
  5043. scp->channel = virt_ctr ? 0 : res.number;
  5044. rval = gdth_eh_bus_reset(scp);
  5045. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5046. scsi_release_command(scp);
  5047. #endif
  5048. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  5049. return -EFAULT;
  5050. break;
  5051. }
  5052. case GDTIOCTL_RESET_DRV:
  5053. return ioc_resetdrv(argp, cmnd);
  5054. default:
  5055. break;
  5056. }
  5057. return 0;
  5058. }
  5059. /* flush routine */
  5060. static void gdth_flush(int hanum)
  5061. {
  5062. int i;
  5063. gdth_ha_str *ha;
  5064. gdth_cmd_str gdtcmd;
  5065. char cmnd[MAX_COMMAND_SIZE];
  5066. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5067. TRACE2(("gdth_flush() hanum %d\n",hanum));
  5068. ha = HADATA(gdth_ctr_tab[hanum]);
  5069. for (i = 0; i < MAX_HDRIVES; ++i) {
  5070. if (ha->hdr[i].present) {
  5071. gdtcmd.BoardNode = LOCALBOARD;
  5072. gdtcmd.Service = CACHESERVICE;
  5073. gdtcmd.OpCode = GDT_FLUSH;
  5074. if (ha->cache_feat & GDT_64BIT) {
  5075. gdtcmd.u.cache64.DeviceNo = i;
  5076. gdtcmd.u.cache64.BlockNo = 1;
  5077. gdtcmd.u.cache64.sg_canz = 0;
  5078. } else {
  5079. gdtcmd.u.cache.DeviceNo = i;
  5080. gdtcmd.u.cache.BlockNo = 1;
  5081. gdtcmd.u.cache.sg_canz = 0;
  5082. }
  5083. TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
  5084. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
  5085. }
  5086. }
  5087. }
  5088. /* shutdown routine */
  5089. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  5090. {
  5091. int hanum;
  5092. #ifndef __alpha__
  5093. gdth_cmd_str gdtcmd;
  5094. char cmnd[MAX_COMMAND_SIZE];
  5095. #endif
  5096. if (notifier_disabled)
  5097. return NOTIFY_OK;
  5098. TRACE2(("gdth_halt() event %d\n",(int)event));
  5099. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  5100. return NOTIFY_DONE;
  5101. notifier_disabled = 1;
  5102. printk("GDT-HA: Flushing all host drives .. ");
  5103. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  5104. gdth_flush(hanum);
  5105. #ifndef __alpha__
  5106. /* controller reset */
  5107. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5108. gdtcmd.BoardNode = LOCALBOARD;
  5109. gdtcmd.Service = CACHESERVICE;
  5110. gdtcmd.OpCode = GDT_RESET;
  5111. TRACE2(("gdth_halt(): reset controller %d\n", hanum));
  5112. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
  5113. #endif
  5114. }
  5115. printk("Done.\n");
  5116. #ifdef GDTH_STATISTICS
  5117. del_timer(&gdth_timer);
  5118. #endif
  5119. return NOTIFY_OK;
  5120. }
  5121. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5122. /* configure lun */
  5123. static int gdth_slave_configure(struct scsi_device *sdev)
  5124. {
  5125. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  5126. sdev->skip_ms_page_3f = 1;
  5127. sdev->skip_ms_page_8 = 1;
  5128. return 0;
  5129. }
  5130. #endif
  5131. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5132. static struct scsi_host_template driver_template = {
  5133. #else
  5134. static Scsi_Host_Template driver_template = {
  5135. #endif
  5136. .proc_name = "gdth",
  5137. .proc_info = gdth_proc_info,
  5138. .name = "GDT SCSI Disk Array Controller",
  5139. .detect = gdth_detect,
  5140. .release = gdth_release,
  5141. .info = gdth_info,
  5142. .queuecommand = gdth_queuecommand,
  5143. .eh_bus_reset_handler = gdth_eh_bus_reset,
  5144. .bios_param = gdth_bios_param,
  5145. .can_queue = GDTH_MAXCMDS,
  5146. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5147. .slave_configure = gdth_slave_configure,
  5148. #endif
  5149. .this_id = -1,
  5150. .sg_tablesize = GDTH_MAXSG,
  5151. .cmd_per_lun = GDTH_MAXC_P_L,
  5152. .unchecked_isa_dma = 1,
  5153. .use_clustering = ENABLE_CLUSTERING,
  5154. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  5155. .use_new_eh_code = 1,
  5156. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
  5157. .highmem_io = 1,
  5158. #endif
  5159. #endif
  5160. };
  5161. #include "scsi_module.c"
  5162. #ifndef MODULE
  5163. __setup("gdth=", option_setup);
  5164. #endif