rt2x00pci.c 11 KB

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  1. /*
  2. Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2x00pci
  19. Abstract: rt2x00 generic pci device routines.
  20. */
  21. /*
  22. * Set enviroment defines for rt2x00.h
  23. */
  24. #define DRV_NAME "rt2x00pci"
  25. #include <linux/dma-mapping.h>
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/pci.h>
  29. #include "rt2x00.h"
  30. #include "rt2x00pci.h"
  31. /*
  32. * Beacon handlers.
  33. */
  34. int rt2x00pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  35. struct ieee80211_tx_control *control)
  36. {
  37. struct rt2x00_dev *rt2x00dev = hw->priv;
  38. struct data_ring *ring =
  39. rt2x00lib_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
  40. struct data_entry *entry = rt2x00_get_data_entry(ring);
  41. /*
  42. * Just in case mac80211 doesn't set this correctly,
  43. * but we need this queue set for the descriptor
  44. * initialization.
  45. */
  46. control->queue = IEEE80211_TX_QUEUE_BEACON;
  47. /*
  48. * Update the beacon entry.
  49. */
  50. memcpy(entry->data_addr, skb->data, skb->len);
  51. rt2x00lib_write_tx_desc(rt2x00dev, entry->priv,
  52. (struct ieee80211_hdr *)skb->data,
  53. skb->len, control);
  54. /*
  55. * Enable beacon generation.
  56. */
  57. rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
  58. return 0;
  59. }
  60. EXPORT_SYMBOL_GPL(rt2x00pci_beacon_update);
  61. /*
  62. * TX data handlers.
  63. */
  64. int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
  65. struct data_ring *ring, struct sk_buff *skb,
  66. struct ieee80211_tx_control *control)
  67. {
  68. struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data;
  69. struct data_entry *entry = rt2x00_get_data_entry(ring);
  70. struct data_desc *txd = entry->priv;
  71. u32 word;
  72. if (rt2x00_ring_full(ring)) {
  73. ieee80211_stop_queue(rt2x00dev->hw, control->queue);
  74. return -EINVAL;
  75. }
  76. rt2x00_desc_read(txd, 0, &word);
  77. if (rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) ||
  78. rt2x00_get_field32(word, TXD_ENTRY_VALID)) {
  79. ERROR(rt2x00dev,
  80. "Arrived at non-free entry in the non-full queue %d.\n"
  81. "Please file bug report to %s.\n",
  82. control->queue, DRV_PROJECT);
  83. ieee80211_stop_queue(rt2x00dev->hw, control->queue);
  84. return -EINVAL;
  85. }
  86. entry->skb = skb;
  87. memcpy(&entry->tx_status.control, control, sizeof(*control));
  88. memcpy(entry->data_addr, skb->data, skb->len);
  89. rt2x00lib_write_tx_desc(rt2x00dev, txd, ieee80211hdr,
  90. skb->len, control);
  91. rt2x00_ring_index_inc(ring);
  92. if (rt2x00_ring_full(ring))
  93. ieee80211_stop_queue(rt2x00dev->hw, control->queue);
  94. return 0;
  95. }
  96. EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data);
  97. /*
  98. * RX data handlers.
  99. */
  100. void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
  101. {
  102. struct data_ring *ring = rt2x00dev->rx;
  103. struct data_entry *entry;
  104. struct data_desc *rxd;
  105. struct sk_buff *skb;
  106. struct rxdata_entry_desc desc;
  107. u32 word;
  108. while (1) {
  109. entry = rt2x00_get_data_entry(ring);
  110. rxd = entry->priv;
  111. rt2x00_desc_read(rxd, 0, &word);
  112. if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC))
  113. break;
  114. memset(&desc, 0x00, sizeof(desc));
  115. rt2x00dev->ops->lib->fill_rxdone(entry, &desc);
  116. /*
  117. * Allocate the sk_buffer, initialize it and copy
  118. * all data into it.
  119. */
  120. skb = dev_alloc_skb(desc.size + NET_IP_ALIGN);
  121. if (!skb)
  122. return;
  123. skb_reserve(skb, NET_IP_ALIGN);
  124. skb_put(skb, desc.size);
  125. memcpy(skb->data, entry->data_addr, desc.size);
  126. /*
  127. * Send the frame to rt2x00lib for further processing.
  128. */
  129. rt2x00lib_rxdone(entry, skb, &desc);
  130. if (test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags)) {
  131. rt2x00_set_field32(&word, RXD_ENTRY_OWNER_NIC, 1);
  132. rt2x00_desc_write(rxd, 0, word);
  133. }
  134. rt2x00_ring_index_inc(ring);
  135. }
  136. }
  137. EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
  138. /*
  139. * Device initialization handlers.
  140. */
  141. #define priv_offset(__ring, __i) \
  142. ({ \
  143. ring->data_addr + (i * ring->desc_size); \
  144. })
  145. #define data_addr_offset(__ring, __i) \
  146. ({ \
  147. (__ring)->data_addr + \
  148. ((__ring)->stats.limit * (__ring)->desc_size) + \
  149. ((__i) * (__ring)->data_size); \
  150. })
  151. #define data_dma_offset(__ring, __i) \
  152. ({ \
  153. (__ring)->data_dma + \
  154. ((__ring)->stats.limit * (__ring)->desc_size) + \
  155. ((__i) * (__ring)->data_size); \
  156. })
  157. static int rt2x00pci_alloc_dma(struct rt2x00_dev *rt2x00dev,
  158. struct data_ring *ring)
  159. {
  160. unsigned int i;
  161. /*
  162. * Allocate DMA memory for descriptor and buffer.
  163. */
  164. ring->data_addr = pci_alloc_consistent(rt2x00dev_pci(rt2x00dev),
  165. rt2x00_get_ring_size(ring),
  166. &ring->data_dma);
  167. if (!ring->data_addr)
  168. return -ENOMEM;
  169. /*
  170. * Initialize all ring entries to contain valid
  171. * addresses.
  172. */
  173. for (i = 0; i < ring->stats.limit; i++) {
  174. ring->entry[i].priv = priv_offset(ring, i);
  175. ring->entry[i].data_addr = data_addr_offset(ring, i);
  176. ring->entry[i].data_dma = data_dma_offset(ring, i);
  177. }
  178. return 0;
  179. }
  180. static void rt2x00pci_free_dma(struct rt2x00_dev *rt2x00dev,
  181. struct data_ring *ring)
  182. {
  183. if (ring->data_addr)
  184. pci_free_consistent(rt2x00dev_pci(rt2x00dev),
  185. rt2x00_get_ring_size(ring),
  186. ring->data_addr, ring->data_dma);
  187. ring->data_addr = NULL;
  188. }
  189. int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
  190. {
  191. struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
  192. struct data_ring *ring;
  193. int status;
  194. /*
  195. * Allocate DMA
  196. */
  197. ring_for_each(rt2x00dev, ring) {
  198. status = rt2x00pci_alloc_dma(rt2x00dev, ring);
  199. if (status)
  200. goto exit;
  201. }
  202. /*
  203. * Register interrupt handler.
  204. */
  205. status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler,
  206. IRQF_SHARED, pci_name(pci_dev), rt2x00dev);
  207. if (status) {
  208. ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
  209. pci_dev->irq, status);
  210. return status;
  211. }
  212. return 0;
  213. exit:
  214. rt2x00pci_uninitialize(rt2x00dev);
  215. return status;
  216. }
  217. EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
  218. void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
  219. {
  220. struct data_ring *ring;
  221. /*
  222. * Free irq line.
  223. */
  224. free_irq(rt2x00dev_pci(rt2x00dev)->irq, rt2x00dev);
  225. /*
  226. * Free DMA
  227. */
  228. ring_for_each(rt2x00dev, ring)
  229. rt2x00pci_free_dma(rt2x00dev, ring);
  230. }
  231. EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
  232. /*
  233. * PCI driver handlers.
  234. */
  235. static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
  236. {
  237. kfree(rt2x00dev->rf);
  238. rt2x00dev->rf = NULL;
  239. kfree(rt2x00dev->eeprom);
  240. rt2x00dev->eeprom = NULL;
  241. if (rt2x00dev->csr_addr) {
  242. iounmap(rt2x00dev->csr_addr);
  243. rt2x00dev->csr_addr = NULL;
  244. }
  245. }
  246. static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
  247. {
  248. struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
  249. rt2x00dev->csr_addr = ioremap(pci_resource_start(pci_dev, 0),
  250. pci_resource_len(pci_dev, 0));
  251. if (!rt2x00dev->csr_addr)
  252. goto exit;
  253. rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
  254. if (!rt2x00dev->eeprom)
  255. goto exit;
  256. rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
  257. if (!rt2x00dev->rf)
  258. goto exit;
  259. return 0;
  260. exit:
  261. ERROR_PROBE("Failed to allocate registers.\n");
  262. rt2x00pci_free_reg(rt2x00dev);
  263. return -ENOMEM;
  264. }
  265. int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  266. {
  267. struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_data;
  268. struct ieee80211_hw *hw;
  269. struct rt2x00_dev *rt2x00dev;
  270. int retval;
  271. retval = pci_request_regions(pci_dev, pci_name(pci_dev));
  272. if (retval) {
  273. ERROR_PROBE("PCI request regions failed.\n");
  274. return retval;
  275. }
  276. retval = pci_enable_device(pci_dev);
  277. if (retval) {
  278. ERROR_PROBE("Enable device failed.\n");
  279. goto exit_release_regions;
  280. }
  281. pci_set_master(pci_dev);
  282. if (pci_set_mwi(pci_dev))
  283. ERROR_PROBE("MWI not available.\n");
  284. if (pci_set_dma_mask(pci_dev, DMA_64BIT_MASK) &&
  285. pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
  286. ERROR_PROBE("PCI DMA not supported.\n");
  287. retval = -EIO;
  288. goto exit_disable_device;
  289. }
  290. hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
  291. if (!hw) {
  292. ERROR_PROBE("Failed to allocate hardware.\n");
  293. retval = -ENOMEM;
  294. goto exit_disable_device;
  295. }
  296. pci_set_drvdata(pci_dev, hw);
  297. rt2x00dev = hw->priv;
  298. rt2x00dev->dev = pci_dev;
  299. rt2x00dev->ops = ops;
  300. rt2x00dev->hw = hw;
  301. retval = rt2x00pci_alloc_reg(rt2x00dev);
  302. if (retval)
  303. goto exit_free_device;
  304. retval = rt2x00lib_probe_dev(rt2x00dev);
  305. if (retval)
  306. goto exit_free_reg;
  307. return 0;
  308. exit_free_reg:
  309. rt2x00pci_free_reg(rt2x00dev);
  310. exit_free_device:
  311. ieee80211_free_hw(hw);
  312. exit_disable_device:
  313. if (retval != -EBUSY)
  314. pci_disable_device(pci_dev);
  315. exit_release_regions:
  316. pci_release_regions(pci_dev);
  317. pci_set_drvdata(pci_dev, NULL);
  318. return retval;
  319. }
  320. EXPORT_SYMBOL_GPL(rt2x00pci_probe);
  321. void rt2x00pci_remove(struct pci_dev *pci_dev)
  322. {
  323. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  324. struct rt2x00_dev *rt2x00dev = hw->priv;
  325. /*
  326. * Free all allocated data.
  327. */
  328. rt2x00lib_remove_dev(rt2x00dev);
  329. rt2x00pci_free_reg(rt2x00dev);
  330. ieee80211_free_hw(hw);
  331. /*
  332. * Free the PCI device data.
  333. */
  334. pci_set_drvdata(pci_dev, NULL);
  335. pci_disable_device(pci_dev);
  336. pci_release_regions(pci_dev);
  337. }
  338. EXPORT_SYMBOL_GPL(rt2x00pci_remove);
  339. #ifdef CONFIG_PM
  340. int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
  341. {
  342. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  343. struct rt2x00_dev *rt2x00dev = hw->priv;
  344. int retval;
  345. retval = rt2x00lib_suspend(rt2x00dev, state);
  346. if (retval)
  347. return retval;
  348. rt2x00pci_free_reg(rt2x00dev);
  349. pci_save_state(pci_dev);
  350. pci_disable_device(pci_dev);
  351. return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
  352. }
  353. EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
  354. int rt2x00pci_resume(struct pci_dev *pci_dev)
  355. {
  356. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  357. struct rt2x00_dev *rt2x00dev = hw->priv;
  358. int retval;
  359. if (pci_set_power_state(pci_dev, PCI_D0) ||
  360. pci_enable_device(pci_dev) ||
  361. pci_restore_state(pci_dev)) {
  362. ERROR(rt2x00dev, "Failed to resume device.\n");
  363. return -EIO;
  364. }
  365. retval = rt2x00pci_alloc_reg(rt2x00dev);
  366. if (retval)
  367. return retval;
  368. retval = rt2x00lib_resume(rt2x00dev);
  369. if (retval)
  370. goto exit_free_reg;
  371. return 0;
  372. exit_free_reg:
  373. rt2x00pci_free_reg(rt2x00dev);
  374. return retval;
  375. }
  376. EXPORT_SYMBOL_GPL(rt2x00pci_resume);
  377. #endif /* CONFIG_PM */
  378. /*
  379. * rt2x00pci module information.
  380. */
  381. MODULE_AUTHOR(DRV_PROJECT);
  382. MODULE_VERSION(DRV_VERSION);
  383. MODULE_DESCRIPTION("rt2x00 library");
  384. MODULE_LICENSE("GPL");