iwl-4965.c 130 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/etherdevice.h>
  39. #include <linux/delay.h>
  40. #define IWL 4965
  41. #include "iwlwifi.h"
  42. #include "iwl-4965.h"
  43. #include "iwl-helpers.h"
  44. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  45. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  46. IWL_RATE_SISO_##s##M_PLCP, \
  47. IWL_RATE_MIMO_##s##M_PLCP, \
  48. IWL_RATE_##r##M_IEEE, \
  49. IWL_RATE_##ip##M_INDEX, \
  50. IWL_RATE_##in##M_INDEX, \
  51. IWL_RATE_##rp##M_INDEX, \
  52. IWL_RATE_##rn##M_INDEX, \
  53. IWL_RATE_##pp##M_INDEX, \
  54. IWL_RATE_##np##M_INDEX }
  55. /*
  56. * Parameter order:
  57. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  58. *
  59. * If there isn't a valid next or previous rate then INV is used which
  60. * maps to IWL_RATE_INVALID
  61. *
  62. */
  63. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  64. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  65. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  66. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  67. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  68. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  69. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  70. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  71. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  72. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  73. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  74. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  75. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  76. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  77. };
  78. static int is_fat_channel(__le32 rxon_flags)
  79. {
  80. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  81. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  82. }
  83. static u8 is_single_stream(struct iwl_priv *priv)
  84. {
  85. #ifdef CONFIG_IWLWIFI_HT
  86. if (!priv->is_ht_enabled || !priv->current_assoc_ht.is_ht ||
  87. (priv->active_rate_ht[1] == 0) ||
  88. (priv->ps_mode == IWL_MIMO_PS_STATIC))
  89. return 1;
  90. #else
  91. return 1;
  92. #endif /*CONFIG_IWLWIFI_HT */
  93. return 0;
  94. }
  95. /*
  96. * Determine how many receiver/antenna chains to use.
  97. * More provides better reception via diversity. Fewer saves power.
  98. * MIMO (dual stream) requires at least 2, but works better with 3.
  99. * This does not determine *which* chains to use, just how many.
  100. */
  101. static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
  102. u8 *idle_state, u8 *rx_state)
  103. {
  104. u8 is_single = is_single_stream(priv);
  105. u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
  106. /* # of Rx chains to use when expecting MIMO. */
  107. if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
  108. *rx_state = 2;
  109. else
  110. *rx_state = 3;
  111. /* # Rx chains when idling and maybe trying to save power */
  112. switch (priv->ps_mode) {
  113. case IWL_MIMO_PS_STATIC:
  114. case IWL_MIMO_PS_DYNAMIC:
  115. *idle_state = (is_cam) ? 2 : 1;
  116. break;
  117. case IWL_MIMO_PS_NONE:
  118. *idle_state = (is_cam) ? *rx_state : 1;
  119. break;
  120. default:
  121. *idle_state = 1;
  122. break;
  123. }
  124. return 0;
  125. }
  126. int iwl_hw_rxq_stop(struct iwl_priv *priv)
  127. {
  128. int rc;
  129. unsigned long flags;
  130. spin_lock_irqsave(&priv->lock, flags);
  131. rc = iwl_grab_restricted_access(priv);
  132. if (rc) {
  133. spin_unlock_irqrestore(&priv->lock, flags);
  134. return rc;
  135. }
  136. /* stop HW */
  137. iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  138. rc = iwl_poll_restricted_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  139. (1 << 24), 1000);
  140. if (rc < 0)
  141. IWL_ERROR("Can't stop Rx DMA.\n");
  142. iwl_release_restricted_access(priv);
  143. spin_unlock_irqrestore(&priv->lock, flags);
  144. return 0;
  145. }
  146. u8 iwl_hw_find_station(struct iwl_priv *priv, const u8 *addr)
  147. {
  148. int i;
  149. int start = 0;
  150. int ret = IWL_INVALID_STATION;
  151. unsigned long flags;
  152. DECLARE_MAC_BUF(mac);
  153. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
  154. (priv->iw_mode == IEEE80211_IF_TYPE_AP))
  155. start = IWL_STA_ID;
  156. if (is_broadcast_ether_addr(addr))
  157. return IWL4965_BROADCAST_ID;
  158. spin_lock_irqsave(&priv->sta_lock, flags);
  159. for (i = start; i < priv->hw_setting.max_stations; i++)
  160. if ((priv->stations[i].used) &&
  161. (!compare_ether_addr
  162. (priv->stations[i].sta.sta.addr, addr))) {
  163. ret = i;
  164. goto out;
  165. }
  166. IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
  167. print_mac(mac, addr), priv->num_stations);
  168. out:
  169. spin_unlock_irqrestore(&priv->sta_lock, flags);
  170. return ret;
  171. }
  172. static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
  173. {
  174. int rc = 0;
  175. unsigned long flags;
  176. spin_lock_irqsave(&priv->lock, flags);
  177. rc = iwl_grab_restricted_access(priv);
  178. if (rc) {
  179. spin_unlock_irqrestore(&priv->lock, flags);
  180. return rc;
  181. }
  182. if (!pwr_max) {
  183. u32 val;
  184. rc = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  185. &val);
  186. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
  187. iwl_set_bits_mask_restricted_reg(
  188. priv, APMG_PS_CTRL_REG,
  189. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  190. ~APMG_PS_CTRL_MSK_PWR_SRC);
  191. } else
  192. iwl_set_bits_mask_restricted_reg(
  193. priv, APMG_PS_CTRL_REG,
  194. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  195. ~APMG_PS_CTRL_MSK_PWR_SRC);
  196. iwl_release_restricted_access(priv);
  197. spin_unlock_irqrestore(&priv->lock, flags);
  198. return rc;
  199. }
  200. static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  201. {
  202. int rc;
  203. unsigned long flags;
  204. spin_lock_irqsave(&priv->lock, flags);
  205. rc = iwl_grab_restricted_access(priv);
  206. if (rc) {
  207. spin_unlock_irqrestore(&priv->lock, flags);
  208. return rc;
  209. }
  210. /* stop HW */
  211. iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  212. iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  213. iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  214. rxq->dma_addr >> 8);
  215. iwl_write_restricted(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  216. (priv->hw_setting.shared_phys +
  217. offsetof(struct iwl_shared, val0)) >> 4);
  218. iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  219. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  220. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  221. IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K |
  222. /*0x10 << 4 | */
  223. (RX_QUEUE_SIZE_LOG <<
  224. FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
  225. /*
  226. * iwl_write32(priv,CSR_INT_COAL_REG,0);
  227. */
  228. iwl_release_restricted_access(priv);
  229. spin_unlock_irqrestore(&priv->lock, flags);
  230. return 0;
  231. }
  232. static int iwl4965_kw_init(struct iwl_priv *priv)
  233. {
  234. unsigned long flags;
  235. int rc;
  236. spin_lock_irqsave(&priv->lock, flags);
  237. rc = iwl_grab_restricted_access(priv);
  238. if (rc)
  239. goto out;
  240. iwl_write_restricted(priv, IWL_FH_KW_MEM_ADDR_REG,
  241. priv->kw.dma_addr >> 4);
  242. iwl_release_restricted_access(priv);
  243. out:
  244. spin_unlock_irqrestore(&priv->lock, flags);
  245. return rc;
  246. }
  247. static int iwl4965_kw_alloc(struct iwl_priv *priv)
  248. {
  249. struct pci_dev *dev = priv->pci_dev;
  250. struct iwl_kw *kw = &priv->kw;
  251. kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
  252. kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
  253. if (!kw->v_addr)
  254. return -ENOMEM;
  255. return 0;
  256. }
  257. #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
  258. ? # x " " : "")
  259. int iwl4965_set_fat_chan_info(struct iwl_priv *priv, int phymode, u16 channel,
  260. const struct iwl_eeprom_channel *eeprom_ch,
  261. u8 fat_extension_channel)
  262. {
  263. struct iwl_channel_info *ch_info;
  264. ch_info = (struct iwl_channel_info *)
  265. iwl_get_channel_info(priv, phymode, channel);
  266. if (!is_channel_valid(ch_info))
  267. return -1;
  268. IWL_DEBUG_INFO("FAT Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  269. " %ddBm): Ad-Hoc %ssupported\n",
  270. ch_info->channel,
  271. is_channel_a_band(ch_info) ?
  272. "5.2" : "2.4",
  273. CHECK_AND_PRINT(IBSS),
  274. CHECK_AND_PRINT(ACTIVE),
  275. CHECK_AND_PRINT(RADAR),
  276. CHECK_AND_PRINT(WIDE),
  277. CHECK_AND_PRINT(NARROW),
  278. CHECK_AND_PRINT(DFS),
  279. eeprom_ch->flags,
  280. eeprom_ch->max_power_avg,
  281. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
  282. && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
  283. "" : "not ");
  284. ch_info->fat_eeprom = *eeprom_ch;
  285. ch_info->fat_max_power_avg = eeprom_ch->max_power_avg;
  286. ch_info->fat_curr_txpow = eeprom_ch->max_power_avg;
  287. ch_info->fat_min_power = 0;
  288. ch_info->fat_scan_power = eeprom_ch->max_power_avg;
  289. ch_info->fat_flags = eeprom_ch->flags;
  290. ch_info->fat_extension_channel = fat_extension_channel;
  291. return 0;
  292. }
  293. static void iwl4965_kw_free(struct iwl_priv *priv)
  294. {
  295. struct pci_dev *dev = priv->pci_dev;
  296. struct iwl_kw *kw = &priv->kw;
  297. if (kw->v_addr) {
  298. pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
  299. memset(kw, 0, sizeof(*kw));
  300. }
  301. }
  302. /**
  303. * iwl4965_txq_ctx_reset - Reset TX queue context
  304. * Destroys all DMA structures and initialise them again
  305. *
  306. * @param priv
  307. * @return error code
  308. */
  309. static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
  310. {
  311. int rc = 0;
  312. int txq_id, slots_num;
  313. unsigned long flags;
  314. iwl4965_kw_free(priv);
  315. iwl_hw_txq_ctx_free(priv);
  316. /* Tx CMD queue */
  317. rc = iwl4965_kw_alloc(priv);
  318. if (rc) {
  319. IWL_ERROR("Keep Warm allocation failed");
  320. goto error_kw;
  321. }
  322. spin_lock_irqsave(&priv->lock, flags);
  323. rc = iwl_grab_restricted_access(priv);
  324. if (unlikely(rc)) {
  325. IWL_ERROR("TX reset failed");
  326. spin_unlock_irqrestore(&priv->lock, flags);
  327. goto error_reset;
  328. }
  329. iwl_write_restricted_reg(priv, SCD_TXFACT, 0);
  330. iwl_release_restricted_access(priv);
  331. spin_unlock_irqrestore(&priv->lock, flags);
  332. rc = iwl4965_kw_init(priv);
  333. if (rc) {
  334. IWL_ERROR("kw_init failed\n");
  335. goto error_reset;
  336. }
  337. /* Tx queue(s) */
  338. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  339. slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
  340. TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
  341. rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
  342. txq_id);
  343. if (rc) {
  344. IWL_ERROR("Tx %d queue init failed\n", txq_id);
  345. goto error;
  346. }
  347. }
  348. return rc;
  349. error:
  350. iwl_hw_txq_ctx_free(priv);
  351. error_reset:
  352. iwl4965_kw_free(priv);
  353. error_kw:
  354. return rc;
  355. }
  356. int iwl_hw_nic_init(struct iwl_priv *priv)
  357. {
  358. int rc;
  359. unsigned long flags;
  360. struct iwl_rx_queue *rxq = &priv->rxq;
  361. u8 rev_id;
  362. u32 val;
  363. u8 val_link;
  364. iwl_power_init_handle(priv);
  365. /* nic_init */
  366. spin_lock_irqsave(&priv->lock, flags);
  367. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  368. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  369. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  370. rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
  371. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  372. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  373. if (rc < 0) {
  374. spin_unlock_irqrestore(&priv->lock, flags);
  375. IWL_DEBUG_INFO("Failed to init the card\n");
  376. return rc;
  377. }
  378. rc = iwl_grab_restricted_access(priv);
  379. if (rc) {
  380. spin_unlock_irqrestore(&priv->lock, flags);
  381. return rc;
  382. }
  383. iwl_read_restricted_reg(priv, APMG_CLK_CTRL_REG);
  384. iwl_write_restricted_reg(priv, APMG_CLK_CTRL_REG,
  385. APMG_CLK_VAL_DMA_CLK_RQT |
  386. APMG_CLK_VAL_BSM_CLK_RQT);
  387. iwl_read_restricted_reg(priv, APMG_CLK_CTRL_REG);
  388. udelay(20);
  389. iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG,
  390. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  391. iwl_release_restricted_access(priv);
  392. iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
  393. spin_unlock_irqrestore(&priv->lock, flags);
  394. /* Determine HW type */
  395. rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
  396. if (rc)
  397. return rc;
  398. IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
  399. iwl4965_nic_set_pwr_src(priv, 1);
  400. spin_lock_irqsave(&priv->lock, flags);
  401. if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
  402. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  403. /* Enable No Snoop field */
  404. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  405. val & ~(1 << 11));
  406. }
  407. spin_unlock_irqrestore(&priv->lock, flags);
  408. /* Read the EEPROM */
  409. rc = iwl_eeprom_init(priv);
  410. if (rc)
  411. return rc;
  412. if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
  413. IWL_ERROR("Older EEPROM detected! Aborting.\n");
  414. return -EINVAL;
  415. }
  416. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  417. /* disable L1 entry -- workaround for pre-B1 */
  418. pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
  419. spin_lock_irqsave(&priv->lock, flags);
  420. /* set CSR_HW_CONFIG_REG for uCode use */
  421. iwl_set_bit(priv, CSR_SW_VER, CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R |
  422. CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  423. CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  424. rc = iwl_grab_restricted_access(priv);
  425. if (rc < 0) {
  426. spin_unlock_irqrestore(&priv->lock, flags);
  427. IWL_DEBUG_INFO("Failed to init the card\n");
  428. return rc;
  429. }
  430. iwl_read_restricted_reg(priv, APMG_PS_CTRL_REG);
  431. iwl_set_bits_restricted_reg(priv, APMG_PS_CTRL_REG,
  432. APMG_PS_CTRL_VAL_RESET_REQ);
  433. udelay(5);
  434. iwl_clear_bits_restricted_reg(priv, APMG_PS_CTRL_REG,
  435. APMG_PS_CTRL_VAL_RESET_REQ);
  436. iwl_release_restricted_access(priv);
  437. spin_unlock_irqrestore(&priv->lock, flags);
  438. iwl_hw_card_show_info(priv);
  439. /* end nic_init */
  440. /* Allocate the RX queue, or reset if it is already allocated */
  441. if (!rxq->bd) {
  442. rc = iwl_rx_queue_alloc(priv);
  443. if (rc) {
  444. IWL_ERROR("Unable to initialize Rx queue\n");
  445. return -ENOMEM;
  446. }
  447. } else
  448. iwl_rx_queue_reset(priv, rxq);
  449. iwl_rx_replenish(priv);
  450. iwl4965_rx_init(priv, rxq);
  451. spin_lock_irqsave(&priv->lock, flags);
  452. rxq->need_update = 1;
  453. iwl_rx_queue_update_write_ptr(priv, rxq);
  454. spin_unlock_irqrestore(&priv->lock, flags);
  455. rc = iwl4965_txq_ctx_reset(priv);
  456. if (rc)
  457. return rc;
  458. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
  459. IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
  460. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
  461. IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
  462. set_bit(STATUS_INIT, &priv->status);
  463. return 0;
  464. }
  465. int iwl_hw_nic_stop_master(struct iwl_priv *priv)
  466. {
  467. int rc = 0;
  468. u32 reg_val;
  469. unsigned long flags;
  470. spin_lock_irqsave(&priv->lock, flags);
  471. /* set stop master bit */
  472. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  473. reg_val = iwl_read32(priv, CSR_GP_CNTRL);
  474. if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
  475. (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
  476. IWL_DEBUG_INFO("Card in power save, master is already "
  477. "stopped\n");
  478. else {
  479. rc = iwl_poll_bit(priv, CSR_RESET,
  480. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  481. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  482. if (rc < 0) {
  483. spin_unlock_irqrestore(&priv->lock, flags);
  484. return rc;
  485. }
  486. }
  487. spin_unlock_irqrestore(&priv->lock, flags);
  488. IWL_DEBUG_INFO("stop master\n");
  489. return rc;
  490. }
  491. void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
  492. {
  493. int txq_id;
  494. unsigned long flags;
  495. /* reset TFD queues */
  496. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  497. spin_lock_irqsave(&priv->lock, flags);
  498. if (iwl_grab_restricted_access(priv)) {
  499. spin_unlock_irqrestore(&priv->lock, flags);
  500. continue;
  501. }
  502. iwl_write_restricted(priv,
  503. IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
  504. 0x0);
  505. iwl_poll_restricted_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
  506. IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
  507. (txq_id), 200);
  508. iwl_release_restricted_access(priv);
  509. spin_unlock_irqrestore(&priv->lock, flags);
  510. }
  511. iwl_hw_txq_ctx_free(priv);
  512. }
  513. int iwl_hw_nic_reset(struct iwl_priv *priv)
  514. {
  515. int rc = 0;
  516. unsigned long flags;
  517. iwl_hw_nic_stop_master(priv);
  518. spin_lock_irqsave(&priv->lock, flags);
  519. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  520. udelay(10);
  521. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  522. rc = iwl_poll_bit(priv, CSR_RESET,
  523. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  524. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  525. udelay(10);
  526. rc = iwl_grab_restricted_access(priv);
  527. if (!rc) {
  528. iwl_write_restricted_reg(priv, APMG_CLK_EN_REG,
  529. APMG_CLK_VAL_DMA_CLK_RQT |
  530. APMG_CLK_VAL_BSM_CLK_RQT);
  531. udelay(10);
  532. iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG,
  533. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  534. iwl_release_restricted_access(priv);
  535. }
  536. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  537. wake_up_interruptible(&priv->wait_command_queue);
  538. spin_unlock_irqrestore(&priv->lock, flags);
  539. return rc;
  540. }
  541. #define REG_RECALIB_PERIOD (60)
  542. /**
  543. * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
  544. *
  545. * This callback is provided in order to queue the statistics_work
  546. * in work_queue context (v. softirq)
  547. *
  548. * This timer function is continually reset to execute within
  549. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  550. * was received. We need to ensure we receive the statistics in order
  551. * to update the temperature used for calibrating the TXPOWER. However,
  552. * we can't send the statistics command from softirq context (which
  553. * is the context which timers run at) so we have to queue off the
  554. * statistics_work to actually send the command to the hardware.
  555. */
  556. static void iwl4965_bg_statistics_periodic(unsigned long data)
  557. {
  558. struct iwl_priv *priv = (struct iwl_priv *)data;
  559. queue_work(priv->workqueue, &priv->statistics_work);
  560. }
  561. /**
  562. * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
  563. *
  564. * This is queued by iwl_bg_statistics_periodic.
  565. */
  566. static void iwl4965_bg_statistics_work(struct work_struct *work)
  567. {
  568. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  569. statistics_work);
  570. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  571. return;
  572. mutex_lock(&priv->mutex);
  573. iwl_send_statistics_request(priv);
  574. mutex_unlock(&priv->mutex);
  575. }
  576. #define CT_LIMIT_CONST 259
  577. #define TM_CT_KILL_THRESHOLD 110
  578. void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  579. {
  580. struct iwl_ct_kill_config cmd;
  581. u32 R1, R2, R3;
  582. u32 temp_th;
  583. u32 crit_temperature;
  584. unsigned long flags;
  585. int rc = 0;
  586. spin_lock_irqsave(&priv->lock, flags);
  587. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  588. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  589. spin_unlock_irqrestore(&priv->lock, flags);
  590. if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
  591. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  592. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  593. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  594. } else {
  595. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  596. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  597. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  598. }
  599. temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
  600. crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
  601. cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
  602. rc = iwl_send_cmd_pdu(priv,
  603. REPLY_CT_KILL_CONFIG_CMD, sizeof(cmd), &cmd);
  604. if (rc)
  605. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  606. else
  607. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
  608. }
  609. #ifdef CONFIG_IWLWIFI_SENSITIVITY
  610. /* "false alarms" are signals that our DSP tries to lock onto,
  611. * but then determines that they are either noise, or transmissions
  612. * from a distant wireless network (also "noise", really) that get
  613. * "stepped on" by stronger transmissions within our own network.
  614. * This algorithm attempts to set a sensitivity level that is high
  615. * enough to receive all of our own network traffic, but not so
  616. * high that our DSP gets too busy trying to lock onto non-network
  617. * activity/noise. */
  618. static int iwl4965_sens_energy_cck(struct iwl_priv *priv,
  619. u32 norm_fa,
  620. u32 rx_enable_time,
  621. struct statistics_general_data *rx_info)
  622. {
  623. u32 max_nrg_cck = 0;
  624. int i = 0;
  625. u8 max_silence_rssi = 0;
  626. u32 silence_ref = 0;
  627. u8 silence_rssi_a = 0;
  628. u8 silence_rssi_b = 0;
  629. u8 silence_rssi_c = 0;
  630. u32 val;
  631. /* "false_alarms" values below are cross-multiplications to assess the
  632. * numbers of false alarms within the measured period of actual Rx
  633. * (Rx is off when we're txing), vs the min/max expected false alarms
  634. * (some should be expected if rx is sensitive enough) in a
  635. * hypothetical listening period of 200 time units (TU), 204.8 msec:
  636. *
  637. * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
  638. *
  639. * */
  640. u32 false_alarms = norm_fa * 200 * 1024;
  641. u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
  642. u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
  643. struct iwl_sensitivity_data *data = NULL;
  644. data = &(priv->sensitivity_data);
  645. data->nrg_auto_corr_silence_diff = 0;
  646. /* Find max silence rssi among all 3 receivers.
  647. * This is background noise, which may include transmissions from other
  648. * networks, measured during silence before our network's beacon */
  649. silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
  650. ALL_BAND_FILTER)>>8);
  651. silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
  652. ALL_BAND_FILTER)>>8);
  653. silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
  654. ALL_BAND_FILTER)>>8);
  655. val = max(silence_rssi_b, silence_rssi_c);
  656. max_silence_rssi = max(silence_rssi_a, (u8) val);
  657. /* Store silence rssi in 20-beacon history table */
  658. data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
  659. data->nrg_silence_idx++;
  660. if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
  661. data->nrg_silence_idx = 0;
  662. /* Find max silence rssi across 20 beacon history */
  663. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
  664. val = data->nrg_silence_rssi[i];
  665. silence_ref = max(silence_ref, val);
  666. }
  667. IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
  668. silence_rssi_a, silence_rssi_b, silence_rssi_c,
  669. silence_ref);
  670. /* Find max rx energy (min value!) among all 3 receivers,
  671. * measured during beacon frame.
  672. * Save it in 10-beacon history table. */
  673. i = data->nrg_energy_idx;
  674. val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
  675. data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
  676. data->nrg_energy_idx++;
  677. if (data->nrg_energy_idx >= 10)
  678. data->nrg_energy_idx = 0;
  679. /* Find min rx energy (max value) across 10 beacon history.
  680. * This is the minimum signal level that we want to receive well.
  681. * Add backoff (margin so we don't miss slightly lower energy frames).
  682. * This establishes an upper bound (min value) for energy threshold. */
  683. max_nrg_cck = data->nrg_value[0];
  684. for (i = 1; i < 10; i++)
  685. max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
  686. max_nrg_cck += 6;
  687. IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
  688. rx_info->beacon_energy_a, rx_info->beacon_energy_b,
  689. rx_info->beacon_energy_c, max_nrg_cck - 6);
  690. /* Count number of consecutive beacons with fewer-than-desired
  691. * false alarms. */
  692. if (false_alarms < min_false_alarms)
  693. data->num_in_cck_no_fa++;
  694. else
  695. data->num_in_cck_no_fa = 0;
  696. IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
  697. data->num_in_cck_no_fa);
  698. /* If we got too many false alarms this time, reduce sensitivity */
  699. if (false_alarms > max_false_alarms) {
  700. IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
  701. false_alarms, max_false_alarms);
  702. IWL_DEBUG_CALIB("... reducing sensitivity\n");
  703. data->nrg_curr_state = IWL_FA_TOO_MANY;
  704. if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
  705. /* Store for "fewer than desired" on later beacon */
  706. data->nrg_silence_ref = silence_ref;
  707. /* increase energy threshold (reduce nrg value)
  708. * to decrease sensitivity */
  709. if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
  710. data->nrg_th_cck = data->nrg_th_cck
  711. - NRG_STEP_CCK;
  712. }
  713. /* increase auto_corr values to decrease sensitivity */
  714. if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
  715. data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
  716. else {
  717. val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
  718. data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
  719. }
  720. val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
  721. data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
  722. /* Else if we got fewer than desired, increase sensitivity */
  723. } else if (false_alarms < min_false_alarms) {
  724. data->nrg_curr_state = IWL_FA_TOO_FEW;
  725. /* Compare silence level with silence level for most recent
  726. * healthy number or too many false alarms */
  727. data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
  728. (s32)silence_ref;
  729. IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
  730. false_alarms, min_false_alarms,
  731. data->nrg_auto_corr_silence_diff);
  732. /* Increase value to increase sensitivity, but only if:
  733. * 1a) previous beacon did *not* have *too many* false alarms
  734. * 1b) AND there's a significant difference in Rx levels
  735. * from a previous beacon with too many, or healthy # FAs
  736. * OR 2) We've seen a lot of beacons (100) with too few
  737. * false alarms */
  738. if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
  739. ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
  740. (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
  741. IWL_DEBUG_CALIB("... increasing sensitivity\n");
  742. /* Increase nrg value to increase sensitivity */
  743. val = data->nrg_th_cck + NRG_STEP_CCK;
  744. data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
  745. /* Decrease auto_corr values to increase sensitivity */
  746. val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
  747. data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
  748. val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
  749. data->auto_corr_cck_mrc =
  750. max((u32)AUTO_CORR_MIN_CCK_MRC, val);
  751. } else
  752. IWL_DEBUG_CALIB("... but not changing sensitivity\n");
  753. /* Else we got a healthy number of false alarms, keep status quo */
  754. } else {
  755. IWL_DEBUG_CALIB(" FA in safe zone\n");
  756. data->nrg_curr_state = IWL_FA_GOOD_RANGE;
  757. /* Store for use in "fewer than desired" with later beacon */
  758. data->nrg_silence_ref = silence_ref;
  759. /* If previous beacon had too many false alarms,
  760. * give it some extra margin by reducing sensitivity again
  761. * (but don't go below measured energy of desired Rx) */
  762. if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
  763. IWL_DEBUG_CALIB("... increasing margin\n");
  764. data->nrg_th_cck -= NRG_MARGIN;
  765. }
  766. }
  767. /* Make sure the energy threshold does not go above the measured
  768. * energy of the desired Rx signals (reduced by backoff margin),
  769. * or else we might start missing Rx frames.
  770. * Lower value is higher energy, so we use max()!
  771. */
  772. data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
  773. IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
  774. data->nrg_prev_state = data->nrg_curr_state;
  775. return 0;
  776. }
  777. static int iwl4965_sens_auto_corr_ofdm(struct iwl_priv *priv,
  778. u32 norm_fa,
  779. u32 rx_enable_time)
  780. {
  781. u32 val;
  782. u32 false_alarms = norm_fa * 200 * 1024;
  783. u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
  784. u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
  785. struct iwl_sensitivity_data *data = NULL;
  786. data = &(priv->sensitivity_data);
  787. /* If we got too many false alarms this time, reduce sensitivity */
  788. if (false_alarms > max_false_alarms) {
  789. IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
  790. false_alarms, max_false_alarms);
  791. val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
  792. data->auto_corr_ofdm =
  793. min((u32)AUTO_CORR_MAX_OFDM, val);
  794. val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
  795. data->auto_corr_ofdm_mrc =
  796. min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
  797. val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
  798. data->auto_corr_ofdm_x1 =
  799. min((u32)AUTO_CORR_MAX_OFDM_X1, val);
  800. val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
  801. data->auto_corr_ofdm_mrc_x1 =
  802. min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
  803. }
  804. /* Else if we got fewer than desired, increase sensitivity */
  805. else if (false_alarms < min_false_alarms) {
  806. IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
  807. false_alarms, min_false_alarms);
  808. val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
  809. data->auto_corr_ofdm =
  810. max((u32)AUTO_CORR_MIN_OFDM, val);
  811. val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
  812. data->auto_corr_ofdm_mrc =
  813. max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
  814. val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
  815. data->auto_corr_ofdm_x1 =
  816. max((u32)AUTO_CORR_MIN_OFDM_X1, val);
  817. val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
  818. data->auto_corr_ofdm_mrc_x1 =
  819. max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
  820. }
  821. else
  822. IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
  823. min_false_alarms, false_alarms, max_false_alarms);
  824. return 0;
  825. }
  826. static int iwl_sensitivity_callback(struct iwl_priv *priv,
  827. struct iwl_cmd *cmd, struct sk_buff *skb)
  828. {
  829. /* We didn't cache the SKB; let the caller free it */
  830. return 1;
  831. }
  832. /* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
  833. static int iwl4965_sensitivity_write(struct iwl_priv *priv, u8 flags)
  834. {
  835. int rc = 0;
  836. struct iwl_sensitivity_cmd cmd ;
  837. struct iwl_sensitivity_data *data = NULL;
  838. struct iwl_host_cmd cmd_out = {
  839. .id = SENSITIVITY_CMD,
  840. .len = sizeof(struct iwl_sensitivity_cmd),
  841. .meta.flags = flags,
  842. .data = &cmd,
  843. };
  844. data = &(priv->sensitivity_data);
  845. memset(&cmd, 0, sizeof(cmd));
  846. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
  847. cpu_to_le16((u16)data->auto_corr_ofdm);
  848. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
  849. cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
  850. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
  851. cpu_to_le16((u16)data->auto_corr_ofdm_x1);
  852. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
  853. cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
  854. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
  855. cpu_to_le16((u16)data->auto_corr_cck);
  856. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
  857. cpu_to_le16((u16)data->auto_corr_cck_mrc);
  858. cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
  859. cpu_to_le16((u16)data->nrg_th_cck);
  860. cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
  861. cpu_to_le16((u16)data->nrg_th_ofdm);
  862. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
  863. __constant_cpu_to_le16(190);
  864. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
  865. __constant_cpu_to_le16(390);
  866. cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
  867. __constant_cpu_to_le16(62);
  868. IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
  869. data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
  870. data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
  871. data->nrg_th_ofdm);
  872. IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
  873. data->auto_corr_cck, data->auto_corr_cck_mrc,
  874. data->nrg_th_cck);
  875. cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
  876. if (flags & CMD_ASYNC)
  877. cmd_out.meta.u.callback = iwl_sensitivity_callback;
  878. /* Don't send command to uCode if nothing has changed */
  879. if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
  880. sizeof(u16)*HD_TABLE_SIZE)) {
  881. IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
  882. return 0;
  883. }
  884. /* Copy table for comparison next time */
  885. memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
  886. sizeof(u16)*HD_TABLE_SIZE);
  887. rc = iwl_send_cmd(priv, &cmd_out);
  888. if (!rc) {
  889. IWL_DEBUG_CALIB("SENSITIVITY_CMD succeeded\n");
  890. return rc;
  891. }
  892. return 0;
  893. }
  894. void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, u8 force)
  895. {
  896. int rc = 0;
  897. int i;
  898. struct iwl_sensitivity_data *data = NULL;
  899. IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
  900. if (force)
  901. memset(&(priv->sensitivity_tbl[0]), 0,
  902. sizeof(u16)*HD_TABLE_SIZE);
  903. /* Clear driver's sensitivity algo data */
  904. data = &(priv->sensitivity_data);
  905. memset(data, 0, sizeof(struct iwl_sensitivity_data));
  906. data->num_in_cck_no_fa = 0;
  907. data->nrg_curr_state = IWL_FA_TOO_MANY;
  908. data->nrg_prev_state = IWL_FA_TOO_MANY;
  909. data->nrg_silence_ref = 0;
  910. data->nrg_silence_idx = 0;
  911. data->nrg_energy_idx = 0;
  912. for (i = 0; i < 10; i++)
  913. data->nrg_value[i] = 0;
  914. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
  915. data->nrg_silence_rssi[i] = 0;
  916. data->auto_corr_ofdm = 90;
  917. data->auto_corr_ofdm_mrc = 170;
  918. data->auto_corr_ofdm_x1 = 105;
  919. data->auto_corr_ofdm_mrc_x1 = 220;
  920. data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
  921. data->auto_corr_cck_mrc = 200;
  922. data->nrg_th_cck = 100;
  923. data->nrg_th_ofdm = 100;
  924. data->last_bad_plcp_cnt_ofdm = 0;
  925. data->last_fa_cnt_ofdm = 0;
  926. data->last_bad_plcp_cnt_cck = 0;
  927. data->last_fa_cnt_cck = 0;
  928. /* Clear prior Sensitivity command data to force send to uCode */
  929. if (force)
  930. memset(&(priv->sensitivity_tbl[0]), 0,
  931. sizeof(u16)*HD_TABLE_SIZE);
  932. rc |= iwl4965_sensitivity_write(priv, flags);
  933. IWL_DEBUG_CALIB("<<return 0x%X\n", rc);
  934. return;
  935. }
  936. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  937. * Called after every association, but this runs only once!
  938. * ... once chain noise is calibrated the first time, it's good forever. */
  939. void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  940. {
  941. struct iwl_chain_noise_data *data = NULL;
  942. int rc = 0;
  943. data = &(priv->chain_noise_data);
  944. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  945. struct iwl_calibration_cmd cmd;
  946. memset(&cmd, 0, sizeof(cmd));
  947. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  948. cmd.diff_gain_a = 0;
  949. cmd.diff_gain_b = 0;
  950. cmd.diff_gain_c = 0;
  951. rc = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  952. sizeof(cmd), &cmd);
  953. msleep(4);
  954. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  955. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  956. }
  957. return;
  958. }
  959. /*
  960. * Accumulate 20 beacons of signal and noise statistics for each of
  961. * 3 receivers/antennas/rx-chains, then figure out:
  962. * 1) Which antennas are connected.
  963. * 2) Differential rx gain settings to balance the 3 receivers.
  964. */
  965. static void iwl4965_noise_calibration(struct iwl_priv *priv,
  966. struct iwl_notif_statistics *stat_resp)
  967. {
  968. struct iwl_chain_noise_data *data = NULL;
  969. int rc = 0;
  970. u32 chain_noise_a;
  971. u32 chain_noise_b;
  972. u32 chain_noise_c;
  973. u32 chain_sig_a;
  974. u32 chain_sig_b;
  975. u32 chain_sig_c;
  976. u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  977. u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  978. u32 max_average_sig;
  979. u16 max_average_sig_antenna_i;
  980. u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
  981. u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
  982. u16 i = 0;
  983. u16 chan_num = INITIALIZATION_VALUE;
  984. u32 band = INITIALIZATION_VALUE;
  985. u32 active_chains = 0;
  986. unsigned long flags;
  987. struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
  988. data = &(priv->chain_noise_data);
  989. /* Accumulate just the first 20 beacons after the first association,
  990. * then we're done forever. */
  991. if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
  992. if (data->state == IWL_CHAIN_NOISE_ALIVE)
  993. IWL_DEBUG_CALIB("Wait for noise calib reset\n");
  994. return;
  995. }
  996. spin_lock_irqsave(&priv->lock, flags);
  997. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  998. IWL_DEBUG_CALIB(" << Interference data unavailable\n");
  999. spin_unlock_irqrestore(&priv->lock, flags);
  1000. return;
  1001. }
  1002. band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
  1003. chan_num = le16_to_cpu(priv->staging_rxon.channel);
  1004. /* Make sure we accumulate data for just the associated channel
  1005. * (even if scanning). */
  1006. if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
  1007. ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
  1008. (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
  1009. IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
  1010. chan_num, band);
  1011. spin_unlock_irqrestore(&priv->lock, flags);
  1012. return;
  1013. }
  1014. /* Accumulate beacon statistics values across 20 beacons */
  1015. chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
  1016. IN_BAND_FILTER;
  1017. chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
  1018. IN_BAND_FILTER;
  1019. chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
  1020. IN_BAND_FILTER;
  1021. chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
  1022. chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
  1023. chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
  1024. spin_unlock_irqrestore(&priv->lock, flags);
  1025. data->beacon_count++;
  1026. data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
  1027. data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
  1028. data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
  1029. data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
  1030. data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
  1031. data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
  1032. IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
  1033. data->beacon_count);
  1034. IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
  1035. chain_sig_a, chain_sig_b, chain_sig_c);
  1036. IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
  1037. chain_noise_a, chain_noise_b, chain_noise_c);
  1038. /* If this is the 20th beacon, determine:
  1039. * 1) Disconnected antennas (using signal strengths)
  1040. * 2) Differential gain (using silence noise) to balance receivers */
  1041. if (data->beacon_count == CAL_NUM_OF_BEACONS) {
  1042. /* Analyze signal for disconnected antenna */
  1043. average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
  1044. average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
  1045. average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
  1046. if (average_sig[0] >= average_sig[1]) {
  1047. max_average_sig = average_sig[0];
  1048. max_average_sig_antenna_i = 0;
  1049. active_chains = (1 << max_average_sig_antenna_i);
  1050. } else {
  1051. max_average_sig = average_sig[1];
  1052. max_average_sig_antenna_i = 1;
  1053. active_chains = (1 << max_average_sig_antenna_i);
  1054. }
  1055. if (average_sig[2] >= max_average_sig) {
  1056. max_average_sig = average_sig[2];
  1057. max_average_sig_antenna_i = 2;
  1058. active_chains = (1 << max_average_sig_antenna_i);
  1059. }
  1060. IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
  1061. average_sig[0], average_sig[1], average_sig[2]);
  1062. IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
  1063. max_average_sig, max_average_sig_antenna_i);
  1064. /* Compare signal strengths for all 3 receivers. */
  1065. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1066. if (i != max_average_sig_antenna_i) {
  1067. s32 rssi_delta = (max_average_sig -
  1068. average_sig[i]);
  1069. /* If signal is very weak, compared with
  1070. * strongest, mark it as disconnected. */
  1071. if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
  1072. data->disconn_array[i] = 1;
  1073. else
  1074. active_chains |= (1 << i);
  1075. IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
  1076. "disconn_array[i] = %d\n",
  1077. i, rssi_delta, data->disconn_array[i]);
  1078. }
  1079. }
  1080. /*If both chains A & B are disconnected -
  1081. * connect B and leave A as is */
  1082. if (data->disconn_array[CHAIN_A] &&
  1083. data->disconn_array[CHAIN_B]) {
  1084. data->disconn_array[CHAIN_B] = 0;
  1085. active_chains |= (1 << CHAIN_B);
  1086. IWL_DEBUG_CALIB("both A & B chains are disconnected! "
  1087. "W/A - declare B as connected\n");
  1088. }
  1089. IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
  1090. active_chains);
  1091. /* Save for use within RXON, TX, SCAN commands, etc. */
  1092. priv->valid_antenna = active_chains;
  1093. /* Analyze noise for rx balance */
  1094. average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
  1095. average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
  1096. average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
  1097. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1098. if (!(data->disconn_array[i]) &&
  1099. (average_noise[i] <= min_average_noise)) {
  1100. /* This means that chain i is active and has
  1101. * lower noise values so far: */
  1102. min_average_noise = average_noise[i];
  1103. min_average_noise_antenna_i = i;
  1104. }
  1105. }
  1106. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  1107. IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
  1108. average_noise[0], average_noise[1],
  1109. average_noise[2]);
  1110. IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
  1111. min_average_noise, min_average_noise_antenna_i);
  1112. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1113. s32 delta_g = 0;
  1114. if (!(data->disconn_array[i]) &&
  1115. (data->delta_gain_code[i] ==
  1116. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  1117. delta_g = average_noise[i] - min_average_noise;
  1118. data->delta_gain_code[i] = (u8)((delta_g *
  1119. 10) / 15);
  1120. if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
  1121. data->delta_gain_code[i])
  1122. data->delta_gain_code[i] =
  1123. CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
  1124. data->delta_gain_code[i] =
  1125. (data->delta_gain_code[i] | (1 << 2));
  1126. } else
  1127. data->delta_gain_code[i] = 0;
  1128. }
  1129. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  1130. data->delta_gain_code[0],
  1131. data->delta_gain_code[1],
  1132. data->delta_gain_code[2]);
  1133. /* Differential gain gets sent to uCode only once */
  1134. if (!data->radio_write) {
  1135. struct iwl_calibration_cmd cmd;
  1136. data->radio_write = 1;
  1137. memset(&cmd, 0, sizeof(cmd));
  1138. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  1139. cmd.diff_gain_a = data->delta_gain_code[0];
  1140. cmd.diff_gain_b = data->delta_gain_code[1];
  1141. cmd.diff_gain_c = data->delta_gain_code[2];
  1142. rc = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  1143. sizeof(cmd), &cmd);
  1144. if (rc)
  1145. IWL_DEBUG_CALIB("fail sending cmd "
  1146. "REPLY_PHY_CALIBRATION_CMD \n");
  1147. /* TODO we might want recalculate
  1148. * rx_chain in rxon cmd */
  1149. /* Mark so we run this algo only once! */
  1150. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  1151. }
  1152. data->chain_noise_a = 0;
  1153. data->chain_noise_b = 0;
  1154. data->chain_noise_c = 0;
  1155. data->chain_signal_a = 0;
  1156. data->chain_signal_b = 0;
  1157. data->chain_signal_c = 0;
  1158. data->beacon_count = 0;
  1159. }
  1160. return;
  1161. }
  1162. static void iwl4965_sensitivity_calibration(struct iwl_priv *priv,
  1163. struct iwl_notif_statistics *resp)
  1164. {
  1165. int rc = 0;
  1166. u32 rx_enable_time;
  1167. u32 fa_cck;
  1168. u32 fa_ofdm;
  1169. u32 bad_plcp_cck;
  1170. u32 bad_plcp_ofdm;
  1171. u32 norm_fa_ofdm;
  1172. u32 norm_fa_cck;
  1173. struct iwl_sensitivity_data *data = NULL;
  1174. struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
  1175. struct statistics_rx *statistics = &(resp->rx);
  1176. unsigned long flags;
  1177. struct statistics_general_data statis;
  1178. data = &(priv->sensitivity_data);
  1179. if (!iwl_is_associated(priv)) {
  1180. IWL_DEBUG_CALIB("<< - not associated\n");
  1181. return;
  1182. }
  1183. spin_lock_irqsave(&priv->lock, flags);
  1184. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  1185. IWL_DEBUG_CALIB("<< invalid data.\n");
  1186. spin_unlock_irqrestore(&priv->lock, flags);
  1187. return;
  1188. }
  1189. /* Extract Statistics: */
  1190. rx_enable_time = le32_to_cpu(rx_info->channel_load);
  1191. fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
  1192. fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
  1193. bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
  1194. bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
  1195. statis.beacon_silence_rssi_a =
  1196. le32_to_cpu(statistics->general.beacon_silence_rssi_a);
  1197. statis.beacon_silence_rssi_b =
  1198. le32_to_cpu(statistics->general.beacon_silence_rssi_b);
  1199. statis.beacon_silence_rssi_c =
  1200. le32_to_cpu(statistics->general.beacon_silence_rssi_c);
  1201. statis.beacon_energy_a =
  1202. le32_to_cpu(statistics->general.beacon_energy_a);
  1203. statis.beacon_energy_b =
  1204. le32_to_cpu(statistics->general.beacon_energy_b);
  1205. statis.beacon_energy_c =
  1206. le32_to_cpu(statistics->general.beacon_energy_c);
  1207. spin_unlock_irqrestore(&priv->lock, flags);
  1208. IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
  1209. if (!rx_enable_time) {
  1210. IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
  1211. return;
  1212. }
  1213. /* These statistics increase monotonically, and do not reset
  1214. * at each beacon. Calculate difference from last value, or just
  1215. * use the new statistics value if it has reset or wrapped around. */
  1216. if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
  1217. data->last_bad_plcp_cnt_cck = bad_plcp_cck;
  1218. else {
  1219. bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
  1220. data->last_bad_plcp_cnt_cck += bad_plcp_cck;
  1221. }
  1222. if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
  1223. data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
  1224. else {
  1225. bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
  1226. data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
  1227. }
  1228. if (data->last_fa_cnt_ofdm > fa_ofdm)
  1229. data->last_fa_cnt_ofdm = fa_ofdm;
  1230. else {
  1231. fa_ofdm -= data->last_fa_cnt_ofdm;
  1232. data->last_fa_cnt_ofdm += fa_ofdm;
  1233. }
  1234. if (data->last_fa_cnt_cck > fa_cck)
  1235. data->last_fa_cnt_cck = fa_cck;
  1236. else {
  1237. fa_cck -= data->last_fa_cnt_cck;
  1238. data->last_fa_cnt_cck += fa_cck;
  1239. }
  1240. /* Total aborted signal locks */
  1241. norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
  1242. norm_fa_cck = fa_cck + bad_plcp_cck;
  1243. IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
  1244. bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
  1245. iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
  1246. iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
  1247. rc |= iwl4965_sensitivity_write(priv, CMD_ASYNC);
  1248. return;
  1249. }
  1250. static void iwl4965_bg_sensitivity_work(struct work_struct *work)
  1251. {
  1252. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1253. sensitivity_work);
  1254. mutex_lock(&priv->mutex);
  1255. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1256. test_bit(STATUS_SCANNING, &priv->status)) {
  1257. mutex_unlock(&priv->mutex);
  1258. return;
  1259. }
  1260. if (priv->start_calib) {
  1261. iwl4965_noise_calibration(priv, &priv->statistics);
  1262. if (priv->sensitivity_data.state ==
  1263. IWL_SENS_CALIB_NEED_REINIT) {
  1264. iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
  1265. priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
  1266. } else
  1267. iwl4965_sensitivity_calibration(priv,
  1268. &priv->statistics);
  1269. }
  1270. mutex_unlock(&priv->mutex);
  1271. return;
  1272. }
  1273. #endif /*CONFIG_IWLWIFI_SENSITIVITY*/
  1274. static void iwl4965_bg_txpower_work(struct work_struct *work)
  1275. {
  1276. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1277. txpower_work);
  1278. /* If a scan happened to start before we got here
  1279. * then just return; the statistics notification will
  1280. * kick off another scheduled work to compensate for
  1281. * any temperature delta we missed here. */
  1282. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1283. test_bit(STATUS_SCANNING, &priv->status))
  1284. return;
  1285. mutex_lock(&priv->mutex);
  1286. /* Regardless of if we are assocaited, we must reconfigure the
  1287. * TX power since frames can be sent on non-radar channels while
  1288. * not associated */
  1289. iwl_hw_reg_send_txpower(priv);
  1290. /* Update last_temperature to keep is_calib_needed from running
  1291. * when it isn't needed... */
  1292. priv->last_temperature = priv->temperature;
  1293. mutex_unlock(&priv->mutex);
  1294. }
  1295. /*
  1296. * Acquire priv->lock before calling this function !
  1297. */
  1298. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  1299. {
  1300. iwl_write_restricted(priv, HBUS_TARG_WRPTR,
  1301. (index & 0xff) | (txq_id << 8));
  1302. iwl_write_restricted_reg(priv, SCD_QUEUE_RDPTR(txq_id), index);
  1303. }
  1304. /*
  1305. * Acquire priv->lock before calling this function !
  1306. */
  1307. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  1308. struct iwl_tx_queue *txq,
  1309. int tx_fifo_id, int scd_retry)
  1310. {
  1311. int txq_id = txq->q.id;
  1312. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  1313. iwl_write_restricted_reg(priv, SCD_QUEUE_STATUS_BITS(txq_id),
  1314. (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  1315. (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
  1316. (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
  1317. (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  1318. SCD_QUEUE_STTS_REG_MSK);
  1319. txq->sched_retry = scd_retry;
  1320. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  1321. active ? "Activete" : "Deactivate",
  1322. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  1323. }
  1324. static const u16 default_queue_to_tx_fifo[] = {
  1325. IWL_TX_FIFO_AC3,
  1326. IWL_TX_FIFO_AC2,
  1327. IWL_TX_FIFO_AC1,
  1328. IWL_TX_FIFO_AC0,
  1329. IWL_CMD_FIFO_NUM,
  1330. IWL_TX_FIFO_HCCA_1,
  1331. IWL_TX_FIFO_HCCA_2
  1332. };
  1333. static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
  1334. {
  1335. set_bit(txq_id, &priv->txq_ctx_active_msk);
  1336. }
  1337. static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
  1338. {
  1339. clear_bit(txq_id, &priv->txq_ctx_active_msk);
  1340. }
  1341. int iwl4965_alive_notify(struct iwl_priv *priv)
  1342. {
  1343. u32 a;
  1344. int i = 0;
  1345. unsigned long flags;
  1346. int rc;
  1347. spin_lock_irqsave(&priv->lock, flags);
  1348. #ifdef CONFIG_IWLWIFI_SENSITIVITY
  1349. memset(&(priv->sensitivity_data), 0,
  1350. sizeof(struct iwl_sensitivity_data));
  1351. memset(&(priv->chain_noise_data), 0,
  1352. sizeof(struct iwl_chain_noise_data));
  1353. for (i = 0; i < NUM_RX_CHAINS; i++)
  1354. priv->chain_noise_data.delta_gain_code[i] =
  1355. CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
  1356. #endif /* CONFIG_IWLWIFI_SENSITIVITY*/
  1357. rc = iwl_grab_restricted_access(priv);
  1358. if (rc) {
  1359. spin_unlock_irqrestore(&priv->lock, flags);
  1360. return rc;
  1361. }
  1362. priv->scd_base_addr = iwl_read_restricted_reg(priv, SCD_SRAM_BASE_ADDR);
  1363. a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
  1364. for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  1365. iwl_write_restricted_mem(priv, a, 0);
  1366. for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
  1367. iwl_write_restricted_mem(priv, a, 0);
  1368. for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
  1369. iwl_write_restricted_mem(priv, a, 0);
  1370. iwl_write_restricted_reg(priv, SCD_DRAM_BASE_ADDR,
  1371. (priv->hw_setting.shared_phys +
  1372. offsetof(struct iwl_shared, queues_byte_cnt_tbls)) >> 10);
  1373. iwl_write_restricted_reg(priv, SCD_QUEUECHAIN_SEL, 0);
  1374. /* initiate the queues */
  1375. for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
  1376. iwl_write_restricted_reg(priv, SCD_QUEUE_RDPTR(i), 0);
  1377. iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  1378. iwl_write_restricted_mem(priv, priv->scd_base_addr +
  1379. SCD_CONTEXT_QUEUE_OFFSET(i),
  1380. (SCD_WIN_SIZE <<
  1381. SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  1382. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  1383. iwl_write_restricted_mem(priv, priv->scd_base_addr +
  1384. SCD_CONTEXT_QUEUE_OFFSET(i) +
  1385. sizeof(u32),
  1386. (SCD_FRAME_LIMIT <<
  1387. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  1388. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  1389. }
  1390. iwl_write_restricted_reg(priv, SCD_INTERRUPT_MASK,
  1391. (1 << priv->hw_setting.max_txq_num) - 1);
  1392. iwl_write_restricted_reg(priv, SCD_TXFACT,
  1393. SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
  1394. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  1395. /* map qos queues to fifos one-to-one */
  1396. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  1397. int ac = default_queue_to_tx_fifo[i];
  1398. iwl4965_txq_ctx_activate(priv, i);
  1399. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  1400. }
  1401. iwl_release_restricted_access(priv);
  1402. spin_unlock_irqrestore(&priv->lock, flags);
  1403. return 0;
  1404. }
  1405. int iwl_hw_set_hw_setting(struct iwl_priv *priv)
  1406. {
  1407. priv->hw_setting.shared_virt =
  1408. pci_alloc_consistent(priv->pci_dev,
  1409. sizeof(struct iwl_shared),
  1410. &priv->hw_setting.shared_phys);
  1411. if (!priv->hw_setting.shared_virt)
  1412. return -1;
  1413. memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl_shared));
  1414. priv->hw_setting.max_txq_num = iwl_param_queues_num;
  1415. priv->hw_setting.ac_queue_count = AC_NUM;
  1416. priv->hw_setting.cck_flag = RATE_MCS_CCK_MSK;
  1417. priv->hw_setting.tx_cmd_len = sizeof(struct iwl_tx_cmd);
  1418. priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
  1419. priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1420. priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
  1421. priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
  1422. return 0;
  1423. }
  1424. /**
  1425. * iwl_hw_txq_ctx_free - Free TXQ Context
  1426. *
  1427. * Destroy all TX DMA queues and structures
  1428. */
  1429. void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
  1430. {
  1431. int txq_id;
  1432. /* Tx queues */
  1433. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  1434. iwl_tx_queue_free(priv, &priv->txq[txq_id]);
  1435. iwl4965_kw_free(priv);
  1436. }
  1437. /**
  1438. * iwl_hw_txq_free_tfd - Free one TFD, those at index [txq->q.last_used]
  1439. *
  1440. * Does NOT advance any indexes
  1441. */
  1442. int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  1443. {
  1444. struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
  1445. struct iwl_tfd_frame *bd = &bd_tmp[txq->q.last_used];
  1446. struct pci_dev *dev = priv->pci_dev;
  1447. int i;
  1448. int counter = 0;
  1449. int index, is_odd;
  1450. /* classify bd */
  1451. if (txq->q.id == IWL_CMD_QUEUE_NUM)
  1452. /* nothing to cleanup after for host commands */
  1453. return 0;
  1454. /* sanity check */
  1455. counter = IWL_GET_BITS(*bd, num_tbs);
  1456. if (counter > MAX_NUM_OF_TBS) {
  1457. IWL_ERROR("Too many chunks: %i\n", counter);
  1458. /* @todo issue fatal error, it is quite serious situation */
  1459. return 0;
  1460. }
  1461. /* unmap chunks if any */
  1462. for (i = 0; i < counter; i++) {
  1463. index = i / 2;
  1464. is_odd = i & 0x1;
  1465. if (is_odd)
  1466. pci_unmap_single(
  1467. dev,
  1468. IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
  1469. (IWL_GET_BITS(bd->pa[index],
  1470. tb2_addr_hi20) << 16),
  1471. IWL_GET_BITS(bd->pa[index], tb2_len),
  1472. PCI_DMA_TODEVICE);
  1473. else if (i > 0)
  1474. pci_unmap_single(dev,
  1475. le32_to_cpu(bd->pa[index].tb1_addr),
  1476. IWL_GET_BITS(bd->pa[index], tb1_len),
  1477. PCI_DMA_TODEVICE);
  1478. if (txq->txb[txq->q.last_used].skb[i]) {
  1479. struct sk_buff *skb = txq->txb[txq->q.last_used].skb[i];
  1480. dev_kfree_skb(skb);
  1481. txq->txb[txq->q.last_used].skb[i] = NULL;
  1482. }
  1483. }
  1484. return 0;
  1485. }
  1486. int iwl_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
  1487. {
  1488. IWL_ERROR("TODO: Implement iwl_hw_reg_set_txpower!\n");
  1489. return -EINVAL;
  1490. }
  1491. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  1492. {
  1493. s32 sign = 1;
  1494. if (num < 0) {
  1495. sign = -sign;
  1496. num = -num;
  1497. }
  1498. if (denom < 0) {
  1499. sign = -sign;
  1500. denom = -denom;
  1501. }
  1502. *res = 1;
  1503. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  1504. return 1;
  1505. }
  1506. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  1507. s32 current_voltage)
  1508. {
  1509. s32 comp = 0;
  1510. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  1511. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  1512. return 0;
  1513. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  1514. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  1515. if (current_voltage > eeprom_voltage)
  1516. comp *= 2;
  1517. if ((comp < -2) || (comp > 2))
  1518. comp = 0;
  1519. return comp;
  1520. }
  1521. static const struct iwl_channel_info *
  1522. iwl4965_get_channel_txpower_info(struct iwl_priv *priv, u8 phymode, u16 channel)
  1523. {
  1524. const struct iwl_channel_info *ch_info;
  1525. ch_info = iwl_get_channel_info(priv, phymode, channel);
  1526. if (!is_channel_valid(ch_info))
  1527. return NULL;
  1528. return ch_info;
  1529. }
  1530. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  1531. {
  1532. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  1533. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  1534. return CALIB_CH_GROUP_5;
  1535. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  1536. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  1537. return CALIB_CH_GROUP_1;
  1538. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  1539. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  1540. return CALIB_CH_GROUP_2;
  1541. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  1542. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  1543. return CALIB_CH_GROUP_3;
  1544. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  1545. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  1546. return CALIB_CH_GROUP_4;
  1547. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  1548. return -1;
  1549. }
  1550. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  1551. {
  1552. s32 b = -1;
  1553. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  1554. if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
  1555. continue;
  1556. if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
  1557. && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
  1558. break;
  1559. }
  1560. return b;
  1561. }
  1562. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  1563. {
  1564. s32 val;
  1565. if (x2 == x1)
  1566. return y1;
  1567. else {
  1568. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  1569. return val + y2;
  1570. }
  1571. }
  1572. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  1573. struct iwl_eeprom_calib_ch_info *chan_info)
  1574. {
  1575. s32 s = -1;
  1576. u32 c;
  1577. u32 m;
  1578. const struct iwl_eeprom_calib_measure *m1;
  1579. const struct iwl_eeprom_calib_measure *m2;
  1580. struct iwl_eeprom_calib_measure *omeas;
  1581. u32 ch_i1;
  1582. u32 ch_i2;
  1583. s = iwl4965_get_sub_band(priv, channel);
  1584. if (s >= EEPROM_TX_POWER_BANDS) {
  1585. IWL_ERROR("Tx Power can not find channel %d ", channel);
  1586. return -1;
  1587. }
  1588. ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
  1589. ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
  1590. chan_info->ch_num = (u8) channel;
  1591. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  1592. channel, s, ch_i1, ch_i2);
  1593. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  1594. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  1595. m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
  1596. measurements[c][m]);
  1597. m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
  1598. measurements[c][m]);
  1599. omeas = &(chan_info->measurements[c][m]);
  1600. omeas->actual_pow =
  1601. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1602. m1->actual_pow,
  1603. ch_i2,
  1604. m2->actual_pow);
  1605. omeas->gain_idx =
  1606. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1607. m1->gain_idx, ch_i2,
  1608. m2->gain_idx);
  1609. omeas->temperature =
  1610. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1611. m1->temperature,
  1612. ch_i2,
  1613. m2->temperature);
  1614. omeas->pa_det =
  1615. (s8) iwl4965_interpolate_value(channel, ch_i1,
  1616. m1->pa_det, ch_i2,
  1617. m2->pa_det);
  1618. IWL_DEBUG_TXPOWER
  1619. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  1620. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  1621. IWL_DEBUG_TXPOWER
  1622. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  1623. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  1624. IWL_DEBUG_TXPOWER
  1625. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  1626. m1->pa_det, m2->pa_det, omeas->pa_det);
  1627. IWL_DEBUG_TXPOWER
  1628. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  1629. m1->temperature, m2->temperature,
  1630. omeas->temperature);
  1631. }
  1632. }
  1633. return 0;
  1634. }
  1635. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  1636. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  1637. static s32 back_off_table[] = {
  1638. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  1639. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  1640. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  1641. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  1642. 10 /* CCK */
  1643. };
  1644. /* Thermal compensation values for txpower for various frequency ranges ...
  1645. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  1646. static struct iwl_txpower_comp_entry {
  1647. s32 degrees_per_05db_a;
  1648. s32 degrees_per_05db_a_denom;
  1649. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  1650. {9, 2}, /* group 0 5.2, ch 34-43 */
  1651. {4, 1}, /* group 1 5.2, ch 44-70 */
  1652. {4, 1}, /* group 2 5.2, ch 71-124 */
  1653. {4, 1}, /* group 3 5.2, ch 125-200 */
  1654. {3, 1} /* group 4 2.4, ch all */
  1655. };
  1656. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  1657. {
  1658. if (!band) {
  1659. if ((rate_power_index & 7) <= 4)
  1660. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  1661. }
  1662. return MIN_TX_GAIN_INDEX;
  1663. }
  1664. struct gain_entry {
  1665. u8 dsp;
  1666. u8 radio;
  1667. };
  1668. static const struct gain_entry gain_table[2][108] = {
  1669. /* 5.2GHz power gain index table */
  1670. {
  1671. {123, 0x3F}, /* highest txpower */
  1672. {117, 0x3F},
  1673. {110, 0x3F},
  1674. {104, 0x3F},
  1675. {98, 0x3F},
  1676. {110, 0x3E},
  1677. {104, 0x3E},
  1678. {98, 0x3E},
  1679. {110, 0x3D},
  1680. {104, 0x3D},
  1681. {98, 0x3D},
  1682. {110, 0x3C},
  1683. {104, 0x3C},
  1684. {98, 0x3C},
  1685. {110, 0x3B},
  1686. {104, 0x3B},
  1687. {98, 0x3B},
  1688. {110, 0x3A},
  1689. {104, 0x3A},
  1690. {98, 0x3A},
  1691. {110, 0x39},
  1692. {104, 0x39},
  1693. {98, 0x39},
  1694. {110, 0x38},
  1695. {104, 0x38},
  1696. {98, 0x38},
  1697. {110, 0x37},
  1698. {104, 0x37},
  1699. {98, 0x37},
  1700. {110, 0x36},
  1701. {104, 0x36},
  1702. {98, 0x36},
  1703. {110, 0x35},
  1704. {104, 0x35},
  1705. {98, 0x35},
  1706. {110, 0x34},
  1707. {104, 0x34},
  1708. {98, 0x34},
  1709. {110, 0x33},
  1710. {104, 0x33},
  1711. {98, 0x33},
  1712. {110, 0x32},
  1713. {104, 0x32},
  1714. {98, 0x32},
  1715. {110, 0x31},
  1716. {104, 0x31},
  1717. {98, 0x31},
  1718. {110, 0x30},
  1719. {104, 0x30},
  1720. {98, 0x30},
  1721. {110, 0x25},
  1722. {104, 0x25},
  1723. {98, 0x25},
  1724. {110, 0x24},
  1725. {104, 0x24},
  1726. {98, 0x24},
  1727. {110, 0x23},
  1728. {104, 0x23},
  1729. {98, 0x23},
  1730. {110, 0x22},
  1731. {104, 0x18},
  1732. {98, 0x18},
  1733. {110, 0x17},
  1734. {104, 0x17},
  1735. {98, 0x17},
  1736. {110, 0x16},
  1737. {104, 0x16},
  1738. {98, 0x16},
  1739. {110, 0x15},
  1740. {104, 0x15},
  1741. {98, 0x15},
  1742. {110, 0x14},
  1743. {104, 0x14},
  1744. {98, 0x14},
  1745. {110, 0x13},
  1746. {104, 0x13},
  1747. {98, 0x13},
  1748. {110, 0x12},
  1749. {104, 0x08},
  1750. {98, 0x08},
  1751. {110, 0x07},
  1752. {104, 0x07},
  1753. {98, 0x07},
  1754. {110, 0x06},
  1755. {104, 0x06},
  1756. {98, 0x06},
  1757. {110, 0x05},
  1758. {104, 0x05},
  1759. {98, 0x05},
  1760. {110, 0x04},
  1761. {104, 0x04},
  1762. {98, 0x04},
  1763. {110, 0x03},
  1764. {104, 0x03},
  1765. {98, 0x03},
  1766. {110, 0x02},
  1767. {104, 0x02},
  1768. {98, 0x02},
  1769. {110, 0x01},
  1770. {104, 0x01},
  1771. {98, 0x01},
  1772. {110, 0x00},
  1773. {104, 0x00},
  1774. {98, 0x00},
  1775. {93, 0x00},
  1776. {88, 0x00},
  1777. {83, 0x00},
  1778. {78, 0x00},
  1779. },
  1780. /* 2.4GHz power gain index table */
  1781. {
  1782. {110, 0x3f}, /* highest txpower */
  1783. {104, 0x3f},
  1784. {98, 0x3f},
  1785. {110, 0x3e},
  1786. {104, 0x3e},
  1787. {98, 0x3e},
  1788. {110, 0x3d},
  1789. {104, 0x3d},
  1790. {98, 0x3d},
  1791. {110, 0x3c},
  1792. {104, 0x3c},
  1793. {98, 0x3c},
  1794. {110, 0x3b},
  1795. {104, 0x3b},
  1796. {98, 0x3b},
  1797. {110, 0x3a},
  1798. {104, 0x3a},
  1799. {98, 0x3a},
  1800. {110, 0x39},
  1801. {104, 0x39},
  1802. {98, 0x39},
  1803. {110, 0x38},
  1804. {104, 0x38},
  1805. {98, 0x38},
  1806. {110, 0x37},
  1807. {104, 0x37},
  1808. {98, 0x37},
  1809. {110, 0x36},
  1810. {104, 0x36},
  1811. {98, 0x36},
  1812. {110, 0x35},
  1813. {104, 0x35},
  1814. {98, 0x35},
  1815. {110, 0x34},
  1816. {104, 0x34},
  1817. {98, 0x34},
  1818. {110, 0x33},
  1819. {104, 0x33},
  1820. {98, 0x33},
  1821. {110, 0x32},
  1822. {104, 0x32},
  1823. {98, 0x32},
  1824. {110, 0x31},
  1825. {104, 0x31},
  1826. {98, 0x31},
  1827. {110, 0x30},
  1828. {104, 0x30},
  1829. {98, 0x30},
  1830. {110, 0x6},
  1831. {104, 0x6},
  1832. {98, 0x6},
  1833. {110, 0x5},
  1834. {104, 0x5},
  1835. {98, 0x5},
  1836. {110, 0x4},
  1837. {104, 0x4},
  1838. {98, 0x4},
  1839. {110, 0x3},
  1840. {104, 0x3},
  1841. {98, 0x3},
  1842. {110, 0x2},
  1843. {104, 0x2},
  1844. {98, 0x2},
  1845. {110, 0x1},
  1846. {104, 0x1},
  1847. {98, 0x1},
  1848. {110, 0x0},
  1849. {104, 0x0},
  1850. {98, 0x0},
  1851. {97, 0},
  1852. {96, 0},
  1853. {95, 0},
  1854. {94, 0},
  1855. {93, 0},
  1856. {92, 0},
  1857. {91, 0},
  1858. {90, 0},
  1859. {89, 0},
  1860. {88, 0},
  1861. {87, 0},
  1862. {86, 0},
  1863. {85, 0},
  1864. {84, 0},
  1865. {83, 0},
  1866. {82, 0},
  1867. {81, 0},
  1868. {80, 0},
  1869. {79, 0},
  1870. {78, 0},
  1871. {77, 0},
  1872. {76, 0},
  1873. {75, 0},
  1874. {74, 0},
  1875. {73, 0},
  1876. {72, 0},
  1877. {71, 0},
  1878. {70, 0},
  1879. {69, 0},
  1880. {68, 0},
  1881. {67, 0},
  1882. {66, 0},
  1883. {65, 0},
  1884. {64, 0},
  1885. {63, 0},
  1886. {62, 0},
  1887. {61, 0},
  1888. {60, 0},
  1889. {59, 0},
  1890. }
  1891. };
  1892. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  1893. u8 is_fat, u8 ctrl_chan_high,
  1894. struct iwl_tx_power_db *tx_power_tbl)
  1895. {
  1896. u8 saturation_power;
  1897. s32 target_power;
  1898. s32 user_target_power;
  1899. s32 power_limit;
  1900. s32 current_temp;
  1901. s32 reg_limit;
  1902. s32 current_regulatory;
  1903. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  1904. int i;
  1905. int c;
  1906. const struct iwl_channel_info *ch_info = NULL;
  1907. struct iwl_eeprom_calib_ch_info ch_eeprom_info;
  1908. const struct iwl_eeprom_calib_measure *measurement;
  1909. s16 voltage;
  1910. s32 init_voltage;
  1911. s32 voltage_compensation;
  1912. s32 degrees_per_05db_num;
  1913. s32 degrees_per_05db_denom;
  1914. s32 factory_temp;
  1915. s32 temperature_comp[2];
  1916. s32 factory_gain_index[2];
  1917. s32 factory_actual_pwr[2];
  1918. s32 power_index;
  1919. /* Sanity check requested level (dBm) */
  1920. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  1921. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  1922. priv->user_txpower_limit);
  1923. return -EINVAL;
  1924. }
  1925. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  1926. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  1927. priv->user_txpower_limit);
  1928. return -EINVAL;
  1929. }
  1930. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  1931. * are used for indexing into txpower table) */
  1932. user_target_power = 2 * priv->user_txpower_limit;
  1933. /* Get current (RXON) channel, band, width */
  1934. ch_info =
  1935. iwl4965_get_channel_txpower_info(priv, priv->phymode, channel);
  1936. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  1937. is_fat);
  1938. if (!ch_info)
  1939. return -EINVAL;
  1940. /* get txatten group, used to select 1) thermal txpower adjustment
  1941. * and 2) mimo txpower balance between Tx chains. */
  1942. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  1943. if (txatten_grp < 0)
  1944. return -EINVAL;
  1945. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  1946. channel, txatten_grp);
  1947. if (is_fat) {
  1948. if (ctrl_chan_high)
  1949. channel -= 2;
  1950. else
  1951. channel += 2;
  1952. }
  1953. /* hardware txpower limits ...
  1954. * saturation (clipping distortion) txpowers are in half-dBm */
  1955. if (band)
  1956. saturation_power = priv->eeprom.calib_info.saturation_power24;
  1957. else
  1958. saturation_power = priv->eeprom.calib_info.saturation_power52;
  1959. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  1960. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  1961. if (band)
  1962. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  1963. else
  1964. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  1965. }
  1966. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  1967. * max_power_avg values are in dBm, convert * 2 */
  1968. if (is_fat)
  1969. reg_limit = ch_info->fat_max_power_avg * 2;
  1970. else
  1971. reg_limit = ch_info->max_power_avg * 2;
  1972. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  1973. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  1974. if (band)
  1975. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  1976. else
  1977. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  1978. }
  1979. /* Interpolate txpower calibration values for this channel,
  1980. * based on factory calibration tests on spaced channels. */
  1981. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  1982. /* calculate tx gain adjustment based on power supply voltage */
  1983. voltage = priv->eeprom.calib_info.voltage;
  1984. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  1985. voltage_compensation =
  1986. iwl4965_get_voltage_compensation(voltage, init_voltage);
  1987. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  1988. init_voltage,
  1989. voltage, voltage_compensation);
  1990. /* get current temperature (Celsius) */
  1991. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  1992. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  1993. current_temp = KELVIN_TO_CELSIUS(current_temp);
  1994. /* select thermal txpower adjustment params, based on channel group
  1995. * (same frequency group used for mimo txatten adjustment) */
  1996. degrees_per_05db_num =
  1997. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  1998. degrees_per_05db_denom =
  1999. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  2000. /* get per-chain txpower values from factory measurements */
  2001. for (c = 0; c < 2; c++) {
  2002. measurement = &ch_eeprom_info.measurements[c][1];
  2003. /* txgain adjustment (in half-dB steps) based on difference
  2004. * between factory and current temperature */
  2005. factory_temp = measurement->temperature;
  2006. iwl4965_math_div_round((current_temp - factory_temp) *
  2007. degrees_per_05db_denom,
  2008. degrees_per_05db_num,
  2009. &temperature_comp[c]);
  2010. factory_gain_index[c] = measurement->gain_idx;
  2011. factory_actual_pwr[c] = measurement->actual_pow;
  2012. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  2013. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  2014. "curr tmp %d, comp %d steps\n",
  2015. factory_temp, current_temp,
  2016. temperature_comp[c]);
  2017. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  2018. factory_gain_index[c],
  2019. factory_actual_pwr[c]);
  2020. }
  2021. /* for each of 33 bit-rates (including 1 for CCK) */
  2022. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  2023. u8 is_mimo_rate;
  2024. union iwl_tx_power_dual_stream tx_power;
  2025. /* for mimo, reduce each chain's txpower by half
  2026. * (3dB, 6 steps), so total output power is regulatory
  2027. * compliant. */
  2028. if (i & 0x8) {
  2029. current_regulatory = reg_limit -
  2030. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  2031. is_mimo_rate = 1;
  2032. } else {
  2033. current_regulatory = reg_limit;
  2034. is_mimo_rate = 0;
  2035. }
  2036. /* find txpower limit, either hardware or regulatory */
  2037. power_limit = saturation_power - back_off_table[i];
  2038. if (power_limit > current_regulatory)
  2039. power_limit = current_regulatory;
  2040. /* reduce user's txpower request if necessary
  2041. * for this rate on this channel */
  2042. target_power = user_target_power;
  2043. if (target_power > power_limit)
  2044. target_power = power_limit;
  2045. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  2046. i, saturation_power - back_off_table[i],
  2047. current_regulatory, user_target_power,
  2048. target_power);
  2049. /* for each of 2 Tx chains (radio transmitters) */
  2050. for (c = 0; c < 2; c++) {
  2051. s32 atten_value;
  2052. if (is_mimo_rate)
  2053. atten_value =
  2054. (s32)le32_to_cpu(priv->card_alive_init.
  2055. tx_atten[txatten_grp][c]);
  2056. else
  2057. atten_value = 0;
  2058. /* calculate index; higher index means lower txpower */
  2059. power_index = (u8) (factory_gain_index[c] -
  2060. (target_power -
  2061. factory_actual_pwr[c]) -
  2062. temperature_comp[c] -
  2063. voltage_compensation +
  2064. atten_value);
  2065. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  2066. power_index); */
  2067. if (power_index < get_min_power_index(i, band))
  2068. power_index = get_min_power_index(i, band);
  2069. /* adjust 5 GHz index to support negative indexes */
  2070. if (!band)
  2071. power_index += 9;
  2072. /* CCK, rate 32, reduce txpower for CCK */
  2073. if (i == POWER_TABLE_CCK_ENTRY)
  2074. power_index +=
  2075. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  2076. /* stay within the table! */
  2077. if (power_index > 107) {
  2078. IWL_WARNING("txpower index %d > 107\n",
  2079. power_index);
  2080. power_index = 107;
  2081. }
  2082. if (power_index < 0) {
  2083. IWL_WARNING("txpower index %d < 0\n",
  2084. power_index);
  2085. power_index = 0;
  2086. }
  2087. /* fill txpower command for this rate/chain */
  2088. tx_power.s.radio_tx_gain[c] =
  2089. gain_table[band][power_index].radio;
  2090. tx_power.s.dsp_predis_atten[c] =
  2091. gain_table[band][power_index].dsp;
  2092. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  2093. "gain 0x%02x dsp %d\n",
  2094. c, atten_value, power_index,
  2095. tx_power.s.radio_tx_gain[c],
  2096. tx_power.s.dsp_predis_atten[c]);
  2097. }/* for each chain */
  2098. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  2099. }/* for each rate */
  2100. return 0;
  2101. }
  2102. /**
  2103. * iwl_hw_reg_send_txpower - Configure the TXPOWER level user limit
  2104. *
  2105. * Uses the active RXON for channel, band, and characteristics (fat, high)
  2106. * The power limit is taken from priv->user_txpower_limit.
  2107. */
  2108. int iwl_hw_reg_send_txpower(struct iwl_priv *priv)
  2109. {
  2110. struct iwl_txpowertable_cmd cmd = { 0 };
  2111. int rc = 0;
  2112. u8 band = 0;
  2113. u8 is_fat = 0;
  2114. u8 ctrl_chan_high = 0;
  2115. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2116. /* If this gets hit a lot, switch it to a BUG() and catch
  2117. * the stack trace to find out who is calling this during
  2118. * a scan. */
  2119. IWL_WARNING("TX Power requested while scanning!\n");
  2120. return -EAGAIN;
  2121. }
  2122. band = ((priv->phymode == MODE_IEEE80211B) ||
  2123. (priv->phymode == MODE_IEEE80211G));
  2124. is_fat = is_fat_channel(priv->active_rxon.flags);
  2125. if (is_fat &&
  2126. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2127. ctrl_chan_high = 1;
  2128. cmd.band = band;
  2129. cmd.channel = priv->active_rxon.channel;
  2130. rc = iwl4965_fill_txpower_tbl(priv, band,
  2131. le16_to_cpu(priv->active_rxon.channel),
  2132. is_fat, ctrl_chan_high, &cmd.tx_power);
  2133. if (rc)
  2134. return rc;
  2135. rc = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  2136. return rc;
  2137. }
  2138. int iwl_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  2139. {
  2140. int rc;
  2141. u8 band = 0;
  2142. u8 is_fat = 0;
  2143. u8 ctrl_chan_high = 0;
  2144. struct iwl_channel_switch_cmd cmd = { 0 };
  2145. const struct iwl_channel_info *ch_info;
  2146. band = ((priv->phymode == MODE_IEEE80211B) ||
  2147. (priv->phymode == MODE_IEEE80211G));
  2148. ch_info = iwl_get_channel_info(priv, priv->phymode, channel);
  2149. is_fat = is_fat_channel(priv->staging_rxon.flags);
  2150. if (is_fat &&
  2151. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2152. ctrl_chan_high = 1;
  2153. cmd.band = band;
  2154. cmd.expect_beacon = 0;
  2155. cmd.channel = cpu_to_le16(channel);
  2156. cmd.rxon_flags = priv->active_rxon.flags;
  2157. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  2158. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  2159. if (ch_info)
  2160. cmd.expect_beacon = is_channel_radar(ch_info);
  2161. else
  2162. cmd.expect_beacon = 1;
  2163. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  2164. ctrl_chan_high, &cmd.tx_power);
  2165. if (rc) {
  2166. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  2167. return rc;
  2168. }
  2169. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  2170. return rc;
  2171. }
  2172. #define RTS_HCCA_RETRY_LIMIT 3
  2173. #define RTS_DFAULT_RETRY_LIMIT 60
  2174. void iwl_hw_build_tx_cmd_rate(struct iwl_priv *priv,
  2175. struct iwl_cmd *cmd,
  2176. struct ieee80211_tx_control *ctrl,
  2177. struct ieee80211_hdr *hdr, int sta_id,
  2178. int is_hcca)
  2179. {
  2180. u8 rate;
  2181. u8 rts_retry_limit = 0;
  2182. u8 data_retry_limit = 0;
  2183. __le32 tx_flags;
  2184. u16 fc = le16_to_cpu(hdr->frame_control);
  2185. tx_flags = cmd->cmd.tx.tx_flags;
  2186. rate = iwl_rates[ctrl->tx_rate].plcp;
  2187. rts_retry_limit = (is_hcca) ?
  2188. RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
  2189. if (ieee80211_is_probe_response(fc)) {
  2190. data_retry_limit = 3;
  2191. if (data_retry_limit < rts_retry_limit)
  2192. rts_retry_limit = data_retry_limit;
  2193. } else
  2194. data_retry_limit = IWL_DEFAULT_TX_RETRY;
  2195. if (priv->data_retry_limit != -1)
  2196. data_retry_limit = priv->data_retry_limit;
  2197. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2198. switch (fc & IEEE80211_FCTL_STYPE) {
  2199. case IEEE80211_STYPE_AUTH:
  2200. case IEEE80211_STYPE_DEAUTH:
  2201. case IEEE80211_STYPE_ASSOC_REQ:
  2202. case IEEE80211_STYPE_REASSOC_REQ:
  2203. if (tx_flags & TX_CMD_FLG_RTS_MSK) {
  2204. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2205. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2206. }
  2207. break;
  2208. default:
  2209. break;
  2210. }
  2211. }
  2212. cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
  2213. cmd->cmd.tx.data_retry_limit = data_retry_limit;
  2214. cmd->cmd.tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, 0);
  2215. cmd->cmd.tx.tx_flags = tx_flags;
  2216. }
  2217. int iwl_hw_get_rx_read(struct iwl_priv *priv)
  2218. {
  2219. struct iwl_shared *shared_data = priv->hw_setting.shared_virt;
  2220. return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
  2221. }
  2222. int iwl_hw_get_temperature(struct iwl_priv *priv)
  2223. {
  2224. return priv->temperature;
  2225. }
  2226. unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  2227. struct iwl_frame *frame, u8 rate)
  2228. {
  2229. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  2230. unsigned int frame_size;
  2231. tx_beacon_cmd = &frame->u.beacon;
  2232. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  2233. tx_beacon_cmd->tx.sta_id = IWL4965_BROADCAST_ID;
  2234. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2235. frame_size = iwl_fill_beacon_frame(priv,
  2236. tx_beacon_cmd->frame,
  2237. BROADCAST_ADDR,
  2238. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  2239. BUG_ON(frame_size > MAX_MPDU_SIZE);
  2240. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  2241. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  2242. tx_beacon_cmd->tx.rate_n_flags =
  2243. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  2244. else
  2245. tx_beacon_cmd->tx.rate_n_flags =
  2246. iwl_hw_set_rate_n_flags(rate, 0);
  2247. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  2248. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  2249. return (sizeof(*tx_beacon_cmd) + frame_size);
  2250. }
  2251. int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  2252. {
  2253. int rc;
  2254. unsigned long flags;
  2255. int txq_id = txq->q.id;
  2256. spin_lock_irqsave(&priv->lock, flags);
  2257. rc = iwl_grab_restricted_access(priv);
  2258. if (rc) {
  2259. spin_unlock_irqrestore(&priv->lock, flags);
  2260. return rc;
  2261. }
  2262. iwl_write_restricted(priv, FH_MEM_CBBC_QUEUE(txq_id),
  2263. txq->q.dma_addr >> 8);
  2264. iwl_write_restricted(
  2265. priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
  2266. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  2267. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
  2268. iwl_release_restricted_access(priv);
  2269. spin_unlock_irqrestore(&priv->lock, flags);
  2270. return 0;
  2271. }
  2272. static inline u8 iwl4965_get_dma_hi_address(dma_addr_t addr)
  2273. {
  2274. return sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0;
  2275. }
  2276. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
  2277. dma_addr_t addr, u16 len)
  2278. {
  2279. int index, is_odd;
  2280. struct iwl_tfd_frame *tfd = ptr;
  2281. u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
  2282. if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
  2283. IWL_ERROR("Error can not send more than %d chunks\n",
  2284. MAX_NUM_OF_TBS);
  2285. return -EINVAL;
  2286. }
  2287. index = num_tbs / 2;
  2288. is_odd = num_tbs & 0x1;
  2289. if (!is_odd) {
  2290. tfd->pa[index].tb1_addr = cpu_to_le32(addr);
  2291. IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
  2292. iwl4965_get_dma_hi_address(addr));
  2293. IWL_SET_BITS(tfd->pa[index], tb1_len, len);
  2294. } else {
  2295. IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
  2296. (u32) (addr & 0xffff));
  2297. IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
  2298. IWL_SET_BITS(tfd->pa[index], tb2_len, len);
  2299. }
  2300. IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
  2301. return 0;
  2302. }
  2303. void iwl_hw_card_show_info(struct iwl_priv *priv)
  2304. {
  2305. u16 hw_version = priv->eeprom.board_revision_4965;
  2306. IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
  2307. ((hw_version >> 8) & 0x0F),
  2308. ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
  2309. IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
  2310. priv->eeprom.board_pba_number_4965);
  2311. }
  2312. #define IWL_TX_CRC_SIZE 4
  2313. #define IWL_TX_DELIMITER_SIZE 4
  2314. int iwl4965_tx_queue_update_wr_ptr(struct iwl_priv *priv,
  2315. struct iwl_tx_queue *txq, u16 byte_cnt)
  2316. {
  2317. int len;
  2318. int txq_id = txq->q.id;
  2319. struct iwl_shared *shared_data = priv->hw_setting.shared_virt;
  2320. if (txq->need_update == 0)
  2321. return 0;
  2322. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  2323. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2324. tfd_offset[txq->q.first_empty], byte_cnt, len);
  2325. if (txq->q.first_empty < IWL4965_MAX_WIN_SIZE)
  2326. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2327. tfd_offset[IWL4965_QUEUE_SIZE + txq->q.first_empty],
  2328. byte_cnt, len);
  2329. return 0;
  2330. }
  2331. /* Set up Rx receiver/antenna/chain usage in "staging" RXON image.
  2332. * This should not be used for scan command ... it puts data in wrong place. */
  2333. void iwl4965_set_rxon_chain(struct iwl_priv *priv)
  2334. {
  2335. u8 is_single = is_single_stream(priv);
  2336. u8 idle_state, rx_state;
  2337. priv->staging_rxon.rx_chain = 0;
  2338. rx_state = idle_state = 3;
  2339. /* Tell uCode which antennas are actually connected.
  2340. * Before first association, we assume all antennas are connected.
  2341. * Just after first association, iwl4965_noise_calibration()
  2342. * checks which antennas actually *are* connected. */
  2343. priv->staging_rxon.rx_chain |=
  2344. cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
  2345. /* How many receivers should we use? */
  2346. iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
  2347. priv->staging_rxon.rx_chain |=
  2348. cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
  2349. priv->staging_rxon.rx_chain |=
  2350. cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
  2351. if (!is_single && (rx_state >= 2) &&
  2352. !test_bit(STATUS_POWER_PMI, &priv->status))
  2353. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2354. else
  2355. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2356. IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
  2357. }
  2358. #ifdef CONFIG_IWLWIFI_HT
  2359. #ifdef CONFIG_IWLWIFI_HT_AGG
  2360. /*
  2361. get the traffic load value for tid
  2362. */
  2363. static u32 iwl4965_tl_get_load(struct iwl_priv *priv, u8 tid)
  2364. {
  2365. u32 load = 0;
  2366. u32 current_time = jiffies_to_msecs(jiffies);
  2367. u32 time_diff;
  2368. s32 index;
  2369. unsigned long flags;
  2370. struct iwl_traffic_load *tid_ptr = NULL;
  2371. if (tid >= TID_MAX_LOAD_COUNT)
  2372. return 0;
  2373. tid_ptr = &(priv->lq_mngr.agg_ctrl.traffic_load[tid]);
  2374. current_time -= current_time % TID_ROUND_VALUE;
  2375. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2376. if (!(tid_ptr->queue_count))
  2377. goto out;
  2378. time_diff = TIME_WRAP_AROUND(tid_ptr->time_stamp, current_time);
  2379. index = time_diff / TID_QUEUE_CELL_SPACING;
  2380. if (index >= TID_QUEUE_MAX_SIZE) {
  2381. u32 oldest_time = current_time - TID_MAX_TIME_DIFF;
  2382. while (tid_ptr->queue_count &&
  2383. (tid_ptr->time_stamp < oldest_time)) {
  2384. tid_ptr->total -= tid_ptr->packet_count[tid_ptr->head];
  2385. tid_ptr->packet_count[tid_ptr->head] = 0;
  2386. tid_ptr->time_stamp += TID_QUEUE_CELL_SPACING;
  2387. tid_ptr->queue_count--;
  2388. tid_ptr->head++;
  2389. if (tid_ptr->head >= TID_QUEUE_MAX_SIZE)
  2390. tid_ptr->head = 0;
  2391. }
  2392. }
  2393. load = tid_ptr->total;
  2394. out:
  2395. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2396. return load;
  2397. }
  2398. /*
  2399. increment traffic load value for tid and also remove
  2400. any old values if passed the certian time period
  2401. */
  2402. static void iwl4965_tl_add_packet(struct iwl_priv *priv, u8 tid)
  2403. {
  2404. u32 current_time = jiffies_to_msecs(jiffies);
  2405. u32 time_diff;
  2406. s32 index;
  2407. unsigned long flags;
  2408. struct iwl_traffic_load *tid_ptr = NULL;
  2409. if (tid >= TID_MAX_LOAD_COUNT)
  2410. return;
  2411. tid_ptr = &(priv->lq_mngr.agg_ctrl.traffic_load[tid]);
  2412. current_time -= current_time % TID_ROUND_VALUE;
  2413. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2414. if (!(tid_ptr->queue_count)) {
  2415. tid_ptr->total = 1;
  2416. tid_ptr->time_stamp = current_time;
  2417. tid_ptr->queue_count = 1;
  2418. tid_ptr->head = 0;
  2419. tid_ptr->packet_count[0] = 1;
  2420. goto out;
  2421. }
  2422. time_diff = TIME_WRAP_AROUND(tid_ptr->time_stamp, current_time);
  2423. index = time_diff / TID_QUEUE_CELL_SPACING;
  2424. if (index >= TID_QUEUE_MAX_SIZE) {
  2425. u32 oldest_time = current_time - TID_MAX_TIME_DIFF;
  2426. while (tid_ptr->queue_count &&
  2427. (tid_ptr->time_stamp < oldest_time)) {
  2428. tid_ptr->total -= tid_ptr->packet_count[tid_ptr->head];
  2429. tid_ptr->packet_count[tid_ptr->head] = 0;
  2430. tid_ptr->time_stamp += TID_QUEUE_CELL_SPACING;
  2431. tid_ptr->queue_count--;
  2432. tid_ptr->head++;
  2433. if (tid_ptr->head >= TID_QUEUE_MAX_SIZE)
  2434. tid_ptr->head = 0;
  2435. }
  2436. }
  2437. index = (tid_ptr->head + index) % TID_QUEUE_MAX_SIZE;
  2438. tid_ptr->packet_count[index] = tid_ptr->packet_count[index] + 1;
  2439. tid_ptr->total = tid_ptr->total + 1;
  2440. if ((index + 1) > tid_ptr->queue_count)
  2441. tid_ptr->queue_count = index + 1;
  2442. out:
  2443. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2444. }
  2445. #define MMAC_SCHED_MAX_NUMBER_OF_HT_BACK_FLOWS 7
  2446. enum HT_STATUS {
  2447. BA_STATUS_FAILURE = 0,
  2448. BA_STATUS_INITIATOR_DELBA,
  2449. BA_STATUS_RECIPIENT_DELBA,
  2450. BA_STATUS_RENEW_ADDBA_REQUEST,
  2451. BA_STATUS_ACTIVE,
  2452. };
  2453. static u8 iwl4964_tl_ba_avail(struct iwl_priv *priv)
  2454. {
  2455. int i;
  2456. struct iwl_lq_mngr *lq;
  2457. u8 count = 0;
  2458. u16 msk;
  2459. lq = (struct iwl_lq_mngr *)&(priv->lq_mngr);
  2460. for (i = 0; i < TID_MAX_LOAD_COUNT ; i++) {
  2461. msk = 1 << i;
  2462. if ((lq->agg_ctrl.granted_ba & msk) ||
  2463. (lq->agg_ctrl.wait_for_agg_status & msk))
  2464. count++;
  2465. }
  2466. if (count < MMAC_SCHED_MAX_NUMBER_OF_HT_BACK_FLOWS)
  2467. return 1;
  2468. return 0;
  2469. }
  2470. static void iwl4965_ba_status(struct iwl_priv *priv,
  2471. u8 tid, enum HT_STATUS status);
  2472. static int iwl4965_perform_addba(struct iwl_priv *priv, u8 tid, u32 length,
  2473. u32 ba_timeout)
  2474. {
  2475. int rc;
  2476. rc = ieee80211_start_BA_session(priv->hw, priv->bssid, tid);
  2477. if (rc)
  2478. iwl4965_ba_status(priv, tid, BA_STATUS_FAILURE);
  2479. return rc;
  2480. }
  2481. static int iwl4965_perform_delba(struct iwl_priv *priv, u8 tid)
  2482. {
  2483. int rc;
  2484. rc = ieee80211_stop_BA_session(priv->hw, priv->bssid, tid);
  2485. if (rc)
  2486. iwl4965_ba_status(priv, tid, BA_STATUS_FAILURE);
  2487. return rc;
  2488. }
  2489. static void iwl4965_turn_on_agg_for_tid(struct iwl_priv *priv,
  2490. struct iwl_lq_mngr *lq,
  2491. u8 auto_agg, u8 tid)
  2492. {
  2493. u32 tid_msk = (1 << tid);
  2494. unsigned long flags;
  2495. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2496. /*
  2497. if ((auto_agg) && (!lq->enable_counter)){
  2498. lq->agg_ctrl.next_retry = 0;
  2499. lq->agg_ctrl.tid_retry = 0;
  2500. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2501. return;
  2502. }
  2503. */
  2504. if (!(lq->agg_ctrl.granted_ba & tid_msk) &&
  2505. (lq->agg_ctrl.requested_ba & tid_msk)) {
  2506. u8 available_queues;
  2507. u32 load;
  2508. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2509. available_queues = iwl4964_tl_ba_avail(priv);
  2510. load = iwl4965_tl_get_load(priv, tid);
  2511. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2512. if (!available_queues) {
  2513. if (auto_agg)
  2514. lq->agg_ctrl.tid_retry |= tid_msk;
  2515. else {
  2516. lq->agg_ctrl.requested_ba &= ~tid_msk;
  2517. lq->agg_ctrl.wait_for_agg_status &= ~tid_msk;
  2518. }
  2519. } else if ((auto_agg) &&
  2520. ((load <= lq->agg_ctrl.tid_traffic_load_threshold) ||
  2521. ((lq->agg_ctrl.wait_for_agg_status & tid_msk))))
  2522. lq->agg_ctrl.tid_retry |= tid_msk;
  2523. else {
  2524. lq->agg_ctrl.wait_for_agg_status |= tid_msk;
  2525. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2526. iwl4965_perform_addba(priv, tid, 0x40,
  2527. lq->agg_ctrl.ba_timeout);
  2528. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2529. }
  2530. }
  2531. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2532. }
  2533. static void iwl4965_turn_on_agg(struct iwl_priv *priv, u8 tid)
  2534. {
  2535. struct iwl_lq_mngr *lq;
  2536. unsigned long flags;
  2537. lq = (struct iwl_lq_mngr *)&(priv->lq_mngr);
  2538. if ((tid < TID_MAX_LOAD_COUNT))
  2539. iwl4965_turn_on_agg_for_tid(priv, lq, lq->agg_ctrl.auto_agg,
  2540. tid);
  2541. else if (tid == TID_ALL_SPECIFIED) {
  2542. if (lq->agg_ctrl.requested_ba) {
  2543. for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++)
  2544. iwl4965_turn_on_agg_for_tid(priv, lq,
  2545. lq->agg_ctrl.auto_agg, tid);
  2546. } else {
  2547. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2548. lq->agg_ctrl.tid_retry = 0;
  2549. lq->agg_ctrl.next_retry = 0;
  2550. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2551. }
  2552. }
  2553. }
  2554. void iwl4965_turn_off_agg(struct iwl_priv *priv, u8 tid)
  2555. {
  2556. u32 tid_msk;
  2557. struct iwl_lq_mngr *lq;
  2558. unsigned long flags;
  2559. lq = (struct iwl_lq_mngr *)&(priv->lq_mngr);
  2560. if ((tid < TID_MAX_LOAD_COUNT)) {
  2561. tid_msk = 1 << tid;
  2562. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2563. lq->agg_ctrl.wait_for_agg_status |= tid_msk;
  2564. lq->agg_ctrl.requested_ba &= ~tid_msk;
  2565. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2566. iwl4965_perform_delba(priv, tid);
  2567. } else if (tid == TID_ALL_SPECIFIED) {
  2568. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2569. for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++) {
  2570. tid_msk = 1 << tid;
  2571. lq->agg_ctrl.wait_for_agg_status |= tid_msk;
  2572. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2573. iwl4965_perform_delba(priv, tid);
  2574. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2575. }
  2576. lq->agg_ctrl.requested_ba = 0;
  2577. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2578. }
  2579. }
  2580. static void iwl4965_ba_status(struct iwl_priv *priv,
  2581. u8 tid, enum HT_STATUS status)
  2582. {
  2583. struct iwl_lq_mngr *lq;
  2584. u32 tid_msk = (1 << tid);
  2585. unsigned long flags;
  2586. lq = (struct iwl_lq_mngr *)&(priv->lq_mngr);
  2587. if ((tid >= TID_MAX_LOAD_COUNT))
  2588. goto out;
  2589. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2590. switch (status) {
  2591. case BA_STATUS_ACTIVE:
  2592. if (!(lq->agg_ctrl.granted_ba & tid_msk))
  2593. lq->agg_ctrl.granted_ba |= tid_msk;
  2594. break;
  2595. default:
  2596. if ((lq->agg_ctrl.granted_ba & tid_msk))
  2597. lq->agg_ctrl.granted_ba &= ~tid_msk;
  2598. break;
  2599. }
  2600. lq->agg_ctrl.wait_for_agg_status &= ~tid_msk;
  2601. if (status != BA_STATUS_ACTIVE) {
  2602. if (lq->agg_ctrl.auto_agg) {
  2603. lq->agg_ctrl.tid_retry |= tid_msk;
  2604. lq->agg_ctrl.next_retry =
  2605. jiffies + msecs_to_jiffies(500);
  2606. } else
  2607. lq->agg_ctrl.requested_ba &= ~tid_msk;
  2608. }
  2609. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2610. out:
  2611. return;
  2612. }
  2613. static void iwl4965_bg_agg_work(struct work_struct *work)
  2614. {
  2615. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2616. agg_work);
  2617. u32 tid;
  2618. u32 retry_tid;
  2619. u32 tid_msk;
  2620. unsigned long flags;
  2621. struct iwl_lq_mngr *lq = (struct iwl_lq_mngr *)&(priv->lq_mngr);
  2622. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2623. retry_tid = lq->agg_ctrl.tid_retry;
  2624. lq->agg_ctrl.tid_retry = 0;
  2625. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2626. if (retry_tid == TID_ALL_SPECIFIED)
  2627. iwl4965_turn_on_agg(priv, TID_ALL_SPECIFIED);
  2628. else {
  2629. for (tid = 0; tid < TID_MAX_LOAD_COUNT; tid++) {
  2630. tid_msk = (1 << tid);
  2631. if (retry_tid & tid_msk)
  2632. iwl4965_turn_on_agg(priv, tid);
  2633. }
  2634. }
  2635. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2636. if (lq->agg_ctrl.tid_retry)
  2637. lq->agg_ctrl.next_retry = jiffies + msecs_to_jiffies(500);
  2638. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2639. return;
  2640. }
  2641. #endif /*CONFIG_IWLWIFI_HT_AGG */
  2642. #endif /* CONFIG_IWLWIFI_HT */
  2643. int iwl4965_tx_cmd(struct iwl_priv *priv, struct iwl_cmd *out_cmd,
  2644. u8 sta_id, dma_addr_t txcmd_phys,
  2645. struct ieee80211_hdr *hdr, u8 hdr_len,
  2646. struct ieee80211_tx_control *ctrl, void *sta_in)
  2647. {
  2648. struct iwl_tx_cmd cmd;
  2649. struct iwl_tx_cmd *tx = (struct iwl_tx_cmd *)&out_cmd->cmd.payload[0];
  2650. dma_addr_t scratch_phys;
  2651. u8 unicast = 0;
  2652. u8 is_data = 1;
  2653. u16 fc;
  2654. u16 rate_flags;
  2655. int rate_index = min(ctrl->tx_rate & 0xffff, IWL_RATE_COUNT - 1);
  2656. #ifdef CONFIG_IWLWIFI_HT
  2657. #ifdef CONFIG_IWLWIFI_HT_AGG
  2658. __le16 *qc;
  2659. #endif /*CONFIG_IWLWIFI_HT_AGG */
  2660. #endif /* CONFIG_IWLWIFI_HT */
  2661. unicast = !is_multicast_ether_addr(hdr->addr1);
  2662. fc = le16_to_cpu(hdr->frame_control);
  2663. if ((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA)
  2664. is_data = 0;
  2665. memcpy(&cmd, &(out_cmd->cmd.tx), sizeof(struct iwl_tx_cmd));
  2666. memset(tx, 0, sizeof(struct iwl_tx_cmd));
  2667. memcpy(tx->hdr, hdr, hdr_len);
  2668. tx->len = cmd.len;
  2669. tx->driver_txop = cmd.driver_txop;
  2670. tx->stop_time.life_time = cmd.stop_time.life_time;
  2671. tx->tx_flags = cmd.tx_flags;
  2672. tx->sta_id = cmd.sta_id;
  2673. tx->tid_tspec = cmd.tid_tspec;
  2674. tx->timeout.pm_frame_timeout = cmd.timeout.pm_frame_timeout;
  2675. tx->next_frame_len = cmd.next_frame_len;
  2676. tx->sec_ctl = cmd.sec_ctl;
  2677. memcpy(&(tx->key[0]), &(cmd.key[0]), 16);
  2678. tx->tx_flags = cmd.tx_flags;
  2679. tx->rts_retry_limit = cmd.rts_retry_limit;
  2680. tx->data_retry_limit = cmd.data_retry_limit;
  2681. scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
  2682. offsetof(struct iwl_tx_cmd, scratch);
  2683. tx->dram_lsb_ptr = cpu_to_le32(scratch_phys);
  2684. tx->dram_msb_ptr = iwl4965_get_dma_hi_address(scratch_phys);
  2685. /* Hard coded to start at the highest retry fallback position
  2686. * until the 4965 specific rate control algorithm is tied in */
  2687. tx->initial_rate_index = LINK_QUAL_MAX_RETRY_NUM - 1;
  2688. /* Alternate between antenna A and B for successive frames */
  2689. if (priv->use_ant_b_for_management_frame) {
  2690. priv->use_ant_b_for_management_frame = 0;
  2691. rate_flags = RATE_MCS_ANT_B_MSK;
  2692. } else {
  2693. priv->use_ant_b_for_management_frame = 1;
  2694. rate_flags = RATE_MCS_ANT_A_MSK;
  2695. }
  2696. if (!unicast || !is_data) {
  2697. if ((rate_index >= IWL_FIRST_CCK_RATE) &&
  2698. (rate_index <= IWL_LAST_CCK_RATE))
  2699. rate_flags |= RATE_MCS_CCK_MSK;
  2700. } else {
  2701. tx->initial_rate_index = 0;
  2702. tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
  2703. }
  2704. tx->rate_n_flags = iwl_hw_set_rate_n_flags(iwl_rates[rate_index].plcp,
  2705. rate_flags);
  2706. if (ieee80211_is_probe_request(fc))
  2707. tx->tx_flags |= TX_CMD_FLG_TSF_MSK;
  2708. else if (ieee80211_is_back_request(fc))
  2709. tx->tx_flags |= TX_CMD_FLG_ACK_MSK |
  2710. TX_CMD_FLG_IMM_BA_RSP_MASK;
  2711. #ifdef CONFIG_IWLWIFI_HT
  2712. #ifdef CONFIG_IWLWIFI_HT_AGG
  2713. qc = ieee80211_get_qos_ctrl(hdr);
  2714. if (qc &&
  2715. (priv->iw_mode != IEEE80211_IF_TYPE_IBSS)) {
  2716. u8 tid = 0;
  2717. tid = (u8) (le16_to_cpu(*qc) & 0xF);
  2718. if (tid < TID_MAX_LOAD_COUNT)
  2719. iwl4965_tl_add_packet(priv, tid);
  2720. }
  2721. if (priv->lq_mngr.agg_ctrl.next_retry &&
  2722. (time_after(priv->lq_mngr.agg_ctrl.next_retry, jiffies))) {
  2723. unsigned long flags;
  2724. spin_lock_irqsave(&priv->lq_mngr.lock, flags);
  2725. priv->lq_mngr.agg_ctrl.next_retry = 0;
  2726. spin_unlock_irqrestore(&priv->lq_mngr.lock, flags);
  2727. schedule_work(&priv->agg_work);
  2728. }
  2729. #endif
  2730. #endif
  2731. return 0;
  2732. }
  2733. /**
  2734. * sign_extend - Sign extend a value using specified bit as sign-bit
  2735. *
  2736. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  2737. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  2738. *
  2739. * @param oper value to sign extend
  2740. * @param index 0 based bit index (0<=index<32) to sign bit
  2741. */
  2742. static s32 sign_extend(u32 oper, int index)
  2743. {
  2744. u8 shift = 31 - index;
  2745. return (s32)(oper << shift) >> shift;
  2746. }
  2747. /**
  2748. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  2749. * @statistics: Provides the temperature reading from the uCode
  2750. *
  2751. * A return of <0 indicates bogus data in the statistics
  2752. */
  2753. int iwl4965_get_temperature(const struct iwl_priv *priv)
  2754. {
  2755. s32 temperature;
  2756. s32 vt;
  2757. s32 R1, R2, R3;
  2758. u32 R4;
  2759. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  2760. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  2761. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  2762. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  2763. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  2764. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  2765. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  2766. } else {
  2767. IWL_DEBUG_TEMP("Running temperature calibration\n");
  2768. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  2769. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  2770. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  2771. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  2772. }
  2773. /*
  2774. * Temperature is only 23 bits so sign extend out to 32
  2775. *
  2776. * NOTE If we haven't received a statistics notification yet
  2777. * with an updated temperature, use R4 provided to us in the
  2778. * ALIVE response. */
  2779. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  2780. vt = sign_extend(R4, 23);
  2781. else
  2782. vt = sign_extend(
  2783. le32_to_cpu(priv->statistics.general.temperature), 23);
  2784. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  2785. R1, R2, R3, vt);
  2786. if (R3 == R1) {
  2787. IWL_ERROR("Calibration conflict R1 == R3\n");
  2788. return -1;
  2789. }
  2790. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  2791. * Add offset to center the adjustment around 0 degrees Centigrade. */
  2792. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  2793. temperature /= (R3 - R1);
  2794. temperature = (temperature * 97) / 100 +
  2795. TEMPERATURE_CALIB_KELVIN_OFFSET;
  2796. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  2797. KELVIN_TO_CELSIUS(temperature));
  2798. return temperature;
  2799. }
  2800. /* Adjust Txpower only if temperature variance is greater than threshold. */
  2801. #define IWL_TEMPERATURE_THRESHOLD 3
  2802. /**
  2803. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  2804. *
  2805. * If the temperature changed has changed sufficiently, then a recalibration
  2806. * is needed.
  2807. *
  2808. * Assumes caller will replace priv->last_temperature once calibration
  2809. * executed.
  2810. */
  2811. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  2812. {
  2813. int temp_diff;
  2814. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  2815. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  2816. return 0;
  2817. }
  2818. temp_diff = priv->temperature - priv->last_temperature;
  2819. /* get absolute value */
  2820. if (temp_diff < 0) {
  2821. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  2822. temp_diff = -temp_diff;
  2823. } else if (temp_diff == 0)
  2824. IWL_DEBUG_POWER("Same temp, \n");
  2825. else
  2826. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  2827. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  2828. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  2829. return 0;
  2830. }
  2831. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  2832. return 1;
  2833. }
  2834. /* Calculate noise level, based on measurements during network silence just
  2835. * before arriving beacon. This measurement can be done only if we know
  2836. * exactly when to expect beacons, therefore only when we're associated. */
  2837. static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
  2838. {
  2839. struct statistics_rx_non_phy *rx_info
  2840. = &(priv->statistics.rx.general);
  2841. int num_active_rx = 0;
  2842. int total_silence = 0;
  2843. int bcn_silence_a =
  2844. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  2845. int bcn_silence_b =
  2846. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  2847. int bcn_silence_c =
  2848. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  2849. if (bcn_silence_a) {
  2850. total_silence += bcn_silence_a;
  2851. num_active_rx++;
  2852. }
  2853. if (bcn_silence_b) {
  2854. total_silence += bcn_silence_b;
  2855. num_active_rx++;
  2856. }
  2857. if (bcn_silence_c) {
  2858. total_silence += bcn_silence_c;
  2859. num_active_rx++;
  2860. }
  2861. /* Average among active antennas */
  2862. if (num_active_rx)
  2863. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  2864. else
  2865. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2866. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  2867. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  2868. priv->last_rx_noise);
  2869. }
  2870. void iwl_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  2871. {
  2872. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2873. int change;
  2874. s32 temp;
  2875. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  2876. (int)sizeof(priv->statistics), pkt->len);
  2877. change = ((priv->statistics.general.temperature !=
  2878. pkt->u.stats.general.temperature) ||
  2879. ((priv->statistics.flag &
  2880. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  2881. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  2882. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  2883. set_bit(STATUS_STATISTICS, &priv->status);
  2884. /* Reschedule the statistics timer to occur in
  2885. * REG_RECALIB_PERIOD seconds to ensure we get a
  2886. * thermal update even if the uCode doesn't give
  2887. * us one */
  2888. mod_timer(&priv->statistics_periodic, jiffies +
  2889. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  2890. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2891. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  2892. iwl4965_rx_calc_noise(priv);
  2893. #ifdef CONFIG_IWLWIFI_SENSITIVITY
  2894. queue_work(priv->workqueue, &priv->sensitivity_work);
  2895. #endif
  2896. }
  2897. /* If the hardware hasn't reported a change in
  2898. * temperature then don't bother computing a
  2899. * calibrated temperature value */
  2900. if (!change)
  2901. return;
  2902. temp = iwl4965_get_temperature(priv);
  2903. if (temp < 0)
  2904. return;
  2905. if (priv->temperature != temp) {
  2906. if (priv->temperature)
  2907. IWL_DEBUG_TEMP("Temperature changed "
  2908. "from %dC to %dC\n",
  2909. KELVIN_TO_CELSIUS(priv->temperature),
  2910. KELVIN_TO_CELSIUS(temp));
  2911. else
  2912. IWL_DEBUG_TEMP("Temperature "
  2913. "initialized to %dC\n",
  2914. KELVIN_TO_CELSIUS(temp));
  2915. }
  2916. priv->temperature = temp;
  2917. set_bit(STATUS_TEMPERATURE, &priv->status);
  2918. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2919. iwl4965_is_temp_calib_needed(priv))
  2920. queue_work(priv->workqueue, &priv->txpower_work);
  2921. }
  2922. static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
  2923. int include_phy,
  2924. struct iwl_rx_mem_buffer *rxb,
  2925. struct ieee80211_rx_status *stats)
  2926. {
  2927. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2928. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2929. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  2930. struct ieee80211_hdr *hdr;
  2931. u16 len;
  2932. __le32 *rx_end;
  2933. unsigned int skblen;
  2934. u32 ampdu_status;
  2935. if (!include_phy && priv->last_phy_res[0])
  2936. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2937. if (!rx_start) {
  2938. IWL_ERROR("MPDU frame without a PHY data\n");
  2939. return;
  2940. }
  2941. if (include_phy) {
  2942. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  2943. rx_start->cfg_phy_cnt);
  2944. len = le16_to_cpu(rx_start->byte_count);
  2945. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  2946. sizeof(struct iwl4965_rx_phy_res) +
  2947. rx_start->cfg_phy_cnt + len);
  2948. } else {
  2949. struct iwl4965_rx_mpdu_res_start *amsdu =
  2950. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2951. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  2952. sizeof(struct iwl4965_rx_mpdu_res_start));
  2953. len = le16_to_cpu(amsdu->byte_count);
  2954. rx_start->byte_count = amsdu->byte_count;
  2955. rx_end = (__le32 *) (((u8 *) hdr) + len);
  2956. }
  2957. if (len > 2342 || len < 16) {
  2958. IWL_DEBUG_DROP("byte count out of range [16,2342]"
  2959. " : %d\n", len);
  2960. return;
  2961. }
  2962. ampdu_status = le32_to_cpu(*rx_end);
  2963. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  2964. /* start from MAC */
  2965. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  2966. skb_put(rxb->skb, len); /* end where data ends */
  2967. /* We only process data packets if the interface is open */
  2968. if (unlikely(!priv->is_open)) {
  2969. IWL_DEBUG_DROP_LIMIT
  2970. ("Dropping packet while interface is not open.\n");
  2971. return;
  2972. }
  2973. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  2974. if (iwl_param_hwcrypto)
  2975. iwl_set_decrypted_flag(priv, rxb->skb,
  2976. ampdu_status, stats);
  2977. iwl_handle_data_packet_monitor(priv, rxb, hdr, len, stats, 0);
  2978. return;
  2979. }
  2980. stats->flag = 0;
  2981. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  2982. if (iwl_param_hwcrypto)
  2983. iwl_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
  2984. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2985. priv->alloc_rxb_skb--;
  2986. rxb->skb = NULL;
  2987. #ifdef LED
  2988. priv->led_packets += len;
  2989. iwl_setup_activity_timer(priv);
  2990. #endif
  2991. }
  2992. /* Calc max signal level (dBm) among 3 possible receivers */
  2993. static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
  2994. {
  2995. /* data from PHY/DSP regarding signal strength, etc.,
  2996. * contents are always there, not configurable by host. */
  2997. struct iwl4965_rx_non_cfg_phy *ncphy =
  2998. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  2999. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  3000. >> IWL_AGC_DB_POS;
  3001. u32 valid_antennae =
  3002. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  3003. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  3004. u8 max_rssi = 0;
  3005. u32 i;
  3006. /* Find max rssi among 3 possible receivers.
  3007. * These values are measured by the digital signal processor (DSP).
  3008. * They should stay fairly constant even as the signal strength varies,
  3009. * if the radio's automatic gain control (AGC) is working right.
  3010. * AGC value (see below) will provide the "interesting" info. */
  3011. for (i = 0; i < 3; i++)
  3012. if (valid_antennae & (1 << i))
  3013. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  3014. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  3015. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  3016. max_rssi, agc);
  3017. /* dBm = max_rssi dB - agc dB - constant.
  3018. * Higher AGC (higher radio gain) means lower signal. */
  3019. return (max_rssi - agc - IWL_RSSI_OFFSET);
  3020. }
  3021. #ifdef CONFIG_IWLWIFI_HT
  3022. /* Parsed Information Elements */
  3023. struct ieee802_11_elems {
  3024. u8 *ds_params;
  3025. u8 ds_params_len;
  3026. u8 *tim;
  3027. u8 tim_len;
  3028. u8 *ibss_params;
  3029. u8 ibss_params_len;
  3030. u8 *erp_info;
  3031. u8 erp_info_len;
  3032. u8 *ht_cap_param;
  3033. u8 ht_cap_param_len;
  3034. u8 *ht_extra_param;
  3035. u8 ht_extra_param_len;
  3036. };
  3037. static int parse_elems(u8 *start, size_t len, struct ieee802_11_elems *elems)
  3038. {
  3039. size_t left = len;
  3040. u8 *pos = start;
  3041. int unknown = 0;
  3042. memset(elems, 0, sizeof(*elems));
  3043. while (left >= 2) {
  3044. u8 id, elen;
  3045. id = *pos++;
  3046. elen = *pos++;
  3047. left -= 2;
  3048. if (elen > left)
  3049. return -1;
  3050. switch (id) {
  3051. case WLAN_EID_DS_PARAMS:
  3052. elems->ds_params = pos;
  3053. elems->ds_params_len = elen;
  3054. break;
  3055. case WLAN_EID_TIM:
  3056. elems->tim = pos;
  3057. elems->tim_len = elen;
  3058. break;
  3059. case WLAN_EID_IBSS_PARAMS:
  3060. elems->ibss_params = pos;
  3061. elems->ibss_params_len = elen;
  3062. break;
  3063. case WLAN_EID_ERP_INFO:
  3064. elems->erp_info = pos;
  3065. elems->erp_info_len = elen;
  3066. break;
  3067. case WLAN_EID_HT_CAPABILITY:
  3068. elems->ht_cap_param = pos;
  3069. elems->ht_cap_param_len = elen;
  3070. break;
  3071. case WLAN_EID_HT_EXTRA_INFO:
  3072. elems->ht_extra_param = pos;
  3073. elems->ht_extra_param_len = elen;
  3074. break;
  3075. default:
  3076. unknown++;
  3077. break;
  3078. }
  3079. left -= elen;
  3080. pos += elen;
  3081. }
  3082. return 0;
  3083. }
  3084. #endif /* CONFIG_IWLWIFI_HT */
  3085. static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
  3086. {
  3087. unsigned long flags;
  3088. spin_lock_irqsave(&priv->sta_lock, flags);
  3089. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  3090. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  3091. priv->stations[sta_id].sta.sta.modify_mask = 0;
  3092. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3093. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3094. iwl_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3095. }
  3096. static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
  3097. {
  3098. /* FIXME: need locking over ps_status ??? */
  3099. u8 sta_id = iwl_hw_find_station(priv, addr);
  3100. if (sta_id != IWL_INVALID_STATION) {
  3101. u8 sta_awake = priv->stations[sta_id].
  3102. ps_status == STA_PS_STATUS_WAKE;
  3103. if (sta_awake && ps_bit)
  3104. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  3105. else if (!sta_awake && !ps_bit) {
  3106. iwl4965_sta_modify_ps_wake(priv, sta_id);
  3107. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  3108. }
  3109. }
  3110. }
  3111. /* Called for REPLY_4965_RX (legacy ABG frames), or
  3112. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  3113. static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
  3114. struct iwl_rx_mem_buffer *rxb)
  3115. {
  3116. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  3117. /* Use phy data (Rx signal strength, etc.) contained within
  3118. * this rx packet for legacy frames,
  3119. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  3120. int include_phy = (pkt->hdr.cmd == REPLY_4965_RX);
  3121. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  3122. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  3123. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  3124. __le32 *rx_end;
  3125. unsigned int len = 0;
  3126. struct ieee80211_hdr *header;
  3127. u16 fc;
  3128. struct ieee80211_rx_status stats = {
  3129. .mactime = le64_to_cpu(rx_start->timestamp),
  3130. .channel = le16_to_cpu(rx_start->channel),
  3131. .phymode =
  3132. (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  3133. MODE_IEEE80211G : MODE_IEEE80211A,
  3134. .antenna = 0,
  3135. .rate = iwl_hw_get_rate(rx_start->rate_n_flags),
  3136. .flag = 0,
  3137. #ifdef CONFIG_IWLWIFI_HT_AGG
  3138. .ordered = 0
  3139. #endif /* CONFIG_IWLWIFI_HT_AGG */
  3140. };
  3141. u8 network_packet;
  3142. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  3143. IWL_DEBUG_DROP
  3144. ("dsp size out of range [0,20]: "
  3145. "%d/n", rx_start->cfg_phy_cnt);
  3146. return;
  3147. }
  3148. if (!include_phy) {
  3149. if (priv->last_phy_res[0])
  3150. rx_start = (struct iwl4965_rx_phy_res *)
  3151. &priv->last_phy_res[1];
  3152. else
  3153. rx_start = NULL;
  3154. }
  3155. if (!rx_start) {
  3156. IWL_ERROR("MPDU frame without a PHY data\n");
  3157. return;
  3158. }
  3159. if (include_phy) {
  3160. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  3161. + rx_start->cfg_phy_cnt);
  3162. len = le16_to_cpu(rx_start->byte_count);
  3163. rx_end = (__le32 *) (pkt->u.raw + rx_start->cfg_phy_cnt +
  3164. sizeof(struct iwl4965_rx_phy_res) + len);
  3165. } else {
  3166. struct iwl4965_rx_mpdu_res_start *amsdu =
  3167. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  3168. header = (void *)(pkt->u.raw +
  3169. sizeof(struct iwl4965_rx_mpdu_res_start));
  3170. len = le16_to_cpu(amsdu->byte_count);
  3171. rx_end = (__le32 *) (pkt->u.raw +
  3172. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  3173. }
  3174. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  3175. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  3176. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  3177. le32_to_cpu(*rx_end));
  3178. return;
  3179. }
  3180. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  3181. stats.freq = ieee80211chan2mhz(stats.channel);
  3182. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  3183. stats.ssi = iwl4965_calc_rssi(rx_start);
  3184. /* Meaningful noise values are available only from beacon statistics,
  3185. * which are gathered only when associated, and indicate noise
  3186. * only for the associated network channel ...
  3187. * Ignore these noise values while scanning (other channels) */
  3188. if (iwl_is_associated(priv) &&
  3189. !test_bit(STATUS_SCANNING, &priv->status)) {
  3190. stats.noise = priv->last_rx_noise;
  3191. stats.signal = iwl_calc_sig_qual(stats.ssi, stats.noise);
  3192. } else {
  3193. stats.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3194. stats.signal = iwl_calc_sig_qual(stats.ssi, 0);
  3195. }
  3196. /* Reset beacon noise level if not associated. */
  3197. if (!iwl_is_associated(priv))
  3198. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3199. #ifdef CONFIG_IWLWIFI_DEBUG
  3200. /* TODO: Parts of iwl_report_frame are broken for 4965 */
  3201. if (iwl_debug_level & (IWL_DL_RX))
  3202. /* Set "1" to report good data frames in groups of 100 */
  3203. iwl_report_frame(priv, pkt, header, 1);
  3204. if (iwl_debug_level & (IWL_DL_RX | IWL_DL_STATS))
  3205. IWL_DEBUG_RX("Rssi %d, noise %d, qual %d, TSF %lu\n",
  3206. stats.ssi, stats.noise, stats.signal,
  3207. (long unsigned int)le64_to_cpu(rx_start->timestamp));
  3208. #endif
  3209. network_packet = iwl_is_network_packet(priv, header);
  3210. if (network_packet) {
  3211. priv->last_rx_rssi = stats.ssi;
  3212. priv->last_beacon_time = priv->ucode_beacon_time;
  3213. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  3214. }
  3215. fc = le16_to_cpu(header->frame_control);
  3216. switch (fc & IEEE80211_FCTL_FTYPE) {
  3217. case IEEE80211_FTYPE_MGMT:
  3218. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3219. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3220. header->addr2);
  3221. switch (fc & IEEE80211_FCTL_STYPE) {
  3222. case IEEE80211_STYPE_PROBE_RESP:
  3223. case IEEE80211_STYPE_BEACON:
  3224. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA &&
  3225. !compare_ether_addr(header->addr2, priv->bssid)) ||
  3226. (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
  3227. !compare_ether_addr(header->addr3, priv->bssid))) {
  3228. struct ieee80211_mgmt *mgmt =
  3229. (struct ieee80211_mgmt *)header;
  3230. u64 timestamp =
  3231. le64_to_cpu(mgmt->u.beacon.timestamp);
  3232. priv->timestamp0 = timestamp & 0xFFFFFFFF;
  3233. priv->timestamp1 =
  3234. (timestamp >> 32) & 0xFFFFFFFF;
  3235. priv->beacon_int = le16_to_cpu(
  3236. mgmt->u.beacon.beacon_int);
  3237. if (priv->call_post_assoc_from_beacon &&
  3238. (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
  3239. priv->call_post_assoc_from_beacon = 0;
  3240. queue_work(priv->workqueue,
  3241. &priv->post_associate.work);
  3242. }
  3243. }
  3244. break;
  3245. case IEEE80211_STYPE_ACTION:
  3246. break;
  3247. /*
  3248. * TODO: There is no callback function from upper
  3249. * stack to inform us when associated status. this
  3250. * work around to sniff assoc_resp management frame
  3251. * and finish the association process.
  3252. */
  3253. case IEEE80211_STYPE_ASSOC_RESP:
  3254. case IEEE80211_STYPE_REASSOC_RESP:
  3255. if (network_packet && iwl_is_associated(priv)) {
  3256. #ifdef CONFIG_IWLWIFI_HT
  3257. u8 *pos = NULL;
  3258. struct ieee802_11_elems elems;
  3259. #endif /*CONFIG_IWLWIFI_HT */
  3260. struct ieee80211_mgmt *mgnt =
  3261. (struct ieee80211_mgmt *)header;
  3262. priv->assoc_id = (~((1 << 15) | (1 << 14))
  3263. & le16_to_cpu(mgnt->u.assoc_resp.aid));
  3264. priv->assoc_capability =
  3265. le16_to_cpu(
  3266. mgnt->u.assoc_resp.capab_info);
  3267. #ifdef CONFIG_IWLWIFI_HT
  3268. pos = mgnt->u.assoc_resp.variable;
  3269. if (!parse_elems(pos,
  3270. len - (pos - (u8 *) mgnt),
  3271. &elems)) {
  3272. if (elems.ht_extra_param &&
  3273. elems.ht_cap_param)
  3274. break;
  3275. }
  3276. #endif /*CONFIG_IWLWIFI_HT */
  3277. /* assoc_id is 0 no association */
  3278. if (!priv->assoc_id)
  3279. break;
  3280. if (priv->beacon_int)
  3281. queue_work(priv->workqueue,
  3282. &priv->post_associate.work);
  3283. else
  3284. priv->call_post_assoc_from_beacon = 1;
  3285. }
  3286. break;
  3287. case IEEE80211_STYPE_PROBE_REQ:
  3288. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  3289. !iwl_is_associated(priv)) {
  3290. DECLARE_MAC_BUF(mac1);
  3291. DECLARE_MAC_BUF(mac2);
  3292. DECLARE_MAC_BUF(mac3);
  3293. IWL_DEBUG_DROP("Dropping (non network): "
  3294. "%s, %s, %s\n",
  3295. print_mac(mac1, header->addr1),
  3296. print_mac(mac2, header->addr2),
  3297. print_mac(mac3, header->addr3));
  3298. return;
  3299. }
  3300. }
  3301. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &stats);
  3302. break;
  3303. case IEEE80211_FTYPE_CTL:
  3304. #ifdef CONFIG_IWLWIFI_HT_AGG
  3305. switch (fc & IEEE80211_FCTL_STYPE) {
  3306. case IEEE80211_STYPE_BACK_REQ:
  3307. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  3308. iwl4965_handle_data_packet(priv, 0, include_phy,
  3309. rxb, &stats);
  3310. break;
  3311. default:
  3312. break;
  3313. }
  3314. #endif
  3315. break;
  3316. case IEEE80211_FTYPE_DATA: {
  3317. DECLARE_MAC_BUF(mac1);
  3318. DECLARE_MAC_BUF(mac2);
  3319. DECLARE_MAC_BUF(mac3);
  3320. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3321. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3322. header->addr2);
  3323. if (unlikely(!network_packet))
  3324. IWL_DEBUG_DROP("Dropping (non network): "
  3325. "%s, %s, %s\n",
  3326. print_mac(mac1, header->addr1),
  3327. print_mac(mac2, header->addr2),
  3328. print_mac(mac3, header->addr3));
  3329. else if (unlikely(is_duplicate_packet(priv, header)))
  3330. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  3331. print_mac(mac1, header->addr1),
  3332. print_mac(mac2, header->addr2),
  3333. print_mac(mac3, header->addr3));
  3334. else
  3335. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  3336. &stats);
  3337. break;
  3338. }
  3339. default:
  3340. break;
  3341. }
  3342. }
  3343. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  3344. * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  3345. static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
  3346. struct iwl_rx_mem_buffer *rxb)
  3347. {
  3348. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  3349. priv->last_phy_res[0] = 1;
  3350. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  3351. sizeof(struct iwl4965_rx_phy_res));
  3352. }
  3353. static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
  3354. struct iwl_rx_mem_buffer *rxb)
  3355. {
  3356. #ifdef CONFIG_IWLWIFI_SENSITIVITY
  3357. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  3358. struct iwl_missed_beacon_notif *missed_beacon;
  3359. missed_beacon = &pkt->u.missed_beacon;
  3360. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  3361. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  3362. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  3363. le32_to_cpu(missed_beacon->total_missed_becons),
  3364. le32_to_cpu(missed_beacon->num_recvd_beacons),
  3365. le32_to_cpu(missed_beacon->num_expected_beacons));
  3366. priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
  3367. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
  3368. queue_work(priv->workqueue, &priv->sensitivity_work);
  3369. }
  3370. #endif /*CONFIG_IWLWIFI_SENSITIVITY*/
  3371. }
  3372. #ifdef CONFIG_IWLWIFI_HT
  3373. #ifdef CONFIG_IWLWIFI_HT_AGG
  3374. static void iwl4965_set_tx_status(struct iwl_priv *priv, int txq_id, int idx,
  3375. u32 status, u32 retry_count, u32 rate)
  3376. {
  3377. struct ieee80211_tx_status *tx_status =
  3378. &(priv->txq[txq_id].txb[idx].status);
  3379. tx_status->flags = status ? IEEE80211_TX_STATUS_ACK : 0;
  3380. tx_status->retry_count += retry_count;
  3381. tx_status->control.tx_rate = rate;
  3382. }
  3383. static void iwl_sta_modify_enable_tid_tx(struct iwl_priv *priv,
  3384. int sta_id, int tid)
  3385. {
  3386. unsigned long flags;
  3387. spin_lock_irqsave(&priv->sta_lock, flags);
  3388. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
  3389. priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
  3390. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3391. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3392. iwl_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3393. }
  3394. static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
  3395. struct iwl_ht_agg *agg,
  3396. struct iwl_compressed_ba_resp*
  3397. ba_resp)
  3398. {
  3399. int i, sh, ack;
  3400. u16 ba_seq_ctl = le16_to_cpu(ba_resp->ba_seq_ctl);
  3401. u32 bitmap0, bitmap1;
  3402. u32 resp_bitmap0 = le32_to_cpu(ba_resp->ba_bitmap0);
  3403. u32 resp_bitmap1 = le32_to_cpu(ba_resp->ba_bitmap1);
  3404. if (unlikely(!agg->wait_for_ba)) {
  3405. IWL_ERROR("Received BA when not expected\n");
  3406. return -EINVAL;
  3407. }
  3408. agg->wait_for_ba = 0;
  3409. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->ba_seq_ctl);
  3410. sh = agg->start_idx - SEQ_TO_INDEX(ba_seq_ctl>>4);
  3411. if (sh < 0) /* tbw something is wrong with indeces */
  3412. sh += 0x100;
  3413. /* don't use 64 bits for now */
  3414. bitmap0 = resp_bitmap0 >> sh;
  3415. bitmap1 = resp_bitmap1 >> sh;
  3416. bitmap0 |= (resp_bitmap1 & ((1<<sh)|((1<<sh)-1))) << (32 - sh);
  3417. if (agg->frame_count > (64 - sh)) {
  3418. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  3419. return -1;
  3420. }
  3421. /* check for success or failure according to the
  3422. * transmitted bitmap and back bitmap */
  3423. bitmap0 &= agg->bitmap0;
  3424. bitmap1 &= agg->bitmap1;
  3425. for (i = 0; i < agg->frame_count ; i++) {
  3426. int idx = (agg->start_idx + i) & 0xff;
  3427. ack = bitmap0 & (1 << i);
  3428. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  3429. ack? "ACK":"NACK", i, idx, agg->start_idx + i);
  3430. iwl4965_set_tx_status(priv, agg->txq_id, idx, ack, 0,
  3431. agg->rate_n_flags);
  3432. }
  3433. IWL_DEBUG_TX_REPLY("Bitmap %x%x\n", bitmap0, bitmap1);
  3434. return 0;
  3435. }
  3436. static inline int iwl_queue_dec_wrap(int index, int n_bd)
  3437. {
  3438. return (index == 0) ? n_bd - 1 : index - 1;
  3439. }
  3440. static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
  3441. struct iwl_rx_mem_buffer *rxb)
  3442. {
  3443. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  3444. struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  3445. int index;
  3446. struct iwl_tx_queue *txq = NULL;
  3447. struct iwl_ht_agg *agg;
  3448. u16 ba_resp_scd_flow = le16_to_cpu(ba_resp->scd_flow);
  3449. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  3450. if (ba_resp_scd_flow >= ARRAY_SIZE(priv->txq)) {
  3451. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  3452. return;
  3453. }
  3454. txq = &priv->txq[ba_resp_scd_flow];
  3455. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  3456. index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  3457. /* TODO: Need to get this copy more sefely - now good for debug */
  3458. /*
  3459. {
  3460. DECLARE_MAC_BUF(mac);
  3461. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  3462. "sta_id = %d\n",
  3463. agg->wait_for_ba,
  3464. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  3465. ba_resp->sta_id);
  3466. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%X%X, scd_flow = "
  3467. "%d, scd_ssn = %d\n",
  3468. ba_resp->tid,
  3469. ba_resp->ba_seq_ctl,
  3470. ba_resp->ba_bitmap1,
  3471. ba_resp->ba_bitmap0,
  3472. ba_resp->scd_flow,
  3473. ba_resp->scd_ssn);
  3474. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%X%X \n",
  3475. agg->start_idx,
  3476. agg->bitmap1,
  3477. agg->bitmap0);
  3478. }
  3479. */
  3480. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  3481. /* releases all the TFDs until the SSN */
  3482. if (txq->q.last_used != (ba_resp_scd_ssn & 0xff))
  3483. iwl_tx_queue_reclaim(priv, ba_resp_scd_flow, index);
  3484. }
  3485. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
  3486. {
  3487. iwl_write_restricted_reg(priv,
  3488. SCD_QUEUE_STATUS_BITS(txq_id),
  3489. (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  3490. (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  3491. }
  3492. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  3493. u16 txq_id)
  3494. {
  3495. u32 tbl_dw_addr;
  3496. u32 tbl_dw;
  3497. u16 scd_q2ratid;
  3498. scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  3499. tbl_dw_addr = priv->scd_base_addr +
  3500. SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  3501. tbl_dw = iwl_read_restricted_mem(priv, tbl_dw_addr);
  3502. if (txq_id & 0x1)
  3503. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  3504. else
  3505. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  3506. iwl_write_restricted_mem(priv, tbl_dw_addr, tbl_dw);
  3507. return 0;
  3508. }
  3509. /**
  3510. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  3511. */
  3512. static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
  3513. int tx_fifo, int sta_id, int tid,
  3514. u16 ssn_idx)
  3515. {
  3516. unsigned long flags;
  3517. int rc;
  3518. u16 ra_tid;
  3519. if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
  3520. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3521. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3522. ra_tid = BUILD_RAxTID(sta_id, tid);
  3523. iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
  3524. spin_lock_irqsave(&priv->lock, flags);
  3525. rc = iwl_grab_restricted_access(priv);
  3526. if (rc) {
  3527. spin_unlock_irqrestore(&priv->lock, flags);
  3528. return rc;
  3529. }
  3530. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3531. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  3532. iwl_set_bits_restricted_reg(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id));
  3533. priv->txq[txq_id].q.last_used = (ssn_idx & 0xff);
  3534. priv->txq[txq_id].q.first_empty = (ssn_idx & 0xff);
  3535. /* supposes that ssn_idx is valid (!= 0xFFF) */
  3536. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3537. iwl_write_restricted_mem(priv,
  3538. priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  3539. (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  3540. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  3541. iwl_write_restricted_mem(priv, priv->scd_base_addr +
  3542. SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  3543. (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  3544. & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  3545. iwl_set_bits_restricted_reg(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
  3546. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  3547. iwl_release_restricted_access(priv);
  3548. spin_unlock_irqrestore(&priv->lock, flags);
  3549. return 0;
  3550. }
  3551. /**
  3552. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  3553. */
  3554. static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
  3555. u16 ssn_idx, u8 tx_fifo)
  3556. {
  3557. unsigned long flags;
  3558. int rc;
  3559. if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
  3560. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3561. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3562. return -EINVAL;
  3563. }
  3564. spin_lock_irqsave(&priv->lock, flags);
  3565. rc = iwl_grab_restricted_access(priv);
  3566. if (rc) {
  3567. spin_unlock_irqrestore(&priv->lock, flags);
  3568. return rc;
  3569. }
  3570. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3571. iwl_clear_bits_restricted_reg(priv, SCD_QUEUECHAIN_SEL, (1 << txq_id));
  3572. priv->txq[txq_id].q.last_used = (ssn_idx & 0xff);
  3573. priv->txq[txq_id].q.first_empty = (ssn_idx & 0xff);
  3574. /* supposes that ssn_idx is valid (!= 0xFFF) */
  3575. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3576. iwl_clear_bits_restricted_reg(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
  3577. iwl4965_txq_ctx_deactivate(priv, txq_id);
  3578. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  3579. iwl_release_restricted_access(priv);
  3580. spin_unlock_irqrestore(&priv->lock, flags);
  3581. return 0;
  3582. }
  3583. #endif/* CONFIG_IWLWIFI_HT_AGG */
  3584. #endif /* CONFIG_IWLWIFI_HT */
  3585. /*
  3586. * RATE SCALE CODE
  3587. */
  3588. int iwl4965_init_hw_rates(struct iwl_priv *priv, struct ieee80211_rate *rates)
  3589. {
  3590. return 0;
  3591. }
  3592. /**
  3593. * iwl4965_add_station - Initialize a station's hardware rate table
  3594. *
  3595. * The uCode contains a table of fallback rates and retries per rate
  3596. * for automatic fallback during transmission.
  3597. *
  3598. * NOTE: This initializes the table for a single retry per data rate
  3599. * which is not optimal. Setting up an intelligent retry per rate
  3600. * requires feedback from transmission, which isn't exposed through
  3601. * rc80211_simple which is what this driver is currently using.
  3602. *
  3603. */
  3604. void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  3605. {
  3606. int i, r;
  3607. struct iwl_link_quality_cmd link_cmd = {
  3608. .reserved1 = 0,
  3609. };
  3610. u16 rate_flags;
  3611. /* Set up the rate scaling to start at 54M and fallback
  3612. * all the way to 1M in IEEE order and then spin on IEEE */
  3613. if (is_ap)
  3614. r = IWL_RATE_54M_INDEX;
  3615. else if (priv->phymode == MODE_IEEE80211A)
  3616. r = IWL_RATE_6M_INDEX;
  3617. else
  3618. r = IWL_RATE_1M_INDEX;
  3619. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  3620. rate_flags = 0;
  3621. if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
  3622. rate_flags |= RATE_MCS_CCK_MSK;
  3623. rate_flags |= RATE_MCS_ANT_B_MSK;
  3624. rate_flags &= ~RATE_MCS_ANT_A_MSK;
  3625. link_cmd.rs_table[i].rate_n_flags =
  3626. iwl_hw_set_rate_n_flags(iwl_rates[r].plcp, rate_flags);
  3627. r = iwl_get_prev_ieee_rate(r);
  3628. }
  3629. link_cmd.general_params.single_stream_ant_msk = 2;
  3630. link_cmd.general_params.dual_stream_ant_msk = 3;
  3631. link_cmd.agg_params.agg_dis_start_th = 3;
  3632. link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
  3633. /* Update the rate scaling for control frame Tx to AP */
  3634. link_cmd.sta_id = is_ap ? IWL_AP_ID : IWL4965_BROADCAST_ID;
  3635. iwl_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd),
  3636. &link_cmd);
  3637. }
  3638. #ifdef CONFIG_IWLWIFI_HT
  3639. static u8 iwl_is_channel_extension(struct iwl_priv *priv, int phymode,
  3640. u16 channel, u8 extension_chan_offset)
  3641. {
  3642. const struct iwl_channel_info *ch_info;
  3643. ch_info = iwl_get_channel_info(priv, phymode, channel);
  3644. if (!is_channel_valid(ch_info))
  3645. return 0;
  3646. if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO)
  3647. return 0;
  3648. if ((ch_info->fat_extension_channel == extension_chan_offset) ||
  3649. (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
  3650. return 1;
  3651. return 0;
  3652. }
  3653. static u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
  3654. const struct sta_ht_info *ht_info)
  3655. {
  3656. if (priv->channel_width != IWL_CHANNEL_WIDTH_40MHZ)
  3657. return 0;
  3658. if (ht_info->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ)
  3659. return 0;
  3660. if (ht_info->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO)
  3661. return 0;
  3662. /* no fat tx allowed on 2.4GHZ */
  3663. if (priv->phymode != MODE_IEEE80211A)
  3664. return 0;
  3665. return (iwl_is_channel_extension(priv, priv->phymode,
  3666. ht_info->control_channel,
  3667. ht_info->extension_chan_offset));
  3668. }
  3669. void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct sta_ht_info *ht_info)
  3670. {
  3671. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  3672. u32 val;
  3673. if (!ht_info->is_ht)
  3674. return;
  3675. if (iwl_is_fat_tx_allowed(priv, ht_info))
  3676. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3677. else
  3678. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
  3679. RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
  3680. if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
  3681. IWL_DEBUG_ASSOC("control diff than current %d %d\n",
  3682. le16_to_cpu(rxon->channel),
  3683. ht_info->control_channel);
  3684. rxon->channel = cpu_to_le16(ht_info->control_channel);
  3685. return;
  3686. }
  3687. /* Note: control channel is oposit to extension channel */
  3688. switch (ht_info->extension_chan_offset) {
  3689. case IWL_EXT_CHANNEL_OFFSET_ABOVE:
  3690. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3691. break;
  3692. case IWL_EXT_CHANNEL_OFFSET_BELOW:
  3693. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3694. break;
  3695. case IWL_EXT_CHANNEL_OFFSET_AUTO:
  3696. rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3697. break;
  3698. default:
  3699. rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3700. break;
  3701. }
  3702. val = ht_info->operating_mode;
  3703. rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
  3704. priv->active_rate_ht[0] = ht_info->supp_rates[0];
  3705. priv->active_rate_ht[1] = ht_info->supp_rates[1];
  3706. iwl4965_set_rxon_chain(priv);
  3707. IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
  3708. "rxon flags 0x%X operation mode :0x%X "
  3709. "extension channel offset 0x%x "
  3710. "control chan %d\n",
  3711. priv->active_rate_ht[0], priv->active_rate_ht[1],
  3712. le32_to_cpu(rxon->flags), ht_info->operating_mode,
  3713. ht_info->extension_chan_offset,
  3714. ht_info->control_channel);
  3715. return;
  3716. }
  3717. void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index)
  3718. {
  3719. __le32 sta_flags;
  3720. struct sta_ht_info *ht_info = &priv->current_assoc_ht;
  3721. priv->current_channel_width = IWL_CHANNEL_WIDTH_20MHZ;
  3722. if (!ht_info->is_ht)
  3723. goto done;
  3724. sta_flags = priv->stations[index].sta.station_flags;
  3725. if (ht_info->tx_mimo_ps_mode == IWL_MIMO_PS_DYNAMIC)
  3726. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  3727. else
  3728. sta_flags &= ~STA_FLG_RTS_MIMO_PROT_MSK;
  3729. sta_flags |= cpu_to_le32(
  3730. (u32)ht_info->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  3731. sta_flags |= cpu_to_le32(
  3732. (u32)ht_info->mpdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  3733. sta_flags &= (~STA_FLG_FAT_EN_MSK);
  3734. ht_info->tx_chan_width = IWL_CHANNEL_WIDTH_20MHZ;
  3735. ht_info->chan_width_cap = IWL_CHANNEL_WIDTH_20MHZ;
  3736. if (iwl_is_fat_tx_allowed(priv, ht_info)) {
  3737. sta_flags |= STA_FLG_FAT_EN_MSK;
  3738. ht_info->chan_width_cap = IWL_CHANNEL_WIDTH_40MHZ;
  3739. if (ht_info->supported_chan_width == IWL_CHANNEL_WIDTH_40MHZ)
  3740. ht_info->tx_chan_width = IWL_CHANNEL_WIDTH_40MHZ;
  3741. }
  3742. priv->current_channel_width = ht_info->tx_chan_width;
  3743. priv->stations[index].sta.station_flags = sta_flags;
  3744. done:
  3745. return;
  3746. }
  3747. #ifdef CONFIG_IWLWIFI_HT_AGG
  3748. static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv,
  3749. int sta_id, int tid, u16 ssn)
  3750. {
  3751. unsigned long flags;
  3752. spin_lock_irqsave(&priv->sta_lock, flags);
  3753. priv->stations[sta_id].sta.station_flags_msk = 0;
  3754. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  3755. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  3756. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  3757. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3758. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3759. iwl_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3760. }
  3761. static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv,
  3762. int sta_id, int tid)
  3763. {
  3764. unsigned long flags;
  3765. spin_lock_irqsave(&priv->sta_lock, flags);
  3766. priv->stations[sta_id].sta.station_flags_msk = 0;
  3767. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  3768. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  3769. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3770. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3771. iwl_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3772. }
  3773. static const u16 default_tid_to_tx_fifo[] = {
  3774. IWL_TX_FIFO_AC1,
  3775. IWL_TX_FIFO_AC0,
  3776. IWL_TX_FIFO_AC0,
  3777. IWL_TX_FIFO_AC1,
  3778. IWL_TX_FIFO_AC2,
  3779. IWL_TX_FIFO_AC2,
  3780. IWL_TX_FIFO_AC3,
  3781. IWL_TX_FIFO_AC3,
  3782. IWL_TX_FIFO_NONE,
  3783. IWL_TX_FIFO_NONE,
  3784. IWL_TX_FIFO_NONE,
  3785. IWL_TX_FIFO_NONE,
  3786. IWL_TX_FIFO_NONE,
  3787. IWL_TX_FIFO_NONE,
  3788. IWL_TX_FIFO_NONE,
  3789. IWL_TX_FIFO_NONE,
  3790. IWL_TX_FIFO_AC3
  3791. };
  3792. static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
  3793. {
  3794. int txq_id;
  3795. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  3796. if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
  3797. return txq_id;
  3798. return -1;
  3799. }
  3800. int iwl_mac_ht_tx_agg_start(struct ieee80211_hw *hw, u8 *da, u16 tid,
  3801. u16 *start_seq_num)
  3802. {
  3803. struct iwl_priv *priv = hw->priv;
  3804. int sta_id;
  3805. int tx_fifo;
  3806. int txq_id;
  3807. int ssn = -1;
  3808. unsigned long flags;
  3809. struct iwl_tid_data *tid_data;
  3810. DECLARE_MAC_BUF(mac);
  3811. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  3812. tx_fifo = default_tid_to_tx_fifo[tid];
  3813. else
  3814. return -EINVAL;
  3815. IWL_WARNING("iwl-AGG iwl_mac_ht_tx_agg_start on da=%s"
  3816. " tid=%d\n", print_mac(mac, da), tid);
  3817. sta_id = iwl_hw_find_station(priv, da);
  3818. if (sta_id == IWL_INVALID_STATION)
  3819. return -ENXIO;
  3820. txq_id = iwl_txq_ctx_activate_free(priv);
  3821. if (txq_id == -1)
  3822. return -ENXIO;
  3823. spin_lock_irqsave(&priv->sta_lock, flags);
  3824. tid_data = &priv->stations[sta_id].tid[tid];
  3825. ssn = SEQ_TO_SN(tid_data->seq_number);
  3826. tid_data->agg.txq_id = txq_id;
  3827. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3828. *start_seq_num = ssn;
  3829. iwl4965_ba_status(priv, tid, BA_STATUS_ACTIVE);
  3830. return iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
  3831. sta_id, tid, ssn);
  3832. }
  3833. int iwl_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, u8 *da, u16 tid,
  3834. int generator)
  3835. {
  3836. struct iwl_priv *priv = hw->priv;
  3837. int tx_fifo_id, txq_id, sta_id, ssn = -1;
  3838. struct iwl_tid_data *tid_data;
  3839. int rc;
  3840. DECLARE_MAC_BUF(mac);
  3841. if (!da) {
  3842. IWL_ERROR("%s: da = NULL\n", __func__);
  3843. return -EINVAL;
  3844. }
  3845. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  3846. tx_fifo_id = default_tid_to_tx_fifo[tid];
  3847. else
  3848. return -EINVAL;
  3849. sta_id = iwl_hw_find_station(priv, da);
  3850. if (sta_id == IWL_INVALID_STATION)
  3851. return -ENXIO;
  3852. tid_data = &priv->stations[sta_id].tid[tid];
  3853. ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
  3854. txq_id = tid_data->agg.txq_id;
  3855. rc = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
  3856. /* FIXME: need more safe way to handle error condition */
  3857. if (rc)
  3858. return rc;
  3859. iwl4965_ba_status(priv, tid, BA_STATUS_INITIATOR_DELBA);
  3860. IWL_DEBUG_INFO("iwl_mac_ht_tx_agg_stop on da=%s tid=%d\n",
  3861. print_mac(mac, da), tid);
  3862. return 0;
  3863. }
  3864. int iwl_mac_ht_rx_agg_start(struct ieee80211_hw *hw, u8 *da,
  3865. u16 tid, u16 start_seq_num)
  3866. {
  3867. struct iwl_priv *priv = hw->priv;
  3868. int sta_id;
  3869. DECLARE_MAC_BUF(mac);
  3870. IWL_WARNING("iwl-AGG iwl_mac_ht_rx_agg_start on da=%s"
  3871. " tid=%d\n", print_mac(mac, da), tid);
  3872. sta_id = iwl_hw_find_station(priv, da);
  3873. iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, start_seq_num);
  3874. return 0;
  3875. }
  3876. int iwl_mac_ht_rx_agg_stop(struct ieee80211_hw *hw, u8 *da,
  3877. u16 tid, int generator)
  3878. {
  3879. struct iwl_priv *priv = hw->priv;
  3880. int sta_id;
  3881. DECLARE_MAC_BUF(mac);
  3882. IWL_WARNING("iwl-AGG iwl_mac_ht_rx_agg_stop on da=%s tid=%d\n",
  3883. print_mac(mac, da), tid);
  3884. sta_id = iwl_hw_find_station(priv, da);
  3885. iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
  3886. return 0;
  3887. }
  3888. #endif /* CONFIG_IWLWIFI_HT_AGG */
  3889. #endif /* CONFIG_IWLWIFI_HT */
  3890. /* Set up 4965-specific Rx frame reply handlers */
  3891. void iwl_hw_rx_handler_setup(struct iwl_priv *priv)
  3892. {
  3893. /* Legacy Rx frames */
  3894. priv->rx_handlers[REPLY_4965_RX] = iwl4965_rx_reply_rx;
  3895. /* High-throughput (HT) Rx frames */
  3896. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
  3897. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
  3898. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  3899. iwl4965_rx_missed_beacon_notif;
  3900. #ifdef CONFIG_IWLWIFI_HT
  3901. #ifdef CONFIG_IWLWIFI_HT_AGG
  3902. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  3903. #endif /* CONFIG_IWLWIFI_AGG */
  3904. #endif /* CONFIG_IWLWIFI */
  3905. }
  3906. void iwl_hw_setup_deferred_work(struct iwl_priv *priv)
  3907. {
  3908. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  3909. INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
  3910. #ifdef CONFIG_IWLWIFI_SENSITIVITY
  3911. INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
  3912. #endif
  3913. #ifdef CONFIG_IWLWIFI_HT
  3914. #ifdef CONFIG_IWLWIFI_HT_AGG
  3915. INIT_WORK(&priv->agg_work, iwl4965_bg_agg_work);
  3916. #endif /* CONFIG_IWLWIFI_AGG */
  3917. #endif /* CONFIG_IWLWIFI_HT */
  3918. init_timer(&priv->statistics_periodic);
  3919. priv->statistics_periodic.data = (unsigned long)priv;
  3920. priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
  3921. }
  3922. void iwl_hw_cancel_deferred_work(struct iwl_priv *priv)
  3923. {
  3924. del_timer_sync(&priv->statistics_periodic);
  3925. cancel_delayed_work(&priv->init_alive_start);
  3926. }
  3927. struct pci_device_id iwl_hw_card_ids[] = {
  3928. {0x8086, 0x4229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  3929. {0x8086, 0x4230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  3930. {0}
  3931. };
  3932. int iwl_eeprom_aqcuire_semaphore(struct iwl_priv *priv)
  3933. {
  3934. u16 count;
  3935. int rc;
  3936. for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
  3937. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  3938. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
  3939. rc = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  3940. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
  3941. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
  3942. EEPROM_SEM_TIMEOUT);
  3943. if (rc >= 0) {
  3944. IWL_DEBUG_IO("Aqcuired semaphore after %d tries.\n",
  3945. count+1);
  3946. return rc;
  3947. }
  3948. }
  3949. return rc;
  3950. }
  3951. inline void iwl_eeprom_release_semaphore(struct iwl_priv *priv)
  3952. {
  3953. iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
  3954. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
  3955. }
  3956. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);