iTCO_wdt.c 24 KB

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  1. /*
  2. * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets)
  3. *
  4. * (c) Copyright 2006-2007 Wim Van Sebroeck <wim@iguana.be>.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
  12. * provide warranty for any of this software. This material is
  13. * provided "AS-IS" and at no charge.
  14. *
  15. * The TCO watchdog is implemented in the following I/O controller hubs:
  16. * (See the intel documentation on http://developer.intel.com.)
  17. * 82801AA (ICH) : document number 290655-003, 290677-014,
  18. * 82801AB (ICHO) : document number 290655-003, 290677-014,
  19. * 82801BA (ICH2) : document number 290687-002, 298242-027,
  20. * 82801BAM (ICH2-M) : document number 290687-002, 298242-027,
  21. * 82801CA (ICH3-S) : document number 290733-003, 290739-013,
  22. * 82801CAM (ICH3-M) : document number 290716-001, 290718-007,
  23. * 82801DB (ICH4) : document number 290744-001, 290745-020,
  24. * 82801DBM (ICH4-M) : document number 252337-001, 252663-005,
  25. * 82801E (C-ICH) : document number 273599-001, 273645-002,
  26. * 82801EB (ICH5) : document number 252516-001, 252517-003,
  27. * 82801ER (ICH5R) : document number 252516-001, 252517-003,
  28. * 82801FB (ICH6) : document number 301473-002, 301474-007,
  29. * 82801FR (ICH6R) : document number 301473-002, 301474-007,
  30. * 82801FBM (ICH6-M) : document number 301473-002, 301474-007,
  31. * 82801FW (ICH6W) : document number 301473-001, 301474-007,
  32. * 82801FRW (ICH6RW) : document number 301473-001, 301474-007,
  33. * 82801GB (ICH7) : document number 307013-002, 307014-009,
  34. * 82801GR (ICH7R) : document number 307013-002, 307014-009,
  35. * 82801GDH (ICH7DH) : document number 307013-002, 307014-009,
  36. * 82801GBM (ICH7-M) : document number 307013-002, 307014-009,
  37. * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009,
  38. * 82801HB (ICH8) : document number 313056-002, 313057-004,
  39. * 82801HR (ICH8R) : document number 313056-002, 313057-004,
  40. * 82801HH (ICH8DH) : document number 313056-002, 313057-004,
  41. * 82801HO (ICH8DO) : document number 313056-002, 313057-004,
  42. * 82801IB (ICH9) : document number 316972-001, 316973-001,
  43. * 82801IR (ICH9R) : document number 316972-001, 316973-001,
  44. * 82801IH (ICH9DH) : document number 316972-001, 316973-001,
  45. * 6300ESB (6300ESB) : document number 300641-003, 300884-010,
  46. * 631xESB (631xESB) : document number 313082-001, 313075-005,
  47. * 632xESB (632xESB) : document number 313082-001, 313075-005
  48. */
  49. /*
  50. * Includes, defines, variables, module parameters, ...
  51. */
  52. /* Module and version information */
  53. #define DRV_NAME "iTCO_wdt"
  54. #define DRV_VERSION "1.02"
  55. #define DRV_RELDATE "26-Jul-2007"
  56. #define PFX DRV_NAME ": "
  57. /* Includes */
  58. #include <linux/module.h> /* For module specific items */
  59. #include <linux/moduleparam.h> /* For new moduleparam's */
  60. #include <linux/types.h> /* For standard types (like size_t) */
  61. #include <linux/errno.h> /* For the -ENODEV/... values */
  62. #include <linux/kernel.h> /* For printk/panic/... */
  63. #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */
  64. #include <linux/watchdog.h> /* For the watchdog specific items */
  65. #include <linux/init.h> /* For __init/__exit/... */
  66. #include <linux/fs.h> /* For file operations */
  67. #include <linux/platform_device.h> /* For platform_driver framework */
  68. #include <linux/pci.h> /* For pci functions */
  69. #include <linux/ioport.h> /* For io-port access */
  70. #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
  71. #include <asm/uaccess.h> /* For copy_to_user/put_user/... */
  72. #include <asm/io.h> /* For inb/outb/... */
  73. /* TCO related info */
  74. enum iTCO_chipsets {
  75. TCO_ICH = 0, /* ICH */
  76. TCO_ICH0, /* ICH0 */
  77. TCO_ICH2, /* ICH2 */
  78. TCO_ICH2M, /* ICH2-M */
  79. TCO_ICH3, /* ICH3-S */
  80. TCO_ICH3M, /* ICH3-M */
  81. TCO_ICH4, /* ICH4 */
  82. TCO_ICH4M, /* ICH4-M */
  83. TCO_CICH, /* C-ICH */
  84. TCO_ICH5, /* ICH5 & ICH5R */
  85. TCO_6300ESB, /* 6300ESB */
  86. TCO_ICH6, /* ICH6 & ICH6R */
  87. TCO_ICH6M, /* ICH6-M */
  88. TCO_ICH6W, /* ICH6W & ICH6RW */
  89. TCO_ICH7, /* ICH7 & ICH7R */
  90. TCO_ICH7M, /* ICH7-M */
  91. TCO_ICH7MDH, /* ICH7-M DH */
  92. TCO_ICH8, /* ICH8 & ICH8R */
  93. TCO_ICH8DH, /* ICH8DH */
  94. TCO_ICH8DO, /* ICH8DO */
  95. TCO_ICH9, /* ICH9 */
  96. TCO_ICH9R, /* ICH9R */
  97. TCO_ICH9DH, /* ICH9DH */
  98. TCO_631XESB, /* 631xESB/632xESB */
  99. };
  100. static struct {
  101. char *name;
  102. unsigned int iTCO_version;
  103. } iTCO_chipset_info[] __devinitdata = {
  104. {"ICH", 1},
  105. {"ICH0", 1},
  106. {"ICH2", 1},
  107. {"ICH2-M", 1},
  108. {"ICH3-S", 1},
  109. {"ICH3-M", 1},
  110. {"ICH4", 1},
  111. {"ICH4-M", 1},
  112. {"C-ICH", 1},
  113. {"ICH5 or ICH5R", 1},
  114. {"6300ESB", 1},
  115. {"ICH6 or ICH6R", 2},
  116. {"ICH6-M", 2},
  117. {"ICH6W or ICH6RW", 2},
  118. {"ICH7 or ICH7R", 2},
  119. {"ICH7-M", 2},
  120. {"ICH7-M DH", 2},
  121. {"ICH8 or ICH8R", 2},
  122. {"ICH8DH", 2},
  123. {"ICH8DO", 2},
  124. {"ICH9", 2},
  125. {"ICH9R", 2},
  126. {"ICH9DH", 2},
  127. {"631xESB/632xESB", 2},
  128. {NULL,0}
  129. };
  130. /*
  131. * This data only exists for exporting the supported PCI ids
  132. * via MODULE_DEVICE_TABLE. We do not actually register a
  133. * pci_driver, because the I/O Controller Hub has also other
  134. * functions that probably will be registered by other drivers.
  135. */
  136. static struct pci_device_id iTCO_wdt_pci_tbl[] = {
  137. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH },
  138. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH0 },
  139. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH2 },
  140. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH2M },
  141. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH3 },
  142. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH3M },
  143. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH4 },
  144. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH4M },
  145. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_CICH },
  146. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH5 },
  147. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_6300ESB },
  148. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH6 },
  149. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH6M },
  150. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH6W },
  151. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH7 },
  152. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH7M },
  153. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH7MDH },
  154. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8 },
  155. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8DH },
  156. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8DO },
  157. { PCI_VENDOR_ID_INTEL, 0x2918, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH9 },
  158. { PCI_VENDOR_ID_INTEL, 0x2916, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH9R },
  159. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH9DH },
  160. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  161. { PCI_VENDOR_ID_INTEL, 0x2671, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  162. { PCI_VENDOR_ID_INTEL, 0x2672, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  163. { PCI_VENDOR_ID_INTEL, 0x2673, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  164. { PCI_VENDOR_ID_INTEL, 0x2674, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  165. { PCI_VENDOR_ID_INTEL, 0x2675, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  166. { PCI_VENDOR_ID_INTEL, 0x2676, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  167. { PCI_VENDOR_ID_INTEL, 0x2677, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  168. { PCI_VENDOR_ID_INTEL, 0x2678, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  169. { PCI_VENDOR_ID_INTEL, 0x2679, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  170. { PCI_VENDOR_ID_INTEL, 0x267a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  171. { PCI_VENDOR_ID_INTEL, 0x267b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  172. { PCI_VENDOR_ID_INTEL, 0x267c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  173. { PCI_VENDOR_ID_INTEL, 0x267d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  174. { PCI_VENDOR_ID_INTEL, 0x267e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  175. { PCI_VENDOR_ID_INTEL, 0x267f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_631XESB },
  176. { 0, }, /* End of list */
  177. };
  178. MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl);
  179. /* Address definitions for the TCO */
  180. #define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 /* TCO base address */
  181. #define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 /* SMI Control and Enable Register */
  182. #define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Current Value */
  183. #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
  184. #define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
  185. #define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
  186. #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
  187. #define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
  188. #define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
  189. #define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
  190. #define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
  191. /* internal variables */
  192. static unsigned long is_active;
  193. static char expect_release;
  194. static struct { /* this is private data for the iTCO_wdt device */
  195. unsigned int iTCO_version; /* TCO version/generation */
  196. unsigned long ACPIBASE; /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
  197. unsigned long __iomem *gcs; /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2) */
  198. spinlock_t io_lock; /* the lock for io operations */
  199. struct pci_dev *pdev; /* the PCI-device */
  200. } iTCO_wdt_private;
  201. static struct platform_device *iTCO_wdt_platform_device; /* the watchdog platform device */
  202. /* module parameters */
  203. #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
  204. static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
  205. module_param(heartbeat, int, 0);
  206. MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
  207. static int nowayout = WATCHDOG_NOWAYOUT;
  208. module_param(nowayout, int, 0);
  209. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  210. /* iTCO Vendor Specific Support hooks */
  211. #ifdef CONFIG_ITCO_VENDOR_SUPPORT
  212. extern void iTCO_vendor_pre_start(unsigned long, unsigned int);
  213. extern void iTCO_vendor_pre_stop(unsigned long);
  214. extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int);
  215. extern void iTCO_vendor_pre_set_heartbeat(unsigned int);
  216. extern int iTCO_vendor_check_noreboot_on(void);
  217. #else
  218. #define iTCO_vendor_pre_start(acpibase, heartbeat) {}
  219. #define iTCO_vendor_pre_stop(acpibase) {}
  220. #define iTCO_vendor_pre_keepalive(acpibase,heartbeat) {}
  221. #define iTCO_vendor_pre_set_heartbeat(heartbeat) {}
  222. #define iTCO_vendor_check_noreboot_on() 1 /* 1=check noreboot; 0=don't check */
  223. #endif
  224. /*
  225. * Some TCO specific functions
  226. */
  227. static inline unsigned int seconds_to_ticks(int seconds)
  228. {
  229. /* the internal timer is stored as ticks which decrement
  230. * every 0.6 seconds */
  231. return (seconds * 10) / 6;
  232. }
  233. static void iTCO_wdt_set_NO_REBOOT_bit(void)
  234. {
  235. u32 val32;
  236. /* Set the NO_REBOOT bit: this disables reboots */
  237. if (iTCO_wdt_private.iTCO_version == 2) {
  238. val32 = readl(iTCO_wdt_private.gcs);
  239. val32 |= 0x00000020;
  240. writel(val32, iTCO_wdt_private.gcs);
  241. } else if (iTCO_wdt_private.iTCO_version == 1) {
  242. pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
  243. val32 |= 0x00000002;
  244. pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
  245. }
  246. }
  247. static int iTCO_wdt_unset_NO_REBOOT_bit(void)
  248. {
  249. int ret = 0;
  250. u32 val32;
  251. /* Unset the NO_REBOOT bit: this enables reboots */
  252. if (iTCO_wdt_private.iTCO_version == 2) {
  253. val32 = readl(iTCO_wdt_private.gcs);
  254. val32 &= 0xffffffdf;
  255. writel(val32, iTCO_wdt_private.gcs);
  256. val32 = readl(iTCO_wdt_private.gcs);
  257. if (val32 & 0x00000020)
  258. ret = -EIO;
  259. } else if (iTCO_wdt_private.iTCO_version == 1) {
  260. pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
  261. val32 &= 0xfffffffd;
  262. pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
  263. pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
  264. if (val32 & 0x00000002)
  265. ret = -EIO;
  266. }
  267. return ret; /* returns: 0 = OK, -EIO = Error */
  268. }
  269. static int iTCO_wdt_start(void)
  270. {
  271. unsigned int val;
  272. spin_lock(&iTCO_wdt_private.io_lock);
  273. iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
  274. /* disable chipset's NO_REBOOT bit */
  275. if (iTCO_wdt_unset_NO_REBOOT_bit()) {
  276. printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
  277. return -EIO;
  278. }
  279. /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
  280. val = inw(TCO1_CNT);
  281. val &= 0xf7ff;
  282. outw(val, TCO1_CNT);
  283. val = inw(TCO1_CNT);
  284. spin_unlock(&iTCO_wdt_private.io_lock);
  285. if (val & 0x0800)
  286. return -1;
  287. return 0;
  288. }
  289. static int iTCO_wdt_stop(void)
  290. {
  291. unsigned int val;
  292. spin_lock(&iTCO_wdt_private.io_lock);
  293. iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
  294. /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
  295. val = inw(TCO1_CNT);
  296. val |= 0x0800;
  297. outw(val, TCO1_CNT);
  298. val = inw(TCO1_CNT);
  299. /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
  300. iTCO_wdt_set_NO_REBOOT_bit();
  301. spin_unlock(&iTCO_wdt_private.io_lock);
  302. if ((val & 0x0800) == 0)
  303. return -1;
  304. return 0;
  305. }
  306. static int iTCO_wdt_keepalive(void)
  307. {
  308. spin_lock(&iTCO_wdt_private.io_lock);
  309. iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
  310. /* Reload the timer by writing to the TCO Timer Counter register */
  311. if (iTCO_wdt_private.iTCO_version == 2) {
  312. outw(0x01, TCO_RLD);
  313. } else if (iTCO_wdt_private.iTCO_version == 1) {
  314. outb(0x01, TCO_RLD);
  315. }
  316. spin_unlock(&iTCO_wdt_private.io_lock);
  317. return 0;
  318. }
  319. static int iTCO_wdt_set_heartbeat(int t)
  320. {
  321. unsigned int val16;
  322. unsigned char val8;
  323. unsigned int tmrval;
  324. tmrval = seconds_to_ticks(t);
  325. /* from the specs: */
  326. /* "Values of 0h-3h are ignored and should not be attempted" */
  327. if (tmrval < 0x04)
  328. return -EINVAL;
  329. if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
  330. ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
  331. return -EINVAL;
  332. iTCO_vendor_pre_set_heartbeat(tmrval);
  333. /* Write new heartbeat to watchdog */
  334. if (iTCO_wdt_private.iTCO_version == 2) {
  335. spin_lock(&iTCO_wdt_private.io_lock);
  336. val16 = inw(TCOv2_TMR);
  337. val16 &= 0xfc00;
  338. val16 |= tmrval;
  339. outw(val16, TCOv2_TMR);
  340. val16 = inw(TCOv2_TMR);
  341. spin_unlock(&iTCO_wdt_private.io_lock);
  342. if ((val16 & 0x3ff) != tmrval)
  343. return -EINVAL;
  344. } else if (iTCO_wdt_private.iTCO_version == 1) {
  345. spin_lock(&iTCO_wdt_private.io_lock);
  346. val8 = inb(TCOv1_TMR);
  347. val8 &= 0xc0;
  348. val8 |= (tmrval & 0xff);
  349. outb(val8, TCOv1_TMR);
  350. val8 = inb(TCOv1_TMR);
  351. spin_unlock(&iTCO_wdt_private.io_lock);
  352. if ((val8 & 0x3f) != tmrval)
  353. return -EINVAL;
  354. }
  355. heartbeat = t;
  356. return 0;
  357. }
  358. static int iTCO_wdt_get_timeleft (int *time_left)
  359. {
  360. unsigned int val16;
  361. unsigned char val8;
  362. /* read the TCO Timer */
  363. if (iTCO_wdt_private.iTCO_version == 2) {
  364. spin_lock(&iTCO_wdt_private.io_lock);
  365. val16 = inw(TCO_RLD);
  366. val16 &= 0x3ff;
  367. spin_unlock(&iTCO_wdt_private.io_lock);
  368. *time_left = (val16 * 6) / 10;
  369. } else if (iTCO_wdt_private.iTCO_version == 1) {
  370. spin_lock(&iTCO_wdt_private.io_lock);
  371. val8 = inb(TCO_RLD);
  372. val8 &= 0x3f;
  373. spin_unlock(&iTCO_wdt_private.io_lock);
  374. *time_left = (val8 * 6) / 10;
  375. } else
  376. return -EINVAL;
  377. return 0;
  378. }
  379. /*
  380. * /dev/watchdog handling
  381. */
  382. static int iTCO_wdt_open (struct inode *inode, struct file *file)
  383. {
  384. /* /dev/watchdog can only be opened once */
  385. if (test_and_set_bit(0, &is_active))
  386. return -EBUSY;
  387. /*
  388. * Reload and activate timer
  389. */
  390. iTCO_wdt_keepalive();
  391. iTCO_wdt_start();
  392. return nonseekable_open(inode, file);
  393. }
  394. static int iTCO_wdt_release (struct inode *inode, struct file *file)
  395. {
  396. /*
  397. * Shut off the timer.
  398. */
  399. if (expect_release == 42) {
  400. iTCO_wdt_stop();
  401. } else {
  402. printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n");
  403. iTCO_wdt_keepalive();
  404. }
  405. clear_bit(0, &is_active);
  406. expect_release = 0;
  407. return 0;
  408. }
  409. static ssize_t iTCO_wdt_write (struct file *file, const char __user *data,
  410. size_t len, loff_t * ppos)
  411. {
  412. /* See if we got the magic character 'V' and reload the timer */
  413. if (len) {
  414. if (!nowayout) {
  415. size_t i;
  416. /* note: just in case someone wrote the magic character
  417. * five months ago... */
  418. expect_release = 0;
  419. /* scan to see whether or not we got the magic character */
  420. for (i = 0; i != len; i++) {
  421. char c;
  422. if (get_user(c, data+i))
  423. return -EFAULT;
  424. if (c == 'V')
  425. expect_release = 42;
  426. }
  427. }
  428. /* someone wrote to us, we should reload the timer */
  429. iTCO_wdt_keepalive();
  430. }
  431. return len;
  432. }
  433. static int iTCO_wdt_ioctl (struct inode *inode, struct file *file,
  434. unsigned int cmd, unsigned long arg)
  435. {
  436. int new_options, retval = -EINVAL;
  437. int new_heartbeat;
  438. void __user *argp = (void __user *)arg;
  439. int __user *p = argp;
  440. static struct watchdog_info ident = {
  441. .options = WDIOF_SETTIMEOUT |
  442. WDIOF_KEEPALIVEPING |
  443. WDIOF_MAGICCLOSE,
  444. .firmware_version = 0,
  445. .identity = DRV_NAME,
  446. };
  447. switch (cmd) {
  448. case WDIOC_GETSUPPORT:
  449. return copy_to_user(argp, &ident,
  450. sizeof (ident)) ? -EFAULT : 0;
  451. case WDIOC_GETSTATUS:
  452. case WDIOC_GETBOOTSTATUS:
  453. return put_user(0, p);
  454. case WDIOC_KEEPALIVE:
  455. iTCO_wdt_keepalive();
  456. return 0;
  457. case WDIOC_SETOPTIONS:
  458. {
  459. if (get_user(new_options, p))
  460. return -EFAULT;
  461. if (new_options & WDIOS_DISABLECARD) {
  462. iTCO_wdt_stop();
  463. retval = 0;
  464. }
  465. if (new_options & WDIOS_ENABLECARD) {
  466. iTCO_wdt_keepalive();
  467. iTCO_wdt_start();
  468. retval = 0;
  469. }
  470. return retval;
  471. }
  472. case WDIOC_SETTIMEOUT:
  473. {
  474. if (get_user(new_heartbeat, p))
  475. return -EFAULT;
  476. if (iTCO_wdt_set_heartbeat(new_heartbeat))
  477. return -EINVAL;
  478. iTCO_wdt_keepalive();
  479. /* Fall */
  480. }
  481. case WDIOC_GETTIMEOUT:
  482. return put_user(heartbeat, p);
  483. case WDIOC_GETTIMELEFT:
  484. {
  485. int time_left;
  486. if (iTCO_wdt_get_timeleft(&time_left))
  487. return -EINVAL;
  488. return put_user(time_left, p);
  489. }
  490. default:
  491. return -ENOTTY;
  492. }
  493. }
  494. /*
  495. * Kernel Interfaces
  496. */
  497. static const struct file_operations iTCO_wdt_fops = {
  498. .owner = THIS_MODULE,
  499. .llseek = no_llseek,
  500. .write = iTCO_wdt_write,
  501. .ioctl = iTCO_wdt_ioctl,
  502. .open = iTCO_wdt_open,
  503. .release = iTCO_wdt_release,
  504. };
  505. static struct miscdevice iTCO_wdt_miscdev = {
  506. .minor = WATCHDOG_MINOR,
  507. .name = "watchdog",
  508. .fops = &iTCO_wdt_fops,
  509. };
  510. /*
  511. * Init & exit routines
  512. */
  513. static int iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device_id *ent, struct platform_device *dev)
  514. {
  515. int ret;
  516. u32 base_address;
  517. unsigned long RCBA;
  518. unsigned long val32;
  519. /*
  520. * Find the ACPI/PM base I/O address which is the base
  521. * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
  522. * ACPIBASE is bits [15:7] from 0x40-0x43
  523. */
  524. pci_read_config_dword(pdev, 0x40, &base_address);
  525. base_address &= 0x0000ff80;
  526. if (base_address == 0x00000000) {
  527. /* Something's wrong here, ACPIBASE has to be set */
  528. printk(KERN_ERR PFX "failed to get TCOBASE address\n");
  529. pci_dev_put(pdev);
  530. return -ENODEV;
  531. }
  532. iTCO_wdt_private.iTCO_version = iTCO_chipset_info[ent->driver_data].iTCO_version;
  533. iTCO_wdt_private.ACPIBASE = base_address;
  534. iTCO_wdt_private.pdev = pdev;
  535. /* Get the Memory-Mapped GCS register, we need it for the NO_REBOOT flag (TCO v2) */
  536. /* To get access to it you have to read RCBA from PCI Config space 0xf0
  537. and use it as base. GCS = RCBA + ICH6_GCS(0x3410). */
  538. if (iTCO_wdt_private.iTCO_version == 2) {
  539. pci_read_config_dword(pdev, 0xf0, &base_address);
  540. RCBA = base_address & 0xffffc000;
  541. iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410),4);
  542. }
  543. /* Check chipset's NO_REBOOT bit */
  544. if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
  545. printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
  546. ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
  547. goto out;
  548. }
  549. /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
  550. iTCO_wdt_set_NO_REBOOT_bit();
  551. /* Set the TCO_EN bit in SMI_EN register */
  552. if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
  553. printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
  554. SMI_EN );
  555. ret = -EIO;
  556. goto out;
  557. }
  558. val32 = inl(SMI_EN);
  559. val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
  560. outl(val32, SMI_EN);
  561. release_region(SMI_EN, 4);
  562. /* The TCO I/O registers reside in a 32-byte range pointed to by the TCOBASE value */
  563. if (!request_region (TCOBASE, 0x20, "iTCO_wdt")) {
  564. printk (KERN_ERR PFX "I/O address 0x%04lx already in use\n",
  565. TCOBASE);
  566. ret = -EIO;
  567. goto out;
  568. }
  569. printk(KERN_INFO PFX "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
  570. iTCO_chipset_info[ent->driver_data].name,
  571. iTCO_chipset_info[ent->driver_data].iTCO_version,
  572. TCOBASE);
  573. /* Clear out the (probably old) status */
  574. outb(0, TCO1_STS);
  575. outb(3, TCO2_STS);
  576. /* Make sure the watchdog is not running */
  577. iTCO_wdt_stop();
  578. /* Check that the heartbeat value is within it's range ; if not reset to the default */
  579. if (iTCO_wdt_set_heartbeat(heartbeat)) {
  580. iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
  581. printk(KERN_INFO PFX "heartbeat value must be 2<heartbeat<39 (TCO v1) or 613 (TCO v2), using %d\n",
  582. heartbeat);
  583. }
  584. ret = misc_register(&iTCO_wdt_miscdev);
  585. if (ret != 0) {
  586. printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n",
  587. WATCHDOG_MINOR, ret);
  588. goto unreg_region;
  589. }
  590. printk (KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
  591. heartbeat, nowayout);
  592. return 0;
  593. unreg_region:
  594. release_region (TCOBASE, 0x20);
  595. out:
  596. if (iTCO_wdt_private.iTCO_version == 2)
  597. iounmap(iTCO_wdt_private.gcs);
  598. pci_dev_put(iTCO_wdt_private.pdev);
  599. iTCO_wdt_private.ACPIBASE = 0;
  600. return ret;
  601. }
  602. static void iTCO_wdt_cleanup(void)
  603. {
  604. /* Stop the timer before we leave */
  605. if (!nowayout)
  606. iTCO_wdt_stop();
  607. /* Deregister */
  608. misc_deregister(&iTCO_wdt_miscdev);
  609. release_region(TCOBASE, 0x20);
  610. if (iTCO_wdt_private.iTCO_version == 2)
  611. iounmap(iTCO_wdt_private.gcs);
  612. pci_dev_put(iTCO_wdt_private.pdev);
  613. iTCO_wdt_private.ACPIBASE = 0;
  614. }
  615. static int iTCO_wdt_probe(struct platform_device *dev)
  616. {
  617. int found = 0;
  618. struct pci_dev *pdev = NULL;
  619. const struct pci_device_id *ent;
  620. spin_lock_init(&iTCO_wdt_private.io_lock);
  621. for_each_pci_dev(pdev) {
  622. ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
  623. if (ent) {
  624. if (!(iTCO_wdt_init(pdev, ent, dev))) {
  625. found++;
  626. break;
  627. }
  628. }
  629. }
  630. if (!found) {
  631. printk(KERN_INFO PFX "No card detected\n");
  632. return -ENODEV;
  633. }
  634. return 0;
  635. }
  636. static int iTCO_wdt_remove(struct platform_device *dev)
  637. {
  638. if (iTCO_wdt_private.ACPIBASE)
  639. iTCO_wdt_cleanup();
  640. return 0;
  641. }
  642. static void iTCO_wdt_shutdown(struct platform_device *dev)
  643. {
  644. iTCO_wdt_stop();
  645. }
  646. #define iTCO_wdt_suspend NULL
  647. #define iTCO_wdt_resume NULL
  648. static struct platform_driver iTCO_wdt_driver = {
  649. .probe = iTCO_wdt_probe,
  650. .remove = iTCO_wdt_remove,
  651. .shutdown = iTCO_wdt_shutdown,
  652. .suspend = iTCO_wdt_suspend,
  653. .resume = iTCO_wdt_resume,
  654. .driver = {
  655. .owner = THIS_MODULE,
  656. .name = DRV_NAME,
  657. },
  658. };
  659. static int __init iTCO_wdt_init_module(void)
  660. {
  661. int err;
  662. printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s (%s)\n",
  663. DRV_VERSION, DRV_RELDATE);
  664. err = platform_driver_register(&iTCO_wdt_driver);
  665. if (err)
  666. return err;
  667. iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0);
  668. if (IS_ERR(iTCO_wdt_platform_device)) {
  669. err = PTR_ERR(iTCO_wdt_platform_device);
  670. goto unreg_platform_driver;
  671. }
  672. return 0;
  673. unreg_platform_driver:
  674. platform_driver_unregister(&iTCO_wdt_driver);
  675. return err;
  676. }
  677. static void __exit iTCO_wdt_cleanup_module(void)
  678. {
  679. platform_device_unregister(iTCO_wdt_platform_device);
  680. platform_driver_unregister(&iTCO_wdt_driver);
  681. printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
  682. }
  683. module_init(iTCO_wdt_init_module);
  684. module_exit(iTCO_wdt_cleanup_module);
  685. MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
  686. MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
  687. MODULE_VERSION(DRV_VERSION);
  688. MODULE_LICENSE("GPL");
  689. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);