cpu5wdt.c 6.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304
  1. /*
  2. * sma cpu5 watchdog driver
  3. *
  4. * Copyright (C) 2003 Heiko Ronsdorf <hero@ihg.uni-duisburg.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/types.h>
  24. #include <linux/errno.h>
  25. #include <linux/miscdevice.h>
  26. #include <linux/fs.h>
  27. #include <linux/init.h>
  28. #include <linux/ioport.h>
  29. #include <linux/timer.h>
  30. #include <linux/completion.h>
  31. #include <linux/jiffies.h>
  32. #include <asm/io.h>
  33. #include <asm/uaccess.h>
  34. #include <linux/watchdog.h>
  35. /* adjustable parameters */
  36. static int verbose = 0;
  37. static int port = 0x91;
  38. static int ticks = 10000;
  39. #define PFX "cpu5wdt: "
  40. #define CPU5WDT_EXTENT 0x0A
  41. #define CPU5WDT_STATUS_REG 0x00
  42. #define CPU5WDT_TIME_A_REG 0x02
  43. #define CPU5WDT_TIME_B_REG 0x03
  44. #define CPU5WDT_MODE_REG 0x04
  45. #define CPU5WDT_TRIGGER_REG 0x07
  46. #define CPU5WDT_ENABLE_REG 0x08
  47. #define CPU5WDT_RESET_REG 0x09
  48. #define CPU5WDT_INTERVAL (HZ/10+1)
  49. /* some device data */
  50. static struct {
  51. struct completion stop;
  52. volatile int running;
  53. struct timer_list timer;
  54. volatile int queue;
  55. int default_ticks;
  56. unsigned long inuse;
  57. } cpu5wdt_device;
  58. /* generic helper functions */
  59. static void cpu5wdt_trigger(unsigned long unused)
  60. {
  61. if ( verbose > 2 )
  62. printk(KERN_DEBUG PFX "trigger at %i ticks\n", ticks);
  63. if( cpu5wdt_device.running )
  64. ticks--;
  65. /* keep watchdog alive */
  66. outb(1, port + CPU5WDT_TRIGGER_REG);
  67. /* requeue?? */
  68. if (cpu5wdt_device.queue && ticks)
  69. mod_timer(&cpu5wdt_device.timer, jiffies + CPU5WDT_INTERVAL);
  70. else {
  71. /* ticks doesn't matter anyway */
  72. complete(&cpu5wdt_device.stop);
  73. }
  74. }
  75. static void cpu5wdt_reset(void)
  76. {
  77. ticks = cpu5wdt_device.default_ticks;
  78. if ( verbose )
  79. printk(KERN_DEBUG PFX "reset (%i ticks)\n", (int) ticks);
  80. }
  81. static void cpu5wdt_start(void)
  82. {
  83. if ( !cpu5wdt_device.queue ) {
  84. cpu5wdt_device.queue = 1;
  85. outb(0, port + CPU5WDT_TIME_A_REG);
  86. outb(0, port + CPU5WDT_TIME_B_REG);
  87. outb(1, port + CPU5WDT_MODE_REG);
  88. outb(0, port + CPU5WDT_RESET_REG);
  89. outb(0, port + CPU5WDT_ENABLE_REG);
  90. mod_timer(&cpu5wdt_device.timer, jiffies + CPU5WDT_INTERVAL);
  91. }
  92. /* if process dies, counter is not decremented */
  93. cpu5wdt_device.running++;
  94. }
  95. static int cpu5wdt_stop(void)
  96. {
  97. if ( cpu5wdt_device.running )
  98. cpu5wdt_device.running = 0;
  99. ticks = cpu5wdt_device.default_ticks;
  100. if ( verbose )
  101. printk(KERN_CRIT PFX "stop not possible\n");
  102. return -EIO;
  103. }
  104. /* filesystem operations */
  105. static int cpu5wdt_open(struct inode *inode, struct file *file)
  106. {
  107. if ( test_and_set_bit(0, &cpu5wdt_device.inuse) )
  108. return -EBUSY;
  109. return nonseekable_open(inode, file);
  110. }
  111. static int cpu5wdt_release(struct inode *inode, struct file *file)
  112. {
  113. clear_bit(0, &cpu5wdt_device.inuse);
  114. return 0;
  115. }
  116. static int cpu5wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  117. {
  118. void __user *argp = (void __user *)arg;
  119. unsigned int value;
  120. static struct watchdog_info ident =
  121. {
  122. .options = WDIOF_CARDRESET,
  123. .identity = "CPU5 WDT",
  124. };
  125. switch(cmd) {
  126. case WDIOC_KEEPALIVE:
  127. cpu5wdt_reset();
  128. break;
  129. case WDIOC_GETSTATUS:
  130. value = inb(port + CPU5WDT_STATUS_REG);
  131. value = (value >> 2) & 1;
  132. if ( copy_to_user(argp, &value, sizeof(int)) )
  133. return -EFAULT;
  134. break;
  135. case WDIOC_GETBOOTSTATUS:
  136. if ( copy_to_user(argp, &value, sizeof(int)) )
  137. return -EFAULT;
  138. break;
  139. case WDIOC_GETSUPPORT:
  140. if ( copy_to_user(argp, &ident, sizeof(ident)) )
  141. return -EFAULT;
  142. break;
  143. case WDIOC_SETOPTIONS:
  144. if ( copy_from_user(&value, argp, sizeof(int)) )
  145. return -EFAULT;
  146. switch(value) {
  147. case WDIOS_ENABLECARD:
  148. cpu5wdt_start();
  149. break;
  150. case WDIOS_DISABLECARD:
  151. return cpu5wdt_stop();
  152. default:
  153. return -EINVAL;
  154. }
  155. break;
  156. default:
  157. return -ENOTTY;
  158. }
  159. return 0;
  160. }
  161. static ssize_t cpu5wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
  162. {
  163. if ( !count )
  164. return -EIO;
  165. cpu5wdt_reset();
  166. return count;
  167. }
  168. static const struct file_operations cpu5wdt_fops = {
  169. .owner = THIS_MODULE,
  170. .llseek = no_llseek,
  171. .ioctl = cpu5wdt_ioctl,
  172. .open = cpu5wdt_open,
  173. .write = cpu5wdt_write,
  174. .release = cpu5wdt_release,
  175. };
  176. static struct miscdevice cpu5wdt_misc = {
  177. .minor = WATCHDOG_MINOR,
  178. .name = "watchdog",
  179. .fops = &cpu5wdt_fops,
  180. };
  181. /* init/exit function */
  182. static int __devinit cpu5wdt_init(void)
  183. {
  184. unsigned int val;
  185. int err;
  186. if ( verbose )
  187. printk(KERN_DEBUG PFX "port=0x%x, verbose=%i\n", port, verbose);
  188. if ( !request_region(port, CPU5WDT_EXTENT, PFX) ) {
  189. printk(KERN_ERR PFX "request_region failed\n");
  190. err = -EBUSY;
  191. goto no_port;
  192. }
  193. if ( (err = misc_register(&cpu5wdt_misc)) < 0 ) {
  194. printk(KERN_ERR PFX "misc_register failed\n");
  195. goto no_misc;
  196. }
  197. /* watchdog reboot? */
  198. val = inb(port + CPU5WDT_STATUS_REG);
  199. val = (val >> 2) & 1;
  200. if ( !val )
  201. printk(KERN_INFO PFX "sorry, was my fault\n");
  202. init_completion(&cpu5wdt_device.stop);
  203. cpu5wdt_device.queue = 0;
  204. clear_bit(0, &cpu5wdt_device.inuse);
  205. setup_timer(&cpu5wdt_device.timer, cpu5wdt_trigger, 0);
  206. cpu5wdt_device.default_ticks = ticks;
  207. printk(KERN_INFO PFX "init success\n");
  208. return 0;
  209. no_misc:
  210. release_region(port, CPU5WDT_EXTENT);
  211. no_port:
  212. return err;
  213. }
  214. static int __devinit cpu5wdt_init_module(void)
  215. {
  216. return cpu5wdt_init();
  217. }
  218. static void __devexit cpu5wdt_exit(void)
  219. {
  220. if ( cpu5wdt_device.queue ) {
  221. cpu5wdt_device.queue = 0;
  222. wait_for_completion(&cpu5wdt_device.stop);
  223. }
  224. misc_deregister(&cpu5wdt_misc);
  225. release_region(port, CPU5WDT_EXTENT);
  226. }
  227. static void __devexit cpu5wdt_exit_module(void)
  228. {
  229. cpu5wdt_exit();
  230. }
  231. /* module entry points */
  232. module_init(cpu5wdt_init_module);
  233. module_exit(cpu5wdt_exit_module);
  234. MODULE_AUTHOR("Heiko Ronsdorf <hero@ihg.uni-duisburg.de>");
  235. MODULE_DESCRIPTION("sma cpu5 watchdog driver");
  236. MODULE_SUPPORTED_DEVICE("sma cpu5 watchdog");
  237. MODULE_LICENSE("GPL");
  238. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  239. module_param(port, int, 0);
  240. MODULE_PARM_DESC(port, "base address of watchdog card, default is 0x91");
  241. module_param(verbose, int, 0);
  242. MODULE_PARM_DESC(verbose, "be verbose, default is 0 (no)");
  243. module_param(ticks, int, 0);
  244. MODULE_PARM_DESC(ticks, "count down ticks, default is 10000");