mce_amd_64.c 15 KB

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  1. /*
  2. * (c) 2005, 2006 Advanced Micro Devices, Inc.
  3. * Your use of this code is subject to the terms and conditions of the
  4. * GNU general public license version 2. See "COPYING" or
  5. * http://www.gnu.org/licenses/gpl.html
  6. *
  7. * Written by Jacob Shin - AMD, Inc.
  8. *
  9. * Support : jacob.shin@amd.com
  10. *
  11. * April 2006
  12. * - added support for AMD Family 0x10 processors
  13. *
  14. * All MC4_MISCi registers are shared between multi-cores
  15. */
  16. #include <linux/cpu.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/kobject.h>
  21. #include <linux/notifier.h>
  22. #include <linux/sched.h>
  23. #include <linux/smp.h>
  24. #include <linux/sysdev.h>
  25. #include <linux/sysfs.h>
  26. #include <asm/apic.h>
  27. #include <asm/mce.h>
  28. #include <asm/msr.h>
  29. #include <asm/percpu.h>
  30. #include <asm/idle.h>
  31. #define PFX "mce_threshold: "
  32. #define VERSION "version 1.1.1"
  33. #define NR_BANKS 6
  34. #define NR_BLOCKS 9
  35. #define THRESHOLD_MAX 0xFFF
  36. #define INT_TYPE_APIC 0x00020000
  37. #define MASK_VALID_HI 0x80000000
  38. #define MASK_CNTP_HI 0x40000000
  39. #define MASK_LOCKED_HI 0x20000000
  40. #define MASK_LVTOFF_HI 0x00F00000
  41. #define MASK_COUNT_EN_HI 0x00080000
  42. #define MASK_INT_TYPE_HI 0x00060000
  43. #define MASK_OVERFLOW_HI 0x00010000
  44. #define MASK_ERR_COUNT_HI 0x00000FFF
  45. #define MASK_BLKPTR_LO 0xFF000000
  46. #define MCG_XBLK_ADDR 0xC0000400
  47. struct threshold_block {
  48. unsigned int block;
  49. unsigned int bank;
  50. unsigned int cpu;
  51. u32 address;
  52. u16 interrupt_enable;
  53. u16 threshold_limit;
  54. struct kobject kobj;
  55. struct list_head miscj;
  56. };
  57. /* defaults used early on boot */
  58. static struct threshold_block threshold_defaults = {
  59. .interrupt_enable = 0,
  60. .threshold_limit = THRESHOLD_MAX,
  61. };
  62. struct threshold_bank {
  63. struct kobject kobj;
  64. struct threshold_block *blocks;
  65. cpumask_t cpus;
  66. };
  67. static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
  68. #ifdef CONFIG_SMP
  69. static unsigned char shared_bank[NR_BANKS] = {
  70. 0, 0, 0, 0, 1
  71. };
  72. #endif
  73. static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  74. /*
  75. * CPU Initialization
  76. */
  77. /* must be called with correct cpu affinity */
  78. static void threshold_restart_bank(struct threshold_block *b,
  79. int reset, u16 old_limit)
  80. {
  81. u32 mci_misc_hi, mci_misc_lo;
  82. rdmsr(b->address, mci_misc_lo, mci_misc_hi);
  83. if (b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
  84. reset = 1; /* limit cannot be lower than err count */
  85. if (reset) { /* reset err count and overflow bit */
  86. mci_misc_hi =
  87. (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
  88. (THRESHOLD_MAX - b->threshold_limit);
  89. } else if (old_limit) { /* change limit w/o reset */
  90. int new_count = (mci_misc_hi & THRESHOLD_MAX) +
  91. (old_limit - b->threshold_limit);
  92. mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
  93. (new_count & THRESHOLD_MAX);
  94. }
  95. b->interrupt_enable ?
  96. (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
  97. (mci_misc_hi &= ~MASK_INT_TYPE_HI);
  98. mci_misc_hi |= MASK_COUNT_EN_HI;
  99. wrmsr(b->address, mci_misc_lo, mci_misc_hi);
  100. }
  101. /* cpu init entry point, called from mce.c with preempt off */
  102. void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
  103. {
  104. unsigned int bank, block;
  105. unsigned int cpu = smp_processor_id();
  106. u32 low = 0, high = 0, address = 0;
  107. for (bank = 0; bank < NR_BANKS; ++bank) {
  108. for (block = 0; block < NR_BLOCKS; ++block) {
  109. if (block == 0)
  110. address = MSR_IA32_MC0_MISC + bank * 4;
  111. else if (block == 1) {
  112. address = (low & MASK_BLKPTR_LO) >> 21;
  113. if (!address)
  114. break;
  115. address += MCG_XBLK_ADDR;
  116. }
  117. else
  118. ++address;
  119. if (rdmsr_safe(address, &low, &high))
  120. break;
  121. if (!(high & MASK_VALID_HI)) {
  122. if (block)
  123. continue;
  124. else
  125. break;
  126. }
  127. if (!(high & MASK_CNTP_HI) ||
  128. (high & MASK_LOCKED_HI))
  129. continue;
  130. if (!block)
  131. per_cpu(bank_map, cpu) |= (1 << bank);
  132. #ifdef CONFIG_SMP
  133. if (shared_bank[bank] && c->cpu_core_id)
  134. break;
  135. #endif
  136. high &= ~MASK_LVTOFF_HI;
  137. high |= K8_APIC_EXT_LVT_ENTRY_THRESHOLD << 20;
  138. wrmsr(address, low, high);
  139. setup_APIC_extended_lvt(K8_APIC_EXT_LVT_ENTRY_THRESHOLD,
  140. THRESHOLD_APIC_VECTOR,
  141. K8_APIC_EXT_INT_MSG_FIX, 0);
  142. threshold_defaults.address = address;
  143. threshold_restart_bank(&threshold_defaults, 0, 0);
  144. }
  145. }
  146. }
  147. /*
  148. * APIC Interrupt Handler
  149. */
  150. /*
  151. * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
  152. * the interrupt goes off when error_count reaches threshold_limit.
  153. * the handler will simply log mcelog w/ software defined bank number.
  154. */
  155. asmlinkage void mce_threshold_interrupt(void)
  156. {
  157. unsigned int bank, block;
  158. struct mce m;
  159. u32 low = 0, high = 0, address = 0;
  160. ack_APIC_irq();
  161. exit_idle();
  162. irq_enter();
  163. memset(&m, 0, sizeof(m));
  164. rdtscll(m.tsc);
  165. m.cpu = smp_processor_id();
  166. /* assume first bank caused it */
  167. for (bank = 0; bank < NR_BANKS; ++bank) {
  168. if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
  169. continue;
  170. for (block = 0; block < NR_BLOCKS; ++block) {
  171. if (block == 0)
  172. address = MSR_IA32_MC0_MISC + bank * 4;
  173. else if (block == 1) {
  174. address = (low & MASK_BLKPTR_LO) >> 21;
  175. if (!address)
  176. break;
  177. address += MCG_XBLK_ADDR;
  178. }
  179. else
  180. ++address;
  181. if (rdmsr_safe(address, &low, &high))
  182. break;
  183. if (!(high & MASK_VALID_HI)) {
  184. if (block)
  185. continue;
  186. else
  187. break;
  188. }
  189. if (!(high & MASK_CNTP_HI) ||
  190. (high & MASK_LOCKED_HI))
  191. continue;
  192. /* Log the machine check that caused the threshold
  193. event. */
  194. do_machine_check(NULL, 0);
  195. if (high & MASK_OVERFLOW_HI) {
  196. rdmsrl(address, m.misc);
  197. rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
  198. m.status);
  199. m.bank = K8_MCE_THRESHOLD_BASE
  200. + bank * NR_BLOCKS
  201. + block;
  202. mce_log(&m);
  203. goto out;
  204. }
  205. }
  206. }
  207. out:
  208. irq_exit();
  209. }
  210. /*
  211. * Sysfs Interface
  212. */
  213. struct threshold_attr {
  214. struct attribute attr;
  215. ssize_t(*show) (struct threshold_block *, char *);
  216. ssize_t(*store) (struct threshold_block *, const char *, size_t count);
  217. };
  218. static cpumask_t affinity_set(unsigned int cpu)
  219. {
  220. cpumask_t oldmask = current->cpus_allowed;
  221. cpumask_t newmask = CPU_MASK_NONE;
  222. cpu_set(cpu, newmask);
  223. set_cpus_allowed(current, newmask);
  224. return oldmask;
  225. }
  226. static void affinity_restore(cpumask_t oldmask)
  227. {
  228. set_cpus_allowed(current, oldmask);
  229. }
  230. #define SHOW_FIELDS(name) \
  231. static ssize_t show_ ## name(struct threshold_block * b, char *buf) \
  232. { \
  233. return sprintf(buf, "%lx\n", (unsigned long) b->name); \
  234. }
  235. SHOW_FIELDS(interrupt_enable)
  236. SHOW_FIELDS(threshold_limit)
  237. static ssize_t store_interrupt_enable(struct threshold_block *b,
  238. const char *buf, size_t count)
  239. {
  240. char *end;
  241. cpumask_t oldmask;
  242. unsigned long new = simple_strtoul(buf, &end, 0);
  243. if (end == buf)
  244. return -EINVAL;
  245. b->interrupt_enable = !!new;
  246. oldmask = affinity_set(b->cpu);
  247. threshold_restart_bank(b, 0, 0);
  248. affinity_restore(oldmask);
  249. return end - buf;
  250. }
  251. static ssize_t store_threshold_limit(struct threshold_block *b,
  252. const char *buf, size_t count)
  253. {
  254. char *end;
  255. cpumask_t oldmask;
  256. u16 old;
  257. unsigned long new = simple_strtoul(buf, &end, 0);
  258. if (end == buf)
  259. return -EINVAL;
  260. if (new > THRESHOLD_MAX)
  261. new = THRESHOLD_MAX;
  262. if (new < 1)
  263. new = 1;
  264. old = b->threshold_limit;
  265. b->threshold_limit = new;
  266. oldmask = affinity_set(b->cpu);
  267. threshold_restart_bank(b, 0, old);
  268. affinity_restore(oldmask);
  269. return end - buf;
  270. }
  271. static ssize_t show_error_count(struct threshold_block *b, char *buf)
  272. {
  273. u32 high, low;
  274. cpumask_t oldmask;
  275. oldmask = affinity_set(b->cpu);
  276. rdmsr(b->address, low, high);
  277. affinity_restore(oldmask);
  278. return sprintf(buf, "%x\n",
  279. (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit));
  280. }
  281. static ssize_t store_error_count(struct threshold_block *b,
  282. const char *buf, size_t count)
  283. {
  284. cpumask_t oldmask;
  285. oldmask = affinity_set(b->cpu);
  286. threshold_restart_bank(b, 1, 0);
  287. affinity_restore(oldmask);
  288. return 1;
  289. }
  290. #define THRESHOLD_ATTR(_name,_mode,_show,_store) { \
  291. .attr = {.name = __stringify(_name), .mode = _mode }, \
  292. .show = _show, \
  293. .store = _store, \
  294. };
  295. #define RW_ATTR(name) \
  296. static struct threshold_attr name = \
  297. THRESHOLD_ATTR(name, 0644, show_## name, store_## name)
  298. RW_ATTR(interrupt_enable);
  299. RW_ATTR(threshold_limit);
  300. RW_ATTR(error_count);
  301. static struct attribute *default_attrs[] = {
  302. &interrupt_enable.attr,
  303. &threshold_limit.attr,
  304. &error_count.attr,
  305. NULL
  306. };
  307. #define to_block(k) container_of(k, struct threshold_block, kobj)
  308. #define to_attr(a) container_of(a, struct threshold_attr, attr)
  309. static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
  310. {
  311. struct threshold_block *b = to_block(kobj);
  312. struct threshold_attr *a = to_attr(attr);
  313. ssize_t ret;
  314. ret = a->show ? a->show(b, buf) : -EIO;
  315. return ret;
  316. }
  317. static ssize_t store(struct kobject *kobj, struct attribute *attr,
  318. const char *buf, size_t count)
  319. {
  320. struct threshold_block *b = to_block(kobj);
  321. struct threshold_attr *a = to_attr(attr);
  322. ssize_t ret;
  323. ret = a->store ? a->store(b, buf, count) : -EIO;
  324. return ret;
  325. }
  326. static struct sysfs_ops threshold_ops = {
  327. .show = show,
  328. .store = store,
  329. };
  330. static struct kobj_type threshold_ktype = {
  331. .sysfs_ops = &threshold_ops,
  332. .default_attrs = default_attrs,
  333. };
  334. static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
  335. unsigned int bank,
  336. unsigned int block,
  337. u32 address)
  338. {
  339. int err;
  340. u32 low, high;
  341. struct threshold_block *b = NULL;
  342. if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
  343. return 0;
  344. if (rdmsr_safe(address, &low, &high))
  345. return 0;
  346. if (!(high & MASK_VALID_HI)) {
  347. if (block)
  348. goto recurse;
  349. else
  350. return 0;
  351. }
  352. if (!(high & MASK_CNTP_HI) ||
  353. (high & MASK_LOCKED_HI))
  354. goto recurse;
  355. b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
  356. if (!b)
  357. return -ENOMEM;
  358. b->block = block;
  359. b->bank = bank;
  360. b->cpu = cpu;
  361. b->address = address;
  362. b->interrupt_enable = 0;
  363. b->threshold_limit = THRESHOLD_MAX;
  364. INIT_LIST_HEAD(&b->miscj);
  365. if (per_cpu(threshold_banks, cpu)[bank]->blocks)
  366. list_add(&b->miscj,
  367. &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
  368. else
  369. per_cpu(threshold_banks, cpu)[bank]->blocks = b;
  370. kobject_set_name(&b->kobj, "misc%i", block);
  371. b->kobj.parent = &per_cpu(threshold_banks, cpu)[bank]->kobj;
  372. b->kobj.ktype = &threshold_ktype;
  373. err = kobject_register(&b->kobj);
  374. if (err)
  375. goto out_free;
  376. recurse:
  377. if (!block) {
  378. address = (low & MASK_BLKPTR_LO) >> 21;
  379. if (!address)
  380. return 0;
  381. address += MCG_XBLK_ADDR;
  382. } else
  383. ++address;
  384. err = allocate_threshold_blocks(cpu, bank, ++block, address);
  385. if (err)
  386. goto out_free;
  387. return err;
  388. out_free:
  389. if (b) {
  390. kobject_unregister(&b->kobj);
  391. kfree(b);
  392. }
  393. return err;
  394. }
  395. /* symlinks sibling shared banks to first core. first core owns dir/files. */
  396. static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
  397. {
  398. int i, err = 0;
  399. struct threshold_bank *b = NULL;
  400. cpumask_t oldmask = CPU_MASK_NONE;
  401. char name[32];
  402. sprintf(name, "threshold_bank%i", bank);
  403. #ifdef CONFIG_SMP
  404. if (cpu_data[cpu].cpu_core_id && shared_bank[bank]) { /* symlink */
  405. i = first_cpu(cpu_core_map[cpu]);
  406. /* first core not up yet */
  407. if (cpu_data[i].cpu_core_id)
  408. goto out;
  409. /* already linked */
  410. if (per_cpu(threshold_banks, cpu)[bank])
  411. goto out;
  412. b = per_cpu(threshold_banks, i)[bank];
  413. if (!b)
  414. goto out;
  415. err = sysfs_create_link(&per_cpu(device_mce, cpu).kobj,
  416. &b->kobj, name);
  417. if (err)
  418. goto out;
  419. b->cpus = cpu_core_map[cpu];
  420. per_cpu(threshold_banks, cpu)[bank] = b;
  421. goto out;
  422. }
  423. #endif
  424. b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
  425. if (!b) {
  426. err = -ENOMEM;
  427. goto out;
  428. }
  429. kobject_set_name(&b->kobj, "threshold_bank%i", bank);
  430. b->kobj.parent = &per_cpu(device_mce, cpu).kobj;
  431. #ifndef CONFIG_SMP
  432. b->cpus = CPU_MASK_ALL;
  433. #else
  434. b->cpus = cpu_core_map[cpu];
  435. #endif
  436. err = kobject_register(&b->kobj);
  437. if (err)
  438. goto out_free;
  439. per_cpu(threshold_banks, cpu)[bank] = b;
  440. oldmask = affinity_set(cpu);
  441. err = allocate_threshold_blocks(cpu, bank, 0,
  442. MSR_IA32_MC0_MISC + bank * 4);
  443. affinity_restore(oldmask);
  444. if (err)
  445. goto out_free;
  446. for_each_cpu_mask(i, b->cpus) {
  447. if (i == cpu)
  448. continue;
  449. err = sysfs_create_link(&per_cpu(device_mce, i).kobj,
  450. &b->kobj, name);
  451. if (err)
  452. goto out;
  453. per_cpu(threshold_banks, i)[bank] = b;
  454. }
  455. goto out;
  456. out_free:
  457. per_cpu(threshold_banks, cpu)[bank] = NULL;
  458. kfree(b);
  459. out:
  460. return err;
  461. }
  462. /* create dir/files for all valid threshold banks */
  463. static __cpuinit int threshold_create_device(unsigned int cpu)
  464. {
  465. unsigned int bank;
  466. int err = 0;
  467. for (bank = 0; bank < NR_BANKS; ++bank) {
  468. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  469. continue;
  470. err = threshold_create_bank(cpu, bank);
  471. if (err)
  472. goto out;
  473. }
  474. out:
  475. return err;
  476. }
  477. /*
  478. * let's be hotplug friendly.
  479. * in case of multiple core processors, the first core always takes ownership
  480. * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  481. */
  482. static void deallocate_threshold_block(unsigned int cpu,
  483. unsigned int bank)
  484. {
  485. struct threshold_block *pos = NULL;
  486. struct threshold_block *tmp = NULL;
  487. struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
  488. if (!head)
  489. return;
  490. list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
  491. kobject_unregister(&pos->kobj);
  492. list_del(&pos->miscj);
  493. kfree(pos);
  494. }
  495. kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
  496. per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
  497. }
  498. static void threshold_remove_bank(unsigned int cpu, int bank)
  499. {
  500. int i = 0;
  501. struct threshold_bank *b;
  502. char name[32];
  503. b = per_cpu(threshold_banks, cpu)[bank];
  504. if (!b)
  505. return;
  506. if (!b->blocks)
  507. goto free_out;
  508. sprintf(name, "threshold_bank%i", bank);
  509. #ifdef CONFIG_SMP
  510. /* sibling symlink */
  511. if (shared_bank[bank] && b->blocks->cpu != cpu) {
  512. sysfs_remove_link(&per_cpu(device_mce, cpu).kobj, name);
  513. per_cpu(threshold_banks, cpu)[bank] = NULL;
  514. return;
  515. }
  516. #endif
  517. /* remove all sibling symlinks before unregistering */
  518. for_each_cpu_mask(i, b->cpus) {
  519. if (i == cpu)
  520. continue;
  521. sysfs_remove_link(&per_cpu(device_mce, i).kobj, name);
  522. per_cpu(threshold_banks, i)[bank] = NULL;
  523. }
  524. deallocate_threshold_block(cpu, bank);
  525. free_out:
  526. kobject_unregister(&b->kobj);
  527. kfree(b);
  528. per_cpu(threshold_banks, cpu)[bank] = NULL;
  529. }
  530. static void threshold_remove_device(unsigned int cpu)
  531. {
  532. unsigned int bank;
  533. for (bank = 0; bank < NR_BANKS; ++bank) {
  534. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  535. continue;
  536. threshold_remove_bank(cpu, bank);
  537. }
  538. }
  539. /* get notified when a cpu comes on/off */
  540. static int threshold_cpu_callback(struct notifier_block *nfb,
  541. unsigned long action, void *hcpu)
  542. {
  543. /* cpu was unsigned int to begin with */
  544. unsigned int cpu = (unsigned long)hcpu;
  545. if (cpu >= NR_CPUS)
  546. goto out;
  547. switch (action) {
  548. case CPU_ONLINE:
  549. case CPU_ONLINE_FROZEN:
  550. threshold_create_device(cpu);
  551. break;
  552. case CPU_DEAD:
  553. case CPU_DEAD_FROZEN:
  554. threshold_remove_device(cpu);
  555. break;
  556. default:
  557. break;
  558. }
  559. out:
  560. return NOTIFY_OK;
  561. }
  562. static struct notifier_block threshold_cpu_notifier = {
  563. .notifier_call = threshold_cpu_callback,
  564. };
  565. static __init int threshold_init_device(void)
  566. {
  567. unsigned lcpu = 0;
  568. /* to hit CPUs online before the notifier is up */
  569. for_each_online_cpu(lcpu) {
  570. int err = threshold_create_device(lcpu);
  571. if (err)
  572. return err;
  573. }
  574. register_hotcpu_notifier(&threshold_cpu_notifier);
  575. return 0;
  576. }
  577. device_initcall(threshold_init_device);