sun4m_smp.c 9.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419
  1. /* sun4m_smp.c: Sparc SUN4M SMP support.
  2. *
  3. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  4. */
  5. #include <asm/head.h>
  6. #include <linux/kernel.h>
  7. #include <linux/sched.h>
  8. #include <linux/threads.h>
  9. #include <linux/smp.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/kernel_stat.h>
  12. #include <linux/init.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/mm.h>
  15. #include <linux/swap.h>
  16. #include <linux/profile.h>
  17. #include <asm/cacheflush.h>
  18. #include <asm/tlbflush.h>
  19. #include <asm/irq_regs.h>
  20. #include <asm/ptrace.h>
  21. #include <asm/atomic.h>
  22. #include <asm/delay.h>
  23. #include <asm/irq.h>
  24. #include <asm/page.h>
  25. #include <asm/pgalloc.h>
  26. #include <asm/pgtable.h>
  27. #include <asm/oplib.h>
  28. #include <asm/cpudata.h>
  29. #include "irq.h"
  30. #define IRQ_RESCHEDULE 13
  31. #define IRQ_STOP_CPU 14
  32. #define IRQ_CROSS_CALL 15
  33. extern ctxd_t *srmmu_ctx_table_phys;
  34. extern void calibrate_delay(void);
  35. extern volatile unsigned long cpu_callin_map[NR_CPUS];
  36. extern unsigned char boot_cpu_id;
  37. extern cpumask_t smp_commenced_mask;
  38. extern int __smp4m_processor_id(void);
  39. /*#define SMP_DEBUG*/
  40. #ifdef SMP_DEBUG
  41. #define SMP_PRINTK(x) printk x
  42. #else
  43. #define SMP_PRINTK(x)
  44. #endif
  45. static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val)
  46. {
  47. __asm__ __volatile__("swap [%1], %0\n\t" :
  48. "=&r" (val), "=&r" (ptr) :
  49. "0" (val), "1" (ptr));
  50. return val;
  51. }
  52. static void smp_setup_percpu_timer(void);
  53. extern void cpu_probe(void);
  54. void __cpuinit smp4m_callin(void)
  55. {
  56. int cpuid = hard_smp_processor_id();
  57. local_flush_cache_all();
  58. local_flush_tlb_all();
  59. /* Get our local ticker going. */
  60. smp_setup_percpu_timer();
  61. calibrate_delay();
  62. smp_store_cpu_info(cpuid);
  63. local_flush_cache_all();
  64. local_flush_tlb_all();
  65. /*
  66. * Unblock the master CPU _only_ when the scheduler state
  67. * of all secondary CPUs will be up-to-date, so after
  68. * the SMP initialization the master will be just allowed
  69. * to call the scheduler code.
  70. */
  71. /* Allow master to continue. */
  72. swap(&cpu_callin_map[cpuid], 1);
  73. /* XXX: What's up with all the flushes? */
  74. local_flush_cache_all();
  75. local_flush_tlb_all();
  76. cpu_probe();
  77. /* Fix idle thread fields. */
  78. __asm__ __volatile__("ld [%0], %%g6\n\t"
  79. : : "r" (&current_set[cpuid])
  80. : "memory" /* paranoid */);
  81. /* Attach to the address space of init_task. */
  82. atomic_inc(&init_mm.mm_count);
  83. current->active_mm = &init_mm;
  84. while (!cpu_isset(cpuid, smp_commenced_mask))
  85. mb();
  86. local_irq_enable();
  87. cpu_set(cpuid, cpu_online_map);
  88. }
  89. /*
  90. * Cycle through the processors asking the PROM to start each one.
  91. */
  92. extern struct linux_prom_registers smp_penguin_ctable;
  93. extern unsigned long trapbase_cpu1[];
  94. extern unsigned long trapbase_cpu2[];
  95. extern unsigned long trapbase_cpu3[];
  96. void __init smp4m_boot_cpus(void)
  97. {
  98. smp_setup_percpu_timer();
  99. local_flush_cache_all();
  100. }
  101. int __cpuinit smp4m_boot_one_cpu(int i)
  102. {
  103. extern unsigned long sun4m_cpu_startup;
  104. unsigned long *entry = &sun4m_cpu_startup;
  105. struct task_struct *p;
  106. int timeout;
  107. int cpu_node;
  108. cpu_find_by_mid(i, &cpu_node);
  109. /* Cook up an idler for this guy. */
  110. p = fork_idle(i);
  111. current_set[i] = task_thread_info(p);
  112. /* See trampoline.S for details... */
  113. entry += ((i-1) * 3);
  114. /*
  115. * Initialize the contexts table
  116. * Since the call to prom_startcpu() trashes the structure,
  117. * we need to re-initialize it for each cpu
  118. */
  119. smp_penguin_ctable.which_io = 0;
  120. smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
  121. smp_penguin_ctable.reg_size = 0;
  122. /* whirrr, whirrr, whirrrrrrrrr... */
  123. printk("Starting CPU %d at %p\n", i, entry);
  124. local_flush_cache_all();
  125. prom_startcpu(cpu_node,
  126. &smp_penguin_ctable, 0, (char *)entry);
  127. /* wheee... it's going... */
  128. for(timeout = 0; timeout < 10000; timeout++) {
  129. if(cpu_callin_map[i])
  130. break;
  131. udelay(200);
  132. }
  133. if (!(cpu_callin_map[i])) {
  134. printk("Processor %d is stuck.\n", i);
  135. return -ENODEV;
  136. }
  137. local_flush_cache_all();
  138. return 0;
  139. }
  140. void __init smp4m_smp_done(void)
  141. {
  142. int i, first;
  143. int *prev;
  144. /* setup cpu list for irq rotation */
  145. first = 0;
  146. prev = &first;
  147. for (i = 0; i < NR_CPUS; i++) {
  148. if (cpu_online(i)) {
  149. *prev = i;
  150. prev = &cpu_data(i).next;
  151. }
  152. }
  153. *prev = first;
  154. local_flush_cache_all();
  155. /* Free unneeded trap tables */
  156. if (!cpu_isset(1, cpu_present_map)) {
  157. ClearPageReserved(virt_to_page(trapbase_cpu1));
  158. init_page_count(virt_to_page(trapbase_cpu1));
  159. free_page((unsigned long)trapbase_cpu1);
  160. totalram_pages++;
  161. num_physpages++;
  162. }
  163. if (!cpu_isset(2, cpu_present_map)) {
  164. ClearPageReserved(virt_to_page(trapbase_cpu2));
  165. init_page_count(virt_to_page(trapbase_cpu2));
  166. free_page((unsigned long)trapbase_cpu2);
  167. totalram_pages++;
  168. num_physpages++;
  169. }
  170. if (!cpu_isset(3, cpu_present_map)) {
  171. ClearPageReserved(virt_to_page(trapbase_cpu3));
  172. init_page_count(virt_to_page(trapbase_cpu3));
  173. free_page((unsigned long)trapbase_cpu3);
  174. totalram_pages++;
  175. num_physpages++;
  176. }
  177. /* Ok, they are spinning and ready to go. */
  178. }
  179. /* At each hardware IRQ, we get this called to forward IRQ reception
  180. * to the next processor. The caller must disable the IRQ level being
  181. * serviced globally so that there are no double interrupts received.
  182. *
  183. * XXX See sparc64 irq.c.
  184. */
  185. void smp4m_irq_rotate(int cpu)
  186. {
  187. int next = cpu_data(cpu).next;
  188. if (next != cpu)
  189. set_irq_udt(next);
  190. }
  191. /* Cross calls, in order to work efficiently and atomically do all
  192. * the message passing work themselves, only stopcpu and reschedule
  193. * messages come through here.
  194. */
  195. void smp4m_message_pass(int target, int msg, unsigned long data, int wait)
  196. {
  197. static unsigned long smp_cpu_in_msg[NR_CPUS];
  198. cpumask_t mask;
  199. int me = smp_processor_id();
  200. int irq, i;
  201. if(msg == MSG_RESCHEDULE) {
  202. irq = IRQ_RESCHEDULE;
  203. if(smp_cpu_in_msg[me])
  204. return;
  205. } else if(msg == MSG_STOP_CPU) {
  206. irq = IRQ_STOP_CPU;
  207. } else {
  208. goto barf;
  209. }
  210. smp_cpu_in_msg[me]++;
  211. if(target == MSG_ALL_BUT_SELF || target == MSG_ALL) {
  212. mask = cpu_online_map;
  213. if(target == MSG_ALL_BUT_SELF)
  214. cpu_clear(me, mask);
  215. for(i = 0; i < 4; i++) {
  216. if (cpu_isset(i, mask))
  217. set_cpu_int(i, irq);
  218. }
  219. } else {
  220. set_cpu_int(target, irq);
  221. }
  222. smp_cpu_in_msg[me]--;
  223. return;
  224. barf:
  225. printk("Yeeee, trying to send SMP msg(%d) on cpu %d\n", msg, me);
  226. panic("Bogon SMP message pass.");
  227. }
  228. static struct smp_funcall {
  229. smpfunc_t func;
  230. unsigned long arg1;
  231. unsigned long arg2;
  232. unsigned long arg3;
  233. unsigned long arg4;
  234. unsigned long arg5;
  235. unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
  236. unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
  237. } ccall_info;
  238. static DEFINE_SPINLOCK(cross_call_lock);
  239. /* Cross calls must be serialized, at least currently. */
  240. void smp4m_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2,
  241. unsigned long arg3, unsigned long arg4, unsigned long arg5)
  242. {
  243. register int ncpus = SUN4M_NCPUS;
  244. unsigned long flags;
  245. spin_lock_irqsave(&cross_call_lock, flags);
  246. /* Init function glue. */
  247. ccall_info.func = func;
  248. ccall_info.arg1 = arg1;
  249. ccall_info.arg2 = arg2;
  250. ccall_info.arg3 = arg3;
  251. ccall_info.arg4 = arg4;
  252. ccall_info.arg5 = arg5;
  253. /* Init receive/complete mapping, plus fire the IPI's off. */
  254. {
  255. cpumask_t mask = cpu_online_map;
  256. register int i;
  257. cpu_clear(smp_processor_id(), mask);
  258. for(i = 0; i < ncpus; i++) {
  259. if (cpu_isset(i, mask)) {
  260. ccall_info.processors_in[i] = 0;
  261. ccall_info.processors_out[i] = 0;
  262. set_cpu_int(i, IRQ_CROSS_CALL);
  263. } else {
  264. ccall_info.processors_in[i] = 1;
  265. ccall_info.processors_out[i] = 1;
  266. }
  267. }
  268. }
  269. {
  270. register int i;
  271. i = 0;
  272. do {
  273. while(!ccall_info.processors_in[i])
  274. barrier();
  275. } while(++i < ncpus);
  276. i = 0;
  277. do {
  278. while(!ccall_info.processors_out[i])
  279. barrier();
  280. } while(++i < ncpus);
  281. }
  282. spin_unlock_irqrestore(&cross_call_lock, flags);
  283. }
  284. /* Running cross calls. */
  285. void smp4m_cross_call_irq(void)
  286. {
  287. int i = smp_processor_id();
  288. ccall_info.processors_in[i] = 1;
  289. ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
  290. ccall_info.arg4, ccall_info.arg5);
  291. ccall_info.processors_out[i] = 1;
  292. }
  293. void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
  294. {
  295. struct pt_regs *old_regs;
  296. int cpu = smp_processor_id();
  297. old_regs = set_irq_regs(regs);
  298. clear_profile_irq(cpu);
  299. profile_tick(CPU_PROFILING);
  300. if(!--prof_counter(cpu)) {
  301. int user = user_mode(regs);
  302. irq_enter();
  303. update_process_times(user);
  304. irq_exit();
  305. prof_counter(cpu) = prof_multiplier(cpu);
  306. }
  307. set_irq_regs(old_regs);
  308. }
  309. extern unsigned int lvl14_resolution;
  310. static void __init smp_setup_percpu_timer(void)
  311. {
  312. int cpu = smp_processor_id();
  313. prof_counter(cpu) = prof_multiplier(cpu) = 1;
  314. load_profile_irq(cpu, lvl14_resolution);
  315. if(cpu == boot_cpu_id)
  316. enable_pil_irq(14);
  317. }
  318. void __init smp4m_blackbox_id(unsigned *addr)
  319. {
  320. int rd = *addr & 0x3e000000;
  321. int rs1 = rd >> 11;
  322. addr[0] = 0x81580000 | rd; /* rd %tbr, reg */
  323. addr[1] = 0x8130200c | rd | rs1; /* srl reg, 0xc, reg */
  324. addr[2] = 0x80082003 | rd | rs1; /* and reg, 3, reg */
  325. }
  326. void __init smp4m_blackbox_current(unsigned *addr)
  327. {
  328. int rd = *addr & 0x3e000000;
  329. int rs1 = rd >> 11;
  330. addr[0] = 0x81580000 | rd; /* rd %tbr, reg */
  331. addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */
  332. addr[4] = 0x8008200c | rd | rs1; /* and reg, 0xc, reg */
  333. }
  334. void __init sun4m_init_smp(void)
  335. {
  336. BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
  337. BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
  338. BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
  339. BTFIXUPSET_CALL(smp_message_pass, smp4m_message_pass, BTFIXUPCALL_NORM);
  340. BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
  341. }