smp-shx3.c 2.7 KB

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  1. /*
  2. * SH-X3 SMP
  3. *
  4. * Copyright (C) 2007 Paul Mundt
  5. * Copyright (C) 2007 Magnus Damm
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/cpumask.h>
  13. #include <linux/smp.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. void __init plat_smp_setup(void)
  17. {
  18. unsigned int cpu = 0;
  19. int i, num;
  20. cpus_clear(cpu_possible_map);
  21. cpu_set(cpu, cpu_possible_map);
  22. __cpu_number_map[0] = 0;
  23. __cpu_logical_map[0] = 0;
  24. /*
  25. * Do this stupidly for now.. we don't have an easy way to probe
  26. * for the total number of cores.
  27. */
  28. for (i = 1, num = 0; i < NR_CPUS; i++) {
  29. cpu_set(i, cpu_possible_map);
  30. __cpu_number_map[i] = ++num;
  31. __cpu_logical_map[num] = i;
  32. }
  33. printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
  34. }
  35. void __init plat_prepare_cpus(unsigned int max_cpus)
  36. {
  37. }
  38. #define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
  39. #define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
  40. #define STBCR_MSTP 0x00000001
  41. #define STBCR_RESET 0x00000002
  42. #define STBCR_LTSLP 0x80000000
  43. #define STBCR_AP_VAL (STBCR_RESET | STBCR_LTSLP)
  44. void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
  45. {
  46. ctrl_outl(entry_point, RESET_REG(cpu));
  47. if (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
  48. ctrl_outl(STBCR_MSTP, STBCR_REG(cpu));
  49. while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
  50. ;
  51. /* Start up secondary processor by sending a reset */
  52. ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu));
  53. }
  54. int plat_smp_processor_id(void)
  55. {
  56. return ctrl_inl(0xff000048); /* CPIDR */
  57. }
  58. void plat_send_ipi(unsigned int cpu, unsigned int message)
  59. {
  60. unsigned long addr = 0xfe410070 + (cpu * 4);
  61. BUG_ON(cpu >= 4);
  62. BUG_ON(message >= SMP_MSG_NR);
  63. ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
  64. }
  65. struct ipi_data {
  66. void (*handler)(void *);
  67. void *arg;
  68. unsigned int message;
  69. };
  70. static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
  71. {
  72. struct ipi_data *id = arg;
  73. unsigned int cpu = hard_smp_processor_id();
  74. unsigned int offs = 4 * cpu;
  75. unsigned int x;
  76. x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
  77. x &= (1 << (id->message << 2));
  78. ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
  79. id->handler(id->arg);
  80. return IRQ_HANDLED;
  81. }
  82. static struct ipi_data ipi_handlers[SMP_MSG_NR];
  83. int plat_register_ipi_handler(unsigned int message,
  84. void (*handler)(void *), void *arg)
  85. {
  86. struct ipi_data *id = &ipi_handlers[message];
  87. BUG_ON(SMP_MSG_NR >= 8);
  88. BUG_ON(message >= SMP_MSG_NR);
  89. id->handler = handler;
  90. id->arg = arg;
  91. id->message = message;
  92. return request_irq(104 + message, ipi_interrupt_handler, 0, "IPI", id);
  93. }