enet.c 29 KB

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  1. /*
  2. * Ethernet driver for Motorola MPC8xx.
  3. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  4. *
  5. * I copied the basic skeleton from the lance driver, because I did not
  6. * know how to write the Linux driver, but I did know how the LANCE worked.
  7. *
  8. * This version of the driver is somewhat selectable for the different
  9. * processor/board combinations. It works for the boards I know about
  10. * now, and should be easily modified to include others. Some of the
  11. * configuration information is contained in <asm/commproc.h> and the
  12. * remainder is here.
  13. *
  14. * Buffer descriptors are kept in the CPM dual port RAM, and the frame
  15. * buffers are in the host memory.
  16. *
  17. * Right now, I am very watseful with the buffers. I allocate memory
  18. * pages and then divide them into 2K frame buffers. This way I know I
  19. * have buffers large enough to hold one frame within one buffer descriptor.
  20. * Once I get this working, I will use 64 or 128 byte CPM buffers, which
  21. * will be much more memory efficient and will easily handle lots of
  22. * small packets.
  23. *
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/sched.h>
  27. #include <linux/string.h>
  28. #include <linux/ptrace.h>
  29. #include <linux/errno.h>
  30. #include <linux/ioport.h>
  31. #include <linux/slab.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/init.h>
  34. #include <linux/delay.h>
  35. #include <linux/netdevice.h>
  36. #include <linux/etherdevice.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/spinlock.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/bitops.h>
  41. #include <asm/8xx_immap.h>
  42. #include <asm/pgtable.h>
  43. #include <asm/mpc8xx.h>
  44. #include <asm/uaccess.h>
  45. #include <asm/commproc.h>
  46. #include <asm/cacheflush.h>
  47. /*
  48. * Theory of Operation
  49. *
  50. * The MPC8xx CPM performs the Ethernet processing on SCC1. It can use
  51. * an aribtrary number of buffers on byte boundaries, but must have at
  52. * least two receive buffers to prevent constant overrun conditions.
  53. *
  54. * The buffer descriptors are allocated from the CPM dual port memory
  55. * with the data buffers allocated from host memory, just like all other
  56. * serial communication protocols. The host memory buffers are allocated
  57. * from the free page pool, and then divided into smaller receive and
  58. * transmit buffers. The size of the buffers should be a power of two,
  59. * since that nicely divides the page. This creates a ring buffer
  60. * structure similar to the LANCE and other controllers.
  61. *
  62. * Like the LANCE driver:
  63. * The driver runs as two independent, single-threaded flows of control. One
  64. * is the send-packet routine, which enforces single-threaded use by the
  65. * cep->tx_busy flag. The other thread is the interrupt handler, which is
  66. * single threaded by the hardware and other software.
  67. *
  68. * The send packet thread has partial control over the Tx ring and the
  69. * 'cep->tx_busy' flag. It sets the tx_busy flag whenever it's queuing a Tx
  70. * packet. If the next queue slot is empty, it clears the tx_busy flag when
  71. * finished otherwise it sets the 'lp->tx_full' flag.
  72. *
  73. * The MBX has a control register external to the MPC8xx that has some
  74. * control of the Ethernet interface. Information is in the manual for
  75. * your board.
  76. *
  77. * The RPX boards have an external control/status register. Consult the
  78. * programming documents for details unique to your board.
  79. *
  80. * For the TQM8xx(L) modules, there is no control register interface.
  81. * All functions are directly controlled using I/O pins. See <asm/commproc.h>.
  82. */
  83. /* The transmitter timeout
  84. */
  85. #define TX_TIMEOUT (2*HZ)
  86. /* The number of Tx and Rx buffers. These are allocated from the page
  87. * pool. The code may assume these are power of two, so it is best
  88. * to keep them that size.
  89. * We don't need to allocate pages for the transmitter. We just use
  90. * the skbuffer directly.
  91. */
  92. #ifdef CONFIG_ENET_BIG_BUFFERS
  93. #define CPM_ENET_RX_PAGES 32
  94. #define CPM_ENET_RX_FRSIZE 2048
  95. #define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE)
  96. #define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES)
  97. #define TX_RING_SIZE 64 /* Must be power of two */
  98. #define TX_RING_MOD_MASK 63 /* for this to work */
  99. #else
  100. #define CPM_ENET_RX_PAGES 4
  101. #define CPM_ENET_RX_FRSIZE 2048
  102. #define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE)
  103. #define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES)
  104. #define TX_RING_SIZE 8 /* Must be power of two */
  105. #define TX_RING_MOD_MASK 7 /* for this to work */
  106. #endif
  107. /* The CPM stores dest/src/type, data, and checksum for receive packets.
  108. */
  109. #define PKT_MAXBUF_SIZE 1518
  110. #define PKT_MINBUF_SIZE 64
  111. #define PKT_MAXBLR_SIZE 1520
  112. /* The CPM buffer descriptors track the ring buffers. The rx_bd_base and
  113. * tx_bd_base always point to the base of the buffer descriptors. The
  114. * cur_rx and cur_tx point to the currently available buffer.
  115. * The dirty_tx tracks the current buffer that is being sent by the
  116. * controller. The cur_tx and dirty_tx are equal under both completely
  117. * empty and completely full conditions. The empty/ready indicator in
  118. * the buffer descriptor determines the actual condition.
  119. */
  120. struct scc_enet_private {
  121. /* The saved address of a sent-in-place packet/buffer, for skfree(). */
  122. struct sk_buff* tx_skbuff[TX_RING_SIZE];
  123. ushort skb_cur;
  124. ushort skb_dirty;
  125. /* CPM dual port RAM relative addresses.
  126. */
  127. cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
  128. cbd_t *tx_bd_base;
  129. cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
  130. cbd_t *dirty_tx; /* The ring entries to be free()ed. */
  131. scc_t *sccp;
  132. /* Virtual addresses for the receive buffers because we can't
  133. * do a __va() on them anymore.
  134. */
  135. unsigned char *rx_vaddr[RX_RING_SIZE];
  136. struct net_device_stats stats;
  137. uint tx_full;
  138. spinlock_t lock;
  139. };
  140. static int scc_enet_open(struct net_device *dev);
  141. static int scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
  142. static int scc_enet_rx(struct net_device *dev);
  143. static void scc_enet_interrupt(void *dev_id);
  144. static int scc_enet_close(struct net_device *dev);
  145. static struct net_device_stats *scc_enet_get_stats(struct net_device *dev);
  146. static void set_multicast_list(struct net_device *dev);
  147. /* Get this from various configuration locations (depends on board).
  148. */
  149. /*static ushort my_enet_addr[] = { 0x0800, 0x3e26, 0x1559 };*/
  150. /* Typically, 860(T) boards use SCC1 for Ethernet, and other 8xx boards
  151. * use SCC2. Some even may use SCC3.
  152. * This is easily extended if necessary.
  153. */
  154. #if defined(CONFIG_SCC3_ENET)
  155. #define CPM_CR_ENET CPM_CR_CH_SCC3
  156. #define PROFF_ENET PROFF_SCC3
  157. #define SCC_ENET 2 /* Index, not number! */
  158. #define CPMVEC_ENET CPMVEC_SCC3
  159. #elif defined(CONFIG_SCC2_ENET)
  160. #define CPM_CR_ENET CPM_CR_CH_SCC2
  161. #define PROFF_ENET PROFF_SCC2
  162. #define SCC_ENET 1 /* Index, not number! */
  163. #define CPMVEC_ENET CPMVEC_SCC2
  164. #elif defined(CONFIG_SCC1_ENET)
  165. #define CPM_CR_ENET CPM_CR_CH_SCC1
  166. #define PROFF_ENET PROFF_SCC1
  167. #define SCC_ENET 0 /* Index, not number! */
  168. #define CPMVEC_ENET CPMVEC_SCC1
  169. #else
  170. #error CONFIG_SCCx_ENET not defined
  171. #endif
  172. static int
  173. scc_enet_open(struct net_device *dev)
  174. {
  175. /* I should reset the ring buffers here, but I don't yet know
  176. * a simple way to do that.
  177. */
  178. netif_start_queue(dev);
  179. return 0; /* Always succeed */
  180. }
  181. static int
  182. scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
  183. {
  184. struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
  185. volatile cbd_t *bdp;
  186. /* Fill in a Tx ring entry */
  187. bdp = cep->cur_tx;
  188. #ifndef final_version
  189. if (bdp->cbd_sc & BD_ENET_TX_READY) {
  190. /* Ooops. All transmit buffers are full. Bail out.
  191. * This should not happen, since cep->tx_busy should be set.
  192. */
  193. printk("%s: tx queue full!.\n", dev->name);
  194. return 1;
  195. }
  196. #endif
  197. /* Clear all of the status flags.
  198. */
  199. bdp->cbd_sc &= ~BD_ENET_TX_STATS;
  200. /* If the frame is short, tell CPM to pad it.
  201. */
  202. if (skb->len <= ETH_ZLEN)
  203. bdp->cbd_sc |= BD_ENET_TX_PAD;
  204. else
  205. bdp->cbd_sc &= ~BD_ENET_TX_PAD;
  206. /* Set buffer length and buffer pointer.
  207. */
  208. bdp->cbd_datlen = skb->len;
  209. bdp->cbd_bufaddr = __pa(skb->data);
  210. /* Save skb pointer.
  211. */
  212. cep->tx_skbuff[cep->skb_cur] = skb;
  213. cep->stats.tx_bytes += skb->len;
  214. cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
  215. /* Push the data cache so the CPM does not get stale memory
  216. * data.
  217. */
  218. flush_dcache_range((unsigned long)(skb->data),
  219. (unsigned long)(skb->data + skb->len));
  220. spin_lock_irq(&cep->lock);
  221. /* Send it on its way. Tell CPM its ready, interrupt when done,
  222. * its the last BD of the frame, and to put the CRC on the end.
  223. */
  224. bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC);
  225. dev->trans_start = jiffies;
  226. /* If this was the last BD in the ring, start at the beginning again.
  227. */
  228. if (bdp->cbd_sc & BD_ENET_TX_WRAP)
  229. bdp = cep->tx_bd_base;
  230. else
  231. bdp++;
  232. if (bdp->cbd_sc & BD_ENET_TX_READY) {
  233. netif_stop_queue(dev);
  234. cep->tx_full = 1;
  235. }
  236. cep->cur_tx = (cbd_t *)bdp;
  237. spin_unlock_irq(&cep->lock);
  238. return 0;
  239. }
  240. static void
  241. scc_enet_timeout(struct net_device *dev)
  242. {
  243. struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
  244. printk("%s: transmit timed out.\n", dev->name);
  245. cep->stats.tx_errors++;
  246. #ifndef final_version
  247. {
  248. int i;
  249. cbd_t *bdp;
  250. printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
  251. cep->cur_tx, cep->tx_full ? " (full)" : "",
  252. cep->cur_rx);
  253. bdp = cep->tx_bd_base;
  254. for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
  255. printk("%04x %04x %08x\n",
  256. bdp->cbd_sc,
  257. bdp->cbd_datlen,
  258. bdp->cbd_bufaddr);
  259. bdp = cep->rx_bd_base;
  260. for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
  261. printk("%04x %04x %08x\n",
  262. bdp->cbd_sc,
  263. bdp->cbd_datlen,
  264. bdp->cbd_bufaddr);
  265. }
  266. #endif
  267. if (!cep->tx_full)
  268. netif_wake_queue(dev);
  269. }
  270. /* The interrupt handler.
  271. * This is called from the CPM handler, not the MPC core interrupt.
  272. */
  273. static void
  274. scc_enet_interrupt(void *dev_id)
  275. {
  276. struct net_device *dev = dev_id;
  277. volatile struct scc_enet_private *cep;
  278. volatile cbd_t *bdp;
  279. ushort int_events;
  280. int must_restart;
  281. cep = (struct scc_enet_private *)dev->priv;
  282. /* Get the interrupt events that caused us to be here.
  283. */
  284. int_events = cep->sccp->scc_scce;
  285. cep->sccp->scc_scce = int_events;
  286. must_restart = 0;
  287. /* Handle receive event in its own function.
  288. */
  289. if (int_events & SCCE_ENET_RXF)
  290. scc_enet_rx(dev_id);
  291. /* Check for a transmit error. The manual is a little unclear
  292. * about this, so the debug code until I get it figured out. It
  293. * appears that if TXE is set, then TXB is not set. However,
  294. * if carrier sense is lost during frame transmission, the TXE
  295. * bit is set, "and continues the buffer transmission normally."
  296. * I don't know if "normally" implies TXB is set when the buffer
  297. * descriptor is closed.....trial and error :-).
  298. */
  299. /* Transmit OK, or non-fatal error. Update the buffer descriptors.
  300. */
  301. if (int_events & (SCCE_ENET_TXE | SCCE_ENET_TXB)) {
  302. spin_lock(&cep->lock);
  303. bdp = cep->dirty_tx;
  304. while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) {
  305. if ((bdp==cep->cur_tx) && (cep->tx_full == 0))
  306. break;
  307. if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
  308. cep->stats.tx_heartbeat_errors++;
  309. if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
  310. cep->stats.tx_window_errors++;
  311. if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
  312. cep->stats.tx_aborted_errors++;
  313. if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
  314. cep->stats.tx_fifo_errors++;
  315. if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
  316. cep->stats.tx_carrier_errors++;
  317. /* No heartbeat or Lost carrier are not really bad errors.
  318. * The others require a restart transmit command.
  319. */
  320. if (bdp->cbd_sc &
  321. (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
  322. must_restart = 1;
  323. cep->stats.tx_errors++;
  324. }
  325. cep->stats.tx_packets++;
  326. /* Deferred means some collisions occurred during transmit,
  327. * but we eventually sent the packet OK.
  328. */
  329. if (bdp->cbd_sc & BD_ENET_TX_DEF)
  330. cep->stats.collisions++;
  331. /* Free the sk buffer associated with this last transmit.
  332. */
  333. dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]);
  334. cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK;
  335. /* Update pointer to next buffer descriptor to be transmitted.
  336. */
  337. if (bdp->cbd_sc & BD_ENET_TX_WRAP)
  338. bdp = cep->tx_bd_base;
  339. else
  340. bdp++;
  341. /* I don't know if we can be held off from processing these
  342. * interrupts for more than one frame time. I really hope
  343. * not. In such a case, we would now want to check the
  344. * currently available BD (cur_tx) and determine if any
  345. * buffers between the dirty_tx and cur_tx have also been
  346. * sent. We would want to process anything in between that
  347. * does not have BD_ENET_TX_READY set.
  348. */
  349. /* Since we have freed up a buffer, the ring is no longer
  350. * full.
  351. */
  352. if (cep->tx_full) {
  353. cep->tx_full = 0;
  354. if (netif_queue_stopped(dev))
  355. netif_wake_queue(dev);
  356. }
  357. cep->dirty_tx = (cbd_t *)bdp;
  358. }
  359. if (must_restart) {
  360. volatile cpm8xx_t *cp;
  361. /* Some transmit errors cause the transmitter to shut
  362. * down. We now issue a restart transmit. Since the
  363. * errors close the BD and update the pointers, the restart
  364. * _should_ pick up without having to reset any of our
  365. * pointers either.
  366. */
  367. cp = cpmp;
  368. cp->cp_cpcr =
  369. mk_cr_cmd(CPM_CR_ENET, CPM_CR_RESTART_TX) | CPM_CR_FLG;
  370. while (cp->cp_cpcr & CPM_CR_FLG);
  371. }
  372. spin_unlock(&cep->lock);
  373. }
  374. /* Check for receive busy, i.e. packets coming but no place to
  375. * put them. This "can't happen" because the receive interrupt
  376. * is tossing previous frames.
  377. */
  378. if (int_events & SCCE_ENET_BSY) {
  379. cep->stats.rx_dropped++;
  380. printk("CPM ENET: BSY can't happen.\n");
  381. }
  382. return;
  383. }
  384. /* During a receive, the cur_rx points to the current incoming buffer.
  385. * When we update through the ring, if the next incoming buffer has
  386. * not been given to the system, we just set the empty indicator,
  387. * effectively tossing the packet.
  388. */
  389. static int
  390. scc_enet_rx(struct net_device *dev)
  391. {
  392. struct scc_enet_private *cep;
  393. volatile cbd_t *bdp;
  394. struct sk_buff *skb;
  395. ushort pkt_len;
  396. cep = (struct scc_enet_private *)dev->priv;
  397. /* First, grab all of the stats for the incoming packet.
  398. * These get messed up if we get called due to a busy condition.
  399. */
  400. bdp = cep->cur_rx;
  401. for (;;) {
  402. if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
  403. break;
  404. #ifndef final_version
  405. /* Since we have allocated space to hold a complete frame, both
  406. * the first and last indicators should be set.
  407. */
  408. if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) !=
  409. (BD_ENET_RX_FIRST | BD_ENET_RX_LAST))
  410. printk("CPM ENET: rcv is not first+last\n");
  411. #endif
  412. /* Frame too long or too short.
  413. */
  414. if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
  415. cep->stats.rx_length_errors++;
  416. if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
  417. cep->stats.rx_frame_errors++;
  418. if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
  419. cep->stats.rx_crc_errors++;
  420. if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
  421. cep->stats.rx_crc_errors++;
  422. /* Report late collisions as a frame error.
  423. * On this error, the BD is closed, but we don't know what we
  424. * have in the buffer. So, just drop this frame on the floor.
  425. */
  426. if (bdp->cbd_sc & BD_ENET_RX_CL) {
  427. cep->stats.rx_frame_errors++;
  428. }
  429. else {
  430. /* Process the incoming frame.
  431. */
  432. cep->stats.rx_packets++;
  433. pkt_len = bdp->cbd_datlen;
  434. cep->stats.rx_bytes += pkt_len;
  435. /* This does 16 byte alignment, much more than we need.
  436. * The packet length includes FCS, but we don't want to
  437. * include that when passing upstream as it messes up
  438. * bridging applications.
  439. */
  440. skb = dev_alloc_skb(pkt_len-4);
  441. if (skb == NULL) {
  442. printk("%s: Memory squeeze, dropping packet.\n", dev->name);
  443. cep->stats.rx_dropped++;
  444. }
  445. else {
  446. skb_put(skb,pkt_len-4); /* Make room */
  447. skb_copy_to_linear_data(skb,
  448. cep->rx_vaddr[bdp - cep->rx_bd_base],
  449. pkt_len-4);
  450. skb->protocol=eth_type_trans(skb,dev);
  451. netif_rx(skb);
  452. }
  453. }
  454. /* Clear the status flags for this buffer.
  455. */
  456. bdp->cbd_sc &= ~BD_ENET_RX_STATS;
  457. /* Mark the buffer empty.
  458. */
  459. bdp->cbd_sc |= BD_ENET_RX_EMPTY;
  460. /* Update BD pointer to next entry.
  461. */
  462. if (bdp->cbd_sc & BD_ENET_RX_WRAP)
  463. bdp = cep->rx_bd_base;
  464. else
  465. bdp++;
  466. }
  467. cep->cur_rx = (cbd_t *)bdp;
  468. return 0;
  469. }
  470. static int
  471. scc_enet_close(struct net_device *dev)
  472. {
  473. /* Don't know what to do yet.
  474. */
  475. netif_stop_queue(dev);
  476. return 0;
  477. }
  478. static struct net_device_stats *scc_enet_get_stats(struct net_device *dev)
  479. {
  480. struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
  481. return &cep->stats;
  482. }
  483. /* Set or clear the multicast filter for this adaptor.
  484. * Skeleton taken from sunlance driver.
  485. * The CPM Ethernet implementation allows Multicast as well as individual
  486. * MAC address filtering. Some of the drivers check to make sure it is
  487. * a group multicast address, and discard those that are not. I guess I
  488. * will do the same for now, but just remove the test if you want
  489. * individual filtering as well (do the upper net layers want or support
  490. * this kind of feature?).
  491. */
  492. static void set_multicast_list(struct net_device *dev)
  493. {
  494. struct scc_enet_private *cep;
  495. struct dev_mc_list *dmi;
  496. u_char *mcptr, *tdptr;
  497. volatile scc_enet_t *ep;
  498. int i, j;
  499. cep = (struct scc_enet_private *)dev->priv;
  500. /* Get pointer to SCC area in parameter RAM.
  501. */
  502. ep = (scc_enet_t *)dev->base_addr;
  503. if (dev->flags&IFF_PROMISC) {
  504. /* Log any net taps. */
  505. printk("%s: Promiscuous mode enabled.\n", dev->name);
  506. cep->sccp->scc_psmr |= SCC_PSMR_PRO;
  507. } else {
  508. cep->sccp->scc_psmr &= ~SCC_PSMR_PRO;
  509. if (dev->flags & IFF_ALLMULTI) {
  510. /* Catch all multicast addresses, so set the
  511. * filter to all 1's.
  512. */
  513. ep->sen_gaddr1 = 0xffff;
  514. ep->sen_gaddr2 = 0xffff;
  515. ep->sen_gaddr3 = 0xffff;
  516. ep->sen_gaddr4 = 0xffff;
  517. }
  518. else {
  519. /* Clear filter and add the addresses in the list.
  520. */
  521. ep->sen_gaddr1 = 0;
  522. ep->sen_gaddr2 = 0;
  523. ep->sen_gaddr3 = 0;
  524. ep->sen_gaddr4 = 0;
  525. dmi = dev->mc_list;
  526. for (i=0; i<dev->mc_count; i++) {
  527. /* Only support group multicast for now.
  528. */
  529. if (!(dmi->dmi_addr[0] & 1))
  530. continue;
  531. /* The address in dmi_addr is LSB first,
  532. * and taddr is MSB first. We have to
  533. * copy bytes MSB first from dmi_addr.
  534. */
  535. mcptr = (u_char *)dmi->dmi_addr + 5;
  536. tdptr = (u_char *)&ep->sen_taddrh;
  537. for (j=0; j<6; j++)
  538. *tdptr++ = *mcptr--;
  539. /* Ask CPM to run CRC and set bit in
  540. * filter mask.
  541. */
  542. cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_SET_GADDR) | CPM_CR_FLG;
  543. /* this delay is necessary here -- Cort */
  544. udelay(10);
  545. while (cpmp->cp_cpcr & CPM_CR_FLG);
  546. }
  547. }
  548. }
  549. }
  550. /* Initialize the CPM Ethernet on SCC. If EPPC-Bug loaded us, or performed
  551. * some other network I/O, a whole bunch of this has already been set up.
  552. * It is no big deal if we do it again, we just have to disable the
  553. * transmit and receive to make sure we don't catch the CPM with some
  554. * inconsistent control information.
  555. */
  556. static int __init scc_enet_init(void)
  557. {
  558. struct net_device *dev;
  559. struct scc_enet_private *cep;
  560. int i, j, k, err;
  561. uint dp_offset;
  562. unsigned char *eap, *ba;
  563. dma_addr_t mem_addr;
  564. bd_t *bd;
  565. volatile cbd_t *bdp;
  566. volatile cpm8xx_t *cp;
  567. volatile scc_t *sccp;
  568. volatile scc_enet_t *ep;
  569. volatile immap_t *immap;
  570. cp = cpmp; /* Get pointer to Communication Processor */
  571. immap = (immap_t *)(mfspr(SPRN_IMMR) & 0xFFFF0000); /* and to internal registers */
  572. bd = (bd_t *)__res;
  573. dev = alloc_etherdev(sizeof(*cep));
  574. if (!dev)
  575. return -ENOMEM;
  576. cep = dev->priv;
  577. spin_lock_init(&cep->lock);
  578. /* Get pointer to SCC area in parameter RAM.
  579. */
  580. ep = (scc_enet_t *)(&cp->cp_dparam[PROFF_ENET]);
  581. /* And another to the SCC register area.
  582. */
  583. sccp = (volatile scc_t *)(&cp->cp_scc[SCC_ENET]);
  584. cep->sccp = (scc_t *)sccp; /* Keep the pointer handy */
  585. /* Disable receive and transmit in case EPPC-Bug started it.
  586. */
  587. sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  588. /* Cookbook style from the MPC860 manual.....
  589. * Not all of this is necessary if EPPC-Bug has initialized
  590. * the network.
  591. * So far we are lucky, all board configurations use the same
  592. * pins, or at least the same I/O Port for these functions.....
  593. * It can't last though......
  594. */
  595. #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
  596. /* Configure port A pins for Txd and Rxd.
  597. */
  598. immap->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
  599. immap->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
  600. immap->im_ioport.iop_paodr &= ~PA_ENET_TXD;
  601. #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
  602. /* Configure port B pins for Txd and Rxd.
  603. */
  604. immap->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
  605. immap->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
  606. immap->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
  607. #else
  608. #error Exactly ONE pair of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
  609. #endif
  610. #if defined(PC_ENET_LBK)
  611. /* Configure port C pins to disable External Loopback
  612. */
  613. immap->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
  614. immap->im_ioport.iop_pcdir |= PC_ENET_LBK;
  615. immap->im_ioport.iop_pcso &= ~PC_ENET_LBK;
  616. immap->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
  617. #endif /* PC_ENET_LBK */
  618. #ifdef PE_ENET_TCLK
  619. /* Configure port E for TCLK and RCLK.
  620. */
  621. cp->cp_pepar |= (PE_ENET_TCLK | PE_ENET_RCLK);
  622. cp->cp_pedir &= ~(PE_ENET_TCLK | PE_ENET_RCLK);
  623. cp->cp_peso &= ~(PE_ENET_TCLK | PE_ENET_RCLK);
  624. #else
  625. /* Configure port A for TCLK and RCLK.
  626. */
  627. immap->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
  628. immap->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
  629. #endif
  630. /* Configure port C pins to enable CLSN and RENA.
  631. */
  632. immap->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
  633. immap->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
  634. immap->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
  635. /* Configure Serial Interface clock routing.
  636. * First, clear all SCC bits to zero, then set the ones we want.
  637. */
  638. cp->cp_sicr &= ~SICR_ENET_MASK;
  639. cp->cp_sicr |= SICR_ENET_CLKRT;
  640. /* Manual says set SDDR, but I can't find anything with that
  641. * name. I think it is a misprint, and should be SDCR. This
  642. * has already been set by the communication processor initialization.
  643. */
  644. /* Allocate space for the buffer descriptors in the DP ram.
  645. * These are relative offsets in the DP ram address space.
  646. * Initialize base addresses for the buffer descriptors.
  647. */
  648. dp_offset = cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
  649. ep->sen_genscc.scc_rbase = dp_offset;
  650. cep->rx_bd_base = cpm_dpram_addr(dp_offset);
  651. dp_offset = cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
  652. ep->sen_genscc.scc_tbase = dp_offset;
  653. cep->tx_bd_base = cpm_dpram_addr(dp_offset);
  654. cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
  655. cep->cur_rx = cep->rx_bd_base;
  656. /* Issue init Rx BD command for SCC.
  657. * Manual says to perform an Init Rx parameters here. We have
  658. * to perform both Rx and Tx because the SCC may have been
  659. * already running.
  660. * In addition, we have to do it later because we don't yet have
  661. * all of the BD control/status set properly.
  662. cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_RX) | CPM_CR_FLG;
  663. while (cp->cp_cpcr & CPM_CR_FLG);
  664. */
  665. /* Initialize function code registers for big-endian.
  666. */
  667. ep->sen_genscc.scc_rfcr = SCC_EB;
  668. ep->sen_genscc.scc_tfcr = SCC_EB;
  669. /* Set maximum bytes per receive buffer.
  670. * This appears to be an Ethernet frame size, not the buffer
  671. * fragment size. It must be a multiple of four.
  672. */
  673. ep->sen_genscc.scc_mrblr = PKT_MAXBLR_SIZE;
  674. /* Set CRC preset and mask.
  675. */
  676. ep->sen_cpres = 0xffffffff;
  677. ep->sen_cmask = 0xdebb20e3;
  678. ep->sen_crcec = 0; /* CRC Error counter */
  679. ep->sen_alec = 0; /* alignment error counter */
  680. ep->sen_disfc = 0; /* discard frame counter */
  681. ep->sen_pads = 0x8888; /* Tx short frame pad character */
  682. ep->sen_retlim = 15; /* Retry limit threshold */
  683. ep->sen_maxflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
  684. ep->sen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
  685. ep->sen_maxd1 = PKT_MAXBLR_SIZE; /* maximum DMA1 length */
  686. ep->sen_maxd2 = PKT_MAXBLR_SIZE; /* maximum DMA2 length */
  687. /* Clear hash tables.
  688. */
  689. ep->sen_gaddr1 = 0;
  690. ep->sen_gaddr2 = 0;
  691. ep->sen_gaddr3 = 0;
  692. ep->sen_gaddr4 = 0;
  693. ep->sen_iaddr1 = 0;
  694. ep->sen_iaddr2 = 0;
  695. ep->sen_iaddr3 = 0;
  696. ep->sen_iaddr4 = 0;
  697. /* Set Ethernet station address.
  698. */
  699. eap = (unsigned char *)&(ep->sen_paddrh);
  700. for (i=5; i>=0; i--)
  701. *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
  702. ep->sen_pper = 0; /* 'cause the book says so */
  703. ep->sen_taddrl = 0; /* temp address (LSB) */
  704. ep->sen_taddrm = 0;
  705. ep->sen_taddrh = 0; /* temp address (MSB) */
  706. /* Now allocate the host memory pages and initialize the
  707. * buffer descriptors.
  708. */
  709. bdp = cep->tx_bd_base;
  710. for (i=0; i<TX_RING_SIZE; i++) {
  711. /* Initialize the BD for every fragment in the page.
  712. */
  713. bdp->cbd_sc = 0;
  714. bdp->cbd_bufaddr = 0;
  715. bdp++;
  716. }
  717. /* Set the last buffer to wrap.
  718. */
  719. bdp--;
  720. bdp->cbd_sc |= BD_SC_WRAP;
  721. bdp = cep->rx_bd_base;
  722. k = 0;
  723. for (i=0; i<CPM_ENET_RX_PAGES; i++) {
  724. /* Allocate a page.
  725. */
  726. ba = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE,
  727. &mem_addr, GFP_KERNEL);
  728. /* BUG: no check for failure */
  729. /* Initialize the BD for every fragment in the page.
  730. */
  731. for (j=0; j<CPM_ENET_RX_FRPPG; j++) {
  732. bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;
  733. bdp->cbd_bufaddr = mem_addr;
  734. cep->rx_vaddr[k++] = ba;
  735. mem_addr += CPM_ENET_RX_FRSIZE;
  736. ba += CPM_ENET_RX_FRSIZE;
  737. bdp++;
  738. }
  739. }
  740. /* Set the last buffer to wrap.
  741. */
  742. bdp--;
  743. bdp->cbd_sc |= BD_SC_WRAP;
  744. /* Let's re-initialize the channel now. We have to do it later
  745. * than the manual describes because we have just now finished
  746. * the BD initialization.
  747. */
  748. cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_TRX) | CPM_CR_FLG;
  749. while (cp->cp_cpcr & CPM_CR_FLG);
  750. cep->skb_cur = cep->skb_dirty = 0;
  751. sccp->scc_scce = 0xffff; /* Clear any pending events */
  752. /* Enable interrupts for transmit error, complete frame
  753. * received, and any transmit buffer we have also set the
  754. * interrupt flag.
  755. */
  756. sccp->scc_sccm = (SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB);
  757. /* Install our interrupt handler.
  758. */
  759. cpm_install_handler(CPMVEC_ENET, scc_enet_interrupt, dev);
  760. /* Set GSMR_H to enable all normal operating modes.
  761. * Set GSMR_L to enable Ethernet to MC68160.
  762. */
  763. sccp->scc_gsmrh = 0;
  764. sccp->scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET);
  765. /* Set sync/delimiters.
  766. */
  767. sccp->scc_dsr = 0xd555;
  768. /* Set processing mode. Use Ethernet CRC, catch broadcast, and
  769. * start frame search 22 bit times after RENA.
  770. */
  771. sccp->scc_psmr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
  772. /* It is now OK to enable the Ethernet transmitter.
  773. * Unfortunately, there are board implementation differences here.
  774. */
  775. #if (!defined (PB_ENET_TENA) && defined (PC_ENET_TENA) && !defined (PE_ENET_TENA))
  776. immap->im_ioport.iop_pcpar |= PC_ENET_TENA;
  777. immap->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
  778. #elif ( defined (PB_ENET_TENA) && !defined (PC_ENET_TENA) && !defined (PE_ENET_TENA))
  779. cp->cp_pbpar |= PB_ENET_TENA;
  780. cp->cp_pbdir |= PB_ENET_TENA;
  781. #elif ( !defined (PB_ENET_TENA) && !defined (PC_ENET_TENA) && defined (PE_ENET_TENA))
  782. cp->cp_pepar |= PE_ENET_TENA;
  783. cp->cp_pedir &= ~PE_ENET_TENA;
  784. cp->cp_peso |= PE_ENET_TENA;
  785. #else
  786. #error Configuration Error: define exactly ONE of PB_ENET_TENA, PC_ENET_TENA, PE_ENET_TENA
  787. #endif
  788. #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
  789. /* And while we are here, set the configuration to enable ethernet.
  790. */
  791. *((volatile uint *)RPX_CSR_ADDR) &= ~BCSR0_ETHLPBK;
  792. *((volatile uint *)RPX_CSR_ADDR) |=
  793. (BCSR0_ETHEN | BCSR0_COLTESTDIS | BCSR0_FULLDPLXDIS);
  794. #endif
  795. #ifdef CONFIG_BSEIP
  796. /* BSE uses port B and C for PHY control.
  797. */
  798. cp->cp_pbpar &= ~(PB_BSE_POWERUP | PB_BSE_FDXDIS);
  799. cp->cp_pbdir |= (PB_BSE_POWERUP | PB_BSE_FDXDIS);
  800. cp->cp_pbdat |= (PB_BSE_POWERUP | PB_BSE_FDXDIS);
  801. immap->im_ioport.iop_pcpar &= ~PC_BSE_LOOPBACK;
  802. immap->im_ioport.iop_pcdir |= PC_BSE_LOOPBACK;
  803. immap->im_ioport.iop_pcso &= ~PC_BSE_LOOPBACK;
  804. immap->im_ioport.iop_pcdat &= ~PC_BSE_LOOPBACK;
  805. #endif
  806. #ifdef CONFIG_FADS
  807. cp->cp_pbpar |= PB_ENET_TENA;
  808. cp->cp_pbdir |= PB_ENET_TENA;
  809. /* Enable the EEST PHY.
  810. */
  811. *((volatile uint *)BCSR1) &= ~BCSR1_ETHEN;
  812. #endif
  813. #ifdef CONFIG_MPC885ADS
  814. /* Deassert PHY reset and enable the PHY.
  815. */
  816. {
  817. volatile uint __iomem *bcsr = ioremap(BCSR_ADDR, BCSR_SIZE);
  818. uint tmp;
  819. tmp = in_be32(bcsr + 1 /* BCSR1 */);
  820. tmp |= BCSR1_ETHEN;
  821. out_be32(bcsr + 1, tmp);
  822. tmp = in_be32(bcsr + 4 /* BCSR4 */);
  823. tmp |= BCSR4_ETH10_RST;
  824. out_be32(bcsr + 4, tmp);
  825. iounmap(bcsr);
  826. }
  827. /* On MPC885ADS SCC ethernet PHY defaults to the full duplex mode
  828. * upon reset. SCC is set to half duplex by default. So this
  829. * inconsistency should be better fixed by the software.
  830. */
  831. #endif
  832. dev->base_addr = (unsigned long)ep;
  833. #if 0
  834. dev->name = "CPM_ENET";
  835. #endif
  836. /* The CPM Ethernet specific entries in the device structure. */
  837. dev->open = scc_enet_open;
  838. dev->hard_start_xmit = scc_enet_start_xmit;
  839. dev->tx_timeout = scc_enet_timeout;
  840. dev->watchdog_timeo = TX_TIMEOUT;
  841. dev->stop = scc_enet_close;
  842. dev->get_stats = scc_enet_get_stats;
  843. dev->set_multicast_list = set_multicast_list;
  844. err = register_netdev(dev);
  845. if (err) {
  846. free_netdev(dev);
  847. return err;
  848. }
  849. /* And last, enable the transmit and receive processing.
  850. */
  851. sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  852. printk("%s: CPM ENET Version 0.2 on SCC%d, ", dev->name, SCC_ENET+1);
  853. for (i=0; i<5; i++)
  854. printk("%02x:", dev->dev_addr[i]);
  855. printk("%02x\n", dev->dev_addr[5]);
  856. return 0;
  857. }
  858. module_init(scc_enet_init);