mpc8xx_pic.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191
  1. #include <linux/kernel.h>
  2. #include <linux/module.h>
  3. #include <linux/stddef.h>
  4. #include <linux/init.h>
  5. #include <linux/sched.h>
  6. #include <linux/signal.h>
  7. #include <linux/irq.h>
  8. #include <linux/dma-mapping.h>
  9. #include <asm/prom.h>
  10. #include <asm/irq.h>
  11. #include <asm/io.h>
  12. #include <asm/8xx_immap.h>
  13. #include <asm/mpc8xx.h>
  14. #include "mpc8xx_pic.h"
  15. #define PIC_VEC_SPURRIOUS 15
  16. extern int cpm_get_irq(struct pt_regs *regs);
  17. static struct irq_host *mpc8xx_pic_host;
  18. #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
  19. static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
  20. static sysconf8xx_t __iomem *siu_reg;
  21. int cpm_get_irq(struct pt_regs *regs);
  22. static void mpc8xx_unmask_irq(unsigned int virq)
  23. {
  24. int bit, word;
  25. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  26. bit = irq_nr & 0x1f;
  27. word = irq_nr >> 5;
  28. ppc_cached_irq_mask[word] |= (1 << (31-bit));
  29. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  30. }
  31. static void mpc8xx_mask_irq(unsigned int virq)
  32. {
  33. int bit, word;
  34. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  35. bit = irq_nr & 0x1f;
  36. word = irq_nr >> 5;
  37. ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
  38. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  39. }
  40. static void mpc8xx_ack(unsigned int virq)
  41. {
  42. int bit;
  43. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  44. bit = irq_nr & 0x1f;
  45. out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
  46. }
  47. static void mpc8xx_end_irq(unsigned int virq)
  48. {
  49. int bit, word;
  50. unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq;
  51. bit = irq_nr & 0x1f;
  52. word = irq_nr >> 5;
  53. ppc_cached_irq_mask[word] |= (1 << (31-bit));
  54. out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  55. }
  56. static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type)
  57. {
  58. struct irq_desc *desc = get_irq_desc(virq);
  59. desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
  60. desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
  61. if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  62. desc->status |= IRQ_LEVEL;
  63. if (flow_type & IRQ_TYPE_EDGE_FALLING) {
  64. irq_hw_number_t hw = (unsigned int)irq_map[virq].hwirq;
  65. unsigned int siel = in_be32(&siu_reg->sc_siel);
  66. /* only external IRQ senses are programmable */
  67. if ((hw & 1) == 0) {
  68. siel |= (0x80000000 >> hw);
  69. out_be32(&siu_reg->sc_siel, siel);
  70. desc->handle_irq = handle_edge_irq;
  71. }
  72. }
  73. return 0;
  74. }
  75. static struct irq_chip mpc8xx_pic = {
  76. .typename = " MPC8XX SIU ",
  77. .unmask = mpc8xx_unmask_irq,
  78. .mask = mpc8xx_mask_irq,
  79. .ack = mpc8xx_ack,
  80. .eoi = mpc8xx_end_irq,
  81. .set_type = mpc8xx_set_irq_type,
  82. };
  83. unsigned int mpc8xx_get_irq(void)
  84. {
  85. int irq;
  86. /* For MPC8xx, read the SIVEC register and shift the bits down
  87. * to get the irq number.
  88. */
  89. irq = in_be32(&siu_reg->sc_sivec) >> 26;
  90. if (irq == PIC_VEC_SPURRIOUS)
  91. irq = NO_IRQ;
  92. return irq_linear_revmap(mpc8xx_pic_host, irq);
  93. }
  94. static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
  95. irq_hw_number_t hw)
  96. {
  97. pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
  98. /* Set default irq handle */
  99. set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
  100. return 0;
  101. }
  102. static int mpc8xx_pic_host_xlate(struct irq_host *h, struct device_node *ct,
  103. u32 *intspec, unsigned int intsize,
  104. irq_hw_number_t *out_hwirq, unsigned int *out_flags)
  105. {
  106. static unsigned char map_pic_senses[4] = {
  107. IRQ_TYPE_EDGE_RISING,
  108. IRQ_TYPE_LEVEL_LOW,
  109. IRQ_TYPE_LEVEL_HIGH,
  110. IRQ_TYPE_EDGE_FALLING,
  111. };
  112. *out_hwirq = intspec[0];
  113. if (intsize > 1 && intspec[1] < 4)
  114. *out_flags = map_pic_senses[intspec[1]];
  115. else
  116. *out_flags = IRQ_TYPE_NONE;
  117. return 0;
  118. }
  119. static struct irq_host_ops mpc8xx_pic_host_ops = {
  120. .map = mpc8xx_pic_host_map,
  121. .xlate = mpc8xx_pic_host_xlate,
  122. };
  123. int mpc8xx_pic_init(void)
  124. {
  125. struct resource res;
  126. struct device_node *np;
  127. int ret;
  128. np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
  129. if (np == NULL)
  130. np = of_find_node_by_type(NULL, "mpc8xx-pic");
  131. if (np == NULL) {
  132. printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
  133. return -ENOMEM;
  134. }
  135. ret = of_address_to_resource(np, 0, &res);
  136. if (ret)
  137. goto out;
  138. siu_reg = ioremap(res.start, res.end - res.start + 1);
  139. if (siu_reg == NULL)
  140. return -EINVAL;
  141. mpc8xx_pic_host = irq_alloc_host(of_node_get(np), IRQ_HOST_MAP_LINEAR,
  142. 64, &mpc8xx_pic_host_ops, 64);
  143. if (mpc8xx_pic_host == NULL) {
  144. printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
  145. ret = -ENOMEM;
  146. }
  147. out:
  148. of_node_put(np);
  149. return ret;
  150. }