smp.c 6.0 KB

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  1. /*
  2. * SMP support for pSeries machines.
  3. *
  4. * Dave Engebretsen, Peter Bergner, and
  5. * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
  6. *
  7. * Plus various changes from other IBM teams...
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version
  12. * 2 of the License, or (at your option) any later version.
  13. */
  14. #undef DEBUG
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/sched.h>
  18. #include <linux/smp.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/delay.h>
  21. #include <linux/init.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/cache.h>
  24. #include <linux/err.h>
  25. #include <linux/sysdev.h>
  26. #include <linux/cpu.h>
  27. #include <asm/ptrace.h>
  28. #include <asm/atomic.h>
  29. #include <asm/irq.h>
  30. #include <asm/page.h>
  31. #include <asm/pgtable.h>
  32. #include <asm/io.h>
  33. #include <asm/prom.h>
  34. #include <asm/smp.h>
  35. #include <asm/paca.h>
  36. #include <asm/time.h>
  37. #include <asm/machdep.h>
  38. #include "xics.h"
  39. #include <asm/cputable.h>
  40. #include <asm/firmware.h>
  41. #include <asm/system.h>
  42. #include <asm/rtas.h>
  43. #include <asm/pSeries_reconfig.h>
  44. #include <asm/mpic.h>
  45. #include <asm/vdso_datapage.h>
  46. #include "plpar_wrappers.h"
  47. #include "pseries.h"
  48. #ifdef DEBUG
  49. #include <asm/udbg.h>
  50. #define DBG(fmt...) udbg_printf(fmt)
  51. #else
  52. #define DBG(fmt...)
  53. #endif
  54. /*
  55. * The primary thread of each non-boot processor is recorded here before
  56. * smp init.
  57. */
  58. static cpumask_t of_spin_map;
  59. extern void generic_secondary_smp_init(unsigned long);
  60. /**
  61. * smp_startup_cpu() - start the given cpu
  62. *
  63. * At boot time, there is nothing to do for primary threads which were
  64. * started from Open Firmware. For anything else, call RTAS with the
  65. * appropriate start location.
  66. *
  67. * Returns:
  68. * 0 - failure
  69. * 1 - success
  70. */
  71. static inline int __devinit smp_startup_cpu(unsigned int lcpu)
  72. {
  73. int status;
  74. unsigned long start_here = __pa((u32)*((unsigned long *)
  75. generic_secondary_smp_init));
  76. unsigned int pcpu;
  77. int start_cpu;
  78. if (cpu_isset(lcpu, of_spin_map))
  79. /* Already started by OF and sitting in spin loop */
  80. return 1;
  81. pcpu = get_hard_smp_processor_id(lcpu);
  82. /* Fixup atomic count: it exited inside IRQ handler. */
  83. task_thread_info(paca[lcpu].__current)->preempt_count = 0;
  84. /*
  85. * If the RTAS start-cpu token does not exist then presume the
  86. * cpu is already spinning.
  87. */
  88. start_cpu = rtas_token("start-cpu");
  89. if (start_cpu == RTAS_UNKNOWN_SERVICE)
  90. return 1;
  91. status = rtas_call(start_cpu, 3, 1, NULL, pcpu, start_here, pcpu);
  92. if (status != 0) {
  93. printk(KERN_ERR "start-cpu failed: %i\n", status);
  94. return 0;
  95. }
  96. return 1;
  97. }
  98. #ifdef CONFIG_XICS
  99. static inline void smp_xics_do_message(int cpu, int msg)
  100. {
  101. set_bit(msg, &xics_ipi_message[cpu].value);
  102. mb();
  103. xics_cause_IPI(cpu);
  104. }
  105. static void smp_xics_message_pass(int target, int msg)
  106. {
  107. unsigned int i;
  108. if (target < NR_CPUS) {
  109. smp_xics_do_message(target, msg);
  110. } else {
  111. for_each_online_cpu(i) {
  112. if (target == MSG_ALL_BUT_SELF
  113. && i == smp_processor_id())
  114. continue;
  115. smp_xics_do_message(i, msg);
  116. }
  117. }
  118. }
  119. static int __init smp_xics_probe(void)
  120. {
  121. xics_request_IPIs();
  122. return cpus_weight(cpu_possible_map);
  123. }
  124. static void __devinit smp_xics_setup_cpu(int cpu)
  125. {
  126. if (cpu != boot_cpuid)
  127. xics_setup_cpu();
  128. if (firmware_has_feature(FW_FEATURE_SPLPAR))
  129. vpa_init(cpu);
  130. cpu_clear(cpu, of_spin_map);
  131. }
  132. #endif /* CONFIG_XICS */
  133. static DEFINE_SPINLOCK(timebase_lock);
  134. static unsigned long timebase = 0;
  135. static void __devinit pSeries_give_timebase(void)
  136. {
  137. spin_lock(&timebase_lock);
  138. rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
  139. timebase = get_tb();
  140. spin_unlock(&timebase_lock);
  141. while (timebase)
  142. barrier();
  143. rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
  144. }
  145. static void __devinit pSeries_take_timebase(void)
  146. {
  147. while (!timebase)
  148. barrier();
  149. spin_lock(&timebase_lock);
  150. set_tb(timebase >> 32, timebase & 0xffffffff);
  151. timebase = 0;
  152. spin_unlock(&timebase_lock);
  153. }
  154. static void __devinit smp_pSeries_kick_cpu(int nr)
  155. {
  156. BUG_ON(nr < 0 || nr >= NR_CPUS);
  157. if (!smp_startup_cpu(nr))
  158. return;
  159. /*
  160. * The processor is currently spinning, waiting for the
  161. * cpu_start field to become non-zero After we set cpu_start,
  162. * the processor will continue on to secondary_start
  163. */
  164. paca[nr].cpu_start = 1;
  165. }
  166. static int smp_pSeries_cpu_bootable(unsigned int nr)
  167. {
  168. /* Special case - we inhibit secondary thread startup
  169. * during boot if the user requests it. Odd-numbered
  170. * cpus are assumed to be secondary threads.
  171. */
  172. if (system_state < SYSTEM_RUNNING &&
  173. cpu_has_feature(CPU_FTR_SMT) &&
  174. !smt_enabled_at_boot && nr % 2 != 0)
  175. return 0;
  176. return 1;
  177. }
  178. #ifdef CONFIG_MPIC
  179. static struct smp_ops_t pSeries_mpic_smp_ops = {
  180. .message_pass = smp_mpic_message_pass,
  181. .probe = smp_mpic_probe,
  182. .kick_cpu = smp_pSeries_kick_cpu,
  183. .setup_cpu = smp_mpic_setup_cpu,
  184. };
  185. #endif
  186. #ifdef CONFIG_XICS
  187. static struct smp_ops_t pSeries_xics_smp_ops = {
  188. .message_pass = smp_xics_message_pass,
  189. .probe = smp_xics_probe,
  190. .kick_cpu = smp_pSeries_kick_cpu,
  191. .setup_cpu = smp_xics_setup_cpu,
  192. .cpu_bootable = smp_pSeries_cpu_bootable,
  193. };
  194. #endif
  195. /* This is called very early */
  196. static void __init smp_init_pseries(void)
  197. {
  198. int i;
  199. DBG(" -> smp_init_pSeries()\n");
  200. /* Mark threads which are still spinning in hold loops. */
  201. if (cpu_has_feature(CPU_FTR_SMT)) {
  202. for_each_present_cpu(i) {
  203. if (i % 2 == 0)
  204. /*
  205. * Even-numbered logical cpus correspond to
  206. * primary threads.
  207. */
  208. cpu_set(i, of_spin_map);
  209. }
  210. } else {
  211. of_spin_map = cpu_present_map;
  212. }
  213. cpu_clear(boot_cpuid, of_spin_map);
  214. /* Non-lpar has additional take/give timebase */
  215. if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) {
  216. smp_ops->give_timebase = pSeries_give_timebase;
  217. smp_ops->take_timebase = pSeries_take_timebase;
  218. }
  219. DBG(" <- smp_init_pSeries()\n");
  220. }
  221. #ifdef CONFIG_MPIC
  222. void __init smp_init_pseries_mpic(void)
  223. {
  224. smp_ops = &pSeries_mpic_smp_ops;
  225. smp_init_pseries();
  226. }
  227. #endif
  228. void __init smp_init_pseries_xics(void)
  229. {
  230. smp_ops = &pSeries_xics_smp_ops;
  231. smp_init_pseries();
  232. }