exception.S 6.8 KB

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  1. /*
  2. * Low level routines for legacy iSeries support.
  3. *
  4. * Extracted from head_64.S
  5. *
  6. * PowerPC version
  7. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  8. *
  9. * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
  10. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  11. * Adapted for Power Macintosh by Paul Mackerras.
  12. * Low-level exception handlers and MMU support
  13. * rewritten by Paul Mackerras.
  14. * Copyright (C) 1996 Paul Mackerras.
  15. *
  16. * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
  17. * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
  18. *
  19. * This file contains the low-level support and setup for the
  20. * PowerPC-64 platform, including trap and interrupt dispatch.
  21. *
  22. * This program is free software; you can redistribute it and/or
  23. * modify it under the terms of the GNU General Public License
  24. * as published by the Free Software Foundation; either version
  25. * 2 of the License, or (at your option) any later version.
  26. */
  27. #include <asm/reg.h>
  28. #include <asm/ppc_asm.h>
  29. #include <asm/asm-offsets.h>
  30. #include <asm/thread_info.h>
  31. #include <asm/ptrace.h>
  32. #include <asm/cputable.h>
  33. #include "exception.h"
  34. .text
  35. .globl system_reset_iSeries
  36. system_reset_iSeries:
  37. mfspr r13,SPRN_SPRG3 /* Get paca address */
  38. mfmsr r24
  39. ori r24,r24,MSR_RI
  40. mtmsrd r24 /* RI on */
  41. lhz r24,PACAPACAINDEX(r13) /* Get processor # */
  42. cmpwi 0,r24,0 /* Are we processor 0? */
  43. bne 1f
  44. b .__start_initialization_iSeries /* Start up the first processor */
  45. 1: mfspr r4,SPRN_CTRLF
  46. li r5,CTRL_RUNLATCH /* Turn off the run light */
  47. andc r4,r4,r5
  48. mtspr SPRN_CTRLT,r4
  49. 1:
  50. HMT_LOW
  51. #ifdef CONFIG_SMP
  52. lbz r23,PACAPROCSTART(r13) /* Test if this processor
  53. * should start */
  54. sync
  55. LOAD_REG_IMMEDIATE(r3,current_set)
  56. sldi r28,r24,3 /* get current_set[cpu#] */
  57. ldx r3,r3,r28
  58. addi r1,r3,THREAD_SIZE
  59. subi r1,r1,STACK_FRAME_OVERHEAD
  60. cmpwi 0,r23,0
  61. beq iSeries_secondary_smp_loop /* Loop until told to go */
  62. b __secondary_start /* Loop until told to go */
  63. iSeries_secondary_smp_loop:
  64. /* Let the Hypervisor know we are alive */
  65. /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
  66. lis r3,0x8002
  67. rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
  68. #else /* CONFIG_SMP */
  69. /* Yield the processor. This is required for non-SMP kernels
  70. which are running on multi-threaded machines. */
  71. lis r3,0x8000
  72. rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
  73. addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
  74. li r4,0 /* "yield timed" */
  75. li r5,-1 /* "yield forever" */
  76. #endif /* CONFIG_SMP */
  77. li r0,-1 /* r0=-1 indicates a Hypervisor call */
  78. sc /* Invoke the hypervisor via a system call */
  79. mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
  80. b 1b /* If SMP not configured, secondaries
  81. * loop forever */
  82. /*** ISeries-LPAR interrupt handlers ***/
  83. STD_EXCEPTION_ISERIES(machine_check, PACA_EXMC)
  84. .globl data_access_iSeries
  85. data_access_iSeries:
  86. mtspr SPRN_SPRG1,r13
  87. BEGIN_FTR_SECTION
  88. mtspr SPRN_SPRG2,r12
  89. mfspr r13,SPRN_DAR
  90. mfspr r12,SPRN_DSISR
  91. srdi r13,r13,60
  92. rlwimi r13,r12,16,0x20
  93. mfcr r12
  94. cmpwi r13,0x2c
  95. beq .do_stab_bolted_iSeries
  96. mtcrf 0x80,r12
  97. mfspr r12,SPRN_SPRG2
  98. END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
  99. EXCEPTION_PROLOG_1(PACA_EXGEN)
  100. EXCEPTION_PROLOG_ISERIES_1
  101. b data_access_common
  102. .do_stab_bolted_iSeries:
  103. mtcrf 0x80,r12
  104. mfspr r12,SPRN_SPRG2
  105. EXCEPTION_PROLOG_1(PACA_EXSLB)
  106. EXCEPTION_PROLOG_ISERIES_1
  107. b .do_stab_bolted
  108. .globl data_access_slb_iSeries
  109. data_access_slb_iSeries:
  110. mtspr SPRN_SPRG1,r13 /* save r13 */
  111. mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
  112. std r3,PACA_EXSLB+EX_R3(r13)
  113. mfspr r3,SPRN_DAR
  114. std r9,PACA_EXSLB+EX_R9(r13)
  115. mfcr r9
  116. #ifdef __DISABLED__
  117. cmpdi r3,0
  118. bge slb_miss_user_iseries
  119. #endif
  120. std r10,PACA_EXSLB+EX_R10(r13)
  121. std r11,PACA_EXSLB+EX_R11(r13)
  122. std r12,PACA_EXSLB+EX_R12(r13)
  123. mfspr r10,SPRN_SPRG1
  124. std r10,PACA_EXSLB+EX_R13(r13)
  125. ld r12,PACALPPACAPTR(r13)
  126. ld r12,LPPACASRR1(r12)
  127. b .slb_miss_realmode
  128. STD_EXCEPTION_ISERIES(instruction_access, PACA_EXGEN)
  129. .globl instruction_access_slb_iSeries
  130. instruction_access_slb_iSeries:
  131. mtspr SPRN_SPRG1,r13 /* save r13 */
  132. mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
  133. std r3,PACA_EXSLB+EX_R3(r13)
  134. ld r3,PACALPPACAPTR(r13)
  135. ld r3,LPPACASRR0(r3) /* get SRR0 value */
  136. std r9,PACA_EXSLB+EX_R9(r13)
  137. mfcr r9
  138. #ifdef __DISABLED__
  139. cmpdi r3,0
  140. bge slb_miss_user_iseries
  141. #endif
  142. std r10,PACA_EXSLB+EX_R10(r13)
  143. std r11,PACA_EXSLB+EX_R11(r13)
  144. std r12,PACA_EXSLB+EX_R12(r13)
  145. mfspr r10,SPRN_SPRG1
  146. std r10,PACA_EXSLB+EX_R13(r13)
  147. ld r12,PACALPPACAPTR(r13)
  148. ld r12,LPPACASRR1(r12)
  149. b .slb_miss_realmode
  150. #ifdef __DISABLED__
  151. slb_miss_user_iseries:
  152. std r10,PACA_EXGEN+EX_R10(r13)
  153. std r11,PACA_EXGEN+EX_R11(r13)
  154. std r12,PACA_EXGEN+EX_R12(r13)
  155. mfspr r10,SPRG1
  156. ld r11,PACA_EXSLB+EX_R9(r13)
  157. ld r12,PACA_EXSLB+EX_R3(r13)
  158. std r10,PACA_EXGEN+EX_R13(r13)
  159. std r11,PACA_EXGEN+EX_R9(r13)
  160. std r12,PACA_EXGEN+EX_R3(r13)
  161. EXCEPTION_PROLOG_ISERIES_1
  162. b slb_miss_user_common
  163. #endif
  164. MASKABLE_EXCEPTION_ISERIES(hardware_interrupt)
  165. STD_EXCEPTION_ISERIES(alignment, PACA_EXGEN)
  166. STD_EXCEPTION_ISERIES(program_check, PACA_EXGEN)
  167. STD_EXCEPTION_ISERIES(fp_unavailable, PACA_EXGEN)
  168. MASKABLE_EXCEPTION_ISERIES(decrementer)
  169. STD_EXCEPTION_ISERIES(trap_0a, PACA_EXGEN)
  170. STD_EXCEPTION_ISERIES(trap_0b, PACA_EXGEN)
  171. .globl system_call_iSeries
  172. system_call_iSeries:
  173. mr r9,r13
  174. mfspr r13,SPRN_SPRG3
  175. EXCEPTION_PROLOG_ISERIES_1
  176. b system_call_common
  177. STD_EXCEPTION_ISERIES(single_step, PACA_EXGEN)
  178. STD_EXCEPTION_ISERIES(trap_0e, PACA_EXGEN)
  179. STD_EXCEPTION_ISERIES(performance_monitor, PACA_EXGEN)
  180. decrementer_iSeries_masked:
  181. /* We may not have a valid TOC pointer in here. */
  182. li r11,1
  183. ld r12,PACALPPACAPTR(r13)
  184. stb r11,LPPACADECRINT(r12)
  185. LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
  186. lwz r12,0(r12)
  187. mtspr SPRN_DEC,r12
  188. /* fall through */
  189. hardware_interrupt_iSeries_masked:
  190. mtcrf 0x80,r9 /* Restore regs */
  191. ld r12,PACALPPACAPTR(r13)
  192. ld r11,LPPACASRR0(r12)
  193. ld r12,LPPACASRR1(r12)
  194. mtspr SPRN_SRR0,r11
  195. mtspr SPRN_SRR1,r12
  196. ld r9,PACA_EXGEN+EX_R9(r13)
  197. ld r10,PACA_EXGEN+EX_R10(r13)
  198. ld r11,PACA_EXGEN+EX_R11(r13)
  199. ld r12,PACA_EXGEN+EX_R12(r13)
  200. ld r13,PACA_EXGEN+EX_R13(r13)
  201. rfid
  202. b . /* prevent speculative execution */
  203. _INIT_STATIC(__start_initialization_iSeries)
  204. /* Clear out the BSS */
  205. LOAD_REG_IMMEDIATE(r11,__bss_stop)
  206. LOAD_REG_IMMEDIATE(r8,__bss_start)
  207. sub r11,r11,r8 /* bss size */
  208. addi r11,r11,7 /* round up to an even double word */
  209. rldicl. r11,r11,61,3 /* shift right by 3 */
  210. beq 4f
  211. addi r8,r8,-8
  212. li r0,0
  213. mtctr r11 /* zero this many doublewords */
  214. 3: stdu r0,8(r8)
  215. bdnz 3b
  216. 4:
  217. LOAD_REG_IMMEDIATE(r1,init_thread_union)
  218. addi r1,r1,THREAD_SIZE
  219. li r0,0
  220. stdu r0,-STACK_FRAME_OVERHEAD(r1)
  221. LOAD_REG_IMMEDIATE(r2,__toc_start)
  222. addi r2,r2,0x4000
  223. addi r2,r2,0x4000
  224. bl .iSeries_early_setup
  225. bl .early_setup
  226. /* relocation is on at this point */
  227. b .start_here_common