fsl_uli1575.c 6.3 KB

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  1. /*
  2. * ULI M1575 setup code - specific to Freescale boards
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/stddef.h>
  12. #include <linux/kernel.h>
  13. #include <linux/pci.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/mc146818rtc.h>
  16. #include <asm/system.h>
  17. #include <asm/pci-bridge.h>
  18. #define ULI_PIRQA 0x08
  19. #define ULI_PIRQB 0x09
  20. #define ULI_PIRQC 0x0a
  21. #define ULI_PIRQD 0x0b
  22. #define ULI_PIRQE 0x0c
  23. #define ULI_PIRQF 0x0d
  24. #define ULI_PIRQG 0x0e
  25. #define ULI_8259_NONE 0x00
  26. #define ULI_8259_IRQ1 0x08
  27. #define ULI_8259_IRQ3 0x02
  28. #define ULI_8259_IRQ4 0x04
  29. #define ULI_8259_IRQ5 0x05
  30. #define ULI_8259_IRQ6 0x07
  31. #define ULI_8259_IRQ7 0x06
  32. #define ULI_8259_IRQ9 0x01
  33. #define ULI_8259_IRQ10 0x03
  34. #define ULI_8259_IRQ11 0x09
  35. #define ULI_8259_IRQ12 0x0b
  36. #define ULI_8259_IRQ14 0x0d
  37. #define ULI_8259_IRQ15 0x0f
  38. u8 uli_pirq_to_irq[8] = {
  39. ULI_8259_IRQ9, /* PIRQA */
  40. ULI_8259_IRQ10, /* PIRQB */
  41. ULI_8259_IRQ11, /* PIRQC */
  42. ULI_8259_IRQ12, /* PIRQD */
  43. ULI_8259_IRQ5, /* PIRQE */
  44. ULI_8259_IRQ6, /* PIRQF */
  45. ULI_8259_IRQ7, /* PIRQG */
  46. ULI_8259_NONE, /* PIRQH */
  47. };
  48. /* set in board code if you want this quirks to do something */
  49. int uses_fsl_uli_m1575;
  50. /* Bridge */
  51. static void __devinit early_uli5249(struct pci_dev *dev)
  52. {
  53. unsigned char temp;
  54. if (!uses_fsl_uli_m1575)
  55. return;
  56. pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO |
  57. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  58. /* read/write lock */
  59. pci_read_config_byte(dev, 0x7c, &temp);
  60. pci_write_config_byte(dev, 0x7c, 0x80);
  61. /* set as P2P bridge */
  62. pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
  63. dev->class |= 0x1;
  64. /* restore lock */
  65. pci_write_config_byte(dev, 0x7c, temp);
  66. }
  67. static void __devinit quirk_uli1575(struct pci_dev *dev)
  68. {
  69. int i;
  70. if (!uses_fsl_uli_m1575)
  71. return;
  72. /*
  73. * ULI1575 interrupts route setup
  74. */
  75. /* ULI1575 IRQ mapping conf register maps PIRQx to IRQn */
  76. for (i = 0; i < 4; i++) {
  77. u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4);
  78. pci_write_config_byte(dev, 0x48 + i, val);
  79. }
  80. /* USB 1.1 OHCI controller 1: dev 28, func 0 - IRQ12 */
  81. pci_write_config_byte(dev, 0x86, ULI_PIRQD);
  82. /* USB 1.1 OHCI controller 2: dev 28, func 1 - IRQ9 */
  83. pci_write_config_byte(dev, 0x87, ULI_PIRQA);
  84. /* USB 1.1 OHCI controller 3: dev 28, func 2 - IRQ10 */
  85. pci_write_config_byte(dev, 0x88, ULI_PIRQB);
  86. /* Lan controller: dev 27, func 0 - IRQ6 */
  87. pci_write_config_byte(dev, 0x89, ULI_PIRQF);
  88. /* AC97 Audio controller: dev 29, func 0 - IRQ6 */
  89. pci_write_config_byte(dev, 0x8a, ULI_PIRQF);
  90. /* Modem controller: dev 29, func 1 - IRQ6 */
  91. pci_write_config_byte(dev, 0x8b, ULI_PIRQF);
  92. /* HD Audio controller: dev 29, func 2 - IRQ6 */
  93. pci_write_config_byte(dev, 0x8c, ULI_PIRQF);
  94. /* SATA controller: dev 31, func 1 - IRQ5 */
  95. pci_write_config_byte(dev, 0x8d, ULI_PIRQE);
  96. /* SMB interrupt: dev 30, func 1 - IRQ7 */
  97. pci_write_config_byte(dev, 0x8e, ULI_PIRQG);
  98. /* PMU ACPI SCI interrupt: dev 30, func 2 - IRQ7 */
  99. pci_write_config_byte(dev, 0x8f, ULI_PIRQG);
  100. /* USB 2.0 controller: dev 28, func 3 */
  101. pci_write_config_byte(dev, 0x74, ULI_8259_IRQ11);
  102. /* Primary PATA IDE IRQ: 14
  103. * Secondary PATA IDE IRQ: 15
  104. */
  105. pci_write_config_byte(dev, 0x44, 0x30 | ULI_8259_IRQ14);
  106. pci_write_config_byte(dev, 0x75, ULI_8259_IRQ15);
  107. }
  108. static void __devinit quirk_final_uli1575(struct pci_dev *dev)
  109. {
  110. /* Set i8259 interrupt trigger
  111. * IRQ 3: Level
  112. * IRQ 4: Level
  113. * IRQ 5: Level
  114. * IRQ 6: Level
  115. * IRQ 7: Level
  116. * IRQ 9: Level
  117. * IRQ 10: Level
  118. * IRQ 11: Level
  119. * IRQ 12: Level
  120. * IRQ 14: Edge
  121. * IRQ 15: Edge
  122. */
  123. if (!uses_fsl_uli_m1575)
  124. return;
  125. outb(0xfa, 0x4d0);
  126. outb(0x1e, 0x4d1);
  127. /* setup RTC */
  128. CMOS_WRITE(RTC_SET, RTC_CONTROL);
  129. CMOS_WRITE(RTC_24H, RTC_CONTROL);
  130. /* ensure month, date, and week alarm fields are ignored */
  131. CMOS_WRITE(0, RTC_VALID);
  132. outb_p(0x7c, 0x72);
  133. outb_p(RTC_ALARM_DONT_CARE, 0x73);
  134. outb_p(0x7d, 0x72);
  135. outb_p(RTC_ALARM_DONT_CARE, 0x73);
  136. }
  137. /* SATA */
  138. static void __devinit quirk_uli5288(struct pci_dev *dev)
  139. {
  140. unsigned char c;
  141. unsigned int d;
  142. if (!uses_fsl_uli_m1575)
  143. return;
  144. /* read/write lock */
  145. pci_read_config_byte(dev, 0x83, &c);
  146. pci_write_config_byte(dev, 0x83, c|0x80);
  147. pci_read_config_dword(dev, PCI_CLASS_REVISION, &d);
  148. d = (d & 0xff) | (PCI_CLASS_STORAGE_SATA_AHCI << 8);
  149. pci_write_config_dword(dev, PCI_CLASS_REVISION, d);
  150. /* restore lock */
  151. pci_write_config_byte(dev, 0x83, c);
  152. /* disable emulated PATA mode enabled */
  153. pci_read_config_byte(dev, 0x84, &c);
  154. pci_write_config_byte(dev, 0x84, c & ~0x01);
  155. }
  156. /* PATA */
  157. static void __devinit quirk_uli5229(struct pci_dev *dev)
  158. {
  159. unsigned short temp;
  160. if (!uses_fsl_uli_m1575)
  161. return;
  162. pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE |
  163. PCI_COMMAND_MASTER | PCI_COMMAND_IO);
  164. /* Enable Native IRQ 14/15 */
  165. pci_read_config_word(dev, 0x4a, &temp);
  166. pci_write_config_word(dev, 0x4a, temp | 0x1000);
  167. }
  168. /* We have to do a dummy read on the P2P for the RTC to work, WTF */
  169. static void __devinit quirk_final_uli5249(struct pci_dev *dev)
  170. {
  171. int i;
  172. u8 *dummy;
  173. struct pci_bus *bus = dev->bus;
  174. for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
  175. if ((bus->resource[i]) &&
  176. (bus->resource[i]->flags & IORESOURCE_MEM)) {
  177. dummy = ioremap(bus->resource[i]->start, 0x4);
  178. if (dummy) {
  179. in_8(dummy);
  180. iounmap(dummy);
  181. }
  182. break;
  183. }
  184. }
  185. }
  186. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
  187. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
  188. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
  189. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
  190. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249);
  191. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575);
  192. int uli_exclude_device(struct pci_controller *hose,
  193. u_char bus, u_char devfn)
  194. {
  195. if (bus == (hose->first_busno + 2)) {
  196. /* exclude Modem controller */
  197. if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1))
  198. return PCIBIOS_DEVICE_NOT_FOUND;
  199. /* exclude HD Audio controller */
  200. if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 2))
  201. return PCIBIOS_DEVICE_NOT_FOUND;
  202. }
  203. return PCIBIOS_SUCCESSFUL;
  204. }