mpc832x_rdb.c 4.2 KB

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  1. /*
  2. * arch/powerpc/platforms/83xx/mpc832x_rdb.c
  3. *
  4. * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
  5. *
  6. * Description:
  7. * MPC832x RDB board specific routines.
  8. * This file is based on mpc832x_mds.c and mpc8313_rdb.c
  9. * Author: Michael Barkowski <michael.barkowski@freescale.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. */
  16. #include <linux/pci.h>
  17. #include <linux/spi/spi.h>
  18. #include <asm/of_platform.h>
  19. #include <asm/time.h>
  20. #include <asm/ipic.h>
  21. #include <asm/udbg.h>
  22. #include <asm/qe.h>
  23. #include <asm/qe_ic.h>
  24. #include <sysdev/fsl_soc.h>
  25. #include "mpc83xx.h"
  26. #undef DEBUG
  27. #ifdef DEBUG
  28. #define DBG(fmt...) udbg_printf(fmt)
  29. #else
  30. #define DBG(fmt...)
  31. #endif
  32. static void mpc83xx_spi_activate_cs(u8 cs, u8 polarity)
  33. {
  34. pr_debug("%s %d %d\n", __func__, cs, polarity);
  35. par_io_data_set(3, 13, polarity);
  36. }
  37. static void mpc83xx_spi_deactivate_cs(u8 cs, u8 polarity)
  38. {
  39. pr_debug("%s %d %d\n", __func__, cs, polarity);
  40. par_io_data_set(3, 13, !polarity);
  41. }
  42. static struct spi_board_info mpc832x_spi_boardinfo = {
  43. .bus_num = 0x4c0,
  44. .chip_select = 0,
  45. .max_speed_hz = 50000000,
  46. /*
  47. * XXX: This is spidev (spi in userspace) stub, should
  48. * be replaced by "mmc_spi" when mmc_spi will hit mainline.
  49. */
  50. .modalias = "spidev",
  51. };
  52. static int __init mpc832x_spi_init(void)
  53. {
  54. if (!machine_is(mpc832x_rdb))
  55. return 0;
  56. par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */
  57. par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */
  58. par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */
  59. par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */
  60. par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */
  61. par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */
  62. par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */
  63. return fsl_spi_init(&mpc832x_spi_boardinfo, 1,
  64. mpc83xx_spi_activate_cs,
  65. mpc83xx_spi_deactivate_cs);
  66. }
  67. device_initcall(mpc832x_spi_init);
  68. /* ************************************************************************
  69. *
  70. * Setup the architecture
  71. *
  72. */
  73. static void __init mpc832x_rdb_setup_arch(void)
  74. {
  75. #if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
  76. struct device_node *np;
  77. #endif
  78. if (ppc_md.progress)
  79. ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
  80. #ifdef CONFIG_PCI
  81. for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
  82. mpc83xx_add_bridge(np);
  83. #endif
  84. #ifdef CONFIG_QUICC_ENGINE
  85. qe_reset();
  86. if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
  87. par_io_init(np);
  88. of_node_put(np);
  89. for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  90. par_io_of_config(np);
  91. }
  92. #endif /* CONFIG_QUICC_ENGINE */
  93. }
  94. static struct of_device_id mpc832x_ids[] = {
  95. { .type = "soc", },
  96. { .compatible = "soc", },
  97. { .type = "qe", },
  98. {},
  99. };
  100. static int __init mpc832x_declare_of_platform_devices(void)
  101. {
  102. if (!machine_is(mpc832x_rdb))
  103. return 0;
  104. /* Publish the QE devices */
  105. of_platform_bus_probe(NULL, mpc832x_ids, NULL);
  106. return 0;
  107. }
  108. device_initcall(mpc832x_declare_of_platform_devices);
  109. void __init mpc832x_rdb_init_IRQ(void)
  110. {
  111. struct device_node *np;
  112. np = of_find_node_by_type(NULL, "ipic");
  113. if (!np)
  114. return;
  115. ipic_init(np, 0);
  116. /* Initialize the default interrupt mapping priorities,
  117. * in case the boot rom changed something on us.
  118. */
  119. ipic_set_default_priority();
  120. of_node_put(np);
  121. #ifdef CONFIG_QUICC_ENGINE
  122. np = of_find_node_by_type(NULL, "qeic");
  123. if (!np)
  124. return;
  125. qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
  126. of_node_put(np);
  127. #endif /* CONFIG_QUICC_ENGINE */
  128. }
  129. /*
  130. * Called very early, MMU is off, device-tree isn't unflattened
  131. */
  132. static int __init mpc832x_rdb_probe(void)
  133. {
  134. unsigned long root = of_get_flat_dt_root();
  135. return of_flat_dt_is_compatible(root, "MPC832xRDB");
  136. }
  137. define_machine(mpc832x_rdb) {
  138. .name = "MPC832x RDB",
  139. .probe = mpc832x_rdb_probe,
  140. .setup_arch = mpc832x_rdb_setup_arch,
  141. .init_IRQ = mpc832x_rdb_init_IRQ,
  142. .get_irq = ipic_get_irq,
  143. .restart = mpc83xx_restart,
  144. .time_init = mpc83xx_time_init,
  145. .calibrate_decr = generic_calibrate_decr,
  146. .progress = udbg_progress,
  147. };