cacheflush.S 1.5 KB

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  1. /*
  2. * vDSO provided cache flush routines
  3. *
  4. * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
  5. * IBM Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <asm/processor.h>
  13. #include <asm/ppc_asm.h>
  14. #include <asm/vdso.h>
  15. #include <asm/asm-offsets.h>
  16. .text
  17. /*
  18. * Default "generic" version of __kernel_sync_dicache.
  19. *
  20. * void __kernel_sync_dicache(unsigned long start, unsigned long end)
  21. *
  22. * Flushes the data cache & invalidate the instruction cache for the
  23. * provided range [start, end[
  24. *
  25. * Note: all CPUs supported by this kernel have a 128 bytes cache
  26. * line size so we don't have to peek that info from the datapage
  27. */
  28. V_FUNCTION_BEGIN(__kernel_sync_dicache)
  29. .cfi_startproc
  30. li r5,127
  31. andc r6,r3,r5 /* round low to line bdy */
  32. subf r8,r6,r4 /* compute length */
  33. add r8,r8,r5 /* ensure we get enough */
  34. srwi. r8,r8,7 /* compute line count */
  35. crclr cr0*4+so
  36. beqlr /* nothing to do? */
  37. mtctr r8
  38. mr r3,r6
  39. 1: dcbst 0,r3
  40. addi r3,r3,128
  41. bdnz 1b
  42. sync
  43. mtctr r8
  44. 1: icbi 0,r6
  45. addi r6,r6,128
  46. bdnz 1b
  47. isync
  48. li r3,0
  49. blr
  50. .cfi_endproc
  51. V_FUNCTION_END(__kernel_sync_dicache)
  52. /*
  53. * POWER5 version of __kernel_sync_dicache
  54. */
  55. V_FUNCTION_BEGIN(__kernel_sync_dicache_p5)
  56. .cfi_startproc
  57. crclr cr0*4+so
  58. sync
  59. isync
  60. li r3,0
  61. blr
  62. .cfi_endproc
  63. V_FUNCTION_END(__kernel_sync_dicache_p5)