ps3.dts 1.8 KB

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  1. /*
  2. * PS3 Game Console device tree.
  3. *
  4. * Copyright (C) 2007 Sony Computer Entertainment Inc.
  5. * Copyright 2007 Sony Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. / {
  21. model = "SonyPS3";
  22. compatible = "sony,ps3";
  23. #size-cells = <2>;
  24. #address-cells = <2>;
  25. chosen {
  26. };
  27. /*
  28. * We'll get the size of the bootmem block from lv1 after startup,
  29. * so we'll put a null entry here.
  30. */
  31. memory {
  32. device_type = "memory";
  33. reg = <0 0 0 0>;
  34. };
  35. /*
  36. * The boot cpu is always zero for PS3.
  37. *
  38. * dtc expects a clock-frequency and timebase-frequency entries, so
  39. * we'll put a null entries here. These will be initialized after
  40. * startup with data from lv1.
  41. *
  42. * Seems the only way currently to indicate a processor has multiple
  43. * threads is with an ibm,ppc-interrupt-server#s entry. We'll put one
  44. * here so we can bring up both of ours. See smp_setup_cpu_maps().
  45. */
  46. cpus {
  47. #size-cells = <0>;
  48. #address-cells = <1>;
  49. cpu@0 {
  50. device_type = "cpu";
  51. reg = <0>;
  52. ibm,ppc-interrupt-server#s = <0 1>;
  53. clock-frequency = <0>;
  54. timebase-frequency = <0>;
  55. i-cache-size = <8000>;
  56. d-cache-size = <8000>;
  57. i-cache-line-size = <80>;
  58. d-cache-line-size = <80>;
  59. };
  60. };
  61. };