mpc832x_mds.dts 7.6 KB

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  1. /*
  2. * MPC8323E EMDS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8323EMDS";
  13. compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. PowerPC,8323@0 {
  20. device_type = "cpu";
  21. reg = <0>;
  22. d-cache-line-size = <20>; // 32 bytes
  23. i-cache-line-size = <20>; // 32 bytes
  24. d-cache-size = <4000>; // L1, 16K
  25. i-cache-size = <4000>; // L1, 16K
  26. timebase-frequency = <0>;
  27. bus-frequency = <0>;
  28. clock-frequency = <0>;
  29. };
  30. };
  31. memory {
  32. device_type = "memory";
  33. reg = <00000000 08000000>;
  34. };
  35. bcsr@f8000000 {
  36. device_type = "board-control";
  37. reg = <f8000000 8000>;
  38. };
  39. soc8323@e0000000 {
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. device_type = "soc";
  43. ranges = <0 e0000000 00100000>;
  44. reg = <e0000000 00000200>;
  45. bus-frequency = <7DE2900>;
  46. wdt@200 {
  47. device_type = "watchdog";
  48. compatible = "mpc83xx_wdt";
  49. reg = <200 100>;
  50. };
  51. i2c@3000 {
  52. device_type = "i2c";
  53. compatible = "fsl-i2c";
  54. reg = <3000 100>;
  55. interrupts = <e 8>;
  56. interrupt-parent = < &ipic >;
  57. dfsrr;
  58. };
  59. serial@4500 {
  60. device_type = "serial";
  61. compatible = "ns16550";
  62. reg = <4500 100>;
  63. clock-frequency = <0>;
  64. interrupts = <9 8>;
  65. interrupt-parent = < &ipic >;
  66. };
  67. serial@4600 {
  68. device_type = "serial";
  69. compatible = "ns16550";
  70. reg = <4600 100>;
  71. clock-frequency = <0>;
  72. interrupts = <a 8>;
  73. interrupt-parent = < &ipic >;
  74. };
  75. crypto@30000 {
  76. device_type = "crypto";
  77. model = "SEC2";
  78. compatible = "talitos";
  79. reg = <30000 7000>;
  80. interrupts = <b 8>;
  81. interrupt-parent = < &ipic >;
  82. /* Rev. 2.2 */
  83. num-channels = <1>;
  84. channel-fifo-len = <18>;
  85. exec-units-mask = <0000004c>;
  86. descriptor-types-mask = <0122003f>;
  87. };
  88. ipic: pic@700 {
  89. interrupt-controller;
  90. #address-cells = <0>;
  91. #interrupt-cells = <2>;
  92. reg = <700 100>;
  93. device_type = "ipic";
  94. };
  95. par_io@1400 {
  96. reg = <1400 100>;
  97. device_type = "par_io";
  98. num-ports = <7>;
  99. pio3: ucc_pin@03 {
  100. pio-map = <
  101. /* port pin dir open_drain assignment has_irq */
  102. 3 4 3 0 2 0 /* MDIO */
  103. 3 5 1 0 2 0 /* MDC */
  104. 0 d 2 0 1 0 /* RX_CLK (CLK9) */
  105. 3 18 2 0 1 0 /* TX_CLK (CLK10) */
  106. 1 1 1 0 1 0 /* TxD1 */
  107. 1 0 1 0 1 0 /* TxD0 */
  108. 1 1 1 0 1 0 /* TxD1 */
  109. 1 2 1 0 1 0 /* TxD2 */
  110. 1 3 1 0 1 0 /* TxD3 */
  111. 1 4 2 0 1 0 /* RxD0 */
  112. 1 5 2 0 1 0 /* RxD1 */
  113. 1 6 2 0 1 0 /* RxD2 */
  114. 1 7 2 0 1 0 /* RxD3 */
  115. 1 8 2 0 1 0 /* RX_ER */
  116. 1 9 1 0 1 0 /* TX_ER */
  117. 1 a 2 0 1 0 /* RX_DV */
  118. 1 b 2 0 1 0 /* COL */
  119. 1 c 1 0 1 0 /* TX_EN */
  120. 1 d 2 0 1 0>;/* CRS */
  121. };
  122. pio4: ucc_pin@04 {
  123. pio-map = <
  124. /* port pin dir open_drain assignment has_irq */
  125. 3 1f 2 0 1 0 /* RX_CLK (CLK7) */
  126. 3 6 2 0 1 0 /* TX_CLK (CLK8) */
  127. 1 12 1 0 1 0 /* TxD0 */
  128. 1 13 1 0 1 0 /* TxD1 */
  129. 1 14 1 0 1 0 /* TxD2 */
  130. 1 15 1 0 1 0 /* TxD3 */
  131. 1 16 2 0 1 0 /* RxD0 */
  132. 1 17 2 0 1 0 /* RxD1 */
  133. 1 18 2 0 1 0 /* RxD2 */
  134. 1 19 2 0 1 0 /* RxD3 */
  135. 1 1a 2 0 1 0 /* RX_ER */
  136. 1 1b 1 0 1 0 /* TX_ER */
  137. 1 1c 2 0 1 0 /* RX_DV */
  138. 1 1d 2 0 1 0 /* COL */
  139. 1 1e 1 0 1 0 /* TX_EN */
  140. 1 1f 2 0 1 0>;/* CRS */
  141. };
  142. };
  143. };
  144. qe@e0100000 {
  145. #address-cells = <1>;
  146. #size-cells = <1>;
  147. device_type = "qe";
  148. model = "QE";
  149. ranges = <0 e0100000 00100000>;
  150. reg = <e0100000 480>;
  151. brg-frequency = <0>;
  152. bus-frequency = <BCD3D80>;
  153. muram@10000 {
  154. device_type = "muram";
  155. ranges = <0 00010000 00004000>;
  156. data-only@0 {
  157. reg = <0 4000>;
  158. };
  159. };
  160. spi@4c0 {
  161. device_type = "spi";
  162. compatible = "fsl_spi";
  163. reg = <4c0 40>;
  164. interrupts = <2>;
  165. interrupt-parent = < &qeic >;
  166. mode = "cpu";
  167. };
  168. spi@500 {
  169. device_type = "spi";
  170. compatible = "fsl_spi";
  171. reg = <500 40>;
  172. interrupts = <1>;
  173. interrupt-parent = < &qeic >;
  174. mode = "cpu";
  175. };
  176. usb@6c0 {
  177. device_type = "usb";
  178. compatible = "qe_udc";
  179. reg = <6c0 40 8B00 100>;
  180. interrupts = <b>;
  181. interrupt-parent = < &qeic >;
  182. mode = "slave";
  183. };
  184. ucc@2200 {
  185. device_type = "network";
  186. compatible = "ucc_geth";
  187. model = "UCC";
  188. device-id = <3>;
  189. reg = <2200 200>;
  190. interrupts = <22>;
  191. interrupt-parent = < &qeic >;
  192. /*
  193. * mac-address is deprecated and will be removed
  194. * in 2.6.25. Only recent versions of
  195. * U-Boot support local-mac-address, however.
  196. */
  197. mac-address = [ 00 00 00 00 00 00 ];
  198. local-mac-address = [ 00 00 00 00 00 00 ];
  199. rx-clock = <19>;
  200. tx-clock = <1a>;
  201. phy-handle = < &phy3 >;
  202. pio-handle = < &pio3 >;
  203. };
  204. ucc@3200 {
  205. device_type = "network";
  206. compatible = "ucc_geth";
  207. model = "UCC";
  208. device-id = <4>;
  209. reg = <3000 200>;
  210. interrupts = <23>;
  211. interrupt-parent = < &qeic >;
  212. /*
  213. * mac-address is deprecated and will be removed
  214. * in 2.6.25. Only recent versions of
  215. * U-Boot support local-mac-address, however.
  216. */
  217. mac-address = [ 00 00 00 00 00 00 ];
  218. local-mac-address = [ 00 00 00 00 00 00 ];
  219. rx-clock = <17>;
  220. tx-clock = <18>;
  221. phy-handle = < &phy4 >;
  222. pio-handle = < &pio4 >;
  223. };
  224. mdio@2320 {
  225. #address-cells = <1>;
  226. #size-cells = <0>;
  227. reg = <2320 18>;
  228. device_type = "mdio";
  229. compatible = "ucc_geth_phy";
  230. phy3: ethernet-phy@03 {
  231. interrupt-parent = < &ipic >;
  232. interrupts = <11 8>;
  233. reg = <3>;
  234. device_type = "ethernet-phy";
  235. };
  236. phy4: ethernet-phy@04 {
  237. interrupt-parent = < &ipic >;
  238. interrupts = <12 8>;
  239. reg = <4>;
  240. device_type = "ethernet-phy";
  241. };
  242. };
  243. qeic: qeic@80 {
  244. interrupt-controller;
  245. device_type = "qeic";
  246. #address-cells = <0>;
  247. #interrupt-cells = <1>;
  248. reg = <80 80>;
  249. big-endian;
  250. interrupts = <20 8 21 8>; //high:32 low:33
  251. interrupt-parent = < &ipic >;
  252. };
  253. };
  254. pci@e0008500 {
  255. interrupt-map-mask = <f800 0 0 7>;
  256. interrupt-map = <
  257. /* IDSEL 0x11 AD17 */
  258. 8800 0 0 1 &ipic 14 8
  259. 8800 0 0 2 &ipic 15 8
  260. 8800 0 0 3 &ipic 16 8
  261. 8800 0 0 4 &ipic 17 8
  262. /* IDSEL 0x12 AD18 */
  263. 9000 0 0 1 &ipic 16 8
  264. 9000 0 0 2 &ipic 17 8
  265. 9000 0 0 3 &ipic 14 8
  266. 9000 0 0 4 &ipic 15 8
  267. /* IDSEL 0x13 AD19 */
  268. 9800 0 0 1 &ipic 17 8
  269. 9800 0 0 2 &ipic 14 8
  270. 9800 0 0 3 &ipic 15 8
  271. 9800 0 0 4 &ipic 16 8
  272. /* IDSEL 0x15 AD21*/
  273. a800 0 0 1 &ipic 14 8
  274. a800 0 0 2 &ipic 15 8
  275. a800 0 0 3 &ipic 16 8
  276. a800 0 0 4 &ipic 17 8
  277. /* IDSEL 0x16 AD22*/
  278. b000 0 0 1 &ipic 17 8
  279. b000 0 0 2 &ipic 14 8
  280. b000 0 0 3 &ipic 15 8
  281. b000 0 0 4 &ipic 16 8
  282. /* IDSEL 0x17 AD23*/
  283. b800 0 0 1 &ipic 16 8
  284. b800 0 0 2 &ipic 17 8
  285. b800 0 0 3 &ipic 14 8
  286. b800 0 0 4 &ipic 15 8
  287. /* IDSEL 0x18 AD24*/
  288. c000 0 0 1 &ipic 15 8
  289. c000 0 0 2 &ipic 16 8
  290. c000 0 0 3 &ipic 17 8
  291. c000 0 0 4 &ipic 14 8>;
  292. interrupt-parent = < &ipic >;
  293. interrupts = <42 8>;
  294. bus-range = <0 0>;
  295. ranges = <02000000 0 90000000 90000000 0 10000000
  296. 42000000 0 80000000 80000000 0 10000000
  297. 01000000 0 00000000 d0000000 0 00100000>;
  298. clock-frequency = <0>;
  299. #interrupt-cells = <1>;
  300. #size-cells = <2>;
  301. #address-cells = <3>;
  302. reg = <e0008500 100>;
  303. compatible = "fsl,mpc8349-pci";
  304. device_type = "pci";
  305. };
  306. };