ebony.dts 6.6 KB

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  1. /*
  2. * Device Tree Source for IBM Ebony
  3. *
  4. * Copyright (c) 2006, 2007 IBM Corp.
  5. * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
  6. *
  7. * FIXME: Draft only!
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without
  11. * any warranty of any kind, whether express or implied.
  12. */
  13. / {
  14. #address-cells = <2>;
  15. #size-cells = <1>;
  16. model = "ibm,ebony";
  17. compatible = "ibm,ebony";
  18. dcr-parent = <&/cpus/PowerPC,440GP@0>;
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. PowerPC,440GP@0 {
  23. device_type = "cpu";
  24. reg = <0>;
  25. clock-frequency = <0>; // Filled in by zImage
  26. timebase-frequency = <0>; // Filled in by zImage
  27. i-cache-line-size = <20>;
  28. d-cache-line-size = <20>;
  29. i-cache-size = <8000>; /* 32 kB */
  30. d-cache-size = <8000>; /* 32 kB */
  31. dcr-controller;
  32. dcr-access-method = "native";
  33. };
  34. };
  35. memory {
  36. device_type = "memory";
  37. reg = <0 0 0>; // Filled in by zImage
  38. };
  39. UIC0: interrupt-controller0 {
  40. compatible = "ibm,uic-440gp", "ibm,uic";
  41. interrupt-controller;
  42. cell-index = <0>;
  43. dcr-reg = <0c0 009>;
  44. #address-cells = <0>;
  45. #size-cells = <0>;
  46. #interrupt-cells = <2>;
  47. };
  48. UIC1: interrupt-controller1 {
  49. compatible = "ibm,uic-440gp", "ibm,uic";
  50. interrupt-controller;
  51. cell-index = <1>;
  52. dcr-reg = <0d0 009>;
  53. #address-cells = <0>;
  54. #size-cells = <0>;
  55. #interrupt-cells = <2>;
  56. interrupts = <1e 4 1f 4>; /* cascade */
  57. interrupt-parent = <&UIC0>;
  58. };
  59. CPC0: cpc {
  60. compatible = "ibm,cpc-440gp";
  61. dcr-reg = <0b0 003 0e0 010>;
  62. // FIXME: anything else?
  63. };
  64. plb {
  65. compatible = "ibm,plb-440gp", "ibm,plb4";
  66. #address-cells = <2>;
  67. #size-cells = <1>;
  68. ranges;
  69. clock-frequency = <0>; // Filled in by zImage
  70. SDRAM0: memory-controller {
  71. compatible = "ibm,sdram-440gp";
  72. dcr-reg = <010 2>;
  73. // FIXME: anything else?
  74. };
  75. SRAM0: sram {
  76. compatible = "ibm,sram-440gp";
  77. dcr-reg = <020 8 00a 1>;
  78. };
  79. DMA0: dma {
  80. // FIXME: ???
  81. compatible = "ibm,dma-440gp";
  82. dcr-reg = <100 027>;
  83. };
  84. MAL0: mcmal {
  85. compatible = "ibm,mcmal-440gp", "ibm,mcmal";
  86. dcr-reg = <180 62>;
  87. num-tx-chans = <4>;
  88. num-rx-chans = <4>;
  89. interrupt-parent = <&MAL0>;
  90. interrupts = <0 1 2 3 4>;
  91. #interrupt-cells = <1>;
  92. #address-cells = <0>;
  93. #size-cells = <0>;
  94. interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
  95. /*RXEOB*/ 1 &UIC0 b 4
  96. /*SERR*/ 2 &UIC1 0 4
  97. /*TXDE*/ 3 &UIC1 1 4
  98. /*RXDE*/ 4 &UIC1 2 4>;
  99. interrupt-map-mask = <ffffffff>;
  100. };
  101. POB0: opb {
  102. compatible = "ibm,opb-440gp", "ibm,opb";
  103. #address-cells = <1>;
  104. #size-cells = <1>;
  105. /* Wish there was a nicer way of specifying a full 32-bit
  106. range */
  107. ranges = <00000000 1 00000000 80000000
  108. 80000000 1 80000000 80000000>;
  109. dcr-reg = <090 00b>;
  110. interrupt-parent = <&UIC1>;
  111. interrupts = <7 4>;
  112. clock-frequency = <0>; // Filled in by zImage
  113. EBC0: ebc {
  114. compatible = "ibm,ebc-440gp", "ibm,ebc";
  115. dcr-reg = <012 2>;
  116. #address-cells = <2>;
  117. #size-cells = <1>;
  118. clock-frequency = <0>; // Filled in by zImage
  119. // ranges property is supplied by zImage
  120. // based on firmware's configuration of the
  121. // EBC bridge
  122. interrupts = <5 4>;
  123. interrupt-parent = <&UIC1>;
  124. small-flash@0,80000 {
  125. compatible = "jedec-flash";
  126. bank-width = <1>;
  127. reg = <0 80000 80000>;
  128. #address-cells = <1>;
  129. #size-cells = <1>;
  130. partition@0 {
  131. label = "OpenBIOS";
  132. reg = <0 80000>;
  133. read-only;
  134. };
  135. };
  136. ds1743@1,0 {
  137. /* NVRAM & RTC */
  138. compatible = "ds1743";
  139. reg = <1 0 2000>;
  140. };
  141. large-flash@2,0 {
  142. compatible = "jedec-flash";
  143. bank-width = <1>;
  144. reg = <2 0 400000>;
  145. #address-cells = <1>;
  146. #size-cells = <1>;
  147. partition@0 {
  148. label = "fs";
  149. reg = <0 380000>;
  150. };
  151. partition@380000 {
  152. label = "firmware";
  153. reg = <380000 80000>;
  154. };
  155. };
  156. ir@3,0 {
  157. reg = <3 0 10>;
  158. };
  159. fpga@7,0 {
  160. compatible = "Ebony-FPGA";
  161. reg = <7 0 10>;
  162. virtual-reg = <e8300000>;
  163. };
  164. };
  165. UART0: serial@40000200 {
  166. device_type = "serial";
  167. compatible = "ns16550";
  168. reg = <40000200 8>;
  169. virtual-reg = <e0000200>;
  170. clock-frequency = <A8C000>;
  171. current-speed = <2580>;
  172. interrupt-parent = <&UIC0>;
  173. interrupts = <0 4>;
  174. };
  175. UART1: serial@40000300 {
  176. device_type = "serial";
  177. compatible = "ns16550";
  178. reg = <40000300 8>;
  179. virtual-reg = <e0000300>;
  180. clock-frequency = <A8C000>;
  181. current-speed = <2580>;
  182. interrupt-parent = <&UIC0>;
  183. interrupts = <1 4>;
  184. };
  185. IIC0: i2c@40000400 {
  186. /* FIXME */
  187. device_type = "i2c";
  188. compatible = "ibm,iic-440gp", "ibm,iic";
  189. reg = <40000400 14>;
  190. interrupt-parent = <&UIC0>;
  191. interrupts = <2 4>;
  192. };
  193. IIC1: i2c@40000500 {
  194. /* FIXME */
  195. device_type = "i2c";
  196. compatible = "ibm,iic-440gp", "ibm,iic";
  197. reg = <40000500 14>;
  198. interrupt-parent = <&UIC0>;
  199. interrupts = <3 4>;
  200. };
  201. GPIO0: gpio@40000700 {
  202. /* FIXME */
  203. compatible = "ibm,gpio-440gp";
  204. reg = <40000700 20>;
  205. };
  206. ZMII0: emac-zmii@40000780 {
  207. compatible = "ibm,zmii-440gp", "ibm,zmii";
  208. reg = <40000780 c>;
  209. };
  210. EMAC0: ethernet@40000800 {
  211. linux,network-index = <0>;
  212. device_type = "network";
  213. compatible = "ibm,emac-440gp", "ibm,emac";
  214. interrupt-parent = <&UIC1>;
  215. interrupts = <1c 4 1d 4>;
  216. reg = <40000800 70>;
  217. local-mac-address = [000000000000]; // Filled in by zImage
  218. mal-device = <&MAL0>;
  219. mal-tx-channel = <0 1>;
  220. mal-rx-channel = <0>;
  221. cell-index = <0>;
  222. max-frame-size = <5dc>;
  223. rx-fifo-size = <1000>;
  224. tx-fifo-size = <800>;
  225. phy-mode = "rmii";
  226. phy-map = <00000001>;
  227. zmii-device = <&ZMII0>;
  228. zmii-channel = <0>;
  229. };
  230. EMAC1: ethernet@40000900 {
  231. linux,network-index = <1>;
  232. device_type = "network";
  233. compatible = "ibm,emac-440gp", "ibm,emac";
  234. interrupt-parent = <&UIC1>;
  235. interrupts = <1e 4 1f 4>;
  236. reg = <40000900 70>;
  237. local-mac-address = [000000000000]; // Filled in by zImage
  238. mal-device = <&MAL0>;
  239. mal-tx-channel = <2 3>;
  240. mal-rx-channel = <1>;
  241. cell-index = <1>;
  242. max-frame-size = <5dc>;
  243. rx-fifo-size = <1000>;
  244. tx-fifo-size = <800>;
  245. phy-mode = "rmii";
  246. phy-map = <00000001>;
  247. zmii-device = <&ZMII0>;
  248. zmii-channel = <1>;
  249. };
  250. GPT0: gpt@40000a00 {
  251. /* FIXME */
  252. reg = <40000a00 d4>;
  253. interrupt-parent = <&UIC0>;
  254. interrupts = <12 4 13 4 14 4 15 4 16 4>;
  255. };
  256. };
  257. PCIX0: pci@1234 {
  258. device_type = "pci";
  259. /* FIXME */
  260. reg = <2 0ec00000 8
  261. 2 0ec80000 f0
  262. 2 0ec80100 fc>;
  263. };
  264. };
  265. chosen {
  266. linux,stdout-path = "/plb/opb/serial@40000200";
  267. };
  268. };