ip22-eisa.c 6.1 KB

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  1. /*
  2. * Basic EISA bus support for the SGI Indigo-2.
  3. *
  4. * (C) 2002 Pascal Dameme <netinet@freesurf.fr>
  5. * and Marc Zyngier <mzyngier@freesurf.fr>
  6. *
  7. * This code is released under both the GPL version 2 and BSD
  8. * licenses. Either license may be used.
  9. *
  10. * This code offers a very basic support for this EISA bus present in
  11. * the SGI Indigo-2. It currently only supports PIO (forget about DMA
  12. * for the time being). This is enough for a low-end ethernet card,
  13. * but forget about your favorite SCSI card...
  14. *
  15. * TODO :
  16. * - Fix bugs...
  17. * - Add ISA support
  18. * - Add DMA (yeah, right...).
  19. * - Fix more bugs.
  20. */
  21. #include <linux/eisa.h>
  22. #include <linux/types.h>
  23. #include <linux/init.h>
  24. #include <linux/irq.h>
  25. #include <linux/kernel_stat.h>
  26. #include <linux/signal.h>
  27. #include <linux/sched.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/delay.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #include <asm/mipsregs.h>
  33. #include <asm/addrspace.h>
  34. #include <asm/processor.h>
  35. #include <asm/sgi/ioc.h>
  36. #include <asm/sgi/mc.h>
  37. #include <asm/sgi/ip22.h>
  38. /* I2 has four EISA slots. */
  39. #define IP22_EISA_MAX_SLOTS 4
  40. #define EISA_MAX_IRQ 16
  41. #define EIU_MODE_REG 0x0001ffc0
  42. #define EIU_STAT_REG 0x0001ffc4
  43. #define EIU_PREMPT_REG 0x0001ffc8
  44. #define EIU_QUIET_REG 0x0001ffcc
  45. #define EIU_INTRPT_ACK 0x00010004
  46. static char __init *decode_eisa_sig(unsigned long addr)
  47. {
  48. static char sig_str[EISA_SIG_LEN];
  49. u8 sig[4];
  50. u16 rev;
  51. int i;
  52. for (i = 0; i < 4; i++) {
  53. sig[i] = inb(addr + i);
  54. if (!i && (sig[0] & 0x80))
  55. return NULL;
  56. }
  57. sig_str[0] = ((sig[0] >> 2) & 0x1f) + ('A' - 1);
  58. sig_str[1] = (((sig[0] & 3) << 3) | (sig[1] >> 5)) + ('A' - 1);
  59. sig_str[2] = (sig[1] & 0x1f) + ('A' - 1);
  60. rev = (sig[2] << 8) | sig[3];
  61. sprintf(sig_str + 3, "%04X", rev);
  62. return sig_str;
  63. }
  64. static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
  65. {
  66. u8 eisa_irq;
  67. u8 dma1, dma2;
  68. eisa_irq = inb(EIU_INTRPT_ACK);
  69. dma1 = inb(EISA_DMA1_STATUS);
  70. dma2 = inb(EISA_DMA2_STATUS);
  71. if (eisa_irq < EISA_MAX_IRQ) {
  72. do_IRQ(eisa_irq);
  73. return IRQ_HANDLED;
  74. }
  75. /* Oops, Bad Stuff Happened... */
  76. printk(KERN_ERR "eisa_irq %d out of bound\n", eisa_irq);
  77. outb(0x20, EISA_INT2_CTRL);
  78. outb(0x20, EISA_INT1_CTRL);
  79. return IRQ_NONE;
  80. }
  81. static void enable_eisa1_irq(unsigned int irq)
  82. {
  83. u8 mask;
  84. mask = inb(EISA_INT1_MASK);
  85. mask &= ~((u8) (1 << irq));
  86. outb(mask, EISA_INT1_MASK);
  87. }
  88. static unsigned int startup_eisa1_irq(unsigned int irq)
  89. {
  90. u8 edge;
  91. /* Only use edge interrupts for EISA */
  92. edge = inb(EISA_INT1_EDGE_LEVEL);
  93. edge &= ~((u8) (1 << irq));
  94. outb(edge, EISA_INT1_EDGE_LEVEL);
  95. enable_eisa1_irq(irq);
  96. return 0;
  97. }
  98. static void disable_eisa1_irq(unsigned int irq)
  99. {
  100. u8 mask;
  101. mask = inb(EISA_INT1_MASK);
  102. mask |= ((u8) (1 << irq));
  103. outb(mask, EISA_INT1_MASK);
  104. }
  105. static void mask_and_ack_eisa1_irq(unsigned int irq)
  106. {
  107. disable_eisa1_irq(irq);
  108. outb(0x20, EISA_INT1_CTRL);
  109. }
  110. static void end_eisa1_irq(unsigned int irq)
  111. {
  112. if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  113. enable_eisa1_irq(irq);
  114. }
  115. static struct irq_chip ip22_eisa1_irq_type = {
  116. .name = "IP22 EISA",
  117. .startup = startup_eisa1_irq,
  118. .ack = mask_and_ack_eisa1_irq,
  119. .mask = disable_eisa1_irq,
  120. .mask_ack = mask_and_ack_eisa1_irq,
  121. .unmask = enable_eisa1_irq,
  122. .end = end_eisa1_irq,
  123. };
  124. static void enable_eisa2_irq(unsigned int irq)
  125. {
  126. u8 mask;
  127. mask = inb(EISA_INT2_MASK);
  128. mask &= ~((u8) (1 << (irq - 8)));
  129. outb(mask, EISA_INT2_MASK);
  130. }
  131. static unsigned int startup_eisa2_irq(unsigned int irq)
  132. {
  133. u8 edge;
  134. /* Only use edge interrupts for EISA */
  135. edge = inb(EISA_INT2_EDGE_LEVEL);
  136. edge &= ~((u8) (1 << (irq - 8)));
  137. outb(edge, EISA_INT2_EDGE_LEVEL);
  138. enable_eisa2_irq(irq);
  139. return 0;
  140. }
  141. static void disable_eisa2_irq(unsigned int irq)
  142. {
  143. u8 mask;
  144. mask = inb(EISA_INT2_MASK);
  145. mask |= ((u8) (1 << (irq - 8)));
  146. outb(mask, EISA_INT2_MASK);
  147. }
  148. static void mask_and_ack_eisa2_irq(unsigned int irq)
  149. {
  150. disable_eisa2_irq(irq);
  151. outb(0x20, EISA_INT2_CTRL);
  152. }
  153. static void end_eisa2_irq(unsigned int irq)
  154. {
  155. if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  156. enable_eisa2_irq(irq);
  157. }
  158. static struct irq_chip ip22_eisa2_irq_type = {
  159. .name = "IP22 EISA",
  160. .startup = startup_eisa2_irq,
  161. .ack = mask_and_ack_eisa2_irq,
  162. .mask = disable_eisa2_irq,
  163. .mask_ack = mask_and_ack_eisa2_irq,
  164. .unmask = enable_eisa2_irq,
  165. .end = end_eisa2_irq,
  166. };
  167. static struct irqaction eisa_action = {
  168. .handler = ip22_eisa_intr,
  169. .name = "EISA",
  170. };
  171. static struct irqaction cascade_action = {
  172. .handler = no_action,
  173. .name = "EISA cascade",
  174. };
  175. int __init ip22_eisa_init(void)
  176. {
  177. int i, c;
  178. char *str;
  179. if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
  180. printk(KERN_INFO "EISA: bus not present.\n");
  181. return 1;
  182. }
  183. printk(KERN_INFO "EISA: Probing bus...\n");
  184. for (c = 0, i = 1; i <= IP22_EISA_MAX_SLOTS; i++) {
  185. if ((str = decode_eisa_sig(0x1000 * i + EISA_VENDOR_ID_OFFSET))) {
  186. printk(KERN_INFO "EISA: slot %d : %s detected.\n",
  187. i, str);
  188. c++;
  189. }
  190. }
  191. printk(KERN_INFO "EISA: Detected %d card%s.\n", c, c < 2 ? "" : "s");
  192. #ifdef CONFIG_ISA
  193. printk(KERN_INFO "ISA support compiled in.\n");
  194. #endif
  195. /* Warning : BlackMagicAhead(tm).
  196. Please wave your favorite dead chicken over the busses */
  197. /* First say hello to the EIU */
  198. outl(0x0000FFFF, EIU_PREMPT_REG);
  199. outl(1, EIU_QUIET_REG);
  200. outl(0x40f3c07F, EIU_MODE_REG);
  201. /* Now be nice to the EISA chipset */
  202. outb(1, EISA_EXT_NMI_RESET_CTRL);
  203. udelay(50); /* Wait long enough for the dust to settle */
  204. outb(0, EISA_EXT_NMI_RESET_CTRL);
  205. outb(0x11, EISA_INT1_CTRL);
  206. outb(0x11, EISA_INT2_CTRL);
  207. outb(0, EISA_INT1_MASK);
  208. outb(8, EISA_INT2_MASK);
  209. outb(4, EISA_INT1_MASK);
  210. outb(2, EISA_INT2_MASK);
  211. outb(1, EISA_INT1_MASK);
  212. outb(1, EISA_INT2_MASK);
  213. outb(0xfb, EISA_INT1_MASK);
  214. outb(0xff, EISA_INT2_MASK);
  215. outb(0, EISA_DMA2_WRITE_SINGLE);
  216. for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
  217. if (i < (SGINT_EISA + 8))
  218. set_irq_chip(i, &ip22_eisa1_irq_type);
  219. else
  220. set_irq_chip(i, &ip22_eisa2_irq_type);
  221. }
  222. /* Cannot use request_irq because of kmalloc not being ready at such
  223. * an early stage. Yes, I've been bitten... */
  224. setup_irq(SGI_EISA_IRQ, &eisa_action);
  225. setup_irq(SGINT_EISA + 2, &cascade_action);
  226. EISA_bus = 1;
  227. return 0;
  228. }