ops-pnx8550.c 6.3 KB

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  1. /*
  2. *
  3. * BRIEF MODULE DESCRIPTION
  4. *
  5. * 2.6 port, Embedded Alley Solutions, Inc
  6. *
  7. * Based on:
  8. * Author: source@mvista.com
  9. *
  10. * This program is free software; you can distribute it and/or modify it
  11. * under the terms of the GNU General Public License (Version 2) as
  12. * published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  17. * for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along
  20. * with this program; if not, write to the Free Software Foundation, Inc.,
  21. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  22. */
  23. #include <linux/types.h>
  24. #include <linux/pci.h>
  25. #include <linux/kernel.h>
  26. #include <linux/init.h>
  27. #include <linux/vmalloc.h>
  28. #include <linux/delay.h>
  29. #include <asm/mach-pnx8550/pci.h>
  30. #include <asm/mach-pnx8550/glb.h>
  31. #include <asm/debug.h>
  32. static inline void clear_status(void)
  33. {
  34. unsigned long pci_stat;
  35. pci_stat = inl(PCI_BASE | PCI_GPPM_STATUS);
  36. outl(pci_stat, PCI_BASE | PCI_GPPM_ICLR);
  37. }
  38. static inline unsigned int
  39. calc_cfg_addr(struct pci_bus *bus, unsigned int devfn, int where)
  40. {
  41. unsigned int addr;
  42. addr = ((bus->number > 0) ? (((bus->number & 0xff) << PCI_CFG_BUS_SHIFT) | 1) : 0);
  43. addr |= ((devfn & 0xff) << PCI_CFG_FUNC_SHIFT) | (where & 0xfc);
  44. return addr;
  45. }
  46. static int
  47. config_access(unsigned int pci_cmd, struct pci_bus *bus, unsigned int devfn, int where, unsigned int pci_mode, unsigned int *val)
  48. {
  49. unsigned int flags;
  50. unsigned long loops = 0;
  51. unsigned long ioaddr = calc_cfg_addr(bus, devfn, where);
  52. local_irq_save(flags);
  53. /*Clear pending interrupt status */
  54. if (inl(PCI_BASE | PCI_GPPM_STATUS)) {
  55. clear_status();
  56. while (!(inl(PCI_BASE | PCI_GPPM_STATUS) == 0)) ;
  57. }
  58. outl(ioaddr, PCI_BASE | PCI_GPPM_ADDR);
  59. if ((pci_cmd == PCI_CMD_IOW) || (pci_cmd == PCI_CMD_CONFIG_WRITE))
  60. outl(*val, PCI_BASE | PCI_GPPM_WDAT);
  61. outl(INIT_PCI_CYCLE | pci_cmd | (pci_mode & PCI_BYTE_ENABLE_MASK),
  62. PCI_BASE | PCI_GPPM_CTRL);
  63. loops =
  64. ((loops_per_jiffy *
  65. PCI_IO_JIFFIES_TIMEOUT) >> (PCI_IO_JIFFIES_SHIFT));
  66. while (1) {
  67. if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_DONE) {
  68. if ((pci_cmd == PCI_CMD_IOR) ||
  69. (pci_cmd == PCI_CMD_CONFIG_READ))
  70. *val = inl(PCI_BASE | PCI_GPPM_RDAT);
  71. clear_status();
  72. local_irq_restore(flags);
  73. return PCIBIOS_SUCCESSFUL;
  74. } else if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_R_MABORT) {
  75. break;
  76. }
  77. loops--;
  78. if (loops == 0) {
  79. printk("%s : Arbiter Locked.\n", __FUNCTION__);
  80. }
  81. }
  82. clear_status();
  83. if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_IOW)) {
  84. printk("%s timeout (GPPM_CTRL=%X) ioaddr %lX pci_cmd %X\n",
  85. __FUNCTION__, inl(PCI_BASE | PCI_GPPM_CTRL), ioaddr,
  86. pci_cmd);
  87. }
  88. if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_CONFIG_READ))
  89. *val = 0xffffffff;
  90. local_irq_restore(flags);
  91. return PCIBIOS_DEVICE_NOT_FOUND;
  92. }
  93. /*
  94. * We can't address 8 and 16 bit words directly. Instead we have to
  95. * read/write a 32bit word and mask/modify the data we actually want.
  96. */
  97. static int
  98. read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
  99. {
  100. unsigned int data = 0;
  101. int err;
  102. if (bus == NULL)
  103. return -1;
  104. err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
  105. switch (where & 0x03) {
  106. case 0:
  107. *val = (unsigned char)(data & 0x000000ff);
  108. break;
  109. case 1:
  110. *val = (unsigned char)((data & 0x0000ff00) >> 8);
  111. break;
  112. case 2:
  113. *val = (unsigned char)((data & 0x00ff0000) >> 16);
  114. break;
  115. case 3:
  116. *val = (unsigned char)((data & 0xff000000) >> 24);
  117. break;
  118. }
  119. return err;
  120. }
  121. static int
  122. read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
  123. {
  124. unsigned int data = 0;
  125. int err;
  126. if (bus == NULL)
  127. return -1;
  128. if (where & 0x01)
  129. return PCIBIOS_BAD_REGISTER_NUMBER;
  130. err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(3 << (where & 3)), &data);
  131. switch (where & 0x02) {
  132. case 0:
  133. *val = (unsigned short)(data & 0x0000ffff);
  134. break;
  135. case 2:
  136. *val = (unsigned short)((data & 0xffff0000) >> 16);
  137. break;
  138. }
  139. return err;
  140. }
  141. static int
  142. read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
  143. {
  144. int err;
  145. if (bus == NULL)
  146. return -1;
  147. if (where & 0x03)
  148. return PCIBIOS_BAD_REGISTER_NUMBER;
  149. err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, 0, val);
  150. return err;
  151. }
  152. static int
  153. write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
  154. {
  155. unsigned int data = (unsigned int)val;
  156. int err;
  157. if (bus == NULL)
  158. return -1;
  159. switch (where & 0x03) {
  160. case 1:
  161. data = (data << 8);
  162. break;
  163. case 2:
  164. data = (data << 16);
  165. break;
  166. case 3:
  167. data = (data << 24);
  168. break;
  169. default:
  170. break;
  171. }
  172. err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(1 << (where & 3)), &data);
  173. return err;
  174. }
  175. static int
  176. write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
  177. {
  178. unsigned int data = (unsigned int)val;
  179. int err;
  180. if (bus == NULL)
  181. return -1;
  182. if (where & 0x01)
  183. return PCIBIOS_BAD_REGISTER_NUMBER;
  184. switch (where & 0x02) {
  185. case 2:
  186. data = (data << 16);
  187. break;
  188. default:
  189. break;
  190. }
  191. err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(3 << (where & 3)), &data);
  192. return err;
  193. }
  194. static int
  195. write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
  196. {
  197. int err;
  198. if (bus == NULL)
  199. return -1;
  200. if (where & 0x03)
  201. return PCIBIOS_BAD_REGISTER_NUMBER;
  202. err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, 0, &val);
  203. return err;
  204. }
  205. static int config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
  206. {
  207. switch (size) {
  208. case 1: {
  209. u8 _val;
  210. int rc = read_config_byte(bus, devfn, where, &_val);
  211. *val = _val;
  212. return rc;
  213. }
  214. case 2: {
  215. u16 _val;
  216. int rc = read_config_word(bus, devfn, where, &_val);
  217. *val = _val;
  218. return rc;
  219. }
  220. default:
  221. return read_config_dword(bus, devfn, where, val);
  222. }
  223. }
  224. static int config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
  225. {
  226. switch (size) {
  227. case 1:
  228. return write_config_byte(bus, devfn, where, (u8) val);
  229. case 2:
  230. return write_config_word(bus, devfn, where, (u16) val);
  231. default:
  232. return write_config_dword(bus, devfn, where, val);
  233. }
  234. }
  235. struct pci_ops pnx8550_pci_ops = {
  236. config_read,
  237. config_write
  238. };